Semiconductor device and semiconductor package

Abstract

The invention discloses a semiconductor device and a semiconductor package. The semiconductor package includes a semiconductor chip including a substrate, an interconnect structure on a front surface of the substrate, and a cushion layer on a front surface of the interconnect structure. The first side surface of the semiconductor chip is inclined relative to or bent relative to the front surface of the semiconductor chip, and is inclined relative to or bent relative to the second side surface of the semiconductor chip. A first side surface of the semiconductor chip is from a point on a side surface of the substrate to an edge of a front surface of the semiconductor chip, and a second side surface of the semiconductor chip is from the point to an edge of a back surface of the semiconductor chip.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0034329 filed on March 12, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of the inventive concept relate to a semiconductor device and a method of manufacturing the same. Background Art

[0003] As semiconductor devices (such as semiconductor packages) become increasingly smaller and feature higher performance, the at least one semiconductor chip included in the semiconductor package is also being reduced in size and achieving higher performance. Multiple semiconductor chips can be formed by separating multiple regions of a wafer. The miniaturization and improved performance of the at least one semiconductor chip increase the difficulty of preventing defects (e.g., cracks, kinks, delamination, etc.) in the semiconductor chips caused by wafer separation. The greater the difficulty in preventing defects, the more difficult it may be to improve the productivity (e.g., yield, cost, time, etc.) of wafer separation. Summary of the Invention

[0004] Example embodiments provide a semiconductor device and a method of manufacturing a semiconductor device, wherein defects in semiconductor chips (e.g., cracks, kinks, peeling, etc.) caused by wafer segmentation can be effectively prevented, and the productivity (e.g., yield, cost, time, etc.) of wafer segmentation can be effectively improved.

[0005] According to an example embodiment, a semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, an interconnect structure, and a pad layer, the interconnect structure being on a front surface of the substrate, and the pad layer being on the front surface of the interconnect structure. When viewed in cross-section, a first side surface of the semiconductor chip is tilted relative to or curved relative to the front surface of the semiconductor chip, and tilted relative to or curved relative to a second side surface of the semiconductor chip, the first side surface of the semiconductor chip extending from a point on the side surface of the substrate to an edge of the front surface of the semiconductor chip, and the second side surface of the semiconductor chip extending from the point to an edge of a back surface of the semiconductor chip.

[0006] According to an exemplary embodiment, a semiconductor package includes a semiconductor chip, the semiconductor chip including a substrate, an interconnect structure, and a pad layer, the interconnect structure being disposed on a front surface of the substrate, and the pad layer being disposed on the front surface of the interconnect structure. When viewed in cross-section, a first side surface of the semiconductor chip has a heat-affected zone extending from a point on the side surface of the substrate to an edge of the front surface of the semiconductor chip. The point is the bottom of the heat-affected zone.

[0007] According to example embodiments, a method of manufacturing a semiconductor package includes forming a groove in a front surface of a wafer using a laser; and separating a plurality of portions of the wafer connected to each other with the groove therebetween by applying tension to the wafer so that the plurality of portions are spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A and Figure 1B are perspective views and cross-sectional views illustrating wafer division of a semiconductor device and a method of manufacturing the semiconductor device according to example embodiments; Figures 2A to 2E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; Figures 3A to 3D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; Figures 4A to 4C is a cross-sectional view illustrating a semiconductor device according to example embodiments; Figures 5A to 5C is a cross-sectional view illustrating a structure in which a memory chip is provided on a front surface of a semiconductor chip of a semiconductor device according to example embodiments; Figures 6A to 6C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; Figure 7A and Figure 7B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; Figure 7C is a cross-sectional view illustrating a semiconductor device according to example embodiments; Figures 8A to 8B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; Figure 8C is a cross-sectional view illustrating a semiconductor device according to example embodiments; Figures 9A to 9C are cross-sectional views illustrating various shapes of recesses in a semiconductor device and a method of manufacturing the semiconductor device according to example embodiments; Figure 10A is a cross-sectional view illustrating a structure in which a plurality of semiconductor chips of a semiconductor package according to example embodiments are connected to each other by direct bonding; and Figure 10B is a cross-sectional view illustrating a structure in which a semiconductor chip of a semiconductor package according to example embodiments is electrically connected to a redistribution line. DETAILED DESCRIPTION

[0009] The detailed description of the inventive concept described below refers to the accompanying drawings, which illustrate, by way of example, specific embodiments in which the inventive concept can be put into practice. These embodiments are described in sufficient detail to enable those skilled in the art to practice the inventive concept. It should be understood that the various embodiments of the inventive concept are different from each other, but are not necessarily mutually exclusive. For example, the specific shapes, structures, and characteristics described herein with respect to the example embodiments may be implemented in other embodiments without departing from the spirit and scope of the inventive concept. In addition, it should be understood that the position or arrangement of the various elements within each disclosed embodiment may be changed without departing from the spirit and scope of the inventive concept. Therefore, the detailed description set forth below is not intended to be construed as having a limiting meaning, and the scope of the present invention is limited only by the appended claims and all equivalents of the contents claimed by those claims. Similar reference numerals in the drawings refer to the same or similar functions in various aspects.

[0010] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings to enable those skilled in the art to easily practice the present invention.

[0011] Throughout the specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that, unless the context indicates otherwise, the component is formed only of that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed only of the listed elements.

[0012] Ordinal numbers such as "first," "second," and "third" may be used merely as labels for specific elements, steps, and the like to distinguish such elements, steps, and the like from one another. Terms not described with "first," "second," and the like in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a particular ordinal number (e.g., "first") in a particular claim may be described elsewhere in the specification or in another claim with a different ordinal number (e.g., "second").

[0013] For example, as can be seen in the drawings, items described herein in the singular may be provided in the plural. Therefore, unless the context indicates otherwise, the description of a single item provided in the plural should be understood to apply to the remaining plural items.

[0014] As used herein, terms such as "same," "equal," "planar," "coplanar," "flat," "parallel," and "perpendicular" encompass the same or nearly the same, including variations that may occur due to conventional manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0015] Figure 1BShown by cutting along the XZ plane Figure 1A The XZ cross section of the wafer 100W is obtained by dividing a specific area (B) of the wafer 100W. The method of manufacturing a semiconductor device (such as a semiconductor package) according to an example embodiment can manufacture a plurality of semiconductor chips ( Figure 4A 100 in ). Figure 1A and Figure 5C , each of the plurality of parts 100U may include a plurality of memory cell arrays MC, and the plurality of memory cell arrays MC may be a semiconductor chip ( Figure 5C As described herein, a semiconductor device may refer to a semiconductor chip formed on a die from a wafer and separated from the wafer, may refer to two or more semiconductor chips stacked on each other (which are part of or form a semiconductor package), or may refer to a semiconductor package or a package-on-package device.

[0016] Reference Figure 1A and Figure 1B The wafer 100W may include a substrate 101W, an interconnection structure 180, and a pad layer 190, and the substrate 101W may include a device layer DL1. The interconnection structure 180 and the pad layer 190 may be formed using a photolithography method. The front surface BS of the wafer 100W may be a memory chip ( Figure 5A 200 of them), multiple semiconductor chips ( Figure 10A 100 in ) and reallocate the structure ( Figure 10B At least one of 1110) provides a layout space and can be flat.

[0017] Figures 2A to 2E Sequentially shown along Figure 1B The scribe lane area Kf of the wafer 100W is divided into a plurality of parts 100U, and Figures 2A to 2E At least one of may be changed or omitted according to design.

[0018] Reference Figure 2A , a method of manufacturing a semiconductor package according to example embodiments may include forming a groove in the front surface BS of the wafer 100W using a laser. The position of the groove may correspond to Figure 1B The scribe area Kf in the groove may have a heat affected zone HAZ.

[0019] For example, a non-photosensitive material (such as a protective layer coating (PLC)) layer may be temporarily placed on the front surface BS, and the PLC layer may have through holes to expose the Figure 1BThe laser irradiator may penetrate the through hole and focus the laser on a local point on the front surface BS of the wafer 100W. For example, the laser irradiator may be a femtosecond laser irradiator or a nanosecond laser irradiator.

[0020] Therefore, the laser irradiator can increase the laser energy at a local point to the ablation threshold power or higher, and a groove can be formed. As the amount of time during which the laser energy at the local point is equal to or greater than the ablation threshold power elapses, the groove can be gradually formed deeper. The heat-affected zone (HAZ) of the groove can continue continuously to the rear end of the groove (for example, the lowest point of the groove).

[0021] The heat-affected zone (HAZ) of the groove can be formed by melting / vaporizing the insulating material and / or metal or semiconductor material included in the substrate 101W, the interconnect structure 180, and the pad layer 190, and can also be formed by melting / vaporizing followed by melting / recrystallization. Therefore, the heat-affected zone (HAZ) of the groove can be in the form of a mixture of semiconductor material and insulating material (e.g., at least one of Si, SiO2, SiN, SiCN, and TEOS) and metal material (e.g., at least one of Cu, Al, a copper alloy, and an aluminum alloy). Alternatively, the heat-affected zone (HAZ) of the groove can have a form in which the insulating material and / or metal material is burned by the laser energy. Alternatively, the heat-affected zone (HAZ) of the groove can have a rougher form due to the laser energy. The heat-affected zone (HAZ) refers to a portion of the wafer that is affected (e.g., deformed, burned, melted, etc.) by heat (e.g., from a laser), and can therefore be a burned zone, a melted zone, or a thermally deformed zone.

[0022] The shape of the groove formed by the laser irradiator can be determined by the design of the lens of the laser irradiator (e.g., lens position, refractive index). For example, the groove can be V-shaped in cross section, and the rear end of the heat-affected zone (HAZ) can be a vertex in cross section. The depth of the groove can be deeper than the total thickness of the interconnect structure 180 and the pad layer 190. The depth of the groove can be deeper than the total thickness of the interconnect structure 180, the pad layer 190, and the device layer DL1. The groove and the heat-affected zone (HAZ) can extend continuously from a point in or on the substrate 101W to the front (upper) surface of the pad layer 190.

[0023] As the laser irradiator irradiates the laser for an increased time and / or number of times, the groove can be formed deeper and the heat-affected zone (HAZ) can be larger. The smaller the heat-affected zone (HAZ), the stronger each of the plurality of sections 100U can be. For example, the strength (e.g., compressive strength) of a semiconductor chip having a heat-affected zone (HAZ) formed when the laser irradiator irradiates the laser once or twice can be 557 MPa or greater, and the strength of a semiconductor chip having a heat-affected zone (HAZ) formed when the laser irradiator irradiates the laser five or more times can be 355 MPa or less. The stronger the semiconductor chip, the lower the probability of defects (e.g., cracks, kinks, delamination, etc.) occurring in the semiconductor chip.

[0024] In a method of manufacturing a semiconductor package according to example embodiments, the groove may be formed such that the depth of the groove and the heat affected zone (HAZ) is shorter than the depth of the semiconductor chip ( Figure 4A Since a portion of the thickness of the substrate 101W can be divided without irradiating the laser, the size of the heat-affected zone HAZ can be reduced, and the semiconductor chip ( Figure 4A 100 in FIG) and can reduce defects (e.g., cracks, kinks, peeling, etc.) in semiconductor chips. Optionally, the method of manufacturing a semiconductor package according to example embodiments can reduce the time and / or number of laser irradiations, thereby effectively improving the productivity (e.g., yield, cost, time, etc.) of wafer separation.

[0025] Reference Figure 2B and Figure 2C , a method of manufacturing a semiconductor package according to example embodiments may include reducing the thickness of the wafer 100W. Figure 2B The thickness reduction operation may include adhering a protection tape TP1 to the front surface BS of the wafer 100W. For example, the protection tape TP1 may include an adhesive layer such as a UV curable film and may include a carrier substrate.

[0026] Reference Figure 2C , the thickness reduction operation may include grinding the back side of the wafer 100W. Thus, a portion of the substrate 101W ( Figure 2B 101Wb in the substrate 101Wa), and only the thinned substrate 101Wa may remain. The thickness of the substrate 101Wa may be greater than the depth of the groove and the heat-affected zone (HAZ) (for example, the substrate 101Wa may extend vertically below the bottom of the groove and the HAZ). For example, the grinding process may be a lapping process, which may include a chemical mechanical polishing (CMP) process and / or an etch-back process. Afterwards, the protective tape TP1 may be removed.

[0027] Reference Figure 2D and Figure 2E, a method of manufacturing a semiconductor package according to example embodiments may include separating the plurality of portions 100U by applying tension to the wafer 100W so that the plurality of portions 100U connected to each other across the groove and the heat affected zone HAZ of the wafer 100W are spaced apart from each other. Figure 2D The separation step may include adhering a tensile tape TP2 to the back surface of the wafer 100W. For example, the tensile tape TP2 may be a die attach film (DAF) and may include an adhesive layer TP2a (such as a UV-curable film) and a base layer TP2b including a material that facilitates elongation by tension.

[0028] Reference Figure 2E The separating step may include separating the plurality of portions 100U by applying tension to the stretch tape TP2. For example, both ends of a device for applying tension may be connected to both ends of the base layer TP2b, and the device may pull the base layer TP2b. For example, the device may include a plurality of rollers disposed at both ends and to which the base layer TP2b is mounted or connected, and tension may be applied to the base layer TP2b via the plurality of rollers by rotating the plurality of rollers in opposite directions.

[0029] By separating the multiple sections 100U, the substrate 101Wa and adhesive layer TP2a can be separated into multiple sections. Depending on the formation of the grooves and the heat-affected zone (HAZ), the portion of the substrate 101Wa that overlaps the HAZ in the Z direction may have lower strength than the remaining portions of the substrate 101Wa. Therefore, applying tension to the tensile tape TP2 allows for stable separation of the multiple sections 100U. If the grooves and the HAZ are V-shaped in cross-section, separation of the multiple sections 100U can begin at the apex of the V and continue to the back (lower surface) of the multiple sections 100U.

[0030] Figures 3A to 3D Show Figures 2A to 2E The order of forming the groove and reducing the thickness of the wafer 100W in the method of manufacturing a semiconductor package is reversed. Figures 3A to 3D , the operation of forming the groove in the method of manufacturing the semiconductor package according to example embodiments may be performed after the operation of reducing the thickness of the wafer 100W.

[0031] Reference Figure 3A , a protection tape TP1 may be provided on the front surface BS of the wafer 100W. Figure 3A and Figure 3B , a portion 101Wb of the substrate 101W may be removed, and only the thinned substrate 101Wa may remain. Figure 3C , a tensile tape TP2 may be provided on the back side (lower surface) of the wafer 100W. Figure 3D , it is possible to form a scribe line on the front surface BS of the wafer 100W along the scribe line area ( Figure 1B Thereafter, a tensile force may be applied to the base layer TP2b of the tensile tape TP2 to separate the plurality of sections 100U.

[0032] Figures 4A to 4C is a cross-sectional view illustrating a portion of a semiconductor device such as a semiconductor package according to example embodiments, and may be manufactured by the above-described method of manufacturing a semiconductor package, but is not limited thereto.

[0033] Reference Figures 4A to 4C The semiconductor chips 100 , 100 b , and 100 c of the semiconductor package according to example embodiments may include a substrate 101 , an interconnection structure 180 disposed on a front (upper surface) of the substrate 101 , and a pad layer 190 disposed on a front (upper surface) of the interconnection structure 180 .

[0034] Reference Figure 4A The first side surface GC of the semiconductor chip 100 “from a point on the side surface of the substrate 101 to the edge of the front surface BS of the semiconductor chip 100” may be inclined relative to the second side surface GD of the semiconductor chip 100 “from a point on the side surface of the substrate 101 to the edge of the back surface of the semiconductor chip 100”, or may be curved relative to the second side surface. The first side surface GC may be tilted relative to the front surface BS (for example, may form an angle greater than 90° with the front surface BS) or may be curved relative to the front surface BS, and the second side surface may be perpendicular to the front surface BS. The first side surface GC of the semiconductor chip 100 may have a heat-affected zone HAZ, and the point on the side surface of the substrate 101 may be the rear end (for example, the lowest point) of the heat-affected zone HAZ. For example, the heat-affected zone HAZ may extend along the side surface of the semiconductor chip 100 to the lowest point, which may correspond to a point on the side surface of the semiconductor chip 100. Above this point, the side surface of the semiconductor chip 100 may have a horizontal slope or may be curved, and below this point, the side surface of the semiconductor chip 100 may have a vertical slope perpendicular to the front surface BS of the semiconductor chip 100 .

[0035] For example, the first side surface GC may be formed by Figure 2A and Figure 3D and thus may be tilted relative to the anteroposterior direction (eg, Z direction) and the lateral direction (eg, X direction). For example, the second side surface may be formed by separating Figure 2EThe second side surface may be formed by the plurality of portions 100U shown in FIG. 1 and may be parallel to the front-to-back direction (e.g., the Z direction) and perpendicular to the lateral direction (e.g., the X direction), and may not have a heat-affected zone (HAZ). The strength of the second side surface may be stronger than the strength of the first side surface GC. In the semiconductor chip 100 of the semiconductor package according to the example embodiment, the reduction in strength due to the formation of the first side surface GC may be reduced, thereby reducing defects in the semiconductor chip 100 (e.g., cracks, kinks, delamination, etc.). Since the reduction in strength due to the process for forming the first side surface GC may be reduced, the productivity of wafer segmentation (e.g., yield, cost, time, etc.) may be effectively improved.

[0036] For example, in a lateral direction (e.g., the X direction) of the semiconductor chip 100, the width W_GC of the first side surface GC of the semiconductor chip 100 may be equal to the maximum width of the heat-affected zone (HAZ), and the width of the heat-affected zone (HAZ) may increase from 0 μm to a maximum width (e.g., a maximum width greater than 3 μm but less than 100 μm) in a direction from a point on the side surface of the substrate 101 to the edge of the front surface BS of the semiconductor chip 100. The width W_GC may be the width in the first horizontal direction (e.g., the X direction) between a vertical line extending from the second side surface GD and an edge between the first side surface GC and the front surface BS when viewed from a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction. Therefore, the first side surface GC may have a maximum height component (D-GC) in the vertical direction and a maximum width component W_GC in the horizontal direction. The width component may refer to the width in the first horizontal direction (e.g., the X direction) between a vertical line extending from the second side surface GD and the edge between the first side surface GC and the front surface BS when viewed from a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction. The height component may refer to the height in the vertical direction (e.g., the Z direction) between a horizontal line extending from the front surface BS and a point on the side surface of the substrate 101 when viewed from a second horizontal direction (e.g., the X direction) perpendicular to both the first horizontal direction (e.g., the X direction) and the vertical direction. The heat-affected zone (HAZ) may extend continuously from the point on the side surface of the substrate 101 to the edge of the front surface BS of the semiconductor chip 100. The roughness of the first side surface GC of the semiconductor chip 100 may be rougher than the roughness of the second side surface of the semiconductor chip 100 (in other words, the first side surface GC of the semiconductor chip 100 may be rougher than the second side surface of the semiconductor chip 100, or the roughness of the first side surface GC of the semiconductor chip 100 may be higher than the roughness of the second side surface of the semiconductor chip 100).

[0037] For example, the side surface of the substrate 101 may have an angular shape at a point on the side surface of the substrate 101. The angle of the angular shape may vary depending on the position of the rear end of the heat affected zone HAZ. The first side surface GC of the semiconductor chip 100 has a substantially flat shape from a point on the side surface of the substrate 101 to the edge of the front surface BS of the semiconductor chip 100, and the second side surface of the semiconductor chip 100 may be substantially flat from a point on the side surface of the substrate 101 to the edge of the back surface of the semiconductor chip 100. Therefore, a line passing through multiple points on the first side surface GC may be deflected relative to a line passing through multiple points on the second side surface. The angle between the first side surface GC and the second side surface may be an obtuse angle. The first side surface GC may have a flat shape with a rougher roughness than the second side surface. The first side surface GC may be an inclined side surface.

[0038] Depending on the width of the scribe line region Kf, the width W_GC of the first side surface GC of the semiconductor chip 100 in the lateral direction (e.g., the X direction) of the semiconductor chip 100 may be greater than 3 μm and less than 100 μm. Depending on the total thickness of the semiconductor chip 100 or the thickness of the pad layer 190, the height D_GC of the first side surface GC of the semiconductor chip 100 in the front-to-back direction (e.g., the Z direction) of the semiconductor chip 100 may be greater than 10 μm and less than 300 μm. For example, the total thickness of the interconnect structure 180 and the pad layer 190 may be 20 μm or less and may be thinner than the height D_GC of the first side surface GC. For example, in some embodiments, the total thickness of the semiconductor chip 100 (e.g., from the topmost surface to the bottommost surface) may be greater than 20 μm and less than or equal to 300 μm and may be thicker than twice the height D_GC of the first side surface GC.

[0039] For example, the width W_GC, height D_GC, thickness, and roughness may be measured, respectively, by analyzing using at least one of a transmission electron microscope (TEM), an atomic force microscope (AFM), a scanning electron microscope (SEM), an optical microscope, and a surface profiler, and may be calculated by averaging corresponding pixels in an image obtained through the above analysis.

[0040] The width W_GC of the first side surface GC of the semiconductor chip 100 in the lateral direction (e.g., X direction) of the semiconductor chip 100 may be 0.1 times or more but 1 times or less of the height D_GC of the first side surface GC of the semiconductor chip 100 in the front-back direction (e.g., Z direction) of the semiconductor chip 100. For example, the ratio of the width W_GC to the height D_GC (e.g., aspect ratio) may be determined by the number of times laser irradiation is performed when forming the first side surface GC, and 0.1 times or more but 1 times or less may be the ratio (e.g., aspect ratio) of the first side surface GC formed by performing laser irradiation two or less times.

[0041] Reference Figures 4A to 4C , the interconnection structure 180 on the substrate 101 includes an interconnection line 185 and an interconnection insulating layer 181 , and the pad layer 190 may include a pad 195 and a pad insulating layer 191 .

[0042] The substrate 101 may include a semiconductor (such as silicon). For example, the substrate 101 may include a device layer DL, and the device layer DL may include various impurity regions and device isolation structures (such as shallow trench isolation (STI) structures) for each device. The semiconductor is not limited to silicon and may be at least one of germanium, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). For example, the device may include a planar MOSFET (metal oxide semiconductor FET), a FinFET whose active region has a fin structure, a multi-bridge channel FET (MBCFET) including a plurality of channels vertically stacked on the active region, or a MOSFET. TM ), or a Gate-All-Around transistor, or a vertical FET (VFET), but is not limited thereto.

[0043] For example, the interconnection insulating layer 181 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN). The space within the interconnection structure 180 not occupied by the interconnection line 185 may be filled. The interconnection line 185 may include an interconnection pattern ( Figure 5B 182) and interconnection vias ( Figure 5B Interconnect 185 may be electrically connected to device layer DL. For example, interconnect 185 may include at least one of copper (Cu), a copper alloy, aluminum (Al), and an aluminum alloy. The metal material is not limited thereto and may be at least one of nickel (Ni), gold (Au), cobalt (Co), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or alloys thereof (e.g., TiN, TaN).

[0044] The pad 195 may be provided at the front (upper surface) of the interconnect structure 180 and may be electrically connected to the interconnect line 185. The pad 195 may include copper (Cu) or a copper alloy, but is not limited thereto, and the pad 195 may include a metal material that the interconnect line 185 may include. The pad insulating layer 191 may surround the pad 195. Each of the interconnect insulating layer 181 and the pad insulating layer 191 may include at least one of SiO2, SiN, SiCN, and tetraethoxysilane (TEOS). Depending on the design (e.g., Figure 10B ), the pad 195 may be disposed on the front surface BS of the semiconductor chip 100 .

[0045] Reference Figure 4B , the semiconductor chip 100b of the semiconductor package according to example embodiments may not have Figure 4A Heat affected zone HAZ. For example, Figure 4A The heat-affected zone (HAZ) may be removed or reduced through additional processes (e.g., a side surface cleaning process or a side surface polishing process). The first side surface GC of the semiconductor chip 100b may be inclined relative to or curved relative to the second side surface of the semiconductor chip 100b, which extends from a point on the side surface of the substrate 101 to an edge of the back surface of the semiconductor chip 100b.

[0046] Reference Figure 4C , the semiconductor chip 100c of the semiconductor package according to example embodiments may have a Figure 4A The total thickness of the semiconductor chip 100c may be thicker than the height D_GC of the first side surface GC, but may be thinner than twice the height D_GC. For example, by further extending Figure 2C The time required for the thickness reduction operation to achieve Figure 4C substrate 101.

[0047] Figures 5A to 5C is a cross-sectional view illustrating a structure in which the memory chip 200 is disposed on the front surface BS of the semiconductor chip 100 of the semiconductor package 300 or 1000 according to example embodiments. Figure 5B It shows Figure 5A A partially enlarged view of a portion (A) of a semiconductor package is shown, and Figure 5A It is along Figure 5C 1-1' is a cross-section of the semiconductor package. Figure 5C Shown in Figure 5A and Figure 5B The semiconductor package 1000 is a semiconductor package in which four (but not limited to four) semiconductor packages 300 are stacked in a front-to-back direction (eg, Z direction). Figures 5A to 5C The semiconductor chip 100 can be connected with Figure 4A The semiconductor chip 100 is the same as, but not limited to, this.

[0048] Reference Figure 5A and Figure 5B , a semiconductor package 300 according to example embodiments may include a memory chip 200 and a semiconductor chip 100 .

[0049] The front surface (upper surface) of the semiconductor chip 100 may be the front surface BS. The first side surface GC of the semiconductor chip 100 may be inclined relative to the second side surface of the semiconductor chip 100 (the lower side surface of the substrate 101) or may be curved than the second side surface, and may be tilted or more curved relative to the front (upper) surface of the semiconductor chip 100 or the front (upper) surface of the memory chip 200. The semiconductor chip 100 and the memory chip 200 may be considered as semiconductor chips (e.g., cell-on-peripheral memory chips), for example, having a memory area and a peripheral area that are hybrid-bonded to each other. In this case, the semiconductor device formed by the combined chip may have a first side surface and may have a second side surface perpendicular to the front surface BS of the semiconductor chip 100, the first side surface being a continuous inclined side surface GC including the entire side surface of the memory chip 200 and a portion of the side surface of the semiconductor chip 100. The first side surface and the second side surface may exhibit a combined Figures 4A to 4C The characteristics and orientation of the first and second side surfaces are discussed.The top surface of the peripheral upper unit memory chip can be described as the front surface of the peripheral upper unit memory chip.

[0050] Reference Figure 5A and Figure 5B , the memory chip 200 of the semiconductor package 300 according to example embodiments may be disposed on an area surrounded by an edge area of ​​the front surface BS of the semiconductor chip 100. For example, the width W of the edge area may be in a range of 5 μm to 50 μm. Preferably, the width W of the edge area may be in a range of 10 μm to 30 μm.

[0051] A protective insulating layer 310 is disposed on the upper surface of the memory chip 200, and connection pads 350 may be formed on the protective insulating layer 310 to electrically connect to the memory cells (e.g., through the plate layer 210). A thickness t1 of the protective insulating layer 310 may be less than a width W of the edge region. Specifically, a thickness t2 (not shown) of the protective insulating layer 310 located on the side surface of the memory chip 200 may be less than the width W of the edge region.

[0052] The semiconductor package 300 according to this embodiment may be a memory device in which memory cells are arranged in three dimensions, and memory cells employed in a memory chip may have a three-dimensional memory cell structure.

[0053] Reference Figure 5BThe device layer DL may include source / drain regions 105, a device isolation layer 110, and circuit elements 120. The source / drain regions 105 and the device isolation layer 110 are within a substrate 101, and the circuit elements 120 are disposed on the substrate 101. The substrate 101 may have an upper surface extending in the X and Y directions. The substrate 101 may have an active region defined by the device isolation layer 110. The impurity-doped source / drain regions 105 may be disposed in the active region. The substrate 101 may include a semiconductor material (e.g., a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, the substrate 101 may be provided as a single crystal bulk wafer.

[0054] In some embodiments, the circuit elements 120 may include planar transistors. Each circuit element 120 may include a circuit gate dielectric layer 122, a spacer layer 124, and a circuit gate electrode 125. Source / drain regions 105 may be disposed on both side surfaces of the circuit gate electrode 125 within the substrate 101.

[0055] The interconnect structure 180 may include an interconnect insulation layer 181 and an interconnect line 185 disposed within the interconnect insulation layer 181. The interconnect line 185 may include an interconnect pattern 182 for interlayer connection and an interconnect via 183 (or "contact plug"). The interconnect line 185 may be connected to the circuit element 120 through the interconnect via 183 (e.g., contact plug).

[0056] Pad layer 190 may include a pad 195 and a pad insulating layer 191 surrounding the side surface of pad 195. Pad 195 may include a bonding via 193 to be connected to interconnect line 185 of interconnect structure 180. In some embodiments, bonding via 193 may have a cylindrical shape, and pad 195 may have a pad shape or a line shape with a relatively large area. Bonding via 193 and pad 195 may include a conductive material (e.g., copper (Cu)).

[0057] The upper surface of the pad 195 may have a flat surface exposed to the upper surface of the semiconductor chip 100. The pad 195 may be configured so that the area required for bonding overlaps with the bonding metal layer 295 of the memory chip 200 at a position corresponding to the pad 195. In some embodiments, the pad 195 may have an area substantially corresponding to the area of ​​the bonding metal layer 295. In addition, the bonding via 193 and the pad 195 may provide a path for electrical connection with the memory chip 200. In some embodiments, some of the pads 195 may not be connected to the interconnection line 185, but may be provided for bonding.

[0058] Reference Figure 5BThe memory chip 200 includes a bonding structure 290 for bonding to the semiconductor chip 100. The bonding structure 290 is similar to the pad layer 190 of the semiconductor chip 100. The bonding structure 290 includes a bonding metal layer 295 and a bonding insulating layer 291. The bonding metal layers 295 are each bonded to the pad 195, and the bonding insulating layer 291 surrounds the side surfaces of the bonding metal layer 295 and is bonded to the pad insulating layer 191.

[0059] The bonding metal layer 295 may have a flat surface exposed to the lower surface of the memory chip 200. The bonding metal layer 295 may be bonded and electrically connected to the pad 195 of the semiconductor chip 100. The bonding via 293 and the bonding metal layer 295 may include a conductive material (eg, copper (Cu)).

[0060] The bonding insulating layer 291 may provide a dielectric-to-dielectric bond with the bonding insulating layer 291 of the memory chip 200 similarly to the pad insulating layer 191, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. A combination of dielectric-to-dielectric bonding and copper (Cu)-to-copper (Cu) bonding may be a hybrid bonding.

[0061] The bonding metal layer 295 may be electrically connected to the memory cell (eg, the vertical channel structure CH and the gate electrode 230 ) through the bonding via 293 . Specifically, the bonding via 293 may be disposed under the cell interconnection structure 280 and connected to the interconnection line (or cell interconnection line) 285 .

[0062] In this embodiment, the device layer DL of the memory chip 200 may include a three-dimensional memory cell structure and a mold insulating layer 270 surrounding the three-dimensional memory cell structure.

[0063] For details, refer to Figure 5B The memory cell structure (or, memory cell layer) of the memory chip 200 may include: a plate layer 210 having a first region R1 and a second region R2, a first horizontal conductive layer 212 and a second horizontal conductive layer 214 on the lower surface of the plate layer 210, gate electrodes 230 stacked on the lower surfaces of the first and second horizontal conductive layers 212 and 214, interlayer insulating layers 225 alternately stacked with the gate electrodes 230, a separation region (not shown) extending through the gate electrodes 230 in one direction, a vertical channel structure CH provided to penetrate the plate layer 210 and the gate electrodes 230 in the first region R1, and input / output contact structures 250A and 250B (e.g., first input / output contact structure 250A and second input / output contact structure 250B) provided to penetrate the plate layer 210 and the gate electrodes 230 in the second region R2. The memory chip 200 may include a base insulating layer 215 on the upper surface of the plate layer 210.

[0064] The memory chip 200 includes a cell interconnect structure 280 and may also include a gate contact 260 and a cell interconnect line 285 located in the second region R2. The gate contact 260 is connected to the gate electrode 230. The cell interconnect line 285 includes a cell contact plug 283 and a cell interconnect pattern 282. The cell contact plug 283 is a structure that connects layers and may have a cylindrical shape. The cell contact plug 283 may have different lengths depending on the connection target (location). The gate contact 260, cell contact plug 283, and cell interconnect line 285 may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. In one embodiment, the cell interconnect structure 280 may include a cell interconnect insulation layer 281.

[0065] The first region R1 of the plate layer 210 is a region where the gate electrodes 230 are vertically stacked and the vertical channel structure CH is provided, and may be a memory cell region where the memory cells are provided. The second region R2 of the plate layer 210 is a region where the gate electrodes 230 extend to different lengths, and may correspond to a connection region for electrically connecting the memory cells to the semiconductor chip 100. The second region R2 may be located at at least one end of the first region R1 in at least one direction (e.g., the X direction).

[0066] like Figure 5A As shown in , plate layer 210 may have a structure that extends continuously throughout semiconductor package 300. Plate layer 210 may include a conductive material. For example, plate layer 210 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, a Group IV semiconductor may include silicon, germanium, or silicon germanium. Plate layer 210 may also include impurities. Plate layer 210 may be provided as a polycrystalline semiconductor layer (such as a polysilicon layer) or an epitaxial layer.

[0067] The first horizontal conductive layer 212 and the second horizontal conductive layer 214 may be sequentially stacked and disposed on the lower surface of the first region R1 of the plate layer 210. The first horizontal conductive layer 212 may not extend into the second region R2 of the plate layer 210, and the second horizontal conductive layer 214 may extend into the second region R2. The first horizontal conductive layer 212 may serve as part of a common source line of the semiconductor package 300, and in some embodiments, the first horizontal conductive layer 212 may function as a common source line together with the plate layer 210. The first horizontal conductive layer 212 surrounds the channel layer 240 and may be directly connected to the channel layer 240.

[0068] Second horizontal conductive layer 214 may contact plate layer 210 in some areas where first horizontal conductive layer 212 and horizontal insulating layer 220 are not provided. Second horizontal conductive layer 214 may cover ends of first horizontal conductive layer 212 or horizontal insulating layer 220 in some areas and may be bent to extend onto the lower surface of plate layer 210.

[0069] The first horizontal conductive layer 212 and the second horizontal conductive layer 214 may include semiconductor materials. For example, both the first horizontal conductive layer 212 and the second horizontal conductive layer 214 may include polysilicon doped with impurities. In some embodiments, the material of the second horizontal conductive layer 214 is not limited to semiconductor materials and may be replaced by an insulating layer.

[0070] Horizontal insulating layer 220 may be provided on the lower surface of plate layer 210 at substantially the same level as first horizontal conductive layer 212 in at least a portion of second region R2. Horizontal insulating layer 220 is alternately stacked on second region R2 of plate layer 210 and may include first and second insulating layers made of different materials. For example, horizontal insulating layer 220 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. In some embodiments, the first insulating layer may be made of the same material as interlayer insulating layer 225, and the second insulating layer may be made of a different material than interlayer insulating layer 225.

[0071] The gate electrodes 230 may be vertically separated and stacked on the lower surface of the plate layer 210 to form a stack structure together with the interlayer insulating layer 225. The stack structure is vertically stacked and may include a lower stack structure and an upper stack structure surrounding the first and second channel structures CH1 and CH2, respectively.

[0072] The gate electrode 230 may include at least one lower gate electrode 230L, a memory gate electrode 230M, and an upper gate electrode 230U. The at least one lower gate electrode 230L forms the gate of a ground select transistor, the memory gate electrode 230M forms a plurality of memory cells, and the upper gate electrode 230U forms the gate of a string select transistor. In some embodiments, the gate electrode 230 may include a gate electrode of an erase transistor disposed below the upper gate electrode 230U and / or on the lower gate electrode 230L and used in an erase operation utilizing a gate-induced drain leakage (GIDL) phenomenon.

[0073] The gate electrodes 230 are vertically stacked on the first region R1 and the second region R2 and spaced apart from each other, and extend at different lengths from the first region R1 to the second region R2. A staircase structure in the form of a staircase may be formed in a portion of the second region R2. The gate electrode 230 may be arranged to have a staircase structure in the Y direction. Due to the staircase structure, the lower gate electrode 230L in the gate electrode 230 extends longer than the upper gate electrode 230U, and the gate electrodes 230 may each have an area whose lower surface is exposed downward by the interlayer insulating layer 225 and other gate electrodes 230, and these areas may also be referred to as "gate pad areas". The gate pad area may correspond to a portion of the bottom of each area of ​​the gate electrode 230 located in the second region R2 of the plate layer 210 among the gate electrodes 230 forming a stacked structure. The gate electrode 230 may be connected to the gate contact 260 in the gate pad area.

[0074] The gate electrode 230 may include a metal material (e.g., tungsten (W)). In some embodiments, the gate electrode 230 may include polysilicon or a metal silicide material. In some embodiments, the gate electrode 230 may also include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0075] Interlayer insulating layers 225 may be provided between gate electrodes 230. Similar to gate electrodes 230, interlayer insulating layers 225 may be provided to be spaced apart from each other in a direction perpendicular to the lower surface of plate layer 210 and to extend in the X direction. For example, interlayer insulating layers 225 may include an insulating material such as silicon oxide or silicon nitride.

[0076] Each of the vertical channel structures CH may have first and second channel structures CH1 and CH2 connected to each other, respectively penetrating the lower and upper stack structures of the gate electrode 230 , and may have bent portions with different widths in a connection region.

[0077] Each of the vertical channel structures CH may include a channel layer 240 disposed within the channel hole, a gate dielectric layer (not shown), a channel-filling insulating layer 247, and a channel pad 249. The channel layer 240 may be formed in a ring shape surrounding the inner channel-filling insulating layer 247, but may also have another shape (such as a cylinder or a prism) without the channel-filling insulating layer 247. The lower portion of the channel layer 240 may be connected to the first horizontal conductive layer 212. For example, the channel layer 240 may include a semiconductor material (such as polycrystalline silicon or single crystal silicon).

[0078] A gate dielectric layer may be disposed between the gate electrode 230 and the channel layer 240. The gate dielectric layer may extend vertically along the channel layer 240. The gate dielectric layer may include a tunneling layer, a charge storage layer, and a portion of a blocking layer stacked sequentially from the channel layer 240. The tunneling layer can tunnel charge into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

[0079] A channel pad 249 may be provided only at the lower end of the second channel structure CH2 below. The channel pad 249 may include, for example, doped polysilicon. The channel layer 240, the gate dielectric layer, and the channel filling insulating layer 247 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. An interlayer insulating layer 225 having a relatively large thickness may also be provided between the first channel structure CH1 and the second channel structure CH2.

[0080] like Figure 5B As shown in FIG, the input / output contact structures 250A and 250B may be spaced apart from the vertical channel structure CH in the X direction. The first input / output contact structure 250A may be disposed around the gate contact 260 and may be disposed in a region including the region between adjacent gate contacts 260 in the X direction. The first input / output contact structure 250A may be disposed in the second region R2, penetrating the plate layer 210, the horizontal insulating layer 220, the second horizontal conductive layer 214, and the gate electrode 230. The first input / output contact structure 250A may electrically connect an input / output pad (not shown) to the circuit element 120 of the semiconductor chip 100. The first input / output contact structure 250A may be disposed to overlap the input / output pad (not shown) in the Z direction. In this embodiment, the second input / output contact structure 250B may electrically connect the circuit element 120 of the semiconductor chip 100 to the connection pad 350 for input / output through the plate layer 210.

[0081] The connection pads 350 may be connected to the input / output contact structures 250A and 250B through pad vias 353. The connection pads 350 may be connected to an electrical connection structure (such as a signal transmission medium of the device (such as a package substrate 1100)) through the upper surface of the semiconductor package 300 (see Figure 5C ).

[0082] As previously described, the protective insulating layer 310 is disposed on the upper surface of the memory chip 200 , and the protective insulating layer 310 may extend to the edge region of the semiconductor chip 100 along the side surface of the memory chip 200 .

[0083] like Figure 5B As shown in , the protective insulating layer 310 may include an insulating cap layer 312, a passivation layer 315, and a blocking insulating film 314, the insulating cap layer 312 being disposed on the upper surface and side surfaces of the memory chip 200, the passivation layer 315 being disposed on the insulating cap layer 312, and the blocking insulating film 314 being disposed between the insulating cap layer 312 and the passivation layer 315. The connection pad 350 is disposed on the insulating cap layer 312, and the passivation layer 315 and the blocking insulating film 314 may be configured to expose a portion of the connection pad 350. For example, the insulating cap layer 312 may include silicon oxide, and the passivation layer 315 may include polyimide or a polyimide-based material. In addition, the blocking insulating film 314 may include, for example, silicon nitride or a silicon nitride-based material.

[0084] Figure 5C Each of the semiconductor packages 300 shown in FIG. 1 may include a semiconductor chip 100 having a peripheral circuit and a memory chip 200 having two memory cell arrays MC arranged in the Y direction. However, the number of memory cell arrays MC is not limited to two and may be one or three or more. As described above, the memory chip 200 is bonded to the inner region of the upper surface of the semiconductor chip 100 except for the edge region, so the stepped structure is confirmed based on the side surface of the semiconductor package 300.

[0085] The semiconductor package 1000 may include a package substrate 1100, semiconductor packages 300, wires 1400 (e.g., bonding wires) electrically connecting the semiconductor package 300 and the package substrate 1100, and a mold layer 1500. The semiconductor package 300 is on the package substrate 1100, and the wires 1400 (e.g., bonding wires) electrically connect the semiconductor package 300 and the package substrate 1100. The mold layer 1500 covers the semiconductor package 300 and the wires 1400 on the package substrate 1100. The package substrate 1100 may be a printed circuit board including an electrical connection structure 1130 on the upper portion of the package. Each semiconductor package 300 may include connection pads 350 for input and output. The semiconductor package according to this embodiment (e.g., semiconductor package (such as, 300)) is not limited to Figure 5C The arrangement shown in the semiconductor package 1000 is shown in FIG. 1 and may be used in other ways for various other semiconductor packages.

[0086] In the previous embodiment, semiconductor package 300 is shown as a nonvolatile memory device in which memory cells are arranged in three dimensions. However, the inventive concepts disclosed herein may also be applied to other memory devices (such as DRAM devices) or other semiconductor packages (such as logic devices). For example, in the case of a DRAM device, a semiconductor package in which a semiconductor chip having DRAM cells and a memory chip including peripheral circuits (or capacitors) are bonded at the wafer level may also have a structure similar to the previous embodiment.

[0087] Figures 6A to 6C A method of manufacturing a semiconductor package according to an example embodiment is shown and can be used to manufacture Figure 5A The semiconductor package 300 is shown, but the embodiment is not limited thereto.

[0088] Reference Figure 6A , the memory chip 200W may include a plurality of memory chip regions 200U, and each of the plurality of memory chip regions 200U may correspond to Figure 1A The memory cell array MC is provided by forming a second device layer DL2 on a second substrate 201W and forming a bonding structure 290 having a bonding metal layer 295 and a bonding insulating layer 291, wherein the bonding metal layer 295 is on the second device layer DL2 and the bonding insulating layer 291 surrounds the bonding metal layer 295. Although not shown in this embodiment, an additional interconnection structure having a cell contact plug or an interconnection line may be provided between the second device layer DL2 and the bonding structure 290 (see FIG. Figure 5B 280 in the ).

[0089] Reference Figure 6B , the memory wafer 200W is bonded to the front surface BS of the wafer 100W. As described above, this bonding process can be performed using a hybrid bonding process. By heating the bonding metal layer 295 and the bonding insulating layer 291 under constant pressure while being bonded to the pad 195 and the pad insulating layer 191, respectively, the plurality of portions 100U and the plurality of memory chip regions 200U can be bonded to each other. Depending on the design, the plurality of memory chip regions 200U of the memory wafer 200W can be bonded to the wafer 100W while being substantially separated.

[0090] Reference Figure 6C , removing the second substrate 201W from the memory wafer 200W. The semiconductor package 300 according to this embodiment may require a pad formation process for external connection. As a method for forming the pad, the second substrate 201W may be removed, as in this process, to expose the surface of the second device layer DL2. In this embodiment, the upper surface 210T of the board layer 210 may be exposed. This process may be performed using chemical mechanical polishing (CMP) or a grinding process.

[0091] Reference Figure 6C The operation of forming the groove in the method of manufacturing a semiconductor package according to example embodiments may be the same as that described above with reference to FIG. Figure 2A and Figure 3D The operation of forming the groove is the same as described above and can be performed after removing the second substrate 201W. In one embodiment, the position of the groove can correspond to the scribe line area Kf of the wafer 100W and the memory scribe line area SL of the memory wafer 200W (see Figure 6A ). The multiple parts 100U of the wafer 100W can be Figures 2A to 2E The method of manufacturing a semiconductor package may be separated or may be Figures 3A to 3D Therefore, it is possible to manufacture a semiconductor package. Figure 5A The semiconductor package 300, but the method is not limited to Figure 5A Example of .

[0092] Figure 7A and Figure 7B A method of manufacturing a semiconductor package according to example embodiments is shown. Figure 7C A semiconductor package 300 b according to example embodiments is shown. Figure 7A and Figure 7B Semiconductor packages manufactured in Figure 6A Semiconductor packages manufactured in Figure 7C semiconductor package 300b. Figure 7C The semiconductor package 300b according to example embodiments shown in FIG. Figure 7A and Figure 7B A method for manufacturing a semiconductor package is shown in FIG.

[0093] Reference Figure 7A The operation of forming the groove in the method of manufacturing the semiconductor package according to example embodiments may include forming the groove in the front surface of the memory chip 200W using a laser, and may be similar to the above-mentioned method. Figure 2A and Figure 3D The operations for forming the grooves are the same as described.

[0094] Reference Figure 7B , the wafer 100W can be bonded to the memory wafer 200W having a groove formed thereon, and can be used as described above with reference to Figure 6C The bonding between the wafer 100W and the memory wafer 200W is similar. Subsequently, a separation process (e.g., dicing using a blade having a predetermined width, or dicing using a laser and / or chemical etching that removes a region of a predetermined width) may be performed on the scribe region Kf of the wafer 100W. This separation process can separate the wafer 100W and the substrate 101W.

[0095] (For example, after the scribe area Kf of the wafer 100W is cut as discussed above) Figure 2E The separation step shown in FIG. 1 separates the plurality of memory chip regions 200U of the memory wafer 200W. Figure 7C A semiconductor package 300b according to example embodiments may include a semiconductor chip 100 and a memory chip 200. At least a portion of a first side surface GC of the semiconductor package 300b may be inclined relative to a side surface of the semiconductor chip 100 (a side surface of the substrate 101, which may be a lower side surface of the semiconductor package 300b) or may be curved relative to the side surface of the semiconductor chip 100, and may be tilted or more curved relative to a front (upper) surface of the semiconductor chip 100 or a front surface (upper surface) of the memory chip 200.

[0096] Figure 8A and Figure 8B A method of manufacturing a semiconductor package according to example embodiments is shown. Figure 8C A plurality of semiconductor packages 300 c according to example embodiments are shown. Figure 8A and Figure 8B Semiconductor packages manufactured in Figure 6B Semiconductor packages manufactured in Figure 8C multiple semiconductor packages in the Figure 8C The plurality of semiconductor packages of the example embodiments shown in FIG. Figure 8A and Figure 8B A method for manufacturing a semiconductor package is shown in FIG.

[0097] Reference Figure 6B and Figure 8A ,from Figure 6B The memory chip 200W is removed from the second substrate 201W, the board layer 210 is removed, and an additional memory chip 200W can be further bonded to the removed location. Figure 6A The bonding structure 290 may be disposed between the plurality of memory chips 200W to provide an electrical connection path between the plurality of memory chips 200W.

[0098] Reference Figure 8B , the operation of forming the groove in the method of manufacturing the semiconductor package according to the example embodiment may include forming the groove in the front surface of the wafer 100W and the plurality of memory chips 200W using a laser, and may be similar to the above reference Figure 2A and Figure 3D The operation of forming the groove is the same as described above. The groove can penetrate the plurality of memory chips 200W. The plurality of memory chips 200W can be arranged on the wafer 100W.

[0099] Reference Figure 8C , can be Figure 2E The separation step shown in FIG. 1 separates the plurality of portions 100U of the wafer 100W, thereby separating the plurality of memory chip regions 200U of each of the plurality of memory wafers 200W. Each semiconductor package 300c according to example embodiments may include a semiconductor chip 100 and a plurality of memory chips 200. The first side surface GC of the semiconductor chip 100 and the side surfaces of the memory chips 200 may be inclined relative to or curved relative to the second side surface (the lower side surface of the substrate 101W) of the semiconductor chip 100. The front (upper) surface of a semiconductor device (such as the semiconductor package 300c) may be the front (upper) surface of the memory chip 200 that is located farthest from the pad layer 190.

[0100] Figures 9A to 9C are cross-sectional views illustrating various shapes of grooves (or heat-affected zones (HAZ1 , HAZ2 , HAZ3 )) of a semiconductor package and a method of manufacturing the semiconductor package according to example embodiments. Figures 9A to 9C The various shapes of the grooves (or heat affected zones (HAZ1, HAZ2, HAZ3)) can be Figures 2A to 8C The process distribution of the semiconductor package and the method of manufacturing the semiconductor package are implemented, and therefore, can replace Figures 2A to 8C A groove (or heat affected zone HAZ) of a semiconductor package and a method of manufacturing the semiconductor package are disclosed, but the embodiment is not limited thereto.

[0101] Reference Figures 9A to 9C The first side surface of the semiconductor chip 100 (the location of the heat-affected zones HAZ1, HAZ2, and HAZ3) extending from a point on the side surface of the substrate 101 to the edge of the front surface BS of the semiconductor chip 100 may be curved relative to the second side surface of the semiconductor chip 100 (the location of the heat-affected zones HAZ1, HAZ2, and HAZ3) extending from a point on the side surface of the substrate 101 to the edge of the back surface of the semiconductor chip 100. The first side surface (the location of the heat-affected zones HAZ1, HAZ2, and HAZ3) may be curved relative to the front surface BS, and the second side surface may be perpendicular to the front surface BS. The first side surface may have heat-affected zones (HAZ1, HAZ2, and HAZ3), and the point on the side surface of the substrate 101 may be the rear end of the heat-affected zones (HAZ1, HAZ2, and HAZ3).

[0102] The degree of curvature of the side surface can be measured using the differential value at each point on the side surface. For example, in an image obtained by analyzing a cross-section of a semiconductor package using at least one of a TEM, AFM, SEM, optical microscope, and surface profilometer, the side surface of the semiconductor chip can be identified visually or through image processing (for example, by extracting points where brightness changes rapidly between pixels). Subsequently, convex or concave portions can be identified based on the differential value at each point on the identified side surface. A parameter representing the degree of curvature of the side surface can then be calculated based on the difference between the peak values ​​of the differential values ​​in the convex or concave portions.

[0103] Reference Figure 9A , one side surface of the heat affected zone HAZ1 may be concave, and the other side surface of the heat affected zone HAZ1 may be convex. Figure 9B , the heat affected zone HAZ2 can be concave on both side surfaces. According to the design, the heat affected zone can be convex on both side surfaces. Figure 9C The heat affected zone HAZ3 can be in a concave-convex form, and can be in a concave and convex form alternating up and down.

[0104] Figure 10A 1 is a cross-sectional view illustrating a structure in which a plurality of semiconductor chips 100 of a semiconductor package 1000b are connected to each other by direct bonding according to an example embodiment. For example, the semiconductor package 1000b may be at least a portion of a high bandwidth memory (HBM) and may be electrically connected to an interposer or a printed circuit board.

[0105] For example, some of the plurality of semiconductor chips 100 may be volatile memory chips (such as dynamic random access memory (DRAM) or static random access memory (SRAM)), or may be non-volatile memory chips (such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). For example, one of the plurality of semiconductor chips 100 may be a logic chip (such as a microprocessor, an analog element, or a digital signal processor).

[0106] Reference Figure 10AAt least one of the plurality of semiconductor chips 100 may further include at least one of a through electrode 153, a back pad 152, and a back insulating layer 151. The plurality of first side surfaces GC “from a point on the side surface of the substrate 101 of each of the plurality of semiconductor chips 100 to an edge of the front surface of each of the plurality of semiconductor chips 100” may be tilted relative to the plurality of second side surfaces “from a point on the side surface of the substrate 101 of each of the plurality of semiconductor chips 100 to an edge of the back surface of each of the plurality of semiconductor chips 100” or may be curved compared to the plurality of second side surfaces.

[0107] Each of the through electrodes 153 may have a pillar structure penetrating the substrate 101. A front end of the through electrode 153 may be electrically connected to the device layer DL or the interconnection structure 180, and a rear end of the through electrode 153 may be electrically connected to the back pad 152. For example, each of the through electrodes 153 may include a via plug and an insulating liner surrounding the via plug.

[0108] For example, the back pad 152 may be provided with a pad ( Figure 4A 195) is implemented in a similar manner, and the back insulating layer 151 can be formed in a manner similar to the pad insulating layer ( Figure 4A 191) in a similar manner.

[0109] Figure 10B is a cross-sectional view illustrating a structure in which the semiconductor chip 100 of the semiconductor package 1000 c is electrically connected to a redistribution line according to example embodiments.

[0110] Reference Figure 10B , the semiconductor chip 100 may be mounted on the redistribution structure 1110 in a flip-chip structure. The semiconductor package 1000c may include at least one of the redistribution structure 1110, the electrical connection structure 1130, the bonding insulation structure 1140, the molding layer 1150, and the bump 1160. For example, the molding layer 1150 and Figure 5C The molding layer 1500 may include epoxy molding compound (EMC).

[0111] The redistribution structure 1110 may have a structure in which at least one redistribution insulating layer 1111 and at least one redistribution layer 1112 are alternately stacked. For example, the redistribution structure 1110 is a supporting substrate on which the semiconductor chip 100 is mounted, and may be a packaging substrate for interconnecting pads 1121 of the semiconductor chip 100. Examples of packaging substrates may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape interconnect substrate, and the like. The redistribution structure 1110 may include a redistribution insulating layer 1111, a redistribution layer 1112, redistribution vias 1113, an upper solder mask layer 1115, and a lower solder mask layer 1116. In example embodiments, the number of redistribution insulating layers 1111 and redistribution layers 1112 forming the redistribution structure 1110 may vary. In some embodiments, the redistribution structure 1110 may be an interposer substrate (e.g., an organic interposer). In some embodiments, the redistribution structure 1110 may be a module substrate, in which case the semiconductor chip 100 may be a semiconductor structure (such as a semiconductor package).

[0112] The redistribution insulation layer 1111 includes an insulating material and may include, for example, a thermosetting resin (such as an epoxy resin) or a thermoplastic resin (such as polyimide). For example, the redistribution insulation layer 1111 may include a photosensitive insulating material (such as a PID (photoimageable dielectric) resin). Alternatively, the redistribution insulation layer 1111 may include a resin mixed with an inorganic filler (for example, an ajinomoto build-up film (ABF)). Alternatively, the redistribution insulation layer 1111 may include a prepreg, a flame retardant (FR-4), or bismaleimide triazine (BT). The redistribution insulation layer 1111 may include the same or different materials. Depending on the material and process constituting each layer, the boundaries between the redistribution insulation layers 1111 may not be distinct.

[0113] The redistribution layer 1112 and the redistribution vias 1113 may form an electrical path. The redistribution layer 1112 and the redistribution vias 1113 may interconnect the semiconductor chip 100 to an area outside the semiconductor chip 100 (e.g., to a fan-out area that does not overlap with the semiconductor chip 100 in the Z direction). Therefore, the semiconductor package 1000c of this embodiment may be referred to as a fan-out semiconductor package. However, the form of the semiconductor package is not limited thereto, and in some embodiments, the semiconductor package 1000c may form a fan-in semiconductor package. The redistribution layer 1112 and the redistribution vias 1113 may include a ground pattern, a power pattern, and a signal pattern. The redistribution layer 1112 may be arranged in a linear shape on the XY plane, and the redistribution vias 1113 may have a cylindrical shape with a side surface skewed so that the width narrows toward the bottom or top. The redistribution vias 1113 are shown as filled via structures whose interiors are completely filled with conductive material, but are not limited thereto. For example, the redistribution via 1113 may have a conformal via shape in which a metal material is formed along an inner wall of a via hole.

[0114] The redistribution layer 1112 and the redistribution vias 1113 may include a conductive material, and may include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on the width of the interconnects of the redistribution layer 1112 or the spacing between the interconnects (e.g., 10 μm to 100 μm), the interconnects of the redistribution layer 1112 may be implemented as wiring on a printed circuit board. Figure 10B The redistribution structure 1110 is shown to be a protruding trace substrate (PTS) having a structure in which the uppermost interconnection layer and the lowermost interconnection layer of the redistribution layer 1112 protrude upward and downward from the uppermost insulating layer and the lowermost insulating layer of the redistribution insulating layer 1111, but depending on the design, the redistribution structure 1110 may be an embedded trace substrate (ETS).

[0115] Redistribution layer 1112 may include a plurality of lower pads 1112P3 exposed through lower solder mask layer 1116. Multiple lower pads 1112P3 may be disposed on the lowest insulating layer among redistribution insulating layers 1111, and lower solder mask layer 1116 may be exposed downward through a plurality of upper and lower vias and electrically connected to a plurality of bumps 1160. Each of multiple lower pads 1112P3 may have a circular or polygonal upper and lower surface. As the diameter of each of multiple bumps 1160 increases, the width of each of multiple lower pads 1112P3 may also increase.

[0116] Upper solder mask layer 1115 and lower solder mask layer 1116 may be solder resist layers that protect redistribution layer 1112 from external physical and chemical damage. Upper solder mask layer 1115 and lower solder mask layer 1116 include insulating materials and may include, for example, prepreg, ABF, FR-4, BT, or photosensitive solder resist (PSR).

[0117] Each of electrical connection structure 1130 and bump 1160 may include, but is not limited to, a low-melting-point metal (melting point lower than that of pad 1121) such as lead (Pb), bismuth (Bi), tin (Sn), or a tin-containing (Sn) alloy (Sn-Ag-Cu). Each of electrical connection structure 1130 and bump 1160 may have a pad, ball, or pin shape and may be made of a single layer or multiple layers. For example, each of electrical connection structure 1130 and bump 1160 may be a solder ball. At a temperature above the melting point, each of electrical connection structure 1130 and bump 1160 may be placed in a fluid state through a reflow process or a thermal compression bonding (TCB) process. Thereafter, as the temperature decreases, each of electrical connection structure 1130 and bump 1160 may be connected to and secured to the pad of redistribution layer 1112.

[0118] As described above, in the semiconductor package and the method of manufacturing the semiconductor package according to example embodiments, defects (e.g., cracks, kinks, delamination, etc.) of the semiconductor chip caused by wafer separation can be effectively prevented, or the productivity (e.g., yield, cost, time, etc.) of the wafer separation can be effectively improved. For example, the semiconductor package and the method of manufacturing the semiconductor package can reduce the heat-affected zone caused by wafer separation, thereby improving the strength of the semiconductor chip and improving the productivity of the wafer separation process related to the heat-affected zone.

[0119] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device comprising: The semiconductor chip includes a substrate, an interconnection structure and a pad layer, wherein the interconnection structure is on the front surface of the substrate, and the pad layer is on the front surface of the interconnection structure. In which, when viewed from a cross-section, the first side surface of the semiconductor chip is tilted relative to or curved relative to the front surface of the semiconductor chip, and is tilted relative to or curved relative to the second side surface of the semiconductor chip, the first side surface of the semiconductor chip extends from a point on the side surface of the substrate to an edge of the front surface of the semiconductor chip, and the second side surface of the semiconductor chip extends from the point to the edge of the back surface of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein The side surface of the substrate has an angular shape at the point.

3. The semiconductor device according to claim 2, wherein The first side surface of the semiconductor chip is flat from the point to the edge of the front surface of the semiconductor chip, and The second side surface of the semiconductor chip has a flat shape from the point to an edge of the back surface of the semiconductor chip.

4. The semiconductor device according to claim 3, wherein The roughness of the first side surface of the semiconductor chip is rougher than the roughness of the second side surface of the semiconductor chip.

5. The semiconductor device according to claim 3, wherein In the horizontal direction of the semiconductor chip, a maximum width component of the first side surface of the semiconductor chip is greater than 3 μm and less than 100 μm, and In a vertical direction of the semiconductor chip, a maximum height component of the first side surface of the semiconductor chip is greater than 10 μm and less than 300 μm. The semiconductor device according to claim 1 , wherein: The maximum width component of the first side surface of the semiconductor chip in the horizontal direction of the semiconductor chip is greater than 0.1 times the maximum height component of the first side surface of the semiconductor chip in the vertical direction of the semiconductor chip and is less than 1 times the maximum height component of the first side surface of the semiconductor chip in the vertical direction of the semiconductor chip.

7. The semiconductor device according to claim 1 , further comprising: a plurality of memory chips on the front surface of the pad layer such that at least portions of the respective memory chips overlap each other in a vertical direction, Each of the plurality of memory chips includes a memory cell layer having memory cells, Among the plurality of memory chips, the memory chip closest to the pad layer further includes a bonding metal layer disposed between the memory cell layer and the semiconductor chip, and The front surface of the semiconductor device is a front surface of a memory chip farthest from a pad layer among the plurality of memory chips.

8. The semiconductor device according to claim 1, further comprising: Memory chip, on the front surface of the pad, Among them, the memory chip includes: a memory cell layer having memory cells; and bonding metal layer between the memory cell layer and the semiconductor chip, and The front surface of the semiconductor device is a front surface of a memory chip.

9. The semiconductor device according to claim 8, further comprising: Connection pads, on the memory chip, The memory cell layer includes a plate layer, a gate electrode and a vertical channel structure, the plate layer is electrically connected to the connection pad, the gate electrodes are stacked on the lower surface of the plate layer and are spaced apart from each other in a first direction perpendicular to the lower surface of the plate layer and are electrically connected to the bonding metal layer, and the vertical channel structure extends in the first direction while penetrating the gate electrode and is electrically connected to the bonding metal layer.

10. The semiconductor device according to claim 1, wherein The number of semiconductor chips is greater than one, and the semiconductor chips are connected to each other by direct bonding.

11. The semiconductor device according to any one of claims 1 to 10, wherein The interconnect structure includes interconnect lines and interconnect insulation layers. The pad layer includes a pad and a pad insulating layer, and Each of the interconnection insulating layer and the pad insulating layer includes at least one of SiO 2 , SiN, SiCN, and tetraethoxysilane.

12. The semiconductor device according to claim 11, wherein The first side surface of the semiconductor chip has a heat-affected zone, and Said point is the lowest point of the heat affected zone.

13. The semiconductor device according to claim 12, wherein In at least a portion of the heat-affected zone, at least one of SiO 2 , SiN, SiCN, and tetraethoxysilane is mixed with the metal material.

14. A semiconductor package, comprising: The semiconductor chip includes a substrate, an interconnection structure and a pad layer, wherein the interconnection structure is arranged on the front surface of the substrate, and the pad layer is arranged on the front surface of the interconnection structure. wherein, when viewed in cross section, the first side surface of the semiconductor chip has a heat-affected zone, the first side surface of the semiconductor chip extending from a point on the side surface of the substrate to an edge of the front surface of the semiconductor chip, Herein, the point is the bottom of the heat-affected zone.

15. The semiconductor package according to claim 14, wherein When viewed in cross section, the second side surface of the semiconductor chip is not a heat-affected zone, the second side surface of the semiconductor chip extends from the point to the edge of the back surface of the semiconductor chip, and The roughness of the first side surface of the semiconductor chip is rougher than the roughness of the second side surface of the semiconductor chip.

16. The semiconductor package according to claim 14, wherein In at least a portion of the heat-affected zone, the insulating material and the metallic material are mixed with each other.

17. The semiconductor package according to claim 14, wherein The width of the heat-affected zone increases from a point on the side surface of the substrate toward an edge of the front surface of the semiconductor chip, and The heat-affected zone extends continuously from the point to the edge of the front surface of the semiconductor chip.

18. The semiconductor package according to claim 14, further comprising: a plurality of memory chips disposed on the front surface of the pad layer such that at least portions of the memory chips overlap each other in a vertical direction, Each of the plurality of memory chips includes a memory cell layer having memory cells, Among the plurality of memory chips, the memory chip disposed closest to the pad layer further includes a bonding metal layer disposed between the memory cell layer and the semiconductor chip, and The front surface of the semiconductor package is a front surface of a memory chip farthest from a pad among the plurality of memory chips.

19. The semiconductor package according to claim 14, further comprising: a memory chip on the front surface of the pad; as well as Connection pads, on the memory chip, Among them, the memory chip includes: a memory cell layer having memory cells; and Bonding metal layer, between the memory cell layer and the semiconductor chip, wherein the front surface of the semiconductor package is the front surface of the memory chip, and The memory cell layer includes a plate layer, a gate electrode and a vertical channel structure, the plate layer is electrically connected to the connection pad, the gate electrodes are stacked on the lower surface of the plate layer and are spaced apart from each other in a first direction perpendicular to the lower surface of the plate layer and are electrically connected to the bonding metal layer, and the vertical channel structure extends in the first direction while penetrating the gate electrode and is electrically connected to the bonding metal layer.

20. The semiconductor package according to claim 14, wherein The number of semiconductor chips is greater than one and the semiconductor chips are connected to each other by direct bonding, and For each semiconductor chip, the first side surface is tilted relative to or curved more than the second side surface, the first side surface extends from a point on the side surface of the substrate of the semiconductor chip to an edge of the front surface of the semiconductor chip, and the second side surface extends from a point on the side surface of the substrate of the semiconductor chip to an edge of the back surface of the semiconductor chip.

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