3D capacitor structure and manufacturing method thereof
By adopting a 3D capacitor structure in the chiplet, using an etch stop layer to control the thickness and a dual-damascene process, the problem of limited capacitor capacitance is solved, and the capacitance is increased and the structural stability is achieved.
Patent Information
- Application Number
- CN202410467015.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-11
- Filing Date
- 2024-04-18
- Publication Date
- 2025-09-12
AI Technical Summary
In the prior art, a single capacitor in a chiplet cannot be made too high due to the limitation of being manufactured on a silicon substrate, resulting in a limited capacitance that cannot be increased.
A 3D capacitor structure is adopted. By stacking multiple sub-capacitor stack structures on the substrate and using an etch stop layer to control the thickness of each layer, multiple electrode contacts are formed to increase the capacitance, and a dual damascene process is combined to form conductor contacts.
The increase in capacitance is achieved while ensuring the stability and collapse resistance of the multilayer structure. The thickness of each layer is controlled by the etch stop layer to obtain the optimal stacking configuration.
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Figure CN120637366A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a capacitor structure, and in particular to a 3D (stereoscopic) capacitor structure and a manufacturing method thereof. Background Art
[0002] Due to the technological bottlenecks brought about by continued chip miniaturization, the industry has shifted from improving processes to increase the number of transistors per silicon wafer to improving overall performance through relatively cost-controlled complex system-on-chip designs. Among these, "chiplets" are receiving significant attention for achieving higher transistor density and performance at a relatively low cost.
[0003] Chiplet is a system-on-chip that is formed by splitting the many components that originally belonged to a single chip into multiple small units, strengthening their functions, redesigning and remanufacturing them, and using advanced packaging technology to form a system-on-chip.
[0004] However, the single capacitor in the chiplet is limited to being manufactured on a silicon substrate, and the capacitor cannot be made too high, so the capacitance is also limited and cannot be increased. Summary of the Invention
[0005] According to one embodiment of the present invention, a 3D capacitor structure includes a substrate, multiple sub-capacitor stacking structures, multiple first electrode contacts, and multiple second electrode contacts. The sub-capacitor stacking structure is arranged on the substrate, wherein each sub-capacitor stacking structure includes a dielectric stack, a lower electrode structure, and an upper electrode structure. The dielectric stack includes a stacked lower dielectric layer, a lower etch stop layer, a middle dielectric layer, an upper etch stop layer, and an upper dielectric layer. The lower electrode structure includes a lower electrode plate arranged in the lower dielectric layer and multiple lower electrode extensions extending from the lower electrode plate upward through the lower etch stop layer to the middle dielectric layer. The upper electrode structure includes an upper electrode plate arranged in the upper dielectric layer and multiple upper electrode extensions extending from the upper electrode plate downward through the upper etch stop layer and the middle dielectric layer to the lower etch stop layer. The multiple first electrode contacts are respectively connected to the lower electrode plates of two adjacent layers in the sub-capacitor stacking structure. The multiple second electrode contacts are respectively connected to the upper electrode plates of two adjacent layers in the sub-capacitor stacking structure.
[0006] According to another embodiment of the present invention, a method for manufacturing a 3D capacitor structure includes the steps of (a) forming a first lower electrode plate on a substrate; (b) forming a first dielectric stack on the first lower electrode plate, wherein the first dielectric stack includes a stacked lower dielectric layer, an etch stop layer, and an upper dielectric layer; (c) forming a plurality of first lower electrode extensions in the first dielectric stack, wherein the plurality of lower electrode extensions extend upward from the first lower electrode plate through the etch stop layer into the upper dielectric layer; and (d) forming a second dielectric stack, wherein the structure of the second dielectric stack is the same as that of the first dielectric stack. (e) forming a plurality of first upper electrode extensions in the second dielectric stack, wherein the plurality of first upper electrode extensions extend through the etch stop layer of the second dielectric stack to the etch stop layer of the first dielectric stack; (f) forming a first upper electrode plate in the upper dielectric layer of the second dielectric stack, wherein the first upper electrode plate is connected to the plurality of first upper electrode extensions; (g) forming a third dielectric stack, wherein the structure of the third dielectric stack is the same as that of the first dielectric stack; and (h) forming a first contact opening through the third dielectric stack, the second dielectric stack, and the first dielectric stack. The method further comprises the steps of: forming a first lower electrode plate through a dielectric layer of the third dielectric layer, wherein the lower electrode plate groove and the first contact opening constitute a first dual inlay opening; forming a conductive material in the first dual inlay opening to simultaneously form a first electrode contact and a second lower electrode plate; repeating steps (b) to (d) to form a fourth dielectric layer, a plurality of second lower electrode extensions, and a fifth dielectric layer; and forming a second contact opening through the fifth dielectric layer, the fourth dielectric layer, and the third dielectric layer until the dielectric layer is exposed. The first upper electrode plate; step (m) forming a plurality of extension openings through the fifth dielectric stack and the upper dielectric layer of the fourth dielectric stack until the etch stop layer of the fourth dielectric stack is exposed; step (n) forming an upper electrode plate groove in the upper dielectric layer of the fifth dielectric stack, the upper electrode plate groove, the plurality of extension openings and the second contact opening constituting a second dual inlaid opening; step (o) forming a conductive material in the second dual inlaid opening to simultaneously form a second electrode contact, a plurality of second upper electrode extensions and a second upper electrode plate; and step (p): repeating steps (g) to (o) at least once. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.
[0008] Figure 1 is a cross-sectional schematic diagram of a 3D capacitor structure according to a first embodiment of the present invention;
[0009] Figure 2 It is along Figure 1 A schematic cross-sectional view of a 3D capacitor structure of line I-I';
[0010] Figure 3 It is along Figure 1 A schematic cross-sectional view of another 3D capacitor structure of the I-I' line;
[0011] Figure 4 is a schematic cross-sectional view of a 3D capacitor structure according to a second embodiment of the present invention;
[0012] Figures 5A to 5S FIG. 4 is a schematic cross-sectional view of the manufacturing process of a 3D capacitor structure according to the third embodiment of the present invention.
[0013] Explanation of Figure Numbers
[0014] 10, 40, 50: 3D capacitor structure;
[0015] 100, 500: substrate;
[0016] 102. LD: lower dielectric layer;
[0017] 104: lower etching stop layer;
[0018] 106: middle dielectric layer;
[0019] 108: upper etching stop layer;
[0020] 110, UD: upper dielectric layer;
[0021] 112: lower electrode plate;
[0022] 114: lower electrode extension;
[0023] 116: upper electrode plate;
[0024] 118: upper electrode extension;
[0025] 120: etching stop layer;
[0026] 122, 534: insulation layer;
[0027] 124, 536: first metal layer;
[0028] 126, 538: second metal layer;
[0029] 502: first lower electrode plate;
[0030] 504, 508, 526: extension opening;
[0031] 506: first lower electrode extension;
[0032] 510: upper electrode plate groove;
[0033] 512: first upper electrode extension;
[0034] 514: first upper electrode plate;
[0035] 516: bottom electrode plate groove;
[0036] 518: second lower electrode plate;
[0037] 520: second lower electrode extension;
[0038] 522: mask layer;
[0039] 524: mask opening;
[0040] 528: upper electrode plate groove;
[0041] 530: second upper electrode extension;
[0042] 532: second upper electrode plate;
[0043] C1: first contact;
[0044] C2: second contact;
[0045] DS: dielectric stack;
[0046] DS1: first dielectric stack;
[0047] DS2: second dielectric stack;
[0048] DS3: third dielectric stack;
[0049] DS4: fourth dielectric stack;
[0050] DS5: fifth dielectric stack;
[0051] E1: first electrode contact;
[0052] E2: second electrode contact;
[0053] EO1: first contact opening;
[0054] EO2: second contact opening;
[0055] LE: lower electrode structure;
[0056] M1, M2: conductor material;
[0057] SC: subcapacitor stack structure;
[0058] SL: etch stop layer;
[0059] UE: upper electrode structure. DETAILED DESCRIPTION
[0060] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0061] Figure 1 is a cross-sectional view of a 3D capacitor structure 10 according to the first embodiment of the present invention. Figure 1 The 3D capacitor structure 10 of this embodiment includes a substrate 100, a plurality of sub-capacitor stack structures SC, a plurality of first electrode contacts E1, and a plurality of second electrode contacts E2. The sub-capacitor stack structure SC is disposed on the substrate 100, wherein each sub-capacitor stack structure SC includes a dielectric stack DS, a lower electrode structure LE, and an upper electrode structure UE. The dielectric stack DS includes a stacked lower dielectric layer 102, a lower etch stop layer 104, a middle dielectric layer 106, an upper etch stop layer 108, and an upper dielectric layer 110. In one embodiment, the lower dielectric layer 102, the middle dielectric layer 106, and the upper dielectric layer 110 include silicon oxide, and the lower etch stop layer 104 and the upper etch stop layer 108 include silicon nitride. However, the present invention is not limited to this. The lower electrode structure LE includes a lower electrode plate 112 disposed within the lower dielectric layer 102 and a plurality of lower electrode extensions 114 extending from the lower electrode plate 112 upward through the lower etch stop layer 104 into the middle dielectric layer 106. The upper electrode structure UE includes an upper electrode plate 116 disposed within the upper dielectric layer 110 and a plurality of upper electrode extensions 118 extending downward from the upper electrode plate 116 through the upper etch-stop layer 108 and the middle dielectric layer 106 to the lower etch-stop layer 104. In other words, the 3D capacitor structure 10 has three sub-capacitor stack structures SC. However, the present invention is not limited to this; in another embodiment, the number of sub-capacitor stack structures SC can be increased.
[0062] exist Figure 1 In the embodiment, the extension direction of the lower electrode extension portion 114 and the upper electrode extension portion 118 is perpendicular to the surface direction of the substrate 100. The surface direction of the lower electrode plate 112 and the upper electrode plate 116 is perpendicular to the extension direction of the first electrode contact E1 and the second electrode contact E2.
[0063] Please continue to refer to Figure 1, multiple first electrode contacts E1 are respectively connected to the lower electrode plates 112 of two adjacent layers in the sub-capacitor stack structure SC, wherein each first electrode contact E1 is directly in contact with the adjacent upper lower electrode plate 112 and the lower upper lower electrode plate 112. Multiple second electrode contacts E2 are respectively connected to the upper electrode plates 116 of two adjacent layers in the sub-capacitor stack structure SC, wherein each second electrode contact E2 is directly in contact with the adjacent upper upper electrode plate 116 and the lower upper electrode plate 116. Since the height of the first electrode contacts E1 and the second electrode contacts E2 connecting the upper and lower sub-capacitor stack structures SC is fixed at approximately one dielectric stack DS, no other connection structure is required to form a stacked 3D capacitor structure 10. In addition, the upper etch stop layer 108 and the lower etch stop layer 104 in the dielectric stack DS are conducive to controlling the thickness of each layer. For example, the size (such as the height) of the upper electrode extension 118 can be controlled by the lower etch stop layer 104, so that the optimal stack can be obtained. Furthermore, another etch stop layer 120 may be added between the upper and lower sub-capacitor stack structures SC to serve as a stop layer during the formation of the lower electrode plate 112 .
[0064] In order to connect the circuits of the 3D capacitor structure 10 to the outside or other components, an interconnection structure may be formed on the substrate 100. For example, the interconnection structure has an insulating layer 122 covering the entire 3D capacitor structure 10, a first contact C1 connected to a lower electrode plate 112, a second contact C2 connected to an upper electrode plate 116, a first metal layer 124 located on the insulating layer 122 and connected to the first contact C1, and a second metal layer 126 located on the insulating layer 122 and connected to the second contact C2. However, the present invention is not limited to this. In another embodiment, the interconnection structure may include multiple first contacts C1 and multiple second contacts C2, and their arrangement positions may vary as needed.
[0065] Figure 2 It is along Figure 1 FIG. 1 is a schematic cross-sectional view of a 3D capacitor structure 10 along line II′. Figure 1 Shown is a cross section in the xz plane. Figure 2 is the cross section of the yz plane, so Figure 2 Only the dielectric stack DS, upper electrode plate 116, lower electrode plate 112, and lower electrode extension 114 of the subcapacitor stack structure SC are shown, while the dotted line portion indicates the location of the upper electrode extension 118. Therefore, in the first embodiment, the lower electrode extension 114 and the upper electrode extension 118 may be strip-shaped structures staggered along the x-direction. However, the present invention is not limited to this.
[0066] Figure 3 It is along Figure 1 FIG. 1 is a schematic cross-sectional view of another 3D capacitor structure 10 along line II′. Figure 3The cross section of the yz plane also shows that the lower electrode extension 114 and the upper electrode extension 118 are columnar structures staggered along the x-direction and the y-direction. Figure 3 The area ratio between the lower electrode extension 114 and the upper electrode extension 118 is Figure 2 The structure is large, so when other structures are the same, Figure 3 Should be compared Figure 2 Has greater capacitance.
[0067] Figure 4 This is a cross-sectional schematic diagram of a 3D capacitor structure 40 according to the second embodiment of the present invention, in which the same figure marks as the first embodiment are used to represent the same or similar parts and components, and the relevant contents of the same or similar parts and components can also refer to the contents of the first embodiment and will not be repeated.
[0068] Please refer to Figure 4 , the 3D capacitor structure 40 of the second embodiment is basically the same as the 3D capacitor structure 10 of the first embodiment, the difference is that the 3D capacitor structure 40 has a total of 8 sub-capacitor stacking structures SC. In order to ensure that the structure of the first contact C1 is stable and does not collapse, the 8 sub-capacitor stacking structures SC can be divided into two groups, and a first contact C1 is provided for every 4 lower electrode plates 112, and connected to the first metal layer 124 by connecting multiple first contact members C1 in series. As for the second electrode contact E2 and the second contact member C2 between the upper electrode plates 116, because of their smaller (lower) size, the original design can be maintained. However, the present invention is not limited to this; in another embodiment, the connection design between the upper electrode plates 116 can be swapped with the connection design between the lower electrode plates 112.
[0069] Figures 5A to 5S This is a cross-sectional diagram of a manufacturing process of a 3D capacitor structure according to the third embodiment of the present invention. Figure 5A The manufacturing method of this embodiment can first form a first lower electrode plate 502 on a substrate 500 by electroplating or other methods (step (a)), and then form a first dielectric stack DS1 on the first lower electrode plate 502 (step (b)). The first dielectric stack DS1 includes a stacked lower dielectric layer LD, an etch stop layer SL, and an upper dielectric layer UD. Then, a photolithography etching process can be used to form a plurality of extension openings 504 in the first dielectric stack DS1. Since there is an etching selectivity ratio between the etch stop layer SL and the upper dielectric layer UD and the lower dielectric layer LD in the first dielectric stack DS1, the aforementioned etching process to form the extension openings 504 will use different etching gases to etch different materials.
[0070] Afterwards, please refer to Figure 5BThen, a conductive material M1 is filled into the extension opening 504 by electroplating or other methods to form a plurality of first lower electrode extensions 506 in the first dielectric stack DS1 (step (c)). The first lower electrode extensions 506 extend upward from the first lower electrode plate 502 through the etch-stop layer SL into the upper dielectric layer UD. In one embodiment, the plurality of first lower electrode extensions 506 extend perpendicular to the plane of the substrate 500.
[0071] Next, please refer to Figure 5C , a planarization process such as chemical mechanical polishing (CMP) can be first performed to leave the first lower electrode extension 506, and then a second dielectric stack DS2 can be formed (step (d)). The structure of the second dielectric stack DS2 is the same as that of the first dielectric stack DS1. However, the thickness and material of each layer of the second dielectric stack DS2 can be adjusted as needed and are not limited to being exactly the same as the first dielectric stack DS1.
[0072] Then, please refer to Figure 5D A plurality of extension openings 508 may be formed in the second dielectric stack DS2 by using a photolithography and etching process until the etch stop layer SL of the first dielectric stack DS1 is exposed, serving as a predetermined formation location for the upper electrode extension.
[0073] Next, please refer to Figure 5E Another photolithography and etching process can be used to form an upper electrode plate trench 510 in the upper dielectric layer UD of the second dielectric stack DS2. The upper electrode plate trench 510 and the extension opening 508 form a dual damascene opening.
[0074] Then, please refer to Figure 5FConductive material M2 is then filled into the upper electrode plate grooves 510 and the extension openings 508 by electroplating or other methods to form a plurality of first upper electrode extensions 512 in the second dielectric stack DS2 (step (e)). A first upper electrode plate 514 is then formed in the upper dielectric layer UD of the second dielectric stack DS2 (step (f)). Because this embodiment utilizes a dual damascene process, the first upper electrode plate 514 and the plurality of first upper electrode extensions 512, which are connected, can be formed simultaneously. However, the present invention is not limited thereto. In another embodiment, the plurality of first upper electrode extensions 512 can be formed first and then the first upper electrode plate 514 can be formed. The first upper electrode extensions 512 extend through the etch-stop layer SL of the second dielectric stack DS2 onto the etch-stop layer SL of the first dielectric stack DS1. In other words, the dimensions (e.g., height) of the first upper electrode extensions 512 can be precisely controlled by the etch-stop layer SL. In one embodiment, the extension direction of the plurality of first upper electrode extensions 512 is perpendicular to the surface direction of the substrate 500. In one embodiment, the plurality of first lower electrode extensions 506 and the plurality of first upper electrode extensions 512 are strip-shaped structures staggered along the x-direction (similar to Figure 2 In another embodiment, the plurality of first lower electrode extensions 506 and the plurality of first upper electrode extensions 512 are columnar structures staggered along the x-direction and the y-direction (similar to Figure 3 structure).
[0075] Next, please refer to Figure 5G , a planarization process such as CMP can be first performed to leave the first upper electrode extension 512 and the first upper electrode plate 514, and then a third dielectric stack DS3 is formed (step (g)). The structure of the third dielectric stack DS3 is the same as that of the first dielectric stack DS1. However, the thickness and material of each layer of the third dielectric stack DS3 can be adjusted as needed, and are not limited to being exactly the same as the first dielectric stack DS1.
[0076] Then, please refer to Figure 5H A photolithography and etching process may be used to form a first contact opening EO1 through the third dielectric stack DS3, the second dielectric stack DS2, and the first dielectric stack DS1 until the first bottom electrode plate 502 is exposed (step (h)).
[0077] Next, please refer to Figure 5I A lower electrode plate trench 516 is formed in the upper dielectric layer UD of the third dielectric stack DS3. The lower electrode plate trench 516 and the first contact opening EO1 form a first dual damascene opening (step (i)). Furthermore, in this embodiment, the etch-stop layer SL of the third dielectric stack DS3 can be used as a stop layer during the step of forming the lower electrode plate trench 516.
[0078] Then, please refer to Figure 5J Electroplating can be used to form a conductive material within the bottom electrode plate groove 516 and the first contact opening EO1 (first dual damascene opening) to simultaneously form the first electrode contact E1 and the second bottom electrode plate 518 (step (j)). In one example, the extension direction of the first electrode contact E1 is perpendicular to the plane direction of the first bottom electrode plate 502.
[0079] Next, please refer to Figure 5K By repeating the steps of forming the first dielectric stack DS1 until forming the second dielectric stack DS2, a fourth dielectric stack DS4, a plurality of second lower electrode extensions 520 and a fifth dielectric stack DS5 can be formed (step (k)).
[0080] Then, please refer to Figure 5L A second contact opening EO2 is formed through the fifth dielectric stack DS5, the fourth dielectric stack DS4 and the third dielectric stack DS3 until the first upper electrode plate 514 is exposed (step (1)).
[0081] Then, please refer to Figure 5M A mask layer 522 may be formed on the fifth dielectric stack DS5 to fill the second contact opening EO2. The mask layer 522 may be made of, for example, SOC or photoresist. A photolithography process may then be used to form a plurality of mask openings 524 in the mask layer 522, serving as locations for forming top electrode extensions.
[0082] Next, please refer to Figure 5N ,by Figure 5M The mask layer 522 is used as an etching mask to etch away the fifth dielectric stack DS5 exposed from the mask opening 524 until the etching stop layer SL of the fourth dielectric stack DS4 is exposed, thereby forming a plurality of extension openings 526 (step (m)). Figure 5M The mask layer 522 is formed.
[0083] Then, please refer to Figure 5O A photolithography and etching process can be used to form an upper electrode plate trench 528 in the upper dielectric layer UD of the fifth dielectric stack DS5 (step (n)). The upper electrode plate trench 528, the plurality of extension openings 526, and the second contact opening EO2 constitute a second dual damascene opening.
[0084] Next, please refer to Figure 5P Conductive material may be formed in the upper electrode plate groove 528, the extension opening 526, and the second contact opening EO2 (second dual damascene opening) by electroplating to simultaneously form the second electrode contact E2, a plurality of second upper electrode extensions 530, and the second upper electrode plate 532 (step (o)). In one embodiment, the extension direction of the second electrode contact E2 is perpendicular to the plane direction of the first upper electrode plate 514.
[0085] Refer again Figure 5Q ,repeat Figure 5G Steps to Figure 5P The step of at least once (step (p)) is repeated to form the 3D capacitor structure 50. The present invention is not limited thereto, and the number of times the aforementioned steps are repeated can be increased as needed to form a 3D capacitor structure with a larger number of stacked structures.
[0086] Next, please refer to Figure 5R To connect the circuits of the 3D capacitor structure 50 to external components or other devices, an interconnect structure may be formed on the substrate 500. For example, a space reserved for contacts is first defined next to the 3D capacitor structure 50, and then an insulating layer 534 is formed to fully cover the entire 3D capacitor structure 50.
[0087] Then, please refer to Figure 5S First, a first contact C1 connected to a first lower electrode plate 502 and a second contact C2 connected to a second upper electrode plate 532 are formed in the insulating layer 534. Then, a first metal layer 536 connected to the first contact C1 and a second metal layer 538 connected to the second contact C2 are formed on the insulating layer 534. However, the present invention is not limited to this. In another embodiment, the interconnect structure may include multiple first contacts C1 and multiple second contacts C2, and their placement can be varied as needed.
[0088] In summary, the present invention stacks multiple subcapacitor stacks, directly connecting them with electrode contacts, to create a compact, overlapping 3D capacitor structure, increasing capacitance while preventing collapse of the multilayer structure. Furthermore, the inclusion of an etch-stop layer within the subcapacitor stack allows for control over the thickness of each layer, resulting in an optimal stack and, in other words, a desired upper limit configuration.
[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A 3D capacitor structure, characterized in that: include: substrate; A plurality of sub-capacitor stack structures are disposed on the substrate, wherein each of the sub-capacitor stack structures comprises: a dielectric stack comprising a stacked lower dielectric layer, a lower etch stop layer, a middle dielectric layer, an upper etch stop layer, and an upper dielectric layer; a lower electrode structure comprising a lower electrode plate disposed in the lower dielectric layer and a plurality of lower electrode extensions extending upward from the lower electrode plate through the lower etch stop layer into the middle dielectric layer; and an upper electrode structure comprising an upper electrode plate disposed in the upper dielectric layer and a plurality of upper electrode extensions extending downward from the upper electrode plate through the upper etch stop layer and the middle dielectric layer to the lower etch stop layer; a plurality of first electrode contacts, respectively connected to the lower electrode plates of two adjacent layers in the plurality of sub-capacitor stack structures; and A plurality of second electrode contacts are respectively connected to the upper electrode plates of two adjacent layers in the plurality of sub-capacitor stack structures.
2. The 3D capacitor structure according to claim 1, wherein: The extension directions of the plurality of lower electrode extensions and the plurality of upper electrode extensions are perpendicular to the surface direction of the substrate.
3. The 3D capacitor structure according to claim 1, wherein: The surface directions of the lower electrode plate and the upper electrode plate are perpendicular to the extending directions of the plurality of first electrode contacts and the plurality of second electrode contacts.
4. The 3D capacitor structure according to claim 1, wherein: The plurality of lower electrode extensions and the plurality of upper electrode extensions are strip structures staggered along the x-direction.
5. The 3D capacitor structure according to claim 1, wherein: The plurality of lower electrode extensions and the plurality of upper electrode extensions are columnar structures staggered along the x-direction and the y-direction.
6. The 3D capacitor structure according to claim 1, wherein: The lower dielectric layer, the middle dielectric layer, and the upper dielectric layer include silicon oxide, and the lower etch stop layer and the upper etch stop layer include silicon nitride.
7. A method for manufacturing a 3D capacitor structure, characterized in that: include: a) forming a first lower electrode plate on a substrate; b) forming a first dielectric stack on the first lower electrode plate, the first dielectric stack comprising a stacked lower dielectric layer, an etch stop layer, and an upper dielectric layer; c) forming a plurality of first lower electrode extensions in the first dielectric stack, wherein the plurality of first lower electrode extensions extend from the first lower electrode plate upward through the etch stop layer into the upper dielectric layer; d) forming a second dielectric stack, the second dielectric stack having the same structure as the first dielectric stack; e) forming a plurality of first upper electrode extensions in the second dielectric stack, wherein the plurality of first upper electrode extensions extend through the etch stop layer of the second dielectric stack and onto the etch stop layer of the first dielectric stack; f) forming a first upper electrode plate in the upper dielectric layer of the second dielectric stack, the first upper electrode plate being connected to the plurality of first upper electrode extensions; g) forming a third dielectric stack, the structure of the third dielectric stack being the same as that of the first dielectric stack; h) forming a first contact opening through the third dielectric stack, the second dielectric stack, and the first dielectric stack until the first bottom electrode plate is exposed; i) forming a lower electrode plate trench in the upper dielectric layer of the third dielectric stack, wherein the lower electrode plate trench and the first contact opening constitute a first dual damascene opening; j) forming a conductive material in the first dual damascene opening to simultaneously form a first electrode contact and a second bottom electrode plate; k) repeating steps b to d to form a fourth dielectric stack, a plurality of second bottom electrode extensions, and a fifth dielectric stack; 1) forming a second contact opening through the fifth dielectric stack, the fourth dielectric stack, and the third dielectric stack until the first top electrode plate is exposed; m) forming a plurality of extension openings through the fifth dielectric stack and the upper dielectric layer of the fourth dielectric stack until the etch stop layer of the fourth dielectric stack is exposed; n) forming an upper electrode plate trench in the upper dielectric layer of the fifth dielectric stack, wherein the upper electrode plate trench, the plurality of extension openings, and the second contact opening constitute a second dual damascene opening; o) forming a conductive material in the second dual damascene opening to simultaneously form a second electrode contact, a plurality of second upper electrode extensions, and a second upper electrode plate; as well as p) Repeat steps g to o at least once.
8. The method for manufacturing a 3D capacitor structure according to claim 7, wherein: The extension directions of the plurality of first lower electrode extensions and the plurality of first upper electrode extensions are perpendicular to the surface direction of the substrate.
9. The method for manufacturing a 3D capacitor structure according to claim 7, wherein: The surface directions of the first lower electrode plate and the first upper electrode plate are perpendicular to the extending directions of the first electrode contact and the second electrode contact.
10. The method for manufacturing a 3D capacitor structure according to claim 7, wherein: The plurality of first lower electrode extensions and the plurality of first upper electrode extensions are strip structures staggered along the x-direction.
11. The method for manufacturing a 3D capacitor structure according to claim 7, wherein: The plurality of first lower electrode extensions and the plurality of first upper electrode extensions are columnar structures staggered along the x-direction and the y-direction.
12. The method for manufacturing a 3D capacitor structure according to claim 7, wherein: In the step of forming the lower electrode plate trench, the etch stop layer of the third dielectric stack is used as a stop layer.