A noise reduction circuit, a power supply circuit, a readout circuit, and a detection circuit

Abstract

The application discloses a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit, and relates to the field of MEMS interface circuits, which is used to reduce the low-frequency noise of a MEMS sensor interface circuit. The power supply circuit comprises a charge pump circuit and a noise reduction circuit, and the noise reduction circuit comprises a reference noise suppression circuit and a charge pump noise suppression circuit. The input end of the reference noise suppression circuit is used for connecting a clock signal, a power supply, a reference voltage and a feedback voltage, the output end is connected to the ground through a capacitor C1, and the output end outputs a second voltage. The power supply voltage of the charge pump noise suppression circuit is used for connecting a first voltage to be reduced, the input end is connected to the second voltage, and the output end respectively outputs a third voltage and the feedback voltage. The application reduces the low-frequency noise transmitted by the high-voltage feedback driving circuit and the charge pump circuit in the MEMS sensor interface circuit, and improves the measurement accuracy of the MEMS sensor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of MEMS interface circuit, in particular to a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit. BACKGROUND

[0002] The combination of the capacitive micro-sensing structure based on MEMS technology and the sensing interface integrated circuit based on CMOS technology realizes the miniaturized design of sensors such as accelerometers, gyroscopes and detectors. In addition, the application of the closed-loop scheme on the sensor greatly improves the linearity of the sensor, but also introduces new noise to the sensor due to the influence of the high-voltage power supply noise on the high-voltage feedback driving circuit.

[0003] Reference Figure 1 In the traditional sensing and detection scheme, in order to improve the range of sensors such as accelerometers, a high-voltage feedback driving circuit (the output voltage is usually as high as tens of volts or even hundreds of volts) is introduced in the closed-loop circuit to offset the large displacement of the movable mass (MASS) caused by the sharp change of acceleration. Since the high-voltage power supply usually uses a charge pump circuit to generate, its output noise is transmitted to the MEMS sensor driving electrodes DT and DB through the circuit line, thereby affecting the measurement accuracy of sensors such as accelerometers, gyroscopes and detectors, especially the detection ability of weak signals. For the sensor, since its output signal is mainly concentrated in the low frequency band and the signal amplitude is very small, it is easily affected by the low-frequency noise (1 / f noise) caused by the CMOS process.

[0004] For 1 / f noise, the main sources in the sensor interface circuit are divided into two parts. One part is the 1 / f noise of each reference voltage VREF in the chip, which will be applied to the signal link when the reference voltage is applied to the signal link. When the amplitude of the weak signal to be detected is in the order of tens of uV, it is easy to be overwhelmed by the inherent low-frequency noise, making it difficult for the detection circuit to distinguish between signal and noise. The second part is the noise of the high-voltage feedback driving power supply. Under normal circumstances, the high-voltage feedback driving power supply (>10V) of the MEMS sensor interface circuit is generated by the power supply (5V or lower) of the chip through the charge pump circuit. Its low-frequency noise is directly applied to the sensitive detection circuit of the MEMS sensor through the high-voltage electrostatic force, so that the sensitive detection circuit of the MEMS sensor appears irregular weak vibration under the influence of the noise, thereby deteriorating the measurement accuracy of the sensor. SUMMARY

[0005] The purpose of the present application is to provide a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit to reduce the low-frequency noise of the MEMS sensor interface circuit.

[0006] The technical scheme adopted by the present application is as follows:

[0007] A noise reduction circuit comprises a reference noise suppression circuit and a charge pump noise suppression circuit;

[0008] The input end of the reference noise suppression circuit is used for connecting a clock signal, a power supply, a reference voltage and a feedback voltage, the output end is grounded through a capacitor C1, and the output end outputs a second voltage;

[0009] The power supply voltage of the charge pump noise suppression circuit is used for connecting a first voltage to be reduced in noise, the input end is connected to the second voltage, and the output end respectively outputs a third voltage and the feedback voltage.

[0010] Further, the reference noise suppression circuit comprises a first chopper circuit, an operational amplifier circuit, a second chopper circuit and a double-ended to single-ended operational amplifier circuit; the input end of the first chopper circuit is used for connecting the clock signal, the reference voltage and the feedback voltage, and the output end is connected to the input end of the operational amplifier circuit; the input end of the second chopper circuit is connected to the output end of the operational amplifier circuit and the clock signal respectively, and the output end is connected to the double-ended to single-ended operational amplifier circuit; the output end of the double-ended to single-ended operational amplifier circuit outputs the second voltage.

[0011] Further, the structures of the first chopper circuit and the second chopper circuit are as follows:

[0012] The first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are included; the source of the first PMOS tube and the source of the second PMOS tube are both connected to a positive input end; the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to a negative input end; the gate of the first PMOS tube and the gate of the fourth PMOS tube are both connected to the clock signal; the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to the clock signal after being inverted; the drain of the first PMOS tube and the drain of the third PMOS tube are both connected to a positive output end; and the drain of the second PMOS tube and the drain of the fourth PMOS tube are both connected to a negative output end.

[0013] Further, the double-ended to single-ended operational amplifier circuit comprises a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a first NPN-type triode, a second NPN-type triode, a first fixed-value resistor and a second fixed-value resistor;

[0014] The source of the fifth PMOS tube is connected to the positive output end of the second chopper circuit, and the drain is respectively connected to the drain of the first NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube;

[0015] The source of the sixth PMOS tube is connected to the negative output end of the second chopper circuit, and the drain is connected to the drain of the second NMOS tube; the drain of the sixth PMOS tube outputs the second voltage;

[0016] The substrate of the fifth PMOS tube is connected to the substrate of the sixth PMOS tube.

[0017] The source of the first NMOS tube is connected to the collector of the first NPN transistor.

[0018] The source of the second NMOS tube is connected to the collector of the second NPN transistor.

[0019] The emitter of the first NPN transistor is grounded through the first fixed resistor, the emitter of the second NPN transistor is grounded through the second fixed resistor, and the base of the first NPN transistor is connected to the base of the second NPN transistor.

[0020] Further, the charge pump noise suppression circuit includes a third NMOS tube, a seventh PMOS tube, a third fixed resistor, a fourth fixed resistor, and a first variable resistor.

[0021] The gate of the third NMOS tube is connected to the second voltage, the source is grounded, and the drain is connected to the gate of the seventh PMOS tube and the third fixed resistor, respectively.

[0022] The source of the seventh PMOS tube is connected to the third fixed resistor and connected to the first voltage; the drain of the seventh PMOS tube is grounded after being connected to the fourth fixed resistor and the first variable resistor in sequence; the drain of the seventh PMOS tube outputs the third voltage.

[0023] The feedback voltage is derived between the fourth fixed resistor and the first variable resistor.

[0024] In another aspect, the present application also provides a power supply circuit, which includes a charge pump circuit and the above-mentioned noise reduction circuit.

[0025] The input end of the charge pump circuit is connected to the power supply, the output end is grounded through the capacitor C2, and the output end outputs the first voltage.

[0026] In another aspect, the present application also provides a readout circuit, which includes the above-mentioned power supply circuit,

[0027] In another aspect, the present application also provides a detection circuit, which includes a capacitive MEMS sensor and the above-mentioned readout circuit, and the readout circuit is connected to the capacitive MEMS sensor.

[0028] In conclusion, the application has the following advantages:

[0029] The low-frequency noise transmitted by the high-voltage feedback driving circuit and the charge pump circuit in the MEMS sensor interface circuit is reduced respectively, the influence of the low-frequency noise on the weak signal detected by the MEMS sensor is reduced, and the measurement accuracy of the MEMS sensor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] The application will be described by way of example and with reference to the drawings, in which:

[0031] Figure 1 is a structure diagram of a detection circuit using a MEMS sensor.

[0032] Figure 2 is a structure diagram of a power supply circuit provided by the embodiment of the application.

[0033] Figure 3 is a structure diagram of a reference noise suppression circuit in the embodiment of the application.

[0034] Figure 4 is a structure diagram of a first chopper circuit in the embodiment of the application.

[0035] Figure 5 is a structure diagram of a double-ended to single-ended operational amplifier circuit in the embodiment of the application.

[0036] Figure 6 is a structure diagram of a charge pump noise suppression circuit in the embodiment of the application.

[0037] Figure 7 is a structure diagram of a noise reduction circuit provided by the embodiment of the application. DETAILED DESCRIPTION

[0038] All features disclosed in this specification, and / or all steps of any methods disclosed in this specification, can be combined in any combination, except combinations where at least some of the features and / or steps are mutually exclusive.

[0039] Any feature disclosed in this specification, unless stated otherwise, can be replaced by any equivalent or similar feature. That is, unless stated otherwise, each feature is one example only of a generic series of equivalent or similar features.

[0040] In the scene of designing MEMS sensors (such as accelerometers, gyroscopes, detectors, etc.) by combining MEMS technology and CMOS technology to miniaturize the detection circuit, the interface circuit will introduce low-frequency noise by high-voltage feedback driving power supply and reference voltage VREF, which will deteriorate the measurement accuracy of the MEMS sensor. Embodiments of the present application provide a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit, which are designed to reduce the low-frequency noise introduced by the reference voltage VREF and the high-voltage feedback driving power supply respectively. The low-dropout linear voltage regulation technology is used to reduce the influence of the low-frequency noise of the reference voltage VREF on the final power supply voltage. At the same time, the chopping technology is used to modulate the low-frequency (1 / F) noise in the reference voltage VREF to high frequency, and the high-frequency noise is filtered out by filtering technology, so as to filter out the low-frequency noise in the reference voltage VREF and reduce the influence of the low-frequency noise of the reference voltage VREF on the final power supply voltage, thereby improving the measurement accuracy of the MEMS sensor.

[0041] Embodiments of the present application provide a noise reduction circuit applied to a power supply circuit of a MEMS sensor readout circuit, which is used to reduce the low-frequency noise in the reference voltage VREF and the high-voltage feedback driving power supply respectively.

[0042] Referring to FIG. 1, the noise reduction circuit is applied to a power supply circuit of a MEMS sensor readout circuit. Figure 2 It is assumed that the high-voltage feedback driving power supply is generated by a charge pump circuit CP boosting the power supply AVDD of the chip. The charge pump circuit CP is designed based on Dickson charge pump, which boosts the 5V power supply AVDD to more than 10V. Due to the influence of the clock, the boosted high-voltage feedback driving power supply usually has large ripple and noise. In the embodiments of the present application, the first voltage PUMP_OUT represents the high-voltage feedback driving power supply to be reduced, and the noise and ripple of the first voltage PUMP_OUT need to be effectively suppressed to meet the detection requirements of high accuracy.

[0043] The noise reduction circuit comprises a reference noise suppression circuit NSC1 and a charge pump noise suppression circuit NSC2, the reference noise suppression circuit NSC1 is used for reducing noise of a reference voltage VREF, and the charge pump noise suppression circuit NSC2 is used for reducing noise of a first voltage PUMP_OUT. The input end of the reference noise suppression circuit NSC1 is used for connecting a clock signal CLK, a power supply AVDD, the reference voltage VREF and a feedback voltage VFB, the output end of the reference noise suppression circuit NSC1 is grounded through a capacitor C1, and the output end outputs a second voltage V01. The power supply voltage of the charge pump noise suppression circuit NSC2 is used for connecting the first voltage PUMP_OUT to be reduced in noise, the input end of the charge pump noise suppression circuit NSC2 is connected to the second voltage V01, and the output end of the charge pump noise suppression circuit NSC2 respectively outputs a third voltage HVOUT and the feedback voltage VFB, and the third voltage HVOUT is a power supply voltage finally output to a high-voltage feedback driving circuit.

[0044] As shown in Figure 3 As an optional embodiment, the reference noise suppression circuit NSC1 comprises a first chopper circuit CHOPPER1, an operational amplifier circuit AMP, a second chopper circuit CHOPPER2 and a differential-to-single-ended operational amplifier circuit D2S. The input end of the first chopper circuit CHOPPER1 is used for connecting the clock signal CLK, the reference voltage VREF and the feedback voltage VFB, the reference voltage VREF is used as a non-inverted input, the feedback voltage VFB is used as an inverted input, and the clock signal CLK is used as a working clock. The output end of the first chopper circuit CHOPPER1 is connected to the input end of the operational amplifier circuit AMP. The input end of the first chopper circuit CHOPPER1 comprises a positive output end and a negative output end, the operational amplifier circuit AMP is a differential amplifier circuit, the positive output end of the first chopper circuit CHOPPER1 is connected to the non-inverted input end of the operational amplifier circuit AMP, and the negative output end is connected to the inverted input end of the operational amplifier circuit AMP. The input end of the second chopper circuit CHOPPER2 is connected to the output end of the operational amplifier circuit AMP and the clock signal CLK. The clock signal CLK is used as a working clock. The input end of the second chopper circuit CHOPPER2 comprises a positive input end and a negative input end, wherein the positive input end is connected to the inverted output end of the operational amplifier circuit AMP, and the negative input end is connected to the non-inverted output end of the operational amplifier circuit AMP. The output end of the second chopper circuit CHOPPER2 is connected to the differential-to-single-ended operational amplifier circuit D2S. The output end of the second chopper circuit CHOPPER2 comprises a positive output end and a negative output end, wherein the positive output end is connected to the non-inverted input end of the differential-to-single-ended operational amplifier circuit D2S, and the negative output end is connected to the inverted input end of the differential-to-single-ended operational amplifier circuit D2S. The output end of the differential-to-single-ended operational amplifier circuit D2S outputs the second voltage V01. That is, the output end of the differential-to-single-ended operational amplifier circuit D2S is connected to the capacitor C1.

[0045] The aforementioned reference noise suppression circuit NSC1 modulates the reference voltage VREF to a high frequency using the clock signal CLK through the first chopper circuit CHOPPER1. The low-frequency noise contained in the reference voltage VREF is also modulated to a high frequency. The operational amplifier circuit AMP amplifies the modulated noise, offset components, and effective signal simultaneously. The second chopper circuit CHOPPER2 demodulates and restores the amplified modulated signal, but the noise and offset components contained in the modulated signal are modulated to the chopper frequency and filtered out.

[0046] The two chopper circuits mentioned above (the first chopper circuit CHOPPER1 and the second chopper circuit CHOPPER2) have the same structure. For ease of explanation, the structure of the first chopper circuit CHOPPER1 will be used as an example here.

[0047] In some alternative implementations, such as Figure 4 As shown, the structure of the first chopper circuit CHOPPER1 is designed as follows: the first chopper circuit CHOPPER1 includes PMOS transistor MP1 (i.e., the first PMOS transistor), PMOS transistor MP2 (i.e., the second PMOS transistor), PMOS transistor MP3 (i.e., the third PMOS transistor) and PMOS transistor MP4 (i.e., the fourth PMOS transistor).

[0048] The sources of MP1 and MP2 are both connected to the first positive input terminal VIP1. For example, the sources of MP1 and MP2 are connected together and then connected to the first positive input terminal VIP1. The sources of MP3 and MP4 are both connected to the first negative input terminal VIN1. The gates of MP1 and MP4 are both connected to the CKP signal, which is equivalent to the clock signal CLK. The gates of MP2 and MP3 are both connected to the CKN signal, which is the inverted version of the clock signal CLK. The drains of MP1 and MP3 are both connected to the first positive output terminal VOP1. The drains of MP2 and MP4 are both connected to the first negative output terminal VON1.

[0049] The structure of the second chopper circuit CHOPPER2 is the same as that of the first chopper circuit CHOPPER1, namely, it includes PMOS transistors MP5, MP6, MP7, and MP8. The connection relationship between these four MOS transistors corresponds to the connection relationship between MP1, MP2, MP3, and MP4. To distinguish it from the other chopper circuits, the two input terminals of the second chopper circuit CHOPPER2 are referred to as the second positive input terminal and the second negative input terminal, and its two output terminals are referred to as the second positive output terminal VOP2 and the second negative output terminal VON2.

[0050] The operational amplifier circuit differentially amplifies the input signal. The operational amplifier circuit can be a packaged device available on the market or can be constructed according to the principle of differential amplification.

[0051] In some alternative embodiments, as shown in FIG. 2, the double-to-single-ended operational amplifier circuit D2S includes a PMOS transistor MP9 (i.e., a fifth PMOS transistor), a PMOS transistor MP10 (i.e., a sixth PMOS transistor), an NMOS transistor MN1 (i.e., a first NMOS transistor), an NMOS transistor MN2 (i.e., a second NMOS transistor), a first NPN transistor NPN1, a second NPN transistor NPN2, a resistor R1, and a resistor R2. Figure 5

[0052] The source of the MP9 is connected to the positive output VOP2 of the second chopping circuit CHOPPER2, and the drain of the MP9 is connected to the drain of the MN1, the gate of the MN1, and the gate of the MN2. The source of the MP10 is connected to the negative output VON2 of the second chopping circuit CHOPPER2, and the drain of the MP10 is connected to the drain of the MN2. The drain of the MP10 outputs the second voltage V01. The substrate of the MP9 is connected to the substrate of the MP10, and the first bias voltage VB1 is inputted. The gate of the MP9 and the gate of the MP10 are inputted with the second bias voltage VB2. The source of the MN1 is connected to the collector of the NPN1. The source of the MN2 is connected to the collector of the NPN2. The MN1 and the MN2 form a current mirror, which realizes the function of converting double-ended input into single-ended output. The emitter of the NPN1 is grounded through the resistor R1. The emitter of the NPN2 is grounded through the resistor R2. The resistors R1 and R2 can effectively suppress the influence of ground noise on the second voltage V01 while improving linearity. The base of the NPN1 and the base of the NPN2 are connected, and the second bias voltage VB3 is inputted. The use of NPN transistors as the current source bias circuit can effectively improve the matching performance of the circuit and further reduce the probability of circuit mismatch, compared with the design using MOS transistors.

[0053] Taking a sine wave signal as an example, signal modulation in the time domain is the multiplication of a signal wave and a carrier wave; signal demodulation is the multiplication of the modulated signal and the carrier wave again. Let the signal wave be , the carrier wave be , t represent time, , and ω represent the angular frequency. Then the modulated signal is:

[0054] Formula 1: ;

[0055] Since the demodulation clock is consistent with the modulation clock, the demodulated signal is:

[0056] Formula 2: . ​

[0057] When the low frequency noise is , after passing through the two chopper circuits, the low frequency noise is decomposed into two parts as shown in equation 2, the low frequency part is 1 / 2 times the original noise, and the high frequency part has been modulated to 2 times the modulation frequency. The low frequency noise is effectively suppressed. When the input offset voltage of the operational amplifier circuit AMP is represented by VOFF, after passing through the chopper circuit, the offset voltage is modulated to the modulation frequency as shown in equation 1, and can be filtered out by a low pass filter.

[0058] As an optional embodiment, as shown in Figure 6 , the charge pump noise suppression circuit NSC2 includes a NMOS transistor MN3 (i.e. the third NMOS transistor), a PMOS transistor MP11 (i.e. the seventh PMOS transistor), a resistor R3, a resistor R4, and a variable resistor VAR1.

[0059] The gate of MN3 is connected to the second voltage V01, the source of MN3 is grounded, and the drain of MN3 is connected to the gate of MP11 and the resistor R3 in sequence. The source of MP11 is connected to the resistor R3 and the first voltage PUMP_OUT. The resistor R3 is used to establish a verified DC operating point for the gate of MP11, and also defines the current in the branch. The drain of MP11 is connected to the resistor R4 and the variable resistor VAR1 in sequence, and then grounded; the drain of MP11 outputs the third voltage HVOUT. The feedback voltage VFB is taken between the resistor R4 and the variable resistor VAR1.

[0060] The above-mentioned partial embodiments of the reference noise suppression circuit NSC1 and the partial embodiments of the charge pump noise suppression circuit NSC2 can be configured into a noise reduction circuit as shown in Figure 7 . According to the noise reduction circuit shown in Figure 7 , the low frequency noise of the first voltage PUMP_OUT can be effectively suppressed while ensuring the efficiency of the power input and output. The low frequency noise suppression capability of the first voltage PUMP_OUT is:

[0061] Equation 3: .

[0062] In the equation, PSR PSR represents the power supply rejection, is the equivalent resistance of the output terminal, Ro3 is the equivalent impedance of the collector of MN3, Gain AMP represents the gain of the operational amplifier circuit AMP, gmn3 represents the transconductance of the NMOS transistor MN3, gmp11 represents the transconductance of the PMOS transistor MP11.

[0063] As can be seen from formula 3, the noise suppression capability of the noise reduction circuit in the above embodiment to the first voltage PUMP_OUT output by the charge pump is approximately the reciprocal of the loop gain thereof, and the noise suppression effect is remarkable.

[0064] In general, the noise reduction circuit provided in the embodiments of the present application has the following features: compared with the conventional direct power supply mode of the charge pump circuit CP, the noise reduction circuit provided in the present application combines the advantages of the chopper circuit and the low-dropout linear voltage stabilizing technology, and effectively suppresses the low-frequency noise of the high-voltage feedback driving power supply and the reference voltage VREF. The advantages are embodied in the following aspects: 1. The output voltage ripple of the charge pump circuit CP is effectively suppressed, and a more stable power supply can be provided for the high-voltage feedback driving circuit in the closed-loop circuit of the MEMS sensor; 2. The chopper technology is used to suppress the low-frequency noise of the reference voltage VREF, and further reduce the influence of the low-frequency noise and the input offset of the operational amplifier on the output high-voltage power supply; 3. The NPN type transistor is reasonably used to effectively improve the matching performance of the circuit and reduce the probability of circuit offset; 4. The low-dropout linear voltage stabilizing technology is used to improve the load regulation of the output high-voltage power supply, and at the same time, the margin loss of the output voltage of the charge pump circuit CP is minimized.

[0065] According to the idea of the present application, the embodiments of the present application further provide a power supply circuit. The power supply circuit is applicable to a MEMS sensor readout circuit. As shown in Figure 1 , the power supply circuit comprises a charge pump circuit CP and the noise reduction circuit designed in any of the above embodiments. The input end of the charge pump circuit CP is used to access the power supply AVDD, the output end is grounded through the capacitor C2, and the output end outputs the first voltage PUMP_OUT.

[0066] In addition, the embodiments of the present application further provide a readout circuit comprising the above power supply circuit. More specifically, in some embodiments, referring to the accompanying Figure 1 , the readout circuit comprises the power supply circuit and a high-voltage feedback driving circuit, and the power supply circuit supplies power for the high-voltage feedback driving circuit, that is, the power supply circuit accesses the third voltage HVOUT output by the power supply circuit to the high-voltage feedback driving circuit.

[0067] In addition, referring to the accompanying Figure 1 , the embodiments of the present application further provide a detection circuit comprising a capacitive MEMS sensor and the above readout circuit. The readout circuit is connected to the capacitive MEMS sensor. According to the embodiments of the readout circuit in the above, the high-voltage feedback driving circuit is connected to the capacitive MEMS sensor, Figure 1 , Cd1 and Cd2 are respectively the equivalent capacitances between the movable mass MASS and the upper plate and the lower plate of the driving capacitor.

[0068] The application is not restricted to the foregoing specific embodiments. The application extends to any novel one, or any novel combination, of the features disclosed in this specification, and to any novel method or process disclosed in this specification or any novel combination thereof.

Claims

1. A noise reduction circuit, characterized by, The reference noise suppression circuit and the charge pump noise suppression circuit are included; The input end of the reference noise suppression circuit is used for connecting a clock signal, a power supply, a reference voltage and a feedback voltage, the output end is grounded through a capacitor C1, and the output end outputs a second voltage; The reference noise suppression circuit includes a first chopper circuit, an operational amplifier circuit, a second chopper circuit and a double-ended to single-ended operational amplifier circuit; the input end of the first chopper circuit is used for connecting the clock signal, the reference voltage and the feedback voltage, and the output end is connected to the input end of the operational amplifier circuit; the input end of the second chopper circuit is connected to the output end of the operational amplifier circuit and the clock signal respectively, and the output end is connected to the double-ended to single-ended operational amplifier circuit; the output end of the double-ended to single-ended operational amplifier circuit outputs the second voltage; The power supply voltage of the charge pump noise suppression circuit is used for connecting a first voltage to be reduced in noise, the input end is connected to the second voltage, and the output end outputs a third voltage and the feedback voltage respectively; the charge pump noise suppression circuit includes a third NMOS tube, a seventh PMOS tube, a third fixed resistor, a fourth fixed resistor and a first variable resistor; the gate of the third NMOS tube is connected to the second voltage, the source is grounded, and the drain is connected to the gate of the seventh PMOS tube and the third fixed resistor respectively; the source of the seventh PMOS tube is connected to the third fixed resistor and connected to the first voltage; the drain of the seventh PMOS tube is grounded after being connected to the fourth fixed resistor and the first variable resistor in sequence; the drain of the seventh PMOS tube outputs the third voltage; the feedback voltage is led out between the fourth fixed resistor and the first variable resistor.

2. The noise reduction circuit of claim 1, wherein, The structures of the first chopper circuit and the second chopper circuit are as follows: It includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; the source of the first PMOS tube and the source of the second PMOS tube are both connected to a positive input end; the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to a negative input end; the gate of the first PMOS tube and the gate of the fourth PMOS tube are both connected to the clock signal; the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to the clock signal after being inverted; the drain of the first PMOS tube and the drain of the third PMOS tube are both connected to a positive output end; the drain of the second PMOS tube and the drain of the fourth PMOS tube are both connected to a negative output end.

3. The noise reduction circuit of claim 1, wherein, The double-ended to single-ended operational amplifier circuit includes a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a first NPN triode, a second NPN triode, a first fixed resistor and a second fixed resistor; The source of the fifth PMOS tube is connected to the positive output end of the second chopper circuit, and the drain is connected to the drain of the first NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube respectively; The source of the sixth PMOS tube is connected to the negative output end of the second chopper circuit, and the drain is connected to the drain of the second NMOS tube; the drain of the sixth PMOS tube outputs the second voltage; The substrate of the fifth PMOS tube is connected to the substrate of the sixth PMOS tube; The source of the first NMOS tube is connected to the collector of the first NPN transistor; The source of the second NMOS tube is connected to the collector of the second NPN transistor; The emitter of the first NPN transistor is grounded through the first fixed resistor, the emitter of the second NPN transistor is grounded through the second fixed resistor, and the base of the first NPN transistor is connected to the base of the second NPN transistor.

4. A power supply circuit, characterized by comprising: The noise reduction circuit comprises a charge pump circuit and a readout circuit as claimed in any one of claims 1-3. The input end of the charge pump circuit is connected to the power supply, the output end is grounded through a capacitor C2, and the output end outputs the first voltage.

5. A sense circuit, characterized by comprising: The power supply circuit comprises the power supply circuit as claimed in claim 4.

6. A detection circuit comprising a capacitive MEMS sensor, characterized in that, The readout circuit as claimed in claim 5 is further connected to the capacitive MEMS sensor.

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