High linearity switch low noise amplifier with logic control

Abstract

The application relates to the technical field of low-noise amplifiers, and discloses a high-linearity switch low-noise amplifier with logic control, which comprises an LNA channel circuit, a Bypass channel circuit, a TX channel circuit and a logic control circuit; the LNA channel circuit comprises a series-parallel switch unit, an amplifier adopting a Cascode combined nonlinear cancellation structure and a bias circuit; the Bypass channel circuit comprises two series-connected switch tubes for variable gain switching and a pi-type attenuator; the TX channel circuit comprises a series-connected double-gate switch tube and a parallel-stacked double-gate switch tube group; and the logic control circuit controls the switch tube states in the LNA channel circuit, the Bypass channel circuit and the TX channel circuit through a first logic level and a second logic level to perform channel switching. The application adopts specific switch architectures in each channel, improves the isolation degree among the three channels, and makes the LNA mode, the Bypass mode and the TX mode all have good linearity and radio frequency performance.

Description

Technical Field

[0001] This invention relates to the field of low-noise amplifier technology, and more specifically to a high-linearity switching low-noise amplifier with logic control. Background Technology

[0002] High-performance switching low-noise amplifiers (LNAs) are an inevitable product of the development of wireless communication towards higher frequencies, higher speeds, and higher integration. Their core lies in achieving high linearity, low noise, and fast switching RF front-end performance through advanced semiconductor processes and circuit design. Current wireless communication systems have increasingly higher requirements for data rates and bandwidth. Higher-order modulation methods are more sensitive to signal purity; any nonlinear distortion will reduce modulation accuracy and increase the bit error rate. Simultaneously, the application of multiple-input multiple-output (MIMO) technology requires each antenna channel to have an independent LNA and switch, which also drives the demand for highly integrated devices, necessitating switching LNAs with even higher performance.

[0003] LNA mode amplifies weak signals while minimizing noise and avoiding signal distortion. However, with today's high-order modulation signals, the linearity of the LNA is extremely demanding, and the linearity of conventional Cascode cannot meet the requirements for higher-order modulation signals. Summary of the Invention

[0004] To address the aforementioned shortcomings in the prior art, this invention provides a high-linearity switching low-noise amplifier with logic control. By employing a specific switching architecture in each channel, the isolation between the three channels is improved, resulting in good linearity and RF performance in LNA mode, Bypass mode, and TX mode, respectively. Furthermore, a specific logic circuit is used to control two logic levels to achieve switching between the three modes.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0006] A high-linearity switching low-noise amplifier with logic control, comprising:

[0007] LNA channel circuit, Bypass channel circuit, TX channel circuit and logic control circuit;

[0008] The LNA channel circuit includes a series-parallel switching unit, an amplifier using Cascode combined with a nonlinear cancellation structure, and a bias circuit.

[0009] The Bypass channel circuitry includes two series-connected switches for variable gain switching, and a π-type attenuator.

[0010] The TX channel circuit includes series-connected dual-gate switches and parallel-stacked dual-gate switch groups;

[0011] The logic control circuit controls the state of the switching transistors in the LNA channel circuit, Bypass channel circuit, and TX channel circuit through the first logic level and the second logic level to perform channel switching.

[0012] Furthermore, amplifiers employing Cascode combined with nonlinear cancellation structures include:

[0013] First amplifying tube, second amplifying tube, and third amplifying tube;

[0014] The gate of the first amplifier transistor is connected to the bias voltage terminal and is connected to the gate of the third amplifier transistor through the sixth capacitor; the drain of the first amplifier transistor is connected to the source of the second amplifier transistor and the drain of the third amplifier transistor respectively; the source of the first amplifier transistor is connected to the source of the third amplifier transistor and is grounded through the first inductor.

[0015] The gate of the second amplifier transistor is connected to the bias voltage terminal and grounded through the first resistor and the eighth capacitor in series; the drain of the second amplifier transistor is grounded through the second inductor and the seventh capacitor in series.

[0016] The gate of the third amplifier tube is connected to the bias voltage terminal.

[0017] Furthermore, the series-parallel switching unit includes:

[0018] The fifth, sixth, and seventh switching transistors;

[0019] The control terminals of the fifth, sixth, and seventh switching transistors are respectively connected to the logic control circuit.

[0020] The output terminal of the fifth switching transistor is connected to the input terminal of the sixth switching transistor, and is connected to the gate of the first amplifying transistor through the fifth capacitor;

[0021] The output of the sixth switch is grounded through the fourth capacitor;

[0022] The input terminal of the seventh switch is connected to the drain of the second amplifier via the ninth capacitor; the output terminal of the seventh switch is connected to the RX output terminal via the tenth capacitor.

[0023] Furthermore, the Bypass channel circuit includes:

[0024] The eighth, ninth, tenth, and eleventh switching transistors;

[0025] The control terminals of the eighth, ninth, tenth, and eleventh switching transistors are respectively connected to the logic control circuit;

[0026] The output terminal of the eighth switch is connected to the input terminals of the tenth and eleventh switches, respectively.

[0027] The output terminal of the tenth switch is connected to one end of the second resistor; the other end of the second resistor is connected to the input terminal of the ninth switch, and grounded through the third resistor and the eleventh capacitor connected in series.

[0028] The output terminal of the eleventh switch is connected to the input terminal of the ninth switch;

[0029] The output of the ninth switch is connected to the RX output via the twelfth capacitor.

[0030] Furthermore, the TX channel circuit includes:

[0031] Second switch, third switch and fourth switch;

[0032] The control terminal of the second switch and the parallel control terminals of the third and fourth switches are respectively connected to the logic control circuit.

[0033] The output terminal of the second switching transistor is connected to the input terminal of the third switching transistor and one end of the second capacitor; the other end of the second capacitor is connected to the TX input terminal.

[0034] The output terminal of the third switch is connected to the input terminal of the fourth switch;

[0035] The output of the fourth switch is grounded through the third capacitor.

[0036] Furthermore, it also includes a first switching transistor;

[0037] The control terminal of the first switching transistor is connected to the logic control circuit.

[0038] The input terminal of the first switch is connected to the input terminal of the second switch, and is connected to the ANT signal terminal through the first capacitor; the output terminal of the first switch is connected to the input terminals of the fifth switch and the eighth switch respectively.

[0039] Furthermore, the logic control circuit includes:

[0040] First transistor and second transistor;

[0041] The drain of the first transistor is connected to the drain of the second transistor, and is also connected to the control terminals of the eighth and ninth switches, as well as the source and gate of the ninth transistor; the sources of both the first and second transistors are grounded; the gate of the second transistor is connected to the LNA enable input terminal; the gate of the first transistor is connected to the TX enable input terminal, and is also connected to the gates of the fourth, sixth, and sixteenth transistors, respectively.

[0042] The source of the fourth transistor is grounded; the drain of the fourth transistor is connected to the control terminal of the first switch and the parallel control terminal of the third and fourth switches, and is connected to the source and gate of the third transistor respectively.

[0043] The source of the sixth transistor is grounded; the drain of the sixth transistor is connected to the source and gate of the fifth transistor, and is connected to the gate of the eighth transistor.

[0044] The source of the eighth transistor is grounded; the drain of the eighth transistor is connected to the source and gate of the seventh transistor, and is connected to the control terminal of the second switch.

[0045] The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the gate of the twelfth transistor and the fourteenth transistor, and is also connected to the source and gate of the eighteenth transistor, respectively.

[0046] The source of the twelfth transistor is grounded; the drain of the twelfth transistor is connected to the source and gate of the thirteenth transistor, and is also connected to the gate of the tenth transistor.

[0047] The source of the tenth transistor is grounded; the drain of the tenth transistor is connected to the source and gate of the eleventh transistor, respectively, and is connected to the parallel control terminal of the fifth and seventh switches.

[0048] The source of the fourteenth transistor is grounded; the drain of the fourteenth transistor is connected to the source and gate of the fifteenth transistor, and is connected to the bias voltage terminal.

[0049] The source of the sixteenth transistor is grounded; the drain of the sixteenth transistor is connected to the source and gate of the eighteenth transistor, and to the gate of the seventeenth transistor.

[0050] The source of the seventeenth transistor is grounded; the gate of the seventeenth transistor is connected to the drain of the nineteenth transistor, and is also connected to the source and gate of the twentieth transistor.

[0051] The source of the nineteenth transistor is grounded; the gate of the nineteenth transistor is connected to the LNA enable input.

[0052] Furthermore, the logic control circuit includes:

[0053] Twenty-first transistor and twenty-second transistor;

[0054] The source of the 21st transistor is grounded; the gate of the 21st transistor is connected to the Bypass selection terminal and to the gate of the 22nd transistor; the drain of the 21st transistor is connected to the control terminal of the 10th switch and to the source and gate of the 24th transistor respectively.

[0055] The source of the 22nd transistor is grounded; the drain of the 22nd transistor is connected to the gate of the 23rd transistor, and is also connected to the source and gate of the 25th transistor, respectively.

[0056] The source of the 23rd transistor is grounded; the drain of the 23rd transistor is connected to the control terminal of the 11th switch, and is also connected to the source and gate of the 26th transistor.

[0057] The present invention has the following beneficial effects:

[0058] The LNA Mode and TX Mode of this invention both employ a series-parallel switch configuration, while the Bypass Mode uses two series-connected switches for variable gain switching. This structure provides high isolation between the three modes, ensuring that other paths do not significantly impact the performance of any given mode, thus improving the linearity and RF performance of each mode. Attached Figure Description

[0059] Figure 1 The block diagram of a high linearity switching low noise amplifier provided for an embodiment of the present invention.

[0060] Figure 2 The schematic diagram of the logic control circuit provided for the embodiments of the present invention.

[0061] Figure 3 The schematic diagram of the logic control circuit for Bypass size attenuation channel switching provided in the embodiment of the present invention.

[0062] Figure 4 The LNA channel amplitude distortion (AMAM) curve provided in this embodiment of the invention.

[0063] Figure 5 The LNA channel amplitude-phase distortion AMPM curve is provided for an embodiment of the present invention.

[0064] Figure 6 The Bypass amplitude distortion AMAM curve provided in this embodiment of the invention.

[0065] Figure 7 The Bypass amplitude-phase distortion (AMPM) curve provided in this embodiment of the invention.

[0066] Figure 8 The AMAM curve of the TX channel is provided for an embodiment of the present invention.

[0067] Figure 9 The AMPM curve of the TX channel is provided for an embodiment of the present invention. Detailed Implementation

[0068] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0069] like Figure 1 As shown, an embodiment of the present invention provides a high linearity switching low noise amplifier with logic control, comprising:

[0070] LNA channel circuit, Bypass channel circuit, TX channel circuit and logic control circuit;

[0071] The LNA channel circuit includes a series-parallel switching unit, an amplifier using Cascode combined with a nonlinear cancellation structure, and a bias circuit.

[0072] The Bypass channel circuitry includes two series-connected switches for variable gain switching, and a π-type attenuator.

[0073] The TX channel circuit includes series-connected dual-gate switches and parallel-stacked dual-gate switch groups;

[0074] The logic control circuit controls the state of the switching transistors in the LNA channel circuit, Bypass channel circuit, and TX channel circuit through the first logic level and the second logic level to perform channel switching.

[0075] This embodiment includes three modes: LNA mode, Bypass mode, and TX mode. The LNA channel consists of a switch, a Cascode cancellation structure, and its bias circuit. The Bypass mode consists of two channels, a low-attenuation mode and a high-attenuation mode, switched by a switch. The TX channel consists of a series dual-gate switch and parallel stacked dual-gate switches. Switching between the three modes is achieved by specific logic circuitry through two logic control levels. By employing a specific series-parallel switch structure for each channel, this invention achieves high isolation between the three channels, allowing the linearity and RF characteristics to perform optimally in each mode.

[0076] In an optional embodiment of the present invention, the amplifier employing Cascode combined with a nonlinear cancellation structure includes:

[0077] First amplifying tube, second amplifying tube, and third amplifying tube;

[0078] The gate of the first amplifier transistor is connected to the bias voltage terminal and is connected to the gate of the third amplifier transistor through the sixth capacitor; the drain of the first amplifier transistor is connected to the source of the second amplifier transistor and the drain of the third amplifier transistor respectively; the source of the first amplifier transistor is connected to the source of the third amplifier transistor and is grounded through the first inductor.

[0079] The gate of the second amplifier transistor is connected to the bias voltage terminal and grounded through the first resistor and the eighth capacitor in series; the drain of the second amplifier transistor is grounded through the second inductor and the seventh capacitor in series.

[0080] The gate of the third amplifier tube is connected to the bias voltage terminal.

[0081] The series-parallel switching unit includes:

[0082] The fifth, sixth, and seventh switching transistors;

[0083] The control terminals of the fifth, sixth, and seventh switching transistors are respectively connected to the logic control circuit.

[0084] The output terminal of the fifth switching transistor is connected to the input terminal of the sixth switching transistor, and is connected to the gate of the first amplifying transistor through the fifth capacitor;

[0085] The output of the sixth switch is grounded through the fourth capacitor;

[0086] The input terminal of the seventh switch is connected to the drain of the second amplifier via the ninth capacitor; the output terminal of the seventh switch is connected to the RX output terminal via the tenth capacitor.

[0087] In this embodiment, the LNA channel employs a Cascode amplifier and a nonlinear cancellation structure. The main amplifier transistor and the auxiliary transistor work together, utilizing the opposite phase characteristics of their third-order nonlinear components to achieve active distortion cancellation. The Cascode structure enhances gain stability through cascaded amplification, while the independent bias adjustment of the auxiliary transistor dynamically balances the nonlinear terms, ensuring low noise figures and significantly suppressing phase and amplitude distortion when amplifying weak signals. Channel switching and physical isolation design ensure no signal leakage when other modes are off, achieving high linearity and low noise RF signal amplification.

[0088] In this embodiment, both LNA Mode and TX Mode employ a series-parallel switch configuration, while Bypass Mode uses two series-connected switches for variable gain switching. This structure provides high isolation between the three modes, ensuring that other paths do not significantly impact the performance of any given mode, thus improving the linearity and RF performance of each mode.

[0089] In an optional embodiment of the present invention, the Bypass channel circuit includes:

[0090] The eighth, ninth, tenth, and eleventh switching transistors;

[0091] The control terminals of the eighth, ninth, tenth, and eleventh switching transistors are respectively connected to the logic control circuit;

[0092] The output terminal of the eighth switch is connected to the input terminals of the tenth and eleventh switches, respectively.

[0093] The output terminal of the tenth switch is connected to one end of the second resistor; the other end of the second resistor is connected to the input terminal of the ninth switch, and grounded through the third resistor and the eleventh capacitor connected in series.

[0094] The output terminal of the eleventh switch is connected to the input terminal of the ninth switch;

[0095] The output of the ninth switch is connected to the RX output via the twelfth capacitor.

[0096] In this embodiment, the Bypass channel includes two paths: one with low attenuation and the other with high attenuation. Variable signal attenuation is achieved through a combination of a π-type attenuation network and switches. The low attenuation path uses a low insertion loss switch for direct connection, while the high attenuation path uses a resistor network to reduce signal strength through voltage division. The two paths are switched by independent switches. The isolation design between the channel switches and the LNA stage avoids parasitic capacitance coupling in the amplifier, ensuring low-distortion transmission even when a strong input signal bypasses the LNA, and preventing amplitude compression and phase distortion caused by signal saturation.

[0097] In an optional embodiment of the present invention, the TX channel circuit includes:

[0098] Second switch, third switch and fourth switch;

[0099] The control terminal of the second switch and the parallel control terminals of the third and fourth switches are respectively connected to the logic control circuit.

[0100] The output terminal of the second switching transistor is connected to the input terminal of the third switching transistor and one end of the second capacitor; the other end of the second capacitor is connected to the TX input terminal.

[0101] The output terminal of the third switch is connected to the input terminal of the fourth switch;

[0102] The output of the fourth switch is grounded through the third capacitor.

[0103] In an optional embodiment of the present invention, this embodiment further includes a first switching transistor;

[0104] The control terminal of the first switching transistor is connected to the logic control circuit.

[0105] The input terminal of the first switch is connected to the input terminal of the second switch, and is connected to the ANT signal terminal through the first capacitor; the output terminal of the first switch is connected to the input terminals of the fifth switch and the eighth switch respectively.

[0106] In this embodiment, the TX channel employs a combination of series dual-gate switches and parallel stacked switches. The series switches provide a low-impedance main path, while the parallel stacked switches form a distributed grounding network. When the transmitted signal is transmitted through the series switches, the stacked switches reduce the voltage stress on a single transistor through multi-stage voltage division, suppressing gate breakdown or parasitic conduction caused by high-power signals. This structure can efficiently transmit high-power signals in the transmission state while preventing reverse leakage to the receiver through physical isolation, ensuring the linearity and power integrity of the transmission link.

[0107] In an optional embodiment of the present invention, such as Figure 2 As shown, the logic control circuit includes:

[0108] First transistor and second transistor;

[0109] The drain of the first transistor is connected to the drain of the second transistor, and is also connected to the control terminals of the eighth and ninth switches, as well as the source and gate of the ninth transistor; the sources of both the first and second transistors are grounded; the gate of the second transistor is connected to the LNA enable input terminal; the gate of the first transistor is connected to the TX enable input terminal, and is also connected to the gates of the fourth, sixth, and sixteenth transistors, respectively.

[0110] The source of the fourth transistor is grounded; the drain of the fourth transistor is connected to the control terminal of the first switch and the parallel control terminal of the third and fourth switches, and is connected to the source and gate of the third transistor respectively.

[0111] The source of the sixth transistor is grounded; the drain of the sixth transistor is connected to the source and gate of the fifth transistor, and is connected to the gate of the eighth transistor.

[0112] The source of the eighth transistor is grounded; the drain of the eighth transistor is connected to the source and gate of the seventh transistor, and is connected to the control terminal of the second switch.

[0113] The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the gate of the twelfth transistor and the fourteenth transistor, and is also connected to the source and gate of the eighteenth transistor, respectively.

[0114] The source of the twelfth transistor is grounded; the drain of the twelfth transistor is connected to the source and gate of the thirteenth transistor, and is also connected to the gate of the tenth transistor.

[0115] The source of the tenth transistor is grounded; the drain of the tenth transistor is connected to the source and gate of the eleventh transistor, respectively, and is connected to the parallel control terminal of the fifth and seventh switches.

[0116] The source of the fourteenth transistor is grounded; the drain of the fourteenth transistor is connected to the source and gate of the fifteenth transistor, and is connected to the bias voltage terminal.

[0117] The source of the sixteenth transistor is grounded; the drain of the sixteenth transistor is connected to the source and gate of the eighteenth transistor, and to the gate of the seventeenth transistor.

[0118] The source of the seventeenth transistor is grounded; the gate of the seventeenth transistor is connected to the drain of the nineteenth transistor, and is also connected to the source and gate of the twentieth transistor.

[0119] The source of the nineteenth transistor is grounded; the gate of the nineteenth transistor is connected to the LNA enable input.

[0120] like Figure 3 As shown, the logic control circuit in this embodiment includes:

[0121] Twenty-first transistor and twenty-second transistor;

[0122] The source of the 21st transistor is grounded; the gate of the 21st transistor is connected to the Bypass selection terminal and to the gate of the 22nd transistor; the drain of the 21st transistor is connected to the control terminal of the 10th switch and to the source and gate of the 24th transistor respectively.

[0123] The source of the 22nd transistor is grounded; the drain of the 22nd transistor is connected to the gate of the 23rd transistor, and is also connected to the source and gate of the 25th transistor, respectively.

[0124] The source of the 23rd transistor is grounded; the drain of the 23rd transistor is connected to the control terminal of the 11th switch, and is also connected to the source and gate of the 26th transistor.

[0125] LEF is an enhancement-mode logic transistor, and LDF is a depletion-mode logic transistor.

[0126] In this embodiment, the logic control circuit generates tri-state control logic through a combination of dual-level signals, driving the switches of each channel to conduct complementaryly. By synchronously adjusting the bias voltage of the amplifier and the switch during mode switching, the leakage path of the non-working channel is completely shut off, achieving high isolation and fast switching between modes, and ensuring optimal performance when each channel works independently.

[0127] This invention has three working modes: LNA mode, Bypass mode, and TX mode.

[0128] In LNA mode, the received RF signal is input through the ANT port and output through the RXout port. The LNA enable is set to high, and the TX enable is set to low, turning on the switches corresponding to nodes M1 and M3, and turning off the switches corresponding to nodes M2 and M4-M6. Bias1-Bias3 provide the necessary operating voltage for the Cascode. At this time, the TX and Bypass paths are disconnected, ensuring high isolation between the LNA channel and other channels, preventing performance degradation. Furthermore, by employing a cancellation structure and designing the bias points of the amplifier's main and auxiliary transistors, the third-order nonlinearity of the main transistor is reduced, achieving nonlinearity cancellation and thus improving the amplifier's linearity. Figure 4 and Figure 5 It can be seen that when the input power is less than -10dBm, the linearity index AMAM is flat and the AMAM change is less than 0.1°.

[0129] When the Bypass channel operates in high attenuation mode, the TX enable, LNA enable, and Bypass channel selection enable are all set to low, turning on the switches corresponding to nodes M1, M4, and M5, and turning off the switches corresponding to nodes M2, M3, and M6. Furthermore, bias1 and bias2 are set to low, disabling the Cascode. In low attenuation mode, the Bypass channel selection enable is set to high, turning on SW11 and disabling SW10. The high attenuation channel achieves greater insertion loss by incorporating π attenuation. Because switches SW5 and SW6 exist in the LNA channel, the Cascode portion of the LNA channel is well isolated from the Bypass, thus preventing a deterioration in the linearity of the Bypass. Figure 6 and Figure 7 It can be seen that in Bypass mode, when the input power is less than IP1dB, the linearity index AMAM is flat and the AMAM change is less than 0.1°.

[0130] In TX mode, the transmit signal is input through the TX port and output through the ANT port. A high level for TX enable and a low level for LNA enable turn on the switch corresponding to node M2, while the switches corresponding to nodes M1, M3, and M4 turn off. Since TX mode is used to transmit high-power signals, it's crucial to consider not only isolation but also preventing power leakage from high-power signals. Therefore, in TX mode, the number of switches stacked in other channels needs to be determined based on the output power of the TX path to prevent power leakage caused by voltage swings in high-power signals, thus improving the linearity of the TX switching mode. Figure 8 and Figure 9 It can be seen that in TX mode, when the output P-0.1dB, the linearity index AMAM is flat and the AMAM change is less than 0.5°.

[0131] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

[0132] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A high-linearity switching low-noise amplifier with logic control, characterized in that, include: LNA channel circuit, Bypass channel circuit, TX channel circuit and logic control circuit; The LNA channel circuit includes a series-parallel switching unit, an amplifier using Cascode combined with a nonlinear cancellation structure, and a bias circuit. Amplifiers employing Cascode combined with nonlinear cancellation structures include: First amplifying tube, second amplifying tube, and third amplifying tube; The gate of the first amplifier transistor is connected to the bias voltage terminal and is connected to the gate of the third amplifier transistor through the sixth capacitor; the drain of the first amplifier transistor is connected to the source of the second amplifier transistor and the drain of the third amplifier transistor respectively; the source of the first amplifier transistor is connected to the source of the third amplifier transistor and is grounded through the first inductor. The gate of the second amplifier transistor is connected to the bias voltage terminal and grounded through the first resistor and the eighth capacitor in series; the drain of the second amplifier transistor is grounded through the second inductor and the seventh capacitor in series. The gate of the third amplifier transistor is connected to the bias voltage terminal; The Bypass channel circuit includes two series-connected switches for variable gain switching, and a π-type attenuator; the Bypass channel circuit includes: The eighth, ninth, tenth, and eleventh switching transistors; The control terminals of the eighth, ninth, tenth, and eleventh switching transistors are respectively connected to the logic control circuit; The output terminal of the eighth switch is connected to the input terminals of the tenth and eleventh switches, respectively. The output terminal of the tenth switch is connected to one end of the second resistor; the other end of the second resistor is connected to the input terminal of the ninth switch, and grounded through the third resistor and the eleventh capacitor connected in series. The output terminal of the eleventh switch is connected to the input terminal of the ninth switch; The output terminal of the ninth switch is connected to the RX output terminal via the twelfth capacitor. The TX channel circuit includes series-connected dual-gate switches and parallel-stacked dual-gate switch groups; The logic control circuit controls the state of the switching transistors in the LNA channel circuit, Bypass channel circuit, and TX channel circuit through the first logic level and the second logic level to perform channel switching.

2. The high linearity switching low noise amplifier with logic control according to claim 1, characterized in that, The series-parallel switching unit includes: The fifth, sixth, and seventh switching transistors; The control terminals of the fifth, sixth, and seventh switching transistors are respectively connected to the logic control circuit. The output terminal of the fifth switching transistor is connected to the input terminal of the sixth switching transistor, and is connected to the gate of the first amplifying transistor through the fifth capacitor; The output of the sixth switch is grounded through the fourth capacitor; The input terminal of the seventh switch is connected to the drain of the second amplifier via the ninth capacitor; the output terminal of the seventh switch is connected to the RX output terminal via the tenth capacitor.

3. The high linearity switching low noise amplifier with logic control according to claim 1, characterized in that, The TX channel circuit includes: Second switch, third switch and fourth switch; The control terminal of the second switch and the parallel control terminals of the third and fourth switches are respectively connected to the logic control circuit. The output terminal of the second switching transistor is connected to the input terminal of the third switching transistor and one end of the second capacitor; the other end of the second capacitor is connected to the TX input terminal. The output terminal of the third switch is connected to the input terminal of the fourth switch; The output of the fourth switch is grounded through the third capacitor.

4. A high-linearity switching low-noise amplifier with logic control according to claim 3, characterized in that, It also includes the first switching transistor; The control terminal of the first switching transistor is connected to the logic control circuit. The input terminal of the first switch is connected to the input terminal of the second switch, and is connected to the ANT signal terminal through the first capacitor; the output terminal of the first switch is connected to the input terminals of the fifth switch and the eighth switch respectively.

5. A high-linearity switching low-noise amplifier with logic control according to claim 4, characterized in that, The logic control circuit includes: First transistor and second transistor; The drain of the first transistor is connected to the drain of the second transistor, and is also connected to the control terminals of the eighth and ninth switches, as well as the source and gate of the ninth transistor; the sources of both the first and second transistors are grounded; the gate of the second transistor is connected to the LNA enable input terminal; the gate of the first transistor is connected to the TX enable input terminal, and is also connected to the gates of the fourth, sixth, and sixteenth transistors, respectively. The source of the fourth transistor is grounded; the drain of the fourth transistor is connected to the control terminal of the first switch and the parallel control terminal of the third and fourth switches, and is connected to the source and gate of the third transistor respectively. The source of the sixth transistor is grounded; the drain of the sixth transistor is connected to the source and gate of the fifth transistor, and is connected to the gate of the eighth transistor. The source of the eighth transistor is grounded; the drain of the eighth transistor is connected to the source and gate of the seventh transistor, and is connected to the control terminal of the second switch. The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the gate of the twelfth transistor and the fourteenth transistor, and is also connected to the source and gate of the eighteenth transistor, respectively. The source of the twelfth transistor is grounded; the drain of the twelfth transistor is connected to the source and gate of the thirteenth transistor, and is also connected to the gate of the tenth transistor. The source of the tenth transistor is grounded; the drain of the tenth transistor is connected to the source and gate of the eleventh transistor, and is connected to the parallel control terminal of the fifth and seventh switches. The source of the fourteenth transistor is grounded; the drain of the fourteenth transistor is connected to the source and gate of the fifteenth transistor, and is connected to the bias voltage terminal. The source of the sixteenth transistor is grounded; the drain of the sixteenth transistor is connected to the source and gate of the eighteenth transistor, and to the gate of the seventeenth transistor. The source of the seventeenth transistor is grounded; the gate of the seventeenth transistor is connected to the drain of the nineteenth transistor, and is also connected to the source and gate of the twentieth transistor. The source of the nineteenth transistor is grounded; the gate of the nineteenth transistor is connected to the LNA enable input.

6. A high-linearity switching low-noise amplifier with logic control according to claim 5, characterized in that, The logic control circuit includes: Twenty-first transistor and twenty-second transistor; The source of the 21st transistor is grounded; the gate of the 21st transistor is connected to the Bypass selection terminal and to the gate of the 22nd transistor; the drain of the 21st transistor is connected to the control terminal of the 10th switch and to the source and gate of the 24th transistor respectively. The source of the 22nd transistor is grounded; the drain of the 22nd transistor is connected to the gate of the 23rd transistor, and is also connected to the source and gate of the 25th transistor, respectively. The source of the 23rd transistor is grounded; the drain of the 23rd transistor is connected to the control terminal of the 11th switch, and is also connected to the source and gate of the 26th transistor.

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