Microprocessor-based variable narrow pulse and high prf control system and method

Abstract

The application discloses a microprocessor-based variable narrow pulse and high PRF control system and method, which comprises a master ARM core module, a clock module and a timer module, the clock module and the timer module are connected with the master ARM core module, the timer module comprises at least two cascaded hardware timers, wherein a first timer TIM5 is configured as a master mode timer, and a second timer TIM2 is configured as a slave mode timer; a trigger output end of the master mode timer is connected with a trigger input end of the slave mode timer, thereby forming a timer linkage structure; the master mode timer is configured to control a pulse repetition frequency PRF, and the slave mode timer is configured to control a pulse width; the clock module is frequency-multiplied through a phase-locked loop to serve as a timer reference clock source. The system can support super-narrow pulse generation, has small pulse width output and small jitter, and the pulse width can be adjusted, so that the cost is reduced, the system is small in size and modular, and is convenient for commercial integrated application.

Description

Technical Field

[0001] This invention relates to the field of ultrasonic signal processing technology, and in particular to a microprocessor-based variable narrow pulse and high PRF control system and method. Background Technology

[0002] There are various methods for generating ultrasonic excitation pulses, and the pulse width and pulse repetition frequency (PRF) can be adjusted through different techniques.

[0003] 1. Arbitrary waveforms can be generated using devices such as arbitrary waveform generators (AWGs) and direct digital synthesis (DDS) technology. The pulse width can be adjusted via software, or the pulse interval (PRF) can be adjusted in real time via programming.

[0004] 2. An avalanche transistor pulse circuit is used. The principle is to generate nanosecond-level narrow pulses using the avalanche breakdown effect. The pulse width can be adjusted by adjusting the transistor's operating point or the load impedance; the PRF is adjusted by controlling the frequency of the trigger signal.

[0005] 3. Based on a high-voltage pulse generator (HVP), a high-voltage short pulse is generated by rapidly discharging a capacitor after charging. Pulse width adjustment can adjust the conduction time of switching devices (such as MOSFETs and IGBTs); PRF adjustment can be controlled by the frequency of an external trigger signal.

[0006] 4. Based on the FPGA logic chip, the internal PLL generates a high-speed 400MHz clock to achieve the output of 5ns pulses. Through the writing of the internal logic program, the output of a high PRF pulse frequency of 80k is achieved.

[0007] The four methods mentioned above each have their own advantages and disadvantages. Some are used for quickly setting up temporary test systems; others are suitable for making circuit modules for use in ultrasonic instruments. The appropriate method should be selected based on the design requirements.

[0008] Of the aforementioned current technologies,

[0009] The first technology has the disadvantage that it requires an existing device as part of the system. High-end waveform generators usually cost hundreds of thousands of dollars, and the device is large and inconvenient to integrate into the ultrasound equipment as a module.

[0010] The second technology, avalanche tubes, can generate very narrow pulses, but they are limited by the heat dissipation of the tubes. Even with tubes and active cooling measures, it is difficult to achieve a high-frequency avalanche effect of 80kHz.

[0011] The third technology can generate a very narrow excitation pulse width, but once the device is fixed, its pulse width is also fixed. It is difficult to control the pulse width through charging and discharging, and the width cannot be adjusted by software. It requires replacing the device, and the pulse width amplitude of the product is also fixed, making it inconvenient to adjust.

[0012] The fourth technology is commonly used in larger instruments and equipment. FPGA devices are relatively large, consume a lot of power and generate a lot of heat, resulting in high costs. They also require external USB control chips, making the modules quite numerous. In addition to the core, FPGAs require multiple voltages, making the power supply module design complex and unsuitable for integration into small, lightweight devices. The biggest problem is in the trigger signal output. Due to the jitter deviation of the FPGA system clock, there is some transmission jitter in the output signal under extremely narrow pulse conditions (such as 5ns-10ns).

[0013] Among the aforementioned current technical implementation methods, some cannot achieve dynamic adjustment of pulse width and PRF; others are devices in themselves and cannot be embedded into the ultrasonic board design system; still others are costly, bulky, and power-consuming, making them unsuitable for integration into lightweight devices.

[0014] Therefore, there is a need for a low-cost, small-sized ultrasonic excitation source with high PRF and adjustable pulse. Summary of the Invention

[0015] In view of this, the purpose of the present invention is to provide a microprocessor-based variable narrow pulse and high PRF control system and method, which utilizes a low-cost and small-sized microprocessor to generate high PRF and pulse width adjustable ultrasonic signals.

[0016] To achieve the above objectives, the present invention provides the following technical solution:

[0017] The present invention provides a microprocessor-based variable narrow pulse and high PRF control system, including a main control ARM core module, a clock module, and a timer module. The clock module and the timer module are respectively connected to the main control ARM core module, and the clock module serves as the reference clock source for the timer.

[0018] The timer module includes at least two cascaded hardware timers, wherein the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer.

[0019] The trigger output terminal of the master mode timer is connected to the trigger input terminal of the slave mode timer to form a timer linkage structure;

[0020] The master mode timer is configured to control the pulse repetition frequency (PRF), and the slave mode timer is configured to control the pulse width.

[0021] Furthermore, the division factor and auto-reload register value of the master mode timer are calculated and determined according to the following formula:

[0022] ARR*(PSC+1)=Ft / PRF;

[0023] Where Ft is the timer reference clock frequency, PSC represents the division factor, ARR represents the value of the auto-reload register, and PRF represents the pulse repetition frequency.

[0024] Furthermore, the comparison register value of the slave mode timer is determined through iterative calculation, specifically including:

[0025] Initialize the comparison register value;

[0026] Calculate the current pulse width: pulsewidth = (PSC + 1) * CCR / Ft;

[0027] Where CCR represents the value of the comparison register; pulsewidth represents the current pulse width;

[0028] The iteration stops when the calculated pulse width value falls within the target pulse width range; otherwise, the CCR value is incremented and the calculation continues.

[0029] Furthermore, the overflow time of the main mode timer is calculated according to the following formula:

[0030] T=(ARR+1)*(PSC+1) / Ft,

[0031] Where T represents the overflow time of the main mode timer.

[0032] Furthermore, the main control ARM core module adopts a Cortex-M7 core architecture;

[0033] The first timer TIM5 is configured to use the system clock generated by the internal phase-locked loop as its clock source;

[0034] The second timer TIM2 receives the trigger output signal TRGO of the first timer TIM5 as an enable signal;

[0035] Set the prescaler PSC and auto-reload register ARR value for the first timer TIM5;

[0036] Set the CCR value of the compare register of the second timer TIM2 to determine the adjustable range of the pulse width;

[0037] A continuously adjustable narrow pulse signal is output from the PWM output pin of the second timer TIM2.

[0038] Furthermore, the PWM output pin is configured in push-pull output mode, and the output signal drives the high-voltage excitation generation module.

[0039] Furthermore, the clock module receives a reference clock from an external crystal oscillator and multiplies it to 120MHz-240MHz via a phase-locked loop.

[0040] Furthermore, it also includes a USB communication interface module, which is configured to receive pulse width and PRF parameter setting instructions from the host computer.

[0041] The present invention provides a microprocessor-based variable narrow pulse and high PRF control method, wherein the microprocessor adopts a Cortex-M7 core architecture, and includes the following steps:

[0042] S1: Use the first timer TIM5 as the master mode timer, and configure its clock source to be the system clock generated by the internal phase-locked loop;

[0043] S2: Use the second timer TIM2 as the slave mode timer and receive the trigger output signal TRGO of the first timer TIM5 as the enable signal;

[0044] S3: Set the prescaler coefficient PSC and the auto-reload register ARR value of the first timer TIM5 through the linkage configuration module, satisfying the formula: ARR×(PSC+1)=Ft / PRF, where Ft is the timer reference clock frequency and PRR is the pulse repetition frequency;

[0045] S4: Dynamically set the CCR value of the comparison register of the second timer TIM2 through the pulse width calculation module to satisfy the narrow pulse width formula: pulsewidth=(PSC+1)×CCR / Ft, where the pulse width is adjustable from 5ns to 1000ns;

[0046] S5: Outputs a continuously adjustable narrow pulse signal through the PWM output pin of the second timer TIM2.

[0047] Furthermore, the configuration process for the main mode timer parameters includes:

[0048] Set the initial value of the frequency division coefficient;

[0049] The value of the autoreload register is calculated using ARR=Floor(Ft / (PRF*(PSC+1))).

[0050] When the calculated overflow time exceeds the preset threshold, increment the PSC value and recalculate the ARR value.

[0051] The beneficial effects of this invention are as follows:

[0052] This invention provides a microprocessor-based variable narrow pulse and high PRF control system and method. The system includes a main control ARM core module, a clock module, and a timer module. The clock module and timer module are connected to the main control ARM core module. The timer module includes at least two cascaded hardware timers, where the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer. The trigger output of the master mode timer is connected to the trigger input of the slave mode timer, forming a timer linkage structure. The master mode timer is configured to control the pulse repetition frequency (PRF), and the slave mode timer is configured to control the pulse width. The clock module uses a phase-locked loop (PLL) to multiply the frequency as the timer reference clock source. This system supports ultra-narrow pulse generation, outputs extremely narrow pulse widths with low jitter, and the pulse width is adjustable. It reduces cost, is small in size, modular, and easy to integrate for commercial applications.

[0053] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0054] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following drawings are provided for illustration.

[0055] Figure 1 The system block diagram is for implementing a narrow pulse source based on M7.

[0056] Figure 2 This is a circuit diagram for implementing a square wave output with adjustable pulse width using timers TIM2 and TIM5 in a linked manner.

[0057] Figure 3 Flowchart of the method for determining the timer divider parameters and the values ​​of the compare register. Detailed Implementation

[0058] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0059] Example 1

[0060] like Figure 1 As shown, Figure 1The system block diagram for the narrow pulse source implementation based on M7 is shown in this embodiment. The microprocessor-based variable narrow pulse and high PRF control system includes a main control ARM core module, a clock module, and a timer module.

[0061] The main control ARM core module is connected to the clock module and the timer module respectively;

[0062] The timer module includes at least two cascaded hardware timers, wherein the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer.

[0063] The trigger output terminal of the master mode timer is connected to the trigger input terminal of the slave mode timer to form a timer linkage structure;

[0064] The master mode timer is configured to control the pulse repetition frequency (PRF), and the slave mode timer is configured to control the pulse width.

[0065] The clock module uses a phase-locked loop to multiply the frequency as the timer reference clock source.

[0066] In this preferred embodiment, the clock module uses a phase-locked loop to multiply the frequency to 240MHz as the timer reference clock source, and the main control ARM core module adopts a Cortex-M7 core architecture; or a high-frequency processor is used, and the processor speed must be at least 200MHz in order to generate a signal with a minimum pulse width of 5ns.

[0067] The frequency division coefficient and auto-reload register value of the master mode timer described in this embodiment are calculated and determined according to the following formula:

[0068] ARR*(PSC+1)=Ft / PRF;

[0069] Where Ft is the timer reference clock frequency; PSC represents the frequency division factor; ARR represents the auto-reload register; and PRF represents the pulse repetition frequency.

[0070] In this embodiment, the CCR value of the slave mode timer is determined through iterative calculation, specifically including:

[0071] Initially set CCR=1;

[0072] Calculate the current pulse width: pulsewidth = (PSC + 1) * CCR / Ft;

[0073] Where CCR represents the comparison register value;

[0074] The iteration stops when the calculated value falls within ±10% of the target pulse width; otherwise, the CCR value is incremented and the calculation continues.

[0075] The overflow time calculation formula for the main mode timer in this embodiment is T=(ARR+1)*(PSC+1) / Ft.

[0076] The ARR value is adjusted cyclically to ensure that the overflow time does not exceed 1 second, i.e., T≤1 second.

[0077] In this embodiment, the output terminal of the timer module is connected to a push-pull output circuit and configured to output a pulse signal with an adjustable pulse width of 5ns-1000ns and an adjustable PRF of 100Hz-80kHz.

[0078] The clock module described in this embodiment includes a crystal oscillator with an accuracy of 20ppm and is connected to an external storage module via an AXI bus. The external storage module includes at least 128KB Flash and 512KB SRAM.

[0079] This embodiment also includes a USB communication interface module, which is configured to receive pulse width and PRF parameter setting instructions from the host computer.

[0080] The microprocessor-based variable narrow pulse and high PRF control method provided in this embodiment includes the following steps:

[0081] Configure the clock division parameter PSC and the auto-reload register ARR value of the master mode timer TIM5 to set the pulse repetition frequency;

[0082] Configure the CCR value of the compare register of slave mode timer TIM2 to set the pulse width;

[0083] Establish a cascading triggering mechanism for master and slave timers, so that the overflow signal of the master mode timer triggers the slave mode timer to work;

[0084] Based on a 240MHz reference clock source, the pulse signal with adjustable pulse width and PRF is directly output through a hardware timer.

[0085] The configuration process of the main mode timer parameters described in this embodiment includes:

[0086] Set the initial value of the frequency division coefficient to 1;

[0087] The value of the autoreload register is calculated using ARR=Floor(Ft / (PRF*(PSC+1))).

[0088] When the calculated overflow time exceeds 1 second, increment the PSC value and recalculate the ARR value.

[0089] In this embodiment, the pulse width adjustment process maintains the consistency of the master and slave timer frequency division coefficients; the slave mode timer ARR value is set to the maximum count value 0xFFFFFFFF; and the CCR value is iteratively adjusted to make the output pulse width fall within the target value ±10% error range.

[0090] Example 2

[0091] like Figure 1 As shown, Figure 1 This embodiment illustrates the system block diagram for a narrow pulse source based on the M7 kernel. Using the M7 kernel as an example, it describes the specific configuration process for implementing a variable narrow pulse and high PRF control system using this method. The overall system framework of the narrow pulse excitation source obtained through this method is as follows: Figure 1 As shown, it mainly includes a main control ARM core module, a clock module, an internal timer module, a power supply module, a JTAG / SW module, an external flash memory module, an internal FIFO module, and serial and SPI interface modules;

[0092] The main control ARM core module uses a Cortex-M7 core, which provides higher computing performance. It features a six-stage pipeline and a dual-issue superscalar architecture, enabling it to execute two instructions in one clock cycle. It supports double-precision floating-point operations, and has separate instruction and data caches, which more effectively reduces latency between the processor and memory, improves processor performance, and provides a guarantee for ultra-narrow pulse source products.

[0093] The clock module uses a high-precision crystal oscillator with an error range of 20ppm, providing a stable baseline clock input for the entire system. Internally, the system clock is multiplied to 240MHz via a phase-locked loop for use by timers and other modules.

[0094] The internal timer module is a hardware module that runs independently of the ARM. Its counting operation does not require the MCU's involvement, making it well-suited as a pulse trigger source. These timer modules can be used for various applications, including time delay, event timing, PWM generation, etc. In this system, we mainly use the timer's PWM function.

[0095] The JTAG / SW module is an ARM debugging / programming tool that supports both SWD (Serial Wire Debug) and JTAG interfaces, making it suitable for development and debugging. The module's circuitry is relatively simple, but electrostatic discharge (ESD) protection is necessary for repeated plugging and unplugging.

[0096] The external storage module includes external flash and SRAM, etc. The M7 contains a rich set of peripheral configuration estimates and performs read and write management operations on these external storage devices through the AXI bus. The system is configured with 128KB of flash and 512KB of SRAM, mainly used to store programs and some business data.

[0097] The internal FIFO module contains various types of FIFO (First In, First Out) structures, which are mainly used for different purposes, such as data transfer, caching, and event management. Direct Memory Access (DMA) controllers typically have built-in FIFOs for efficient data transfer between main memory and peripherals. When peripherals (such as ADCs, SPI, I2C, etc.) need to exchange data with memory, the DMA controller can utilize FIFOs to reduce the CPU load and achieve high-speed data transfer.

[0098] The serial port and SPI interface modules are peripherals of the ARM processor. Serial communication (USART) is a method of data transmission in microcontrollers. It supports full-duplex communication, which means that data can be sent and received simultaneously, and also supports half-duplex communication. In this system, it is mainly used for printing and debugging. The SPI interface is a commonly used interface for external devices. It is mainly used for interconnection and data reading and writing with external devices. It has relatively rich configuration firmware and can adapt to different SPI interface devices.

[0099] The power module converts the 15V power supply into several different voltages, such as 5V, 3.3V, and 2.5V, to power various functional modules.

[0100] After the system is built, the timers for the system modules need to be configured, and the operation and coordination of each module need to be coordinated through programming. Simultaneously, host computer software needs to be written to control the smaller modules via the USB interface and send various parameters.

[0101] Finally, a pulse excitation source with adjustable pulse width and adjustable output frequency is output through the hardware timer output port, which is used to drive the subsequent high voltage excitation generation module.

[0102] This embodiment generates a long pulse through clock-timer linkage: the ARM timer TIM contains a counter, a prescaler, and an auto-reload register. These three registers constitute the core of the timer, and this circuit is called the time base unit. All three registers are 16-bit, and 2 to the power of 16 equals 65536. This means that if the prescaler and auto-reload register are both set to their maximum values, the maximum timer duration is 59.65 seconds, close to one minute. The STM32 timer also supports cascading, where the output of one timer is used as the input of another. Combined, the maximum timer duration is 59.65 seconds × 65536 × 65536, which is approximately over eight thousand years.

[0103] Therefore, using a single timer is insufficient to output a continuous pulse according to the PRF; a timer-linked method is required to output a continuous pulse.

[0104] The internal trigger input uses one timer as a prescaler for another timer. In hardware, the advanced control timer and the general-purpose timer are internally connected, enabling timer cascading. The master-mode timer can reset, start, stop, or clock the slave-mode timer.

[0105] This system uses timers TIM2 and TIM5 in a linked manner to achieve adjustable pulse width square wave output. The specific connection method is as follows: Figure 2 As shown, Figure 2 This is a circuit diagram illustrating the adjustable pulse width square wave output using timers TIM2 and TIM5 in a synchronized manner. Timer 5 is in master mode, with its counting clock derived from the system clock. Timer 2 is in slave mode. The timer enable operation of TIM5 serves as the trigger output signal. Figure 2 The [TRGO] and [TR1] signals trigger TIM2 and enable its counter, while simultaneously outputting a PWM waveform with adjustable frequency, duty cycle, and pulse count. The specific configuration process is as follows:

[0106] 1. Enable clock and GPIO configuration

[0107] First, the clock of the corresponding GPIO port needs to be enabled by calling the initialization function, and the pull-up / pull-down settings and output mode of the relevant IO ports need to be configured. Here, push-pull output mode is adopted. The TIM5 pin is set to PA2 and PA3 respectively, which can be used as virtual pins and not used; the TIM2 pin is PA5, which is set as the final pulse output source.

[0108] 2. Timer initialization

[0109] The timer initialization functions are called to initialize Timer 2 and Timer 5 respectively. Parameters such as the timer clock frequency and counting period (value of the Automatic Reload Register ARR) need to be set. The PWM waveform output of TIM5 serves as the trigger input for TIM2, with TIM2 configured in Trigger Slave mode. TIM5 is configured in Master mode, triggered by an internal counter, with the clock source set to the internal clock. The final output pulse signal is generated by pin PA5 of TIM2.

[0110] 3. PWM Channel Configuration

[0111] Use the CubeMX tool to configure the PWM channel of the relevant timer, specifying parameters such as the output channel number, the initial value of the pulse width, and the positive and negative polarities of the PWM waveform.

[0112] 4. Start PWM output

[0113] Finally, the hardware start output function is called to start the PWM output, enabling the timer's PWM signal generation and pin output.

[0114] The method for determining the timer division parameters and the equivalent values ​​of the comparator register in this embodiment is as follows: After the two timers have completed their basic configuration, it is also necessary to determine the timer division coefficient PSC, the autoreload value ARR, and the comparator register CRR value based on the input pulse width and repetition frequency PRF.

[0115] Based on the actual range of PRF values ​​and the latest pulse width value, the counting frequency configuration parameter of Timer 5 is PSC, therefore the counting frequency of Timer 5 is set to Ft / PSC+1;

[0116] The calculation mode is set to cumulative counting. When the calculation is full, an overflow signal is given, and the counting starts again from 0.

[0117] The clock signal is input from 16MHz. After multiple internal clock PLL conversions, the clock used by the counter is 120MHz, which is Ft=120MHz.

[0118] The timer count overflow time is determined by the configuration parameters ARR and PSC, and the overflow time is T=T=(ARR+1)*(PSC+1) / Ft.

[0119] like Figure 3 As shown, Figure 3 The flowchart illustrates the method for determining the timer division parameters and the comparison register values. The method provided in this embodiment can conveniently implement the ultrasonic pulse triggering mechanism. The specific process is as follows:

[0120] Step 1: Try setting the frequency division coefficient PSC to 1. Calculate the autoreset value (ARR) of timer 5 by setting the user-defined PRF value. The calculation formula is: ARR*(PSC+1)=Ft / PRF;

[0121] Step 2: Calculate T=(ARR+1)*(PSC+1) / Ft, and determine if its value is greater than 1s. If not, PSC+1 and return to step 1. If yes, proceed to step 3.

[0122] Step 3: After determining the PSC value, calculate and determine the counting frequency of timer 5, F=Ft / (PSC+1);

[0123] Step 4: Determine the output pulse width of Timer 5 as pulsewidth = (PSC+1)*CCR / Ft. Set the output comparator register CCR to 1 and determine if the pulse width is greater than 300ns. If it is, proceed to the next step; otherwise, increment CCR by 1. Repeat this process until the next step.

[0124] Step 5: Determine the PSC value of Timer 2, and keep it consistent with Timer 5. Timer 5 will trigger the timer, which means it will be triggered according to the input PRF value.

[0125] Step 6: Set the ARR value of Timer 2 to the maximum of 0xFFFFFFFF. The purpose of setting it to the maximum is to obtain the minimum pulse width.

[0126] Step 7: Determine the value of CCR. Calculate using a loop, first setting CCR=1;

[0127] The output pulse width of timer 2 is calculated using the formula pulsewidth=(PSC+1)*CCR / Ft. If it is within +10% of the set pulse width, it is considered suitable; otherwise, CCR+1 is applied, and the process is repeated until a suitable value is found.

[0128] This embodiment obtains an extremely narrow pulse width of approximately 5 ns from the excitation source by following the steps described above; moreover, the pulse width needs to be variable, ranging from 5 ns to 1000 ns; the pulse repetition frequency (PRF) is also adjustable, with a wide adjustment range from 100 to 80 kHz. This means that up to 80,000 excitation pulses can be generated within 1 second, which can be used in the field of ultrasonic testing.

[0129] The above-described embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention. The scope of protection of the present invention is defined by the claims.

Claims

1. A microprocessor-based variable narrow pulse and high PRF control system, comprising a main control ARM core module, a clock module, and a timer module, wherein the clock module and the timer module are respectively connected to the main control ARM core module, and the clock module serves as the timer reference clock source, characterized in that: The timer module includes at least two cascaded hardware timers, wherein the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer. The trigger output terminal of the master mode timer is connected to the trigger input terminal of the slave mode timer to form a timer linkage structure; The master mode timer is configured to control the pulse repetition frequency (PRF), and the slave mode timer is configured to control the pulse width. The division factor and auto-reload register value of the master mode timer are calculated and determined according to the following formula: (ARR+1)*(PSC+1)=Ft / PRF; Where Ft is the timer reference clock frequency, PSC represents the division factor, ARR represents the value of the auto-reload register, and PRF represents the pulse repetition frequency; The comparison register value of the slave mode timer is determined through iterative calculation, specifically including: Initialize the comparison register value; Calculate the current pulse width: pulsewidth = (PSC + 1) * CCR / Ft; Where CCR represents the value of the comparison register; pulsewidth represents the current pulse width; The iteration stops when the calculated pulse width value falls within the target pulse width range; otherwise, the CCR value is incremented and the calculation continues.

2. The microprocessor-based variable narrow pulse and high PRF control system as described in claim 1, characterized in that: The overflow time of the main mode timer is calculated according to the following formula: T = (ARR + 1) * (PSC + 1) / Ft, where T represents the overflow time of the main mode timer.

3. The microprocessor-based variable narrow pulse and high PRF control system as described in claim 1, characterized in that: The main control ARM core module adopts the Cortex-M7 core architecture; The first timer TIM5 is configured to use the system clock generated by the internal phase-locked loop as its clock source; The second timer TIM2 receives the trigger output signal TRGO of the first timer TIM5 as an enable signal; Set the prescaler PSC and auto-reload register ARR value for the first timer TIM5; Set the CCR value of the compare register of the second timer TIM2 to determine the adjustable range of the pulse width; A continuously adjustable narrow pulse signal is output from the PWM output pin of the second timer TIM2.

4. The microprocessor-based variable narrow pulse and high PRF control system as described in claim 3, characterized in that: The PWM output pin is configured in push-pull output mode, and the output signal drives the high-voltage excitation generation module.

5. The microprocessor-based variable narrow pulse and high PRF control system as described in claim 1, characterized in that: The clock module receives a reference clock from an external crystal oscillator and multiplies it to 120MHz-240MHz via a phase-locked loop.

6. The microprocessor-based variable narrow pulse and high PRF control system as described in claim 1, characterized in that: It also includes a USB communication interface module, which is configured to receive pulse width and PRF parameter setting instructions from the host computer.

7. A microprocessor-based variable narrow pulse and high PRF control method, wherein the microprocessor adopts a Cortex-M7 core architecture, characterized in that... Includes the following steps: S1: Use the first timer TIM5 as the master mode timer, and configure its clock source to be the system clock generated by the internal phase-locked loop; S2: Use the second timer TIM2 as the slave mode timer and receive the trigger output signal TRGO of the first timer TIM5 as the enable signal; S3: Set the prescaler coefficient PSC and the auto-reload register ARR value of the first timer TIM5 through the linkage configuration module, satisfying the formula: (ARR+1)×(PSC+1)=Ft / PRF, where Ft is the timer reference clock frequency and PRF is the pulse repetition frequency; S4: Dynamically set the CCR value of the comparison register of the second timer TIM2 through the pulse width calculation module to satisfy the narrow pulse width formula: pulsewidth=(PSC+1)×CCR / Ft, where the pulse width is adjustable from 5ns to 1000ns; S5: Outputs a continuously adjustable narrow pulse signal through the PWM output pin of the second timer TIM2.

8. The microprocessor-based variable narrow pulse and high PRF control method as described in claim 7, characterized in that: The configuration process for the main mode timer parameters includes: Set the initial value of the frequency division coefficient; The value of the autoreload register is calculated using ARR=Floor(Ft / (PRF*(PSC+1))). When the calculated overflow time exceeds the preset threshold, the PSC value is incremented and the ARR value is recalculated.

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