Method, device, storage medium and computer device for H.264 encoding of an image based on wavefront parallel processing

Abstract

The embodiment of the application discloses a kind of based on wavefront parallel processing to the method, device, storage medium and computer equipment of image H.264 encoding, it is related to image processing field.The application is processed adjacent macroblock line by double encoder parallelly, and respectively first buffer and second buffer are written to encoding bit stream.In macroblock line encoding completion, first buffer remaining bit stream and entropy encoding remaining bit stream are merged in real time, if the length after merging is less than 8 integer multiples, then appropriate bit stream is dynamically taken from the head of second buffer and spliced, complete code stream in line with H.264 standard is generated and outputed.After encoding is completed, the minimum splicing length is used as the offset of second buffer, continue to output byte stream, and the encoding of next macroblock line is started.The application only needs double macroblock line buffer, significantly improves the encoding speed, reduces memory occupation, and does not need to modify decoder, and compatibility is strong.

Description

Technical Field

[0001] This application relates to the field of image processing, and in particular to a method, apparatus, storage medium, and computer device for H.264 encoding of images based on wavefront parallel processing. Background Technology

[0002] H.264 (Advanced Video Coding, AVC), a video coding standard jointly developed by the International Organization for Standardization (ISO / IEC) and the International Telecommunication Union (ITU-T), is widely used in digital television, video conferencing, and streaming media transmission due to its high compression performance and broad compatibility. The H.264 standard achieves efficient compression of video data through core technologies such as intra-frame prediction, inter-frame prediction, and entropy coding. However, its coding process is essentially serial, making it difficult to fully utilize the parallel computing capabilities of modern multi-core processors or dedicated hardware accelerators.

[0003] With the continuous improvement of video resolution and frame rate (such as 4K / 8K ultra-high-definition video), traditional serial encoding methods face severe challenges in terms of processing complexity, encoding speed, and real-time performance. To improve encoding efficiency, the industry has attempted to introduce parallelization tools (such as macroblock-level parallelism, slice-level parallelism, or wavefront parallel processing (WPP)). By decomposing the encoding task into multiple subtasks and executing them in parallel, the encoding throughput can be significantly improved. However, such parallelization schemes usually require modifications to the syntax structure or encoding flow of the H.264 protocol. For example, additional parallel markers or synchronization information may be introduced into the encoded bitstream to coordinate the processing boundaries of different parallel units; the encoding order of macroblocks or slices may be changed to adapt to the needs of parallel computing; and control fields may be added to the frame header, slice header, or macroblock header to identify the parallel processing status.

[0004] While the above modifications can improve parallel performance, they will cause the encoded bitstream to not conform to the syntax specifications of the standard H.264 protocol, leading to the following problems: the modified bitstream cannot be correctly parsed by the standard H.264 decoder, resulting in decoding failure or abnormal picture; a dedicated decoder needs to be developed or existing equipment needs to be upgraded, which increases deployment costs and technical barriers.

[0005] Currently, no existing technology offers a solution for achieving efficient parallel encoding while fully adhering to the H.264 protocol syntax. Therefore, how to improve encoding efficiency using parallelization tools without modifying the H.264 standard syntax, while ensuring the compatibility and decodeability of the encoded bitstream, has become a pressing technical problem. Summary of the Invention

[0006] This application provides a method, apparatus, storage medium, and computer device for H.264 encoding of images based on wavefront parallel processing, which can solve the problem that the use of wavefront parallel processing in H.264 encoding leads to incompatibility with the existing H.264 protocol. The technical solution is as follows:

[0007] In a first aspect, embodiments of this application provide a method for H.264 encoding of images based on wavefront parallel processing, the method comprising:

[0008] Divide the image to be encoded into multiple macroblock rows;

[0009] The first encoder is used to perform H.264 encoding on the k-th macroblock line, the encoded bit stream is written into the first buffer, and then one byte of encoded bit stream is output in real time in the first buffer;

[0010] The (k+1)th macroblock line is H.264 encoded using the second encoder, and the encoded bit stream is written into the second buffer.

[0011] When the last macroblock in the k macroblock rows completes entropy coding, the remaining bit stream of the storage medium of the first buffer is obtained, and the remaining bit stream of the entropy coding of the k macroblock row is obtained. The remaining bit stream of the storage medium and the remaining bit stream of the entropy coding are merged to obtain the merged remaining bit stream.

[0012] If the length of the merged remaining bit stream is equal to 8, the merged remaining bit stream is output, and one byte of encoded bit stream is output from the head of the second buffer each time.

[0013] If the length of the merged remaining bit stream is not an integer multiple of 8, calculate the minimum splicing length such that the sum of the minimum splicing length and the length of the merged remaining bit stream is equal to the minimum integer multiple of 8. Take out the encoded bit stream from the head of the second buffer according to the minimum splicing length, splice the taken out encoded bit stream and the merged remaining bit stream to obtain the final bit stream, and output the final bit stream.

[0014] After all the encoded bit streams of the kth macroblock line are output in the first buffer, the minimum splicing length is used as the bit offset of the second buffer, and one byte of encoded bits is output in the second buffer each time according to the bit offset; and the k+2th macroblock line is encoded using the first encoder, and the encoded bits are written into the first buffer.

[0015] Secondly, embodiments of this application provide an apparatus for H.264 encoding of images based on wavefront parallel processing, the apparatus comprising:

[0016] The partitioning module is used to divide the image to be encoded into multiple macroblock rows;

[0017] The read / write control module is used to perform H.264 encoding on the kth macroblock line using the first encoder, write the encoded bit stream into the first buffer, and then output a byte of encoded bit stream in the first buffer in real time.

[0018] The read / write control module is also used to perform H.264 encoding on the (k+1)th macroblock line using the second encoder and write the encoded bit stream into the second buffer;

[0019] The bitstream splicing module is used to obtain the remaining bitstream of the storage medium of the first buffer and the remaining bitstream of the entropy encoding of the kth macroblock line when the last macroblock in the k macroblock lines is entropy encoded, and to merge the remaining bitstream of the storage medium and the remaining bitstream of the entropy encoding to obtain a merged remaining bitstream.

[0020] The bitstream splicing module is also used to output the merged remaining bitstream if the length of the merged remaining bitstream is equal to 8, and output one byte of encoded bitstream from the head of the second buffer each time.

[0021] The bitstream splicing module is further configured to calculate a minimum splicing length if the length of the merged remaining bitstream is not an integer multiple of 8, such that the sum of the minimum splicing length and the length of the merged remaining bitstream is equal to a minimum integer multiple of 8; extract the encoded bitstream from the head of the second buffer according to the minimum splicing length; splice the extracted encoded bitstream and the merged remaining bitstream to obtain the final bitstream; and output the final bitstream.

[0022] The read / write control module is further configured to, after all the encoded bit streams of the kth macroblock line in the first buffer are output, use the minimum splicing length as the bit offset of the second buffer, and output one byte of encoded bits in the second buffer each time according to the bit offset; and encode the (k+2)th macroblock line using the first encoder, and write the encoded bits into the first buffer.

[0023] Thirdly, embodiments of this application provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the above-described method steps.

[0024] Fourthly, embodiments of this application provide a computer device, which may include: a processor and a memory; wherein the memory stores a computer program, the computer program being adapted to be loaded by the processor and to execute the above-described method steps.

[0025] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0026] The bitstream splicing technology proposed in this application is specifically designed for a dual-core wavefront parallel coding algorithm. By using a first encoder and a second encoder to encode adjacent macroblock lines in parallel, the coding efficiency is significantly improved. The device in this application is entirely implemented by programmable logic (PL), avoiding the delays caused by software intervention in traditional schemes and further accelerating the coding output speed.

[0027] This application achieves efficient output of the encoded bitstream by outputting a one-byte encoded bitstream in real time and rapidly merging the remaining bitstream when the macroblock line encoding is complete. In particular, when processing the merging of the remaining bitstream, the continuity and real-time performance of the bitstream are ensured by calculating the minimum splicing length and dynamically adjusting the length of the bitstream taken from the second buffer, thereby significantly improving the overall encoding output speed.

[0028] This application requires only two macroblock line (MB) buffers to achieve real-time byte realignment and concatenation operations, significantly reducing memory consumption compared to traditional solutions that require larger buffers. This not only lowers hardware costs but also improves the overall energy efficiency of the system.

[0029] The bitstream splicing technology in this application ensures that the generated bitstream fully conforms to the H.264 standard through precise byte realignment and splicing operations without modifying the H.264 decoder. This means that the decoder can seamlessly parse the bitstream generated by this application without any special processing or modification, thus guaranteeing the compatibility and universality of the bitstream.

[0030] By dynamically calculating the minimum concatenation length and retrieving the encoded bitstream from the second buffer according to this length for concatenation, this application achieves flexibility in real-time byte realignment and concatenation operations. This flexibility allows this application to adapt to the needs of different encoding scenarios, such as different macroblock line sizes and different encoding rates, thereby improving the system's adaptability and robustness. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the system architecture provided in the embodiments of this application;

[0033] Figure 2This is a flowchart illustrating the method for H.264 encoding of images based on wavefront parallel processing provided in this application embodiment;

[0034] Figure 3 This is a schematic diagram illustrating the principle of bitstream splicing provided in the embodiments of this application;

[0035] Figure 4 This is a schematic diagram of the structure of a device for H.264 encoding of images based on wavefront parallel processing provided in this application;

[0036] Figure 5 This is a schematic diagram of the structure of a computer device provided in this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0038] It should be noted that the method for H.264 encoding of images based on wavefront parallel processing provided in this application is generally executed by computer equipment, and correspondingly, the device for H.264 encoding of images based on wavefront parallel processing is generally located in computer equipment.

[0039] Figure 1 An exemplary system architecture is shown that can be applied to the method or apparatus for H.264 encoding of images based on wavefront parallel processing, which is applicable to this application.

[0040] like Figure 1 As shown, the system architecture may include: a controller ( Figure 1 (Not shown in the diagram) First encoder, second encoder, first buffer, second buffer, and bitstream splicing module. The controller controls the first encoder, second encoder, first buffer, second buffer, and bitstream splicing module. The first buffer and second buffer can be located inside the bitstream splicing module. The first buffer and second buffer can be set separately or set in the same chip. The first buffer and second buffer can be BRAM (Block Random Access Memory).

[0041] Each module in the system architecture can be implemented using at least one hardware form of Field-Programmable Gate Array (FPGA) or Programmable Logic Array (PLA).

[0042] The image to be encoded is divided into multiple macroblock rows, each macroblock row containing multiple macroblocks. A first encoder and a second encoder perform H.264 encoding on adjacent macroblock rows in parallel and alternately, with a certain time delay between the first encoder and the second encoder. A first buffer stores the encoded bitstream generated by the first encoder, and a second buffer stores the encoded bitstream generated by the second encoder. A bitstream concatenation module concatenates the encoded bitstreams from the first buffer and the second buffer to obtain a bitstream conforming to the standard H.264 protocol.

[0043] The computer devices covered by this application include, but are not limited to, smartphones, tablets, laptops, and desktop computers.

[0044] It should be understood that Figure 1 The number of units and modules shown is for illustrative purposes only. The number can be arbitrary, depending on implementation needs.

[0045] The following will be combined with the appendix Figure 2 This application provides a detailed description of the method for H.264 encoding of images based on wavefront parallel processing, as provided in the embodiments of this application. The apparatus for H.264 encoding of images based on wavefront parallel processing in the embodiments of this application can be... Figure 1 The computer equipment shown.

[0046] Please see Figure 2 This document provides a flowchart illustrating a method for H.264 encoding of images based on wavefront parallel processing, as described in an embodiment of this application. Figure 2 As shown, the method described in this application embodiment may include the following steps:

[0047] S201. Divide the image to be encoded into multiple macroblock rows.

[0048] The computer equipment first divides the image to be encoded horizontally into multiple macroblock rows, each macroblock row containing several macroblocks. A macroblock is the basic unit of H.264 encoding, typically a 16×16 pixel luma block and its corresponding chroma block. During division, it must be ensured that the width of the macroblock row is the same as the image width, and the height is an integer multiple of the macroblock height (e.g., a multiple of 16 pixels).

[0049] S202. Use the first encoder to perform H.264 encoding on the k-th macroblock line, write the encoded bit stream into the first buffer, and then output a byte of encoded bit stream in real time in the first buffer.

[0050] Here, k is an integer greater than or equal to 1. The computer device starts the first encoder (such as an example of an H.264 encoder) to encode the k-th macroblock line, generating a compressed bitstream. The encoding process includes steps such as intra / inter-frame prediction, transform quantization, and entropy coding. The encoded bitstream is written to the first buffer (Buffer 1), and the buffer outputs the bitstream in real time in bytes (8 bits) to ensure low latency.

[0051] S203. Use the second encoder to perform H.264 encoding on the (k+1)th macroblock line and write the encoded bit stream into the second buffer.

[0052] While the first encoder processes the k-th macroblock line, the computer device starts the second encoder to encode the (k+1)-th macroblock line in parallel, and the generated bitstream is written to the second buffer (Buffer 2). The second buffer only stores data and does not output it temporarily, waiting for subsequent synchronization operations.

[0053] S204. When the last macroblock in the k macroblock rows completes entropy encoding, obtain the remaining bit stream of the storage medium of the first buffer and the remaining bit stream of the entropy encoding of the kth macroblock row. Merge the remaining bit stream of the storage medium and the remaining bit stream of the entropy encoding to obtain the merged remaining bit stream.

[0054] When the last macroblock of the k-th macroblock line is entropy encoded, the computer device extracts the remaining unoutput bit stream (which may be less than 8 bits) from the first buffer and the entropy encoder respectively, and merges the two into a continuous bit stream to ensure that all unoutput bits are preserved.

[0055] In some possible embodiments of this application, the encoder tracks the index of the currently encoded macroblock line in real time (e.g., via an internal counter or status register) while processing macroblock lines one by one. When the last macroblock in the k-th macroblock line is encoded (e.g., entropy encoding is completed, and the final bitstream is generated), the encoder determines that the macroblock line encoding is complete. The encoder triggers the generation of a completion notification message through a hardware signal or software interrupt, ensuring that the notification is strictly synchronized with the encoding completion event.

[0056] The completion notification message contains the following key information:

[0057] Macroblock line index: Explicitly identifies the k-th macroblock line (e.g., by the numeric k or a unique identifier).

[0058] Timestamp: Records the time when the coding was completed (optional, used for debugging or synchronization).

[0059] Verification information: such as CRC checksum, to ensure that the message has not been tampered with during transmission.

[0060] Messages are transmitted to subsequent processing modules (such as buffer management units or output controllers) via the computer device's internal bus (e.g., PCIe, AXI) or shared memory area. The computer device enables efficient collaboration between the encoder and subsequent modules, ensuring accurate notification and timely processing of macroblock line encoding completion, making it suitable for video encoding systems with high real-time requirements.

[0061] S205. If the length of the merged remaining bit stream is equal to 8, the merged remaining bit stream will be output, and one byte of encoded bit stream will be output from the head of the second buffer each time.

[0062] If the length of the remaining bitstream after merging is exactly a multiple of 8 (such as 8, 16, etc.), the computer device directly outputs the bitstream and begins to output the encoded data of the (k+1)th macroblock line byte by byte from the head of the second buffer, achieving seamless connection.

[0063] S206. If the length of the merged remaining bit stream is not an integer multiple of 8, calculate the minimum splicing length such that the sum of the minimum splicing length and the length of the merged remaining bit stream is equal to the minimum integer multiple of 8. Take out the encoded bit stream from the head of the second buffer according to the minimum splicing length, splice the taken-out encoded bit stream and the merged remaining bit stream to obtain the final bit stream, and output the final bit stream.

[0064] If the length of the remaining bitstream after merging is less than 8 or not a multiple of 8 (such as 7 or 9 bits), the computer calculates the number of bits (such as 1 bit or 7 bits) that need to be added from the second buffer to make the total length a multiple of 8. Then, the corresponding length of the bitstream is taken from the head of Buffer 2, concatenated with the remaining bitstream, and output.

[0065] For example:

[0066] The remaining bitstream is merged to 1011100 (7 bits), which needs to be padded with 1 bit. Take 1 from the beginning of Buffer 2 and concatenate it to output 10111001 (8 bits).

[0067] The remaining value after merging is 101110000 (9 bits), which needs to be padded with 7 bits. Take 1010101 from Buffer 2 and concatenate it to get 1011100001010101.

[0068] In some embodiments of this application, when the length L of the merged remaining bitstream is... remain When the length is not a multiple of 8, the minimum splicing length L needs to be calculated. pad , so that:

[0069] L remain +L pad =8×n (n∈N+,n≥1), where n is the smallest positive integer that satisfies the condition.

[0070] The minimum splicing length L is calculated using the following formula. pad =8-(L) remain mod8)

[0071] Example 1: L remain =7 (e.g., 1011100), L pad =8-(7mod8)=8-7=1, so 1 bit needs to be added from the second buffer (e.g., 1), and the result after splicing is 10111001 (8 bits).

[0072] Example 2: L remain =9 (e.g., 101110000), L pad =8-(9mod8)=8-1=7, so 7 bits need to be added from the second buffer (e.g., 1010101), and the result after splicing is 1011100001010101.

[0073] Example 3: L remain =15 (e.g., 101110000101111), L pad =8-(15mod8)=8-7=1, so 1 bit (e.g., 0) needs to be added from the second buffer. After concatenation, it becomes 1011100001011110 (16 bits, first output the first 8 bits 10111000, then output the remaining 8 bits of data).

[0074] It should be noted that the length of the concatenated bitstream is 8×n, but in actual output, only the first 8 bits may be output (as in Example 3), with the remaining parts to be processed in subsequent steps. After concatenation, the offset of the second buffer should be increased by L. pad This ensures that subsequent outputs start from the correct position.

[0075] S207. After all the encoded bit streams of the kth macroblock line are output in the first buffer, the minimum splicing length is used as the bit offset of the second buffer, and one byte of encoded bits is output in the second buffer each time according to the bit offset; and the k+2th macroblock line is encoded using the first encoder, and the encoded bits are written into the first buffer.

[0076] In this process, after all the data for the k-th macroblock line is output from Buffer 1, the computer uses the previous minimum concatenation length (e.g., 1 or 7 bits) as the offset for Buffer 2, skips the used bits, and outputs the data in Buffer 2 byte by byte from the offset position. At the same time, the first encoder starts processing the (k+2)-th macroblock line, and the encoding result is written to Buffer 1, realizing the alternating operation of the two buffers.

[0077] For example: If the minimum concatenation length is 1 bit, and the original data in Buffer 2 is 1010101011001100..., after skipping the first bit, the output starts from the second bit 01010101. The first encoder then encodes the (k+2)th line and writes the result to Buffer 1.

[0078] See Figure 3 The diagram illustrates the encoding principle of this application. The first buffer i stores the encoded bits of the k-th macroblock row, and the second buffer j stores the encoded bits of the (k+1)-th macroblock row. After encoding a macroblock in the k-th macroblock row, the first encoder writes the encoded bits into the first buffer i. Then, it outputs encoded bits a1b1 from the first buffer i in real-time, byte by byte. When the last macroblock in the k-th macroblock row completes entropy encoding, it obtains the remaining bit stream a3 from the storage medium in the first buffer i, and the remaining entropy encoded bits c. After merging, it obtains the merged remaining bits a3c. The merged remaining bits are not a multiple of 8 and are less than 8. At this time, encoded bits b3 are taken from the head of the second buffer j and merged to obtain a3cb3. The merged bits are equal to 8. The merged bits are output, and the bit offset of the second buffer j is set to the length of b3. One byte is taken from the second buffer j for output each time.

[0079] In some possible embodiments of this application, when data needs to be read from the first buffer or the second buffer and the unread data is greater than 2 bytes, a minimum 2-byte interval is always maintained between the read pointer and the write pointer. This interval is enforced by hardware or software logic to ensure that the read pointer does not catch up with the write pointer, thus avoiding data overwriting or race conditions.

[0080] The 2-byte interval allows the correct byte data to be retrieved even when there is an offset during reading.

[0081] The controller writes 1 byte of valid data to the buffer each time. The write pointer increments by 1 byte each time, pointing to the next writable location.

[0082] The computer device reads 2 bytes of data from the buffer at a time (current read pointer position and next position). After reading, only 1 byte of valid data is extracted, and then the read pointer is incremented by only 1 byte. The interval between read and write pointers is monitored by a hardware counter or software state machine. If the interval is less than 2 bytes, a blocking or waiting mechanism is triggered until the write pointer moves forward.

[0083] In some possible embodiments of this application, a start flag is set in the encoding bits of the first macroblock of the k macroblock rows, and an end flag is set in the encoding bits of the last macroblock; the encoding bit stream of the k macroblock rows in the first buffer is determined to be completely output based on the start flag and the end flag.

[0084] In the encoded bitstream of the first macroblock in the k-th macroblock row, a start flag bit is embedded using a specific bit pattern (such as 0x01 or 0b1010).

[0085] Flags are typically located in reserved fields in the macroblock header or as dedicated bits extended by the protocol to ensure that they do not interfere with the original encoded data (such as the NAL unit structure of H.264).

[0086] End Flag: An end flag (such as 0x02 or 0b1100) is embedded in the encoded bitstream of the last macroblock in the k-th macroblock line through a similar mechanism.

[0087] The flag bit needs to be distinguished from the start flag bit to avoid misjudgment (e.g., by using different bit sequences or positions).

[0088] The computer device reads the encoded bitstream byte by byte from the first buffer and tracks the currently processed macroblock using a state machine or parser. The parser locates the boundaries of the first and last macroblocks based on macroblock header information (such as macroblock type and size). When parsing the first macroblock, it checks for a predefined start flag in its bitstream. When parsing the last macroblock, it checks for a predefined end flag in its bitstream. Flag matching can be achieved through bit-by-bit comparison or hash verification, ensuring high accuracy.

[0089] Computer equipment maintenance has two status flags:

[0090] start_flag_detected: Initially False, it is set to True after the start flag is detected.

[0091] end_flag_detected: Initially False, it is set to True after the end flag is detected.

[0092] The encoded bitstream of the k-th macroblock line is considered to have been completely output only if both start_flag_detected and end_flag_detected are True. If only the start flag is detected but the end flag is not, the data is considered incomplete, and subsequent data must be waited for or a retransmission must be triggered.

[0093] If no start flag is detected, the current buffer data is discarded, and the system waits for the start flag of the next macroblock line. If no end flag is detected, but the buffer has reached the end, a timeout mechanism is triggered or the encoder is requested to retransmit the data. The validity of the flags is verified using redundancy checks (such as CRC) to avoid misjudgments due to bit errors. If the flag verification fails, the current flag is ignored, and subsequent data parsing continues.

[0094] In this embodiment, start and end flags provide clear macroblock line boundary identifiers, ensuring the integrity and correctness of the encoded bitstream. Using these flags to quickly locate macroblock line boundaries reduces unnecessary buffer traversal and improves processing efficiency. Fault tolerance mechanisms and redundancy checks reduce the risk of data loss or errors, making it suitable for unreliable transmission environments.

[0095] This application includes the following beneficial effects:

[0096] The bitstream splicing technology proposed in this application is specifically designed for a dual-core wavefront parallel coding algorithm. By using a first encoder and a second encoder to encode adjacent macroblock lines in parallel, the coding efficiency is significantly improved. The device in this application is entirely implemented by programmable logic (PL), avoiding the delays caused by software intervention in traditional schemes and further accelerating the coding output speed.

[0097] This application achieves efficient output of the encoded bitstream by outputting a one-byte encoded bitstream in real time and rapidly merging the remaining bitstream when the macroblock line encoding is complete. In particular, when processing the merging of the remaining bitstream, the continuity and real-time performance of the bitstream are ensured by calculating the minimum splicing length and dynamically adjusting the length of the bitstream taken from the second buffer, thereby significantly improving the overall encoding output speed.

[0098] This application requires only two macroblock line (MB) buffers to achieve real-time byte realignment and concatenation operations, significantly reducing memory consumption compared to traditional solutions that require larger buffers. This not only lowers hardware costs but also improves the overall energy efficiency of the system.

[0099] The bitstream splicing technology in this application ensures that the generated bitstream fully conforms to the H.264 standard through precise byte realignment and splicing operations without modifying the H.264 decoder. This means that the decoder can seamlessly parse the bitstream generated by this application without any special processing or modification, thus guaranteeing the compatibility and universality of the bitstream.

[0100] By dynamically calculating the minimum concatenation length and retrieving the encoded bitstream from the second buffer according to this length for concatenation, this application achieves flexibility in real-time byte realignment and concatenation operations. This flexibility allows this application to adapt to the needs of different encoding scenarios, such as different macroblock line sizes and different encoding rates, thereby improving the system's adaptability and robustness.

[0101] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0102] Please see Figure 4 This illustration shows a schematic diagram of an apparatus for H.264 encoding of images based on wavefront parallel processing, provided in an exemplary embodiment of this application, hereinafter referred to as apparatus 4. Apparatus 4 can be implemented as all or part of a computer device through software, hardware, or a combination of both. Apparatus 4 includes: a partitioning unit 401, a read / write control unit 402, and a bitstream splicing unit 403.

[0103] The partitioning module 401 is used to divide the image to be encoded into multiple macroblock rows;

[0104] The read / write control module 402 is used to perform H.264 encoding on the kth macroblock line using the first encoder, write the encoded bit stream into the first buffer, and then output a byte of encoded bit stream in the first buffer in real time.

[0105] The read / write control module 402 is also used to perform H.264 encoding on the (k+1)th macroblock line using the second encoder and write the encoded bit stream into the second buffer;

[0106] The bitstream splicing module 403 is used to obtain the remaining bitstream of the storage medium of the first buffer and the remaining bitstream of the entropy encoding of the kth macroblock line when the last macroblock in the k macroblock line completes entropy encoding, and to merge the remaining bitstream of the storage medium and the remaining bitstream of the entropy encoding to obtain a merged remaining bitstream.

[0107] The bitstream splicing module 403 is also used to output the merged remaining bitstream if the length of the merged remaining bitstream is equal to 8, and output one byte of encoded bitstream from the head of the second buffer each time.

[0108] The bitstream splicing module 403 is further configured to calculate a minimum splicing length if the length of the merged remaining bitstream is not an integer multiple of 8, such that the sum of the minimum splicing length and the length of the merged remaining bitstream is equal to a minimum integer multiple of 8, extract the encoded bitstream from the head of the second buffer according to the minimum splicing length, splice the extracted encoded bitstream and the merged remaining bitstream to obtain the final bitstream, and output the final bitstream;

[0109] The read / write control module 402 is further configured to, after all the encoded bit streams of the kth macroblock line in the first buffer are output, use the minimum splicing length as the bit offset of the second buffer, and output one byte of encoded bits in the second buffer each time according to the bit offset; and use the first encoder to encode the (k+2)th macroblock line, and write the encoded bits into the first buffer.

[0110] In one or more possible embodiments, the interval between the read pointer and the write pointer of the first buffer and the second buffer is 2 bytes.

[0111] In one or more possible embodiments, the first buffer and the second buffer are block random access memories.

[0112] In one or more possible embodiments, the resolution of each macroblock in a macroblock row is 16*16.

[0113] In one or more possible embodiments, calculating the minimum splice length includes:

[0114] L pad =8-(L) remain mod 8), Lpad represents the minimum splicing length, L remain This indicates the length of the remaining bit stream, and mod represents the modulo operation.

[0115] In one or more possible embodiments, the encoder sends a completion notification message when the last macroblock in the k macroblock lines is completed, the completion notification message indicating that the kth macroblock line has been completed.

[0116] In one or more possible embodiments, a start flag is set in the encoding bits of the first macroblock of the k macroblock rows, and an end flag is set in the encoding bits of the last macroblock; the entire encoded bit stream of the k macroblock rows in the first buffer is determined to be output based on the start flag and the end flag.

[0117] It should be noted that the apparatus 4 provided in the above embodiments, when executing the method for H.264 encoding of images based on wavefront parallel processing, is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the above functions. In addition, the apparatus for H.264 encoding of images based on wavefront parallel processing provided in the above embodiments and the method embodiment for H.264 encoding of images based on wavefront parallel processing belong to the same concept, and the implementation process is detailed in the method embodiment, which will not be repeated here.

[0118] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0119] This application also provides a computer storage medium that can store multiple instructions, which are adapted to be loaded and executed by a processor as described above. Figure 2 The method steps of the illustrated embodiment can be found in the following documentation for detailed execution. Figure 2 The specific details of the illustrated embodiments will not be elaborated here.

[0120] This application also provides a computer program product storing at least one instruction, which is loaded and executed by the processor to implement the method for H.264 encoding of images based on wavefront parallel processing as described in the above embodiments.

[0121] Please see Figure 5 This document provides a schematic diagram of the structure of a computer device according to an embodiment of this application. Figure 5 As shown, the computer device 500 may include: at least one processor 501, at least one network interface 504, user interface 503, memory 505, and at least one communication bus 502.

[0122] The communication bus 502 is used to enable communication between these components.

[0123] The user interface 503 may include a display screen and a camera. Optionally, the user interface 503 may also include a standard wired interface and a wireless interface.

[0124] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0125] The processor 501 may include one or more processing cores. The processor 501 connects to various parts within the computer device 500 using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 505, and by calling data stored in the memory 505. Optionally, the processor 501 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 501 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip, without being integrated into the processor 501.

[0126] The memory 505 may include random access memory (RAM) or read-only memory. Optionally, the memory 505 may include a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 505 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 505 may also be at least one storage device located remotely from the aforementioned processor 501. Figure 5 As shown, the memory 505, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.

[0127] exist Figure 5In the computer device 500 shown, the user interface 503 is mainly used to provide an input interface for the user and to obtain the user's input data; while the processor 501 can be used to call the application program stored in the memory 505 and specifically execute, such as Figure 2 The method shown can be referred to for details. Figure 2 As shown, it will not be elaborated further here.

[0128] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0129] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A method for H.264 encoding of images based on wavefront parallel processing, characterized in that, include: Divide the image to be encoded into multiple macroblock rows; The first encoder is used to perform H.264 encoding on the k-th macroblock line, the encoded bit stream is written into the first buffer, and then one byte of encoded bit stream is output in real time in the first buffer; The (k+1)th macroblock line is H.264 encoded using the second encoder, and the encoded bit stream is written into the second buffer. When the last macroblock in the k macroblock rows completes entropy coding, the remaining bit stream of the storage medium of the first buffer is obtained, and the remaining bit stream of the entropy coding of the k macroblock row is obtained. The remaining bit stream of the storage medium and the remaining bit stream of the entropy coding are merged to obtain the merged remaining bit stream. If the length of the merged remaining bit stream is equal to 8, the merged remaining bit stream is output, and one byte of encoded bit stream is output from the head of the second buffer each time. If the length of the merged remaining bit stream is not an integer multiple of 8, calculate the minimum splicing length such that the sum of the minimum splicing length and the length of the merged remaining bit stream is equal to the minimum integer multiple of 8. Take out the encoded bit stream from the head of the second buffer according to the minimum splicing length, splice the taken out encoded bit stream and the merged remaining bit stream to obtain the final bit stream, and output the final bit stream. After all the encoded bit streams of the kth macroblock line are output in the first buffer, the minimum splicing length is used as the bit offset of the second buffer, and one byte of encoded bits is output in the second buffer each time according to the bit offset; and the k+2th macroblock line is encoded using the first encoder, and the encoded bits are written into the first buffer.

2. The method according to claim 1, characterized in that, The minimum interval between the read pointer and write pointer of the first buffer and the second buffer during the reading phase is 2 bytes.

3. The method according to claim 1 or 2, characterized in that, The first buffer and the second buffer are block random access memory.

4. The method according to claim 3, characterized in that, The resolution of each macroblock in a macroblock row is 16*16.

5. The method according to claim 1, 2, or 4, characterized in that, The calculation of the minimum splicing length includes: L pad =8-(L) remain mod 8), L pad L represents the minimum splicing length. remain This indicates the length of the remaining bit stream, and mod represents the modulo operation.

6. The method according to claim 5, characterized in that, When the encoder finishes encoding the last macroblock in the k macroblock lines, it sends a completion notification message, which indicates that the kth macroblock line has finished encoding.

7. The method according to claim 1, 2, 4, or 6, characterized in that, The first macroblock of the k macroblock rows has a start flag bit in its encoding bits, and the last macroblock has an end flag bit in its encoding bits; based on the start flag bit and the end flag bit, the entire encoded bit stream of the k macroblock rows in the first buffer is output.

8. An apparatus for H.264 encoding of images based on wavefront parallel processing, characterized in that, include: The partitioning module is used to divide the image to be encoded into multiple macroblock rows; The read / write control module is used to perform H.264 encoding on the kth macroblock line using the first encoder, write the encoded bit stream into the first buffer, and then output a byte of encoded bit stream in the first buffer in real time. The read / write control module is also used to perform H.264 encoding on the (k+1)th macroblock line using the second encoder and write the encoded bit stream into the second buffer; The bitstream splicing module is used to obtain the remaining bitstream of the storage medium of the first buffer and the remaining bitstream of the entropy encoding of the kth macroblock line when the last macroblock in the k macroblock line is entropy encoded, and to merge the remaining bitstream of the storage medium and the remaining bitstream of the entropy encoding to obtain a merged remaining bitstream. The bitstream splicing module is also used to output the merged remaining bitstream if the length of the merged remaining bitstream is equal to 8, and output one byte of encoded bitstream from the head of the second buffer each time. The bitstream splicing module is further configured to calculate a minimum splicing length if the length of the merged remaining bitstream is not an integer multiple of 8, such that the sum of the minimum splicing length and the length of the merged remaining bitstream is equal to a minimum integer multiple of 8; extract the encoded bitstream from the head of the second buffer according to the minimum splicing length; splice the extracted encoded bitstream and the merged remaining bitstream to obtain the final bitstream; and output the final bitstream. The read / write control module is further configured to, after all the encoded bit streams of the kth macroblock line in the first buffer are output, use the minimum splicing length as the bit offset of the second buffer, and output one byte of encoded bits in the second buffer each time according to the bit offset; and encode the (k+2)th macroblock line using the first encoder, and write the encoded bits into the first buffer.

9. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions, which are adapted to be loaded by a processor and executed as method steps as claimed in any one of claims 1 to 7.

10. A computer device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed the method steps as claimed in any one of claims 1 to 7.

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