A silicon carbide power device and its fabrication method, chip

Abstract

This application belongs to the field of power device technology and provides a silicon carbide power device and its fabrication method and chip. By setting multiple P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating islands helps to reduce the capacitance between the first electrode layer and the gate in the device, thereby improving the switching characteristics of the device. Furthermore, in the case of a shallow P-type well region and a deep doped current extension region, the trade-off between breakdown voltage and on-resistance can be effectively balanced, so that the on-resistance is optimized without affecting the breakdown voltage, thus meeting the performance requirements of high-power applications.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and particularly relates to a silicon carbide power device and its preparation method and chip. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, possesses advantages such as a wide bandgap, high critical breakdown electric field, and high saturation drift velocity, enabling SiC power devices to exhibit unique advantages in high-voltage, high-power, and high-frequency applications. However, existing SiC planar MOS device structures still have room for optimization in terms of the trade-off between on-resistance and breakdown voltage. To improve device integration density and performance, researchers have proposed various improvement schemes, such as employing embedded gate structures and optimizing channel distribution.

[0003] However, existing SiC MOS devices still have some issues regarding short-circuit performance and reliability. Particularly under high current conditions, the devices are prone to thermal failure, affecting their long-term stability. Furthermore, traditional SiC MOS device structures struggle to simultaneously achieve low on-resistance (Ron) and high breakdown voltage (BV), limiting their widespread adoption in high-power applications. Therefore, developing a novel SiC planar MOS structure that optimizes on-resistance and improves short-circuit withstand capability without compromising the device's breakdown voltage performance is of great significance. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a silicon carbide power device and its fabrication method and chip, which can optimize on-resistance and improve short-circuit withstand capability without affecting the device's withstand voltage performance.

[0005] The first aspect of this application provides a silicon carbide power device, which includes: a silicon carbide substrate, a first electrode layer, an N-type drift region, a P-type floating island, a top epitaxial region, a current spread region, an N-type heavily doped region, a P-type well region, a P-type heavily doped region, a gate dielectric layer, a gate layer, and a second electrode layer.

[0006] The first electrode layer is located on the back side of the silicon carbide substrate, the N-type drift region is located on the front side of the silicon carbide substrate, and a plurality of P-type floating islands are disposed between the N-type drift region and the top epitaxial region;

[0007] The current extension region, the P-type well region, and the heavily doped P-type region are located on the top epitaxial region, and the heavily doped P-type region and the P-type well region are provided on both sides of the current extension region. The P-type well region is located between the heavily doped P-type region and the current extension region. The depth of the current extension region is greater than the depth of the P-type well region. The doping concentration of the P-type well region is less than the doping concentration of the heavily doped P-type region. The doping concentration of the current extension region is greater than the doping concentration of the top epitaxial region.

[0008] The N-type heavily doped region is formed on the horizontal portion of the P-type well region. The gate dielectric layer is located on the N-type heavily doped region, the P-type well region, and the current extension region. The gate dielectric layer encapsulates the gate layer. The second electrode layer covers the gate dielectric layer and is in contact with the N-type heavily doped region and the P-type heavily doped region.

[0009] In some embodiments, the gate dielectric layer includes a plurality of gate layers, the plurality of gate layers are isolated from each other by the gate dielectric layer, and at least two of the gate layers are disposed opposite to the vertical portions of the P-type well regions on both sides of the current extension region.

[0010] In some embodiments, a P-type shallow doped region is provided between the current extension region and the gate dielectric layer, the P-type shallow doped region being in contact with the gate dielectric layer and located within the groove of the current extension region.

[0011] In some embodiments, the current extension region has a concave structure, and a portion of the protrusions of the gate dielectric layer fill the groove of the current extension region.

[0012] In some embodiments, the top epitaxial region has a concave structure, and the doping concentration of the top epitaxial region is different from that of the N-type drift region.

[0013] In some embodiments, the width of the P-type floating island is equal to or greater than the width of the current extension region; at least one P-type floating island is disposed opposite to the current extension region, and at least two P-type floating islands are disposed opposite to the heavily doped P-type regions on both sides of the current extension region.

[0014] In some embodiments, the silicon carbide substrate is P-type doped, and an N-type buffer layer is further disposed between the silicon carbide substrate and the N-type drift region.

[0015] A second aspect of this application also provides a method for fabricating a silicon carbide power device, the method comprising:

[0016] An N-type drift region is formed on a silicon carbide substrate, and multiple regions on the N-type drift region are implanted with P-type ions to form multiple P-type floating islands;

[0017] A secondary epitaxial growth process is performed to form a top epitaxial region, and the top epitaxial region is etched to make it a concave structure.

[0018] A current extension region, an N-type heavily doped region, a P-type well region, and a P-type heavily doped region are formed using a self-aligned process; wherein the current extension region, the P-type well region, and the P-type heavily doped region are located on the top epitaxial region, and the P-type heavily doped region and the P-type well region are provided on both sides of the current extension region, with the P-type well region located between the P-type heavily doped region and the current extension region;

[0019] A gate dielectric layer is formed on the N-type heavily doped region, P-type well region, and current extension region, and a gate layer is formed by polysilicon deposition, so that the gate dielectric layer encapsulates the gate layer.

[0020] A first electrode layer is formed on the back side of the silicon carbide substrate, and a second electrode layer is formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region.

[0021] In some embodiments, forming an N-type drift region on a silicon carbide substrate includes:

[0022] An N-type buffer layer is formed on a silicon carbide substrate, and an N-type drift region is formed on the N-type buffer layer.

[0023] A third aspect of this application also provides a chip, the chip comprising a silicon carbide power device as described in any of the preceding embodiments.

[0024] The beneficial effects of the embodiments of this application are as follows: By providing multiple P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be strengthened. At the same time, the self-depletion effect of the P-type floating islands helps to reduce the capacitance between the first electrode layer and the gate in the device, thereby improving the switching characteristics of the device. Furthermore, in the case of a shallower P-type well region and a deeper doped current extension region, the trade-off between breakdown voltage and on-resistance can be effectively balanced, so that the on-resistance of the device is optimized without affecting the breakdown voltage, thus meeting the performance requirements of high-power applications. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0032] Figure 8 This is a schematic flowchart of a method for fabricating a silicon carbide power device according to an embodiment of this application;

[0033] Figure 9 This is a schematic diagram of some steps in a method for fabricating a silicon carbide power device provided in an embodiment of this application. Detailed Implementation

[0034] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0035] Existing SiC MOS devices still have some issues regarding short-circuit performance and reliability. Particularly under high current conditions, the devices are prone to thermal failure, affecting their long-term stability. Furthermore, traditional SiC MOS device structures struggle to simultaneously achieve low on-resistance (Ron) and high breakdown voltage (BV), limiting their widespread adoption in high-power applications. Therefore, developing a novel SiC planar MOS structure that optimizes on-resistance and improves short-circuit withstand capability without compromising the device's breakdown voltage performance is of great significance.

[0036] To address the aforementioned technical problems, this application provides a silicon carbide power device, see [link to relevant documentation]. Figure 1 As shown, the silicon carbide power device in this embodiment includes: a silicon carbide substrate 110, a first electrode layer 510, an N-type drift region 120, a P-type floating island 210, a top epitaxial region 130, a current extension region 310, an N-type heavily doped region 340, a P-type well region 320, a P-type heavily doped region 330, a gate dielectric layer 410, a gate layer 420, and a second electrode layer 520.

[0037] The first electrode layer 510 is located on the back side of the silicon carbide substrate 110, and the N-type drift region 120 is located on the front side of the silicon carbide substrate 110. Multiple P-type floating islands 210 are disposed between the N-type drift region 120 and the top epitaxial region 130. The current extension region 310, the P-type well region 320, and the heavily doped P-type region 330 are located on the top epitaxial region 130. A heavily doped P-type region 330 and a P-type well region 320 are disposed on both sides of the current extension region 310. The P-type well region 320 is located between the heavily doped P-type region 330 and the current extension region 310. The depth of the current extension region 310 is greater than the depth of the P-type well region 320. The P-type well region 320 has an L-shaped structure, and the vertical part of the P-type well region 320 is in contact with the current extension region 310. The N-type heavily doped region 340 is formed on the horizontal part of the P-type well region 320. The gate dielectric layer 410 is located on the N-type heavily doped region, the P-type well region 320, and the current extension region 310, and the gate dielectric layer 410 wraps the gate layer 420. The second electrode layer 520 covers the gate dielectric layer 410 and is in contact with the N-type heavily doped region 340 and the P-type heavily doped region 330.

[0038] In this embodiment, the P-type well region 320 is shallowly doped, while the current extension region 310 is N-type doped and deeply doped. The doping concentration of the P-type well region 320 is less than that of the heavily doped P-type region 330, and the doping concentration of the current extension region 310 is greater than that of the top epitaxial region 130. By setting multiple P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be strengthened. At the same time, the self-depletion effect of the P-type floating islands 210 helps to reduce the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device. Furthermore, the depth of the current extension region 310 exceeds the depth of the P-type well region 320, which can effectively balance the trade-off between breakdown voltage and on-resistance in the case of a shallower P-type well region 320 and a deeper doped current extension region 310. This allows the device to optimize the on-resistance without affecting the breakdown voltage, thus meeting the performance requirements of high-power applications. The structural design in this embodiment not only reduces the device area by 8-10% under the same on-resistance specifications, thus lowering chip costs, but also improves the device's withstand voltage, conduction performance, and short-circuit performance through optimized design, significantly enhancing the overall performance of the SiC planar MOS device.

[0039] In some embodiments, the depth of the P-type well region 320 is less than the depth of the current extension region 310, the upper surface of the P-type well region 320 is flush with the upper surface of the current extension region 310, the thickness of the current extension region 310 is at least six-fifths of the thickness of the P-type well region 320, and the thickness of the P-type well region 320 is 0.6-0.7 μm.

[0040] In some embodiments, the P-type well region 320 has an L-shaped structure, the gate layer 420 has a U-shaped structure, the vertical portion of the P-type well region 320 contacted by the first side of the current extension region 310 is opposite to the first end of the gate layer 420, the vertical portion of the P-type well region 320 contacted by the second side of the current extension region 310 is opposite to the second end of the gate layer 420, and the width of the vertical portion of the P-type well region 320 is smaller than the width of the two ends of the gate layer 420.

[0041] In some embodiments, a plurality of P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 are arranged in an array in cross-section. The P-type floating islands 210 are located at the junction of the N-type drift region 120 and the top epitaxial region 130. The N-type drift region 120 has a plurality of grooves at the junction for setting the P-type floating islands 210. Furthermore, a portion of the P-type floating islands 210 are arranged opposite to the P-type heavily doped region 330, another portion of the P-type floating islands 210 are arranged opposite to the P-type well region 320, and yet another portion of the P-type floating islands 210 are arranged opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be strengthened. At the same time, the self-depletion effect of the P-type floating islands 210 helps to reduce the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0042] In some embodiments, the thickness of the plurality of P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 is related to their position. The thickness of some P-type floating islands 210 disposed opposite to the P-type heavily doped region 330 is greater than the thickness of some P-type floating islands 210 disposed opposite to the P-type well region 320. The thickness of some P-type floating islands 210 disposed opposite to the P-type well region 320 is greater than the thickness of some P-type floating islands 210 disposed opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be adjusted according to the current density of the current flowing between the first electrode layer 510 and the second electrode layer 520, thereby enhancing the short-circuit characteristics. At the same time, it is beneficial to reduce the thickness of the P-type well region 320. The self-depletion effect of the P-type floating islands 210 is beneficial to reduce the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0043] In some embodiments, the width of the plurality of P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 is related to their position. The width of some P-type floating islands 210 disposed opposite to the P-type heavily doped region 330 is greater than the width of some P-type floating islands 210 disposed opposite to the P-type well region 320. The width of some P-type floating islands 210 disposed opposite to the P-type well region 320 is greater than the width of some P-type floating islands 210 disposed opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be adjusted according to the current density of the current flowing between the first electrode layer 510 and the second electrode layer 520, thereby enhancing the short-circuit characteristics. At the same time, it is beneficial to reduce the thickness of the P-type well region 320. The self-depletion effect of the P-type floating islands 210 is beneficial to reduce the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0044] In some embodiments, the area of ​​the plurality of P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 is related to their position. The area of ​​some P-type floating islands 210 disposed opposite to the P-type heavily doped region 330 is larger than the area of ​​some P-type floating islands 210 disposed opposite to the P-type well region 320. The area of ​​some P-type floating islands 210 disposed opposite to the P-type well region 320 is larger than the area of ​​some P-type floating islands 210 disposed opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be adjusted according to the current density of the current flowing between the first electrode layer 510 and the second electrode layer 520, thereby enhancing the short-circuit characteristics. At the same time, it is beneficial to reduce the thickness of the P-type well region 320. The self-depletion effect of the P-type floating islands 210 is beneficial to reduce the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0045] In some embodiments, the ion implantation dose of the P-type well region 320 is 5-13E12 / cm². 2 .

[0046] In some embodiments, the junction depth of the P-type well region 320 ranges from 0.6 to 0.7 μm.

[0047] In some embodiments, the ion implantation dose of the heavily doped N-type region 340 is 2-8E15 / cm². 2 .

[0048] In some embodiments, N-type heavily doped regions 340 are provided on both sides of the current extension region 310. The junction depth of the N-type heavily doped regions 340 is 0.3-0.4 μm. The N-type heavily doped regions 340 are used to form a good ohmic contact with the second electrode layer 520.

[0049] In some embodiments, the ion implantation dose of the current extension region 310 is 1E13-1E14 / cm². 2 .

[0050] In some embodiments, the junction depth of the current extension region 310 is 0.8-1.0 μm. The junction depth of the current extension region 310 exceeds the junction depth of the P-type well region 320, which optimizes the BV-Ron tradeoff. This allows the device to optimize the on-resistance (Ron) without affecting the breakdown voltage (BV). When the junction depth of the current extension region 310 is 0.8-1.0 μm, and the junction depth of the current extension region 310 exceeds the junction depth of the P-type well region 320 by about 0.2-0.3 μm, the on-resistance (Ron) is reduced by 10%, resulting in a better BV-Ron tradeoff and meeting the device performance requirements of high-power applications.

[0051] In some embodiments, the doping depth of the current extension region 310 is greater than the doping depth of the P-type well region 320, such that the top epitaxial region 130 has a groove structure opposite to the gate layer 420. In this case, the thickness of the current extension region 310 is greater than the thickness of the P-type well region 320, and the difference between the thickness of the current extension region 310 and the thickness of the P-type well region 320 is 0.2-0.3 μm.

[0052] In some embodiments, the second electrode layer 520 may be a source layer, and the first electrode layer 510 may be a source layer.

[0053] In some embodiments, the lower surface of the heavily doped N-type region 340 is flush with the upper surface of the heavily doped P-type region 330, and the thickness of the heavily doped N-type region 340 is 0.3-0.4 μm. A shallow trench of 0.3-0.4 μm is formed by source etching, which increases the contact area between the second electrode layer 520 and the heavily doped N-type region 340, effectively reducing the contact resistance, which is beneficial for reducing the cell size and further reducing the specific on-resistance of the device.

[0054] In some embodiments, the junction depth of the heavily doped P-type region 330 is 1.0-1.1 μm, exceeding the thickness of the P-type well region 320 by 0.6-0.8 μm, in order to optimize the electric field distribution and form a good ground.

[0055] In some embodiments, P-type well regions 320 are provided on both sides adjacent to the current extension region 310. The P-type well regions 320 have an L-shaped structure. An N-type heavily doped region 340 is formed on the horizontal portion of the P-type well region 320, and the P-type heavily doped region 330 is in contact with the P-type well region 320. The thickness of the P-type heavily doped region 330 is greater than the thickness of the horizontal portion of the P-type well region 320. By etching a shallow trench structure at the source, the implantation depth of the P-type heavily doped region 330 can be made deeper. The P-type heavily doped region 330 is located directly below the shallow trench at the source, and its width is the same as that of the trench. The P-type heavily doped region 330 is 0.3-0.4 μm deeper than that of a conventional MOS, that is, its depth exceeds the depth of the horizontal portion of the P-type well region 320 by at least 0.6-0.8 μm. In this way, the breakdown voltage performance of the device can be optimized, and the reliability and stability of the device can be significantly improved.

[0056] In some embodiments, multiple P-type floating islands 210 can be formed on the N-type drift region 120 by P-type ion implantation. The multiple P-type floating islands 210 are arranged in parallel, which can increase the clamping effect on the saturation current and enhance the short-circuit characteristics. At the same time, the self-depletion effect of the floating islands is equivalent to connecting the depletion region capacitance in series between the gate and the drain, thereby reducing the total Cgd of the device and improving the switching characteristics of the device.

[0057] In some embodiments, the spacing between adjacent P-type floating islands 210 is the same.

[0058] In some embodiments, the width of the P-type floating island 210 is 0.6-1 μm, and the thickness of the P-type floating island 210 is 0.4-0.6 μm.

[0059] In some embodiments, the gate layer 420 has a convex structure, and the gate dielectric layer 410 has a protrusion structure opposite to the gate layer 420. This protrusion structure extends into the current extension region 310, making the insulating layer between the gate and drain of the device thicker and reducing Cgd. In this way, the thickness of the central gate dielectric can be increased to withstand the high electric field, enhancing the reliability of the gate dielectric layer 410 and strengthening the switching characteristics of the device.

[0060] In some embodiments, the gate dielectric layer 410 is silicon oxide.

[0061] In some embodiments, see Figure 2 As shown, the gate dielectric layer 410 includes a plurality of gate layers 420, which are isolated from each other by the gate dielectric layer 410, and at least two gate layers 420 are disposed opposite to the vertical portions of the P-type well regions 320 on both sides of the current extension region 310.

[0062] In this embodiment, as Figure 2As shown, the gate dielectric layer 410 includes a gate layer 421 and a gate layer 422. The gate layer 421 is disposed opposite to the vertical portion of the P-type well region 320 on the first side of the current extension region 310, and the gate layer 422 is disposed opposite to the vertical portion of the P-type well region 320 on the second side of the current extension region 310. By optimizing the doping concentration and depth of each region and adopting a special gate structure design, the on-resistance and breakdown voltage of the device are effectively balanced, thereby improving the short-circuit withstand capability and switching performance of the device.

[0063] In some embodiments, see Figure 3 As shown, a P-type shallow doped region 430 is provided between the current extension region 310 and the gate dielectric layer 410. The P-type shallow doped region 430 is in contact with the gate dielectric layer 410 and is located in the groove of the current extension region 310.

[0064] In this embodiment, the gate dielectric layer 410 can be protected by setting a P-type shallow doped region 430.

[0065] In some embodiments, see Figure 4 As shown, the current extension region 310 has a concave structure, and part of the protruding structure of the gate dielectric layer 410 fills the groove of the current extension region 310.

[0066] In this embodiment, the protrusion structure of the gate dielectric layer 410 is opposite to the center of the gate. It can be formed by etching silicon carbide material downward along the center of the gate to form a shallow trench and filling it with dielectric material. By forming a partial protrusion structure in the direction of the current extension region 310 in the gate dielectric layer 410, it is beneficial to protect the gate dielectric layer 410.

[0067] In some embodiments, see Figure 5 As shown, the top epitaxial region 130 has a concave structure, and the doping concentration of the top epitaxial region 130 is different from that of the N-type drift region 120.

[0068] In this embodiment, the top epitaxial region 130 and the N-type drift region 120 have the same doping type. The thickness of the top epitaxial region 130 is about 1.5-2.5 μm. The doping concentration of the top epitaxial region 130 is less than that of the current extension region 310, and the doping concentration of the top epitaxial region 130 is greater than that of the N-type drift region 120. In this way, the Ron-BV trade-off can be further optimized.

[0069] In some embodiments, such as Figure 5 As shown, the groove of the gate layer 420 is opposite to the groove of the current extension region 310.

[0070] In some embodiments, see Figure 6As shown, the plurality of P-type floating islands 210 include P-type floating island 211, P-type floating island 212, and P-type floating island 213. P-type floating island 211 is disposed opposite to the P-type heavily doped region 330 on the first side of the current extension region 310, P-type floating island 212 is disposed opposite to the P-type heavily doped region 330 on the second side of the current extension region 310, and P-type floating island 213 is disposed opposite to the current extension region 310.

[0071] In some embodiments, see Figure 6 As shown, the width of the P-type floating island 210 is equal to or greater than the width of the current extension region 310; at least one P-type floating island 210 is disposed opposite to the current extension region 310, and at least two P-type floating islands 210 are disposed opposite to the P-type heavily doped regions 330 on both sides of the current extension region 310.

[0072] In some embodiments, participate Figure 7 As shown, the silicon carbide substrate 110 is P-type doped, and an N-type buffer layer 121 is also provided between the silicon carbide substrate 110 and the N-type drift region 120.

[0073] In this embodiment, the second electrode layer 520 can be the emitter and the first electrode layer 510 can be the collector, thereby forming an IGBT structure on a P-type substrate.

[0074] This application also provides a method for fabricating a silicon carbide power device, see [link to relevant documentation]. Figure 8 As shown, the preparation method includes steps S100 to S500.

[0075] In step S100, an N-type drift region 120 is formed on a silicon carbide substrate 110, and multiple regions on the N-type drift region 120 are implanted with P-type ions to form multiple P-type floating islands 210.

[0076] In this embodiment, an N-type drift region 120 can be formed on the silicon carbide substrate 110 using an epitaxial process, such as... Figure 9 The schematic structure (a) is shown in the figure. Then, multiple regions on the N-type drift region 120 are implanted with P-type ions to form multiple P-type floating islands 210, as shown in the figure. Figure 9 The schematic structure (b) is shown in the figure.

[0077] In some embodiments, the doping concentration of the silicon carbide substrate 110 is greater than the doping concentration of the N-type drift region 120.

[0078] In step S200, a secondary epitaxial growth is performed to form the top epitaxial region 130, and the top epitaxial region 130 is etched to make the top epitaxial region 130 a concave structure.

[0079] In this embodiment, a top epitaxial region 130 covering multiple P-shaped floating islands 210 is formed through a further epitaxial process, such as... Figure 9As shown in the schematic structure (c), a shallow source trench is etched on the top epitaxial region 130 to form a micro-trench in the middle of the JFET, as shown. Figure 9 The schematic structure (d) is shown in the figure.

[0080] In step S300, a self-aligned process is used to form a current extension region 310, an N-type heavily doped region 340, a P-type well region 320, and a P-type heavily doped region 330.

[0081] In this embodiment, multiple ion implantations are performed using a self-aligned process, such as... Figure 9 As shown in the schematic structure (e), the current extension region 310, the P-type well region 320 and the P-type heavily doped region 330 are located on the top epitaxial region 130, and the P-type heavily doped region 330 and the P-type well region 320 are provided on both sides of the current extension region 310. The P-type well region 320 is located between the P-type heavily doped region 330 and the current extension region 310.

[0082] In step S400, a gate dielectric layer 410 is formed on the N-type heavily doped region, the P-type well region 320, and the current extension region 310, and a gate layer 420 is formed by a polysilicon deposition process, so that the gate dielectric layer 410 encapsulates the gate layer 420.

[0083] In this embodiment, a gate dielectric layer covering the N-type heavily doped region, the P-type well region 320, and the current extension region 310 can be formed by a thermal oxidation process, such as... Figure 9 As shown in the schematic structure (f), a gate layer 420 is formed by chemical vapor deposition, followed by thermal oxidation and etching to obtain a gate dielectric layer 410 encapsulating the gate layer 420, as shown in the diagram. Figure 9 The schematic structure (g) is shown in the figure.

[0084] In step S500, a first electrode layer 510 is formed on the back side of the silicon carbide substrate 110, and a second electrode layer 520 is formed on the gate dielectric layer 410, the N-type heavily doped region 340, and the P-type heavily doped region 330, as shown below. Figure 9 The schematic structure (h) is shown in the figure.

[0085] In some embodiments, step S100, forming an N-type drift region 120 on a silicon carbide substrate 110, includes forming an N-type buffer layer 121 on the silicon carbide substrate 110 and forming an N-type drift region 120 on the N-type buffer layer 121.

[0086] In this embodiment, if the silicon carbide substrate 110 is P-type doped, an N-type buffer layer can be formed on the silicon carbide substrate 110 by epitaxy. In this case, the second electrode layer 520 can be the emitter and the first electrode layer 510 can be the collector, thereby forming an IGBT structure on a P-type substrate.

[0087] This application also provides a chip, which includes a silicon carbide power device as described in any of the preceding embodiments.

[0088] In this embodiment, the chip includes a chip substrate, on which one or more silicon carbide power devices are disposed.

[0089] In some embodiments, the silicon carbide power device can be any one of silicon carbide MOSFET, silicon carbide transistor, or silicon carbide IGBT.

[0090] The silicon carbide device described in any of the above embodiments can be applied to any high-voltage power device based on SiC material, including but not limited to silicon carbide MOSFETs, silicon carbide diodes, silicon carbide IGBTs, etc.

[0091] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the silicon carbide power device fabrication method.

[0092] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0093] In this embodiment, by setting multiple P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating islands helps to reduce the capacitance between the first electrode layer 510 and the gate in the device, thereby improving the switching characteristics of the device. Furthermore, in the case of a shallower P-type well region and a deeper doped current extension region, the trade-off between breakdown voltage and on-resistance can be effectively balanced, so that the on-resistance is optimized without affecting the breakdown voltage, thus meeting the performance requirements of high-power applications.

[0094] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0095] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0097] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0098] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide power device, characterized in that, The silicon carbide power device includes: a silicon carbide substrate, a first electrode layer, an N-type drift region, a P-type floating island, a top epitaxial region, a current spread region, an N-type heavily doped region, a P-type well region, a P-type heavily doped region, a gate dielectric layer, a gate layer, and a second electrode layer. The first electrode layer is located on the back side of the silicon carbide substrate, the N-type drift region is located on the front side of the silicon carbide substrate, and a plurality of P-type floating islands are disposed between the N-type drift region and the top epitaxial region; The current extension region, P-type well region, and heavily doped P-type region are located on the top epitaxial region. The heavily doped P-type region and P-type well region are located on both sides of the current extension region. The P-type well region is located between the heavily doped P-type region and the current extension region. The depth of the current extension region is greater than the depth of the P-type well region. The doping concentration of the P-type well region is less than the doping concentration of the heavily doped P-type region. The doping concentration of the current extension region is greater than the doping concentration of the top epitaxial region. Multiple P-type floating islands between the N-type drift region and the top epitaxial region are arranged in an array in cross-section. The P-type floating islands are located at the boundary between the N-type drift region and the top epitaxial region. The N-type drift region has multiple grooves at the boundary for arranging the P-type floating islands. A portion of the P-type floating islands are positioned opposite the heavily doped P-type region, a portion are positioned opposite the P-type well region, and a portion are positioned opposite the current extension region. The width of the P-type floating island is equal to or greater than the width of the current extension region. The N-type heavily doped region is formed on the horizontal portion of the P-type well region. The gate dielectric layer is located on the N-type heavily doped region, the P-type well region, and the current extension region. The gate dielectric layer encapsulates the gate layer. The second electrode layer covers the gate dielectric layer and is in contact with the N-type heavily doped region and the P-type heavily doped region.

2. The silicon carbide power device as described in claim 1, characterized in that, The gate dielectric layer includes a plurality of gate layers, which are isolated from each other by the gate dielectric layer, and at least two of the gate layers are disposed opposite to the vertical portions of the P-type well regions on both sides of the current extension region.

3. The silicon carbide power device as described in claim 1, characterized in that, A P-type shallow doped region is provided between the current extension region and the gate dielectric layer. The P-type shallow doped region is in contact with the gate dielectric layer and is located within the groove of the current extension region.

4. The silicon carbide power device as described in claim 1, characterized in that, The current extension region has a concave structure, and part of the protruding structure of the gate dielectric layer fills the groove of the current extension region.

5. The silicon carbide power device as described in claim 1, characterized in that, The top epitaxial region has a concave structure, and the doping concentration of the top epitaxial region is different from that of the N-type drift region.

6. The silicon carbide power device as described in claim 1, characterized in that, At least one of the P-type floating islands is disposed opposite to the current extension region, and at least two of the P-type floating islands are disposed opposite to the P-type heavily doped regions on both sides of the current extension region.

7. The silicon carbide power device as described in claim 1, characterized in that, The silicon carbide substrate is P-type doped, and an N-type buffer layer is also provided between the silicon carbide substrate and the N-type drift region.

8. A method for fabricating a silicon carbide power device, characterized in that, The preparation method includes: An N-type drift region is formed on a silicon carbide substrate, and multiple regions on the N-type drift region are implanted with P-type ions to form multiple P-type floating islands; A secondary epitaxial growth process is performed to form a top epitaxial region, and the top epitaxial region is etched to make it a concave structure. A self-aligned process is used to form a current-spreading region, an N-type heavily doped region, a P-type well region, and a P-type heavily doped region. The current-spreading region, the P-type well region, and the P-type heavily doped region are located on the top epitaxial region, with the P-type heavily doped region and the P-type well region located on both sides of the current-spreading region. The P-type well region is located between the P-type heavily doped region and the current-spreading region. Multiple P-type floating islands are arranged in an array in cross-section between the N-type drift region and the top epitaxial region. The P-type floating islands are located at the boundary between the N-type drift region and the top epitaxial region. The N-type drift region has multiple grooves at the boundary for accommodating the P-type floating islands. A portion of the P-type floating islands are positioned opposite the P-type heavily doped region, a portion are positioned opposite the P-type well region, and a portion are positioned opposite the current-spreading region. The width of each P-type floating island is equal to or greater than the width of the current-spreading region. A gate dielectric layer is formed on the N-type heavily doped region, P-type well region, and current extension region, and a gate layer is formed by polysilicon deposition, so that the gate dielectric layer encapsulates the gate layer. A first electrode layer is formed on the back side of the silicon carbide substrate, and a second electrode layer is formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region.

9. The preparation method according to claim 8, characterized in that, The formation of an N-type drift region on a silicon carbide substrate includes: An N-type buffer layer is formed on a silicon carbide substrate, and an N-type drift region is formed on the N-type buffer layer.

10. A chip, characterized in that, The chip includes the silicon carbide power device as described in any one of claims 1-7.

Images