Backside cross-coupled interconnect

Abstract

Techniques are provided herein for forming integrated circuits having backside interconnect structures coupled between different transistor elements (e.g., between source or drain regions and / or gate structures). The backside interconnect structure may be used to replace the frontside local interconnect structure, thereby releasing more space in the frontside interconnect region. In one such example, a first semiconductor device includes a first semiconductor region extending from a first source or drain region and a first gate structure extending over the first semiconductor region, and the second semiconductor device includes a second semiconductor region extending from the second source or drain region and a second gate structure extending over the second semiconductor region. A conductive structure is coupled between a bottom surface of each of the first source or drain region, the second source or drain region, and a portion of the first gate structure.

Description

Background Art

[0001] As the size of integrated circuits continues to shrink, numerous challenges arise. For example, reducing the size of memory and logic cells within the interconnect structure is becoming increasingly difficult due to the reduced device pitch at the device level. Routing multiple logic signals between transistor elements in the interconnect region results in inefficient use of space and crowded metal lines, which can increase parasitic effects. Consequently, significant challenges remain in creating these high-density semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A is a top view of an integrated circuit structure including backside interconnects to route logic signals between different source or drain regions and gate structures according to an embodiment of the present disclosure.

[0003] Figure 1B and Figure 1C According to an embodiment of the present disclosure Figure 1A Different cross-sectional views of an integrated circuit showing backside interconnects coupled to source or drain regions and gates of the same transistor (1B) and coupled between adjacent source or drain regions of different transistors (1C).

[0004] Figure 2A and Figure 2B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of a stage in an example process for an integrated circuit with backside interconnects.

[0005] Figure 3A and Figure 3B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0006] Figure 4A and Figure 4B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0007] Figure 5A and Figure 5B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0008] Figure 6A and Figure 6B The present invention is a method for forming a configuration such as Figure 1A-C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0009] Figure 7A and Figure 7B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0010] Figure 8A and Figure 8B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0011] Figure 9A and Figure 9B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0012] Figure 10A and Figure 10B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0013] Figure 11A and Figure 11B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0014] Figure 12A and Figure 12B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0015] Figure 13A and Figure 13B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0016] Figure 14A and Figure 14B The present invention is a method for forming a configuration such as Figure 1A -C is a cross-sectional view of another stage in the exemplary process of an integrated circuit with backside interconnects.

[0017] Figure 15 is a cross-sectional view of an integrated circuit having backside interconnects and backside power rails according to an embodiment of the present disclosure.

[0018] Figure 16A This is a circuit diagram of an SRAM cell.

[0019] Figure 16B According to an embodiment of the present disclosure, Figure 16A A top view of the transistor layout of an SRAM cell with backside interconnects for local cross-coupling connections.

[0020] Figure 17 A cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0021] Figure 18 According to an embodiment of the present disclosure, Figure 1A -C is a flow chart of a manufacturing process of a semiconductor device with backside interconnection.

[0022] Figure 19 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0023] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For example, although some of the drawings generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have imperfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topologies or otherwise be non-smooth, given the real-world limitations of processing equipment and the technology used. DETAILED DESCRIPTION

[0024] Provided herein is a technique for forming an integrated circuit having a backside interconnect structure coupled between different transistor elements (e.g., between source or drain regions and / or gate structures). The backside interconnect structure can be used to replace the frontside local interconnect structure, thereby freeing up more space in the frontside interconnect area (e.g., for metal 0 lines). The technique can be used in any number of integrated circuit applications and is particularly useful with respect to logic and memory cells, such as those using finFETs or full-all-around gate transistors (e.g., ribbon FETs and nanowire FETs) or fork-shaped transistors (e.g., nanosheet FETs). In one such example, a first semiconductor device includes a first semiconductor region extending from a first source or drain region and a first gate structure extending above the first semiconductor region, and a second semiconductor device includes a second semiconductor region extending from a second source or drain region and a second gate structure extending above the second semiconductor region. A conductive structure is coupled between the bottom surface of each of the first source or drain region, the second source or drain region, and the first gate structure. The conductive structure can be formed on the back side of the integrated circuit after removing the substrate from the back side. Many variations and embodiments will be apparent from this disclosure.

[0025] General Overview

[0026] As mentioned above, there are still many significant challenges with respect to integrated circuit manufacturing. In more detail, some circuit designs require complex connections between the individual transistor elements of a given device layer. Due to inherent limitations in transistor layout, providing these connections typically requires the use of local interconnect layers within the interconnect region. The interconnect region includes one or more interconnect levels formed above the device of the device layer during back-end processing (sometimes referred to as back-end process or BEOL processing). However, the presence of local interconnect layers reduces the amount of space available for certain signal tracks within the lower interconnect levels (e.g., metal 0 lines). In a specific example, SRAM cells are typically used in memory architectures and utilize local interconnects between the individual transistor elements. These local interconnects use a large amount of available space above the device, making it more difficult to route power, ground, bit lines, and word lines to the transistors.

[0027] Therefore, and in accordance with embodiments of the present disclosure, techniques are provided herein for forming backside interconnect structures to provide connections between any number of transistor source or drain regions and / or gate structures. In some examples, a backside interconnect structure is used to replace a front-side local interconnect layer, which can free up more space for metal 0 signal tracks in the interconnect area. According to some embodiments, a given backside interconnect structure can extend linearly between adjacent source or drain regions, or can have a nonlinear shape to extend between the back sides of any transistor element (e.g., source or drain region and gate structure). For example, a backside interconnect structure can have an 'L' shape to connect adjacent source or drain regions aligned along the Y direction, with one or more gate structures (or conductive portions of gate trenches) aligned with any source or drain region along the X direction. In some examples, a backside interconnect structure extends under any number of source or drain regions without providing any electrical connection to them (e.g., overhanging under the source or drain region). The backside interconnect structure can include any suitable conductive material, such as tungsten, titanium, tantalum, ruthenium, molybdenum, or cobalt, or nitrides of any of these. In some examples, the backside interconnect structure includes a conductive liner layer of titanium nitride, as one example.

[0028] According to an embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; and a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in a second direction. The second source or drain region is spaced apart from the first source or drain region along the second direction. The integrated circuit also includes a conductive structure on a lower side of each of the first source or drain region, the second source or drain region, and the first gate structure.

[0029] According to another embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending from the first source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction; a third semiconductor device having a third semiconductor region extending from the second source or drain region in the first direction and a third gate structure extending over the third semiconductor region in the second direction; a fourth semiconductor device having a fourth semiconductor region extending from the third source or drain region in the first direction and a fourth gate structure extending over the fourth semiconductor region in the second direction; a fifth semiconductor device having a fifth semiconductor region extending from the fourth source or drain region in the first direction and a fifth gate structure extending over the fifth semiconductor region in the second direction; and a sixth semiconductor device having a sixth semiconductor region extending from the fourth source or drain region in the first direction and a sixth gate structure extending over the sixth semiconductor region in the second direction. The first gate structure and the third gate structure are coupled together in a first gate trench, and the fourth gate structure and the sixth gate structure are coupled together in a second gate trench parallel to the first gate trench. The integrated circuit also includes a conductive structure on an underside of each of the first source or drain region, the second source or drain region, and the conductive portion of the second gate trench.

[0030] According to another embodiment, a method of forming an integrated circuit includes: forming a first fin including a first semiconductor region and a second fin including a second semiconductor region extending above a substrate; forming a first dielectric layer, wherein the first dielectric layer is adjacent to a sub-fin portion of each of the first fin and the second fin; forming a sacrificial gate and a spacer structure above the first fin and the second fin; removing the portions of the first fin and the second fin not covered by the sacrificial gate and the spacer structure; forming a first source or drain region at an exposed end of the first semiconductor region and a second source or drain region at an exposed end of the second semiconductor region; replacing the sacrificial gate with a first gate structure located above the first semiconductor region and a second gate structure located above the second semiconductor region; removing the substrate to expose the back side of the first dielectric layer; replacing the sub-fin portion of each of the first fin and the second fin with the second dielectric layer; forming a groove through both the first dielectric layer and the second dielectric layer so as to expose the bottom surface of the first source or drain region, the bottom surface of the second source or drain region and the bottom surface of the first gate structure; and forming a conductive structure within the groove.

[0031] These techniques can be used with any type of non-planar transistor, including finFETs (sometimes called double-gate transistors or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called all-around transistors), to name a few. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-first process or a gate-last process (sometimes called a replacement metal gate or RMG process), or any other gate formation process. Any number of semiconductor materials can be used in forming the transistor, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0032] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy (including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM)), compositional mapping, X-ray crystallography or diffraction (XRD), energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF-SIMS), atom probe imaging or tomography, local electrode atom probe (LEAP) technology, 3D tomography, or high-resolution physical or chemical analysis, to name a few suitable example analytical tools. For example, in some example embodiments, such tools can indicate the presence of a backside conductive layer beneath a transistor extending between different source or drain regions and / or gate structures. The backside conductive layer can be in a first backside interconnect layer, and additional backside interconnect layers can be disposed below the first backside interconnect layer. One or more additional conductive layers can be disposed within any additional backside interconnect layer, such as a power or ground rail.

[0033] It should be readily understood that the meaning of "above" and "over" in this disclosure should be interpreted in the broadest sense, such that "above" and "over" not only mean "directly on" something, but also include the meaning of having intermediate features or layers on something. In addition, spatially relative terms (e.g., "below," "below," "lower," "above," "upper," "top," "bottom," etc.) may be used herein to describe the relationship of one element or feature to another (some) element or feature as shown in the figures for ease of description. In addition to the orientations shown in the figures, spatially relative terms are also intended to include different orientations of the device in use and operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and accordingly the spatially relative descriptors used herein may be interpreted in the same manner.

[0034] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire structure below or above, or may have an extent that is less than the extent of the structure below or above. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure, wherein the layer has a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal surfaces at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved), having a relatively uniform thickness across the layer.

[0035] As used herein, "compositionally different" or "compositionally dissimilar" materials refer to two materials that have different chemical compositions. This compositional difference can be, for example, by virtue of an element being present in one material but not in the other (e.g., SiGe is compositionally different from silicon), or by virtue of a material having all of the same elements as the second material, but at least one of these elements being intentionally provided in one material at a different concentration relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this chemical composition difference, the materials can also have different dopants (e.g., gallium and magnesium) or the same dopants but at different concentrations. In other embodiments, compositionally dissimilar materials can also refer to two materials having different crystal orientations. For example, (110) silicon is compositionally different or distinct from (100) silicon. Forming a stack having different orientations can be achieved, for example, using blanket wafer layer transfer. If the two materials are elementally different, one material has an element that is not present in the other material.

[0036] Architecture

[0037] Figure 1A is a top view of a portion of an integrated circuit 100 including various semiconductor devices (eg, a first semiconductor device 102 and an adjacent second semiconductor device 104 ) according to an embodiment of the present disclosure. Figure 1B According to an embodiment, Figure 1A A cross-sectional view of the XZ plane with the X-axis identified by the dotted line. Figure 1C According to an embodiment, Figure 1AThe Y-axis in FIG is a cross-sectional view of the YZ plane, with the Y-axis being identified by a dashed line. Each semiconductor device can be a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate (e.g., finFET) or a gate-all-around (GAA) transistor, but other transistor topologies and types can also benefit from the techniques provided herein. The examples herein illustrate semiconductor devices having a GAA structure (e.g., having nanoribbons or nanowires extending between source and drain regions).

[0038] The semiconductor device 102 / 104 includes a semiconductor region extending in a first direction (e.g., along the X-axis) between corresponding source or drain regions, wherein the gate structure 106 extends across the semiconductor region in a second direction (e.g., along the Y-axis). In the example shown, the gate structure 106 covers the semiconductor region extending between the source or drain regions, but these regions may be Figure 1B Any number of parallel gate structures 106 can be formed on the integrated circuit to form any number of transistors. According to some embodiments, the first semiconductor device 102 and the second semiconductor device 104 share the same gate structure 106. In some examples, dielectric gate cuts can separate the gate structure 106 into separate gate structures for each of the first semiconductor device 102 and the second semiconductor device 104.

[0039] According to some embodiments, the first semiconductor device 102 includes a semiconductor region extending along a first direction between a first source or drain region 108a and a second source or drain region 108b, and the second semiconductor device 104 includes a semiconductor region extending along the first direction between a third source or drain region 110a and a fourth source or drain region 110b. Any semiconductor material suitable for source and drain regions (e.g., Group IV and Group III-V semiconductor materials) can be used for either of the source or drain regions 108 / 110 shown. In either case, the composition and doping of the source or drain regions can be the same or different depending on the polarity of the transistor. In an example, the first semiconductor device 102 is an NMOS device, and the first and second source or drain regions 108a / 108b are doped with an n-type dopant (e.g., phosphorus or arsenic), and the second semiconductor device 104 is a PMOS device, and the third and fourth source or drain regions 110a / 110b are doped with a p-type dopant (e.g., boron). Any number of source and drain configurations and materials may be used.In some embodiments, the second source or drain region 108b is omitted (eg, replaced with a dielectric material).

[0040] According to some embodiments, a backside conductive layer 112 is provided below the device to connect between any number of transistor elements. In the example shown, the backside conductive layer 112 connects at least the first source or drain region 108a, the third source or drain region 110a, and the portion between the first source or drain region 108a and the second source or drain region 108b of the gate structure 106. The backside conductive layer 112 may include any suitable conductive material, such as tungsten, titanium, tantalum, ruthenium, molybdenum, or cobalt, or a nitride of any of these. The backside conductive layer 112 may also include a conductive liner including titanium nitride. According to some embodiments, the backside conductive layer 112 may be patterned to have a nonlinear shape to connect between different elements that are not all aligned along the X or Y axis. In the example shown, the backside conductive layer 112 includes an 'L' shape, with a first portion extending along a first direction between the first source or drain region 108a and the gate structure 106, and a second portion extending along a second direction between the third source or drain region 110a and the first source or drain region 108a.

[0041] Figure 1B and Figure 1C More detailed cross-sectional views are provided along two portions of the backside conductive layer 112, in accordance with some embodiments. Note that the same first source or drain region 108a is provided in each orthogonal cross-section. Figure 1B A first portion of the backside conductive layer 112 is shown extending below the first source or drain region 108a and the gate structure 106 and between the first source or drain region 108a and the gate structure 106. According to some embodiments, a semiconductor region of the first semiconductor device 102 including one or more nanoribbons 114 is also shown. The nanoribbon 114 can be part of a fin formed from a material deposited onto a substrate. The fin includes alternating layers of material (e.g., alternating silicon layers and SiGe layers) that facilitate the formation of nanowires or nanoribbons during a gate formation process, wherein one type of alternating layers is selectively etched away to release another type of alternating layers in the channel region so that a full-all-around gate process can then be performed. In other embodiments, a solid fin of semiconductor material (e.g., silicon or silicon germanium) is provided as the semiconductor region extending between the first source or drain region 108a and the second source or drain region 108b.

[0042] Gate structure 106 extends over nanoribbon 114 along a second direction (e.g., along the Y-axis) to form a transistor gate (or a dummy gate structure in examples where second source or drain region 108b is omitted). Gate structure 106 may include a gate dielectric and a gate electrode on the gate dielectric. The gate electrode may represent any number of conductive layers, and the gate dielectric may represent any number of dielectric layers. The gate electrode may comprise any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some embodiments, the gate electrode comprises one or more work function metals surrounding nanoribbon 114. In some embodiments, a p-channel device comprises a work function metal comprising titanium surrounding one or more semiconductor regions, and an n-channel device comprises a work function metal comprising tungsten surrounding one or more semiconductor regions. The gate electrode may further comprise a fill metal or other conductive material surrounding the work function metal to provide a complete gate electrode structure. The gate dielectric may comprise any suitable gate dielectric material(s). In some embodiments, the gate dielectric comprises a layer of native oxide material (e.g., silicon oxide) on nanoribbon 114 or other semiconductor regions, and a layer of high-k dielectric material (e.g., hafnium oxide) on the native oxide.

[0043] According to some embodiments, a spacer structure 116 is present along the sidewalls of the gate structure 106. The spacer structure 116 can be any suitable dielectric material, such as silicon nitride, and provides spacing between the gate structure 106 and the adjacent source or drain regions 108a / 108b. The spacer structure 116 can extend along the gate structure sidewalls in the second direction and along the Z-axis for the entire height of the gate structure 106. In some embodiments, a gate cap 118 is disposed over the gate structure 106 and can extend along the gate structure 106 in the second direction. The gate cap 118 can be any suitable dielectric material, such as silicon nitride. In some examples, the gate cap 118 is the same dielectric material as the spacer structure 116.

[0044] Figure 1C A second portion of the backside conductive layer 112 is shown below and extending between the first source or drain region 108a and the third source or drain region 110a. Figure 1C The source / drain trenches shown in FIG may include a dielectric filler 120 around and / or over each source or drain region aligned within the source / drain trenches. Figure 1B A dielectric filler 120 is seen above the top of the first source or drain region 108a and the second source or drain region 108b in FIG. The dielectric filler 120 may include any suitable dielectric material, such as silicon dioxide.

[0045] In accordance with some embodiments, a backside dielectric layer 122 is provided beneath the semiconductor device. The backside dielectric layer 122 may represent a single dielectric layer or a plurality of dielectric layers or materials. In accordance with some embodiments, the backside dielectric layer 122 may be the first layer of a backside interconnect structure. The backside conductive layer 112 may extend through the backside dielectric layer 122 to contact the bottom surfaces of any number of transistor elements. In the example shown, the backside conductive layer 112 contacts the first source or drain region 108a, the third source or drain region 110a, and the bottom surface of the gate structure 106. Note that any gate dielectric is removed from the bottom surface of the gate structure 106 so that the backside conductive layer 112 directly contacts the gate electrode of the gate structure 106. The backside dielectric layer 122 may be any suitable dielectric material, such as silicon dioxide.

[0046] According to some embodiments, any number of front-side conductive contacts can be formed on the top surface of one or more source or drain regions. In an example, portions of dielectric fill 120 are removed from above any number of source or drain regions, and the front-side contacts are formed in place on the top surface of the source or drain regions. The front-side conductive contacts can include any suitable conductive material, such as tungsten, titanium, tantalum, ruthenium, molybdenum, or cobalt, or nitrides of any of these.

[0047] Manufacturing method

[0048] Figures 2A-14A and Figures 2B-14B Included are cross-sectional views that collectively illustrate an example process for forming an integrated circuit configured with a backside conductive layer coupled between different source or drain regions according to an embodiment of the present disclosure. Figures 2A-14A Indicates along Figure 1B A similar cross-sectional view taken in the XZ plane of Figures 2B-14B Indicates along Figure 1C Each set of figures sharing the same letter shows an example structure resulting from the process flow up to that point in time, so the depicted structure evolves as the process flow continues. Figures 14A-14B ends up in the structure shown in , which is similar to Figure 1B and Figure 1C Such a structure may be part of an entire integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and / or memory cells and analog mixed-signal circuitry. Thus, the illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuit systems not shown. Example materials and process parameters are given, but the present disclosure is not intended to be limited to any particular such materials or parameters, as will be understood.

[0049] Figure 2A and Figure 2B Each shows a cross-sectional view through a substrate 201 having a series of material layers formed thereon, according to an embodiment of the present disclosure. Alternating material layers can be deposited on substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating sacrificial layers 202 and semiconductor layers 204 can be deposited on substrate 201.

[0050] Substrate 201 can be, for example, a bulk substrate comprising a Group IV semiconductor material (e.g., silicon, germanium, or silicon germanium), a Group III-V semiconductor material (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, substrate 201 can be a semiconductor-on-insulator substrate having a desired semiconductor layer above a buried insulator layer (e.g., silicon above silicon dioxide). Alternatively, substrate 201 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used.

[0051] According to some embodiments, semiconductor layer 204 has a different material composition than sacrificial layer 202. In some embodiments, semiconductor layer 204 is silicon germanium (SiGe), while sacrificial layer 202 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a Group III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of semiconductor layer 204 and sacrificial layer 202, the germanium concentration between semiconductor layer 204 and sacrificial layer 202 is different. For example, semiconductor layer 204 may include a higher germanium content than sacrificial layer 202.

[0052] Although the dimensions may vary from one exemplary embodiment to the next, the thickness of each semiconductor layer 204 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each semiconductor layer 204 is substantially the same (e.g., within 1-2 nm). The thickness of each sacrificial layer 202 may be approximately the same as the thickness of each semiconductor layer 204 (e.g., about 5-20 nm). Each of the semiconductor layer 204 and the sacrificial layer 202 may be deposited using any known material deposition technique (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or epitaxial growth).

[0053] Figure 3A and Figure 3B The following are respectively shown according to the embodiment Figure 2A and Figure 2BThe structure shown is a cross-sectional view after forming a cap layer 302 and subsequently forming fins below the cap layer 302. The cap layer 302 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 302 is patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layer 202 and semiconductor layer 204. Figure 3A As shown, cap layer 302 extends along the top of each fin in a first direction.

[0054] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of substrate 201. The portion of substrate 201 below the fin is not etched and creates a sub-fin region 304. The etched portion of substrate 201 can be filled with a dielectric layer 306 that acts as shallow trench isolation (STI) between adjacent fins. Dielectric layer 306 can be any suitable dielectric material, such as silicon oxide. In accordance with some embodiments, sub-fin region 304 represents the remaining portion of substrate 201 between dielectric layers 306.

[0055] Figure 4A and Figure 4B According to some embodiments Figure 3A and Figure 3B A cross-sectional view of the structure shown after forming a sacrificial gate 402. The gate mask layer can first be patterned into strips that extend orthogonally across each fin (e.g., in the second direction) so as to form the corresponding sacrificial gate 402 as a strip below the gate mask layer. Thereafter, the gate mask layer can be removed, or the gate mask layer can be retained as a cap layer above each sacrificial gate 402. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate mask layer. The sacrificial gate 402 can be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 402 includes polysilicon.

[0056] According to some embodiments, spacer structures 404 are formed along the sidewalls of the sacrificial gate 402. The spacer structures 404 may be deposited and then etched back such that the spacer structures 404 mostly remain only on the sidewalls of any exposed structures. Figure 4BIn the cross-sectional view of , a spacer structure 404 may also be formed over the dielectric layer 306 along the sidewalls of the exposed fin. Such sidewall spacers on the fin may be removed during later processing when the source or drain regions are formed. According to some embodiments, the spacer structure 404 may be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon carbon oxynitride. In one such embodiment, the spacer structure 404 includes a nitride and the dielectric layer 306 includes an oxide to provide a degree of etch selectivity during final gate processing. Other etch-selective dielectric schemes (e.g., oxide / carbide, carbide / nitride) may also be used for the spacer structure 404 and the dielectric layer 306. In other embodiments, the spacer structure 404 and the dielectric layer 306 are identical in composition or otherwise similar, where etch selectivity is not employed.

[0057] Figure 5A and Figure 5B According to some embodiments Figure 4A and Figure 4B The structure shown is a cross-sectional view after removing the exposed portion of the fin not protected by the sacrificial gate 402 and the spacer structure 404. The exposed fin portion can be removed using any anisotropic etching process, such as reactive ion etching (RIE). According to some embodiments, removing the exposed fin portion creates source or drain trenches alternating with the gate trenches (now filled with the sacrificial gate 402) along a first direction.

[0058] According to some embodiments, a portion of substrate 201 is also removed during the etching process to form a recessed region below the top surface of substrate 201. In some examples, at least a portion of sub-fin region 304 is removed such that the top surface of sub-fin region 304 is recessed below the top surface of dielectric layer 306. In some examples, a sacrificial plug can be formed within the etched recess to be later removed during formation of the backside contact. In some examples, when the top surface of sub-fin region 304 is recessed below the top surface of dielectric layer 306, the final source or drain region can extend below the top surface of sub-fin region 304.

[0059] Figure 6A and Figure 6B The embodiment according to the present disclosure is shown Figure 5A and Figure 5B4. A cross-sectional view of the structure shown after removing portions of the sacrificial layer 202 and subsequently forming the inner spacers 602. An isotropic etching process can be used to selectively recess the exposed ends of each sacrificial layer 202 (e.g., while etching relatively little of the semiconductor layer 204). The inner spacers 602 can have a material composition similar to or identical to that of the spacer structure 404. Thus, the inner spacers 602 can be any suitable dielectric material that selectively exhibits high etching of semiconductor materials such as silicon and / or silicon germanium. For example, the inner spacers 602 can be conformally deposited over the sides of the fin structure using a conformal deposition process such as CVD or ALD, and then etched back using an isotropic etching process to expose the ends of the semiconductor layer 204. According to some embodiments, the inner spacers 602 have a width similar to that of the spacer structure 404 (e.g., along the first direction).

[0060] Figure 7A and Figure 7B The following are respectively shown according to some embodiments Figure 6A and Figure 6B The structure shown is a cross-sectional view after forming a source or drain region 702 within the source / drain trench. The source or drain region may be formed in the area previously occupied by the exposed fin between the spacer structures 404. In accordance with some embodiments, the first semiconductor device includes a first source or drain region 702a and a second source or drain region 702b, as shown in FIG. Figure 7A As shown. The first source or drain region 702a is also Figure 7B and is adjacent to a third source or drain region 702c from the second semiconductor device.

[0061] According to some embodiments, the source or drain regions 702 are epitaxially grown from the exposed semiconductor material at the ends of the semiconductor layer 204. In some example embodiments, the first and second source or drain regions 702a / 702b are NMOS source or drain regions (e.g., epitaxial silicon), and the third source or drain region 702c is a PMOS source or drain region (e.g., epitaxial SiGe). As described above, each of the source or drain regions 702 may extend below the top surface of the sub-fin region 304, as shown in FIG. Figure 7A As shown (and extending below the top surface of dielectric layer 306, as shown Figure 7B shown).

[0062] According to some embodiments, a dielectric filler 704 is provided within the source / drain trench. In some examples, the dielectric filler 704 occupies the remaining volume within the source / drain trench around and above the source or drain region 702. The dielectric filler 704 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 704 extends upwardly to the top surface of the spacer structure 404 and is flush with the top surface of the spacer structure 404 (e.g., after a polishing process), such as Figure 7A As seen in.

[0063] Figure 8A and Figure 8B The following are respectively shown according to some embodiments Figure 7A and Figure 7B The structure shown is a cross-sectional view after removal of the sacrificial gate 402 and sacrificial layer 202. In examples where the gate mask layer is still present, it will be removed at this time. Once the sacrificial gate 402 is removed, the fin extending between the spacer structures 404 is exposed.

[0064] In an example where the fin includes alternating semiconductor layers, the sacrificial layer 202 is selectively removed to leave a nanoribbon 802 extending between corresponding source or drain regions (e.g., between the first source or drain region 702a and the second source or drain region 702b). Each vertical collection of nanoribbons 802 represents a semiconductor region of a different semiconductor device. It should be understood that the nanoribbons 802 can also be nanowires or nanosheets. The sacrificial gate 402 and the sacrificial layer 202 can be removed using the same isotropic etching process or different isotropic etching processes.

[0065] Figure 9A and Figure 9B The following are respectively shown according to some embodiments Figure 8A and Figure 8BThe structure shown is a cross-sectional view after forming a gate structure 902 including a gate dielectric and a gate electrode, and a subsequent gate cap 904. A gate dielectric may first be formed around the nanoribbon 802 before forming the gate electrode, which may include one or more conductive layers. The gate dielectric may include any suitable dielectric material (e.g., silicon dioxide and / or a high-k dielectric material). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric includes a hafnium oxide layer having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric includes a first layer on the nanoribbon 802 and a second layer on the first layer. The first layer may be an oxide of a semiconductor material such as nanoribbon 802 (eg, silicon dioxide), and the second layer may be a high-k dielectric material (eg, hafnium oxide).

[0066] The one or more conductive layers that make up the gate electrode can be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few. In some embodiments, the gate electrode comprises doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode may comprise, for example, a metal filler material and one or more work function layers, a resistance reducing layer, and / or a barrier layer. The work function layer may comprise, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate.

[0067] The gate cap 904 can be formed by first recessing the gate electrode and filling the recess with a dielectric material. The dielectric material can then be polished so that its top surface is substantially coplanar with the top surface of the spacer structure 404 and / or the dielectric filler 704. In some embodiments, the gate structure 902 can extend below the top surface of the sub-fin region 304 within the gate trench.

[0068] Figure 10A and Figure 10B The following are respectively shown according to some embodiments Figure 9A and Figure 9BThe structure shown is a cross-sectional view after forming front side conductive contacts 1002 within the source / drain trenches and on any number of source or drain regions. In the example shown, a single front side conductive contact 1002 is formed above the second source or drain region 702b. The front side conductive contact 1002 may include any suitable conductive material for making electrical contact with the underlying second source or drain region 702b, such as tungsten, molybdenum, ruthenium, or cobalt. Figure 10A As seen in the cross-section of FIG, a portion of the dielectric fill 704 is recessed to expose at least the top surface of the second source or drain region 702b, and a front side conductive contact 1002 is formed within the recess using any suitable metal deposition process. According to some embodiments, the front side conductive contact 1002 includes one or more silicide layers directly on the exposed surface of the second source or drain region 702b.

[0069] Figure 11A and Figure 11B The following are respectively shown according to some embodiments Figure 10A and Figure 10B The structure shown is a cross-sectional view after removal of the bulk portion of substrate 201. Substrate 201 can be removed from the backside via any combination of grinding, polishing, and / or etching processes. In some embodiments, substrate 201 can continue to be thinned from the backside until the bottom surface of dielectric layer 306 or sub-fin region 304 is exposed. In some examples, the backside polishing process can be continued until the bottom surfaces of at least both dielectric layer 306 and sub-fin region 304 are exposed.

[0070] Figure 12A and Figure 12B The following are respectively shown according to some embodiments Figure 11A and Figure 11B 1. A cross-sectional view of the structure shown after removing the sub-fin region 304 and subsequently forming the backside dielectric layer 1202. The exposed semiconductor material of the sub-fin region 304 can be removed using an isotropic etching process. The area left after removing the sub-fin region 304 can then be filled with a dielectric material to form the backside dielectric layer 1202. In some embodiments, the backside dielectric layer 1202 includes the same material as the dielectric layer 306 so that there is little discernible difference between them. The backside dielectric layer 1202 can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. According to some embodiments, the backside dielectric layer 1202 is polished after its deposition so that the bottom surface of the backside dielectric layer 1202 is substantially coplanar with the bottom surface of the dielectric layer 306.

[0071] It should be noted that in some embodiments, after forming backside dielectric layer 1202, portions of sub-fin region 304 may remain beneath nanoribbon 802. This may occur in examples where source or drain region 702 extends below the top surface of sub-fin region 304 and portions of gate structure 902 extend below the top surface of sub-fin region 304. The presence of any remaining portions of sub-fin region 304 does not change the remaining manufacturing process to form the backside interconnect.

[0072] Figure 13A and Figure 13B The following are respectively shown according to some embodiments Figure 12A and Figure 12B The structure shown is a cross-sectional view after a backside recess 1302 is formed through the backside dielectric layer 1202 and the dielectric layer 306. The backside recess 1302 can be formed using an RIE process to etch away portions of the backside dielectric layer 1202 and the dielectric layer 306 to expose the undersides of the various transistor elements. In the example shown, the "L"-shaped backside recess 1302 exposes the bottom surface of the first source or drain region 702a, the bottom surface of the third source or drain region 702c, and the bottom surface of the gate structure 902. The gate dielectric can be exposed first at the bottom of the gate electrode of the gate structure 902 and, if not already removed during the RIE process, removed using any suitable isotropic etching process to expose the gate electrode. The backside recess 1302 extends through the entire thickness of the backside dielectric layer 1202 and / or the dielectric layer 306.

[0073] Figure 14A and Figure 14B The following are respectively shown according to some embodiments Figure 13A and Figure 13B 14. The structure shown is a cross-sectional view after forming a backside interconnect 1402. The backside interconnect 1402 can be formed within the backside recess 1302 and on the bottom surface of each transistor element, thereby conductively connecting them together. In the example shown, the backside interconnect 1402 contacts the first source or drain region 702a, the third source or drain region 702c, and the bottom surface of the gate structure 902. Thus, the backside interconnect 1402 may include a first portion extending in a first direction (e.g., Figure 14A ) and a second portion extending in a second direction (as seen in Figure 14B), where the two portions are connected at a common point below the first source or drain region 702a. The backside interconnect 1402 may comprise any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt. The bottom surface of the backside interconnect 1402 may be polished using any known polishing technique (e.g., chemical mechanical polishing) so that it is substantially coplanar with the bottom surface of the backside dielectric layer 1202 and / or dielectric layer 306. The backside interconnect 1402 may comprise both a conductive liner along the edge of the structure and a conductive filler on the conductive liner. The conductive liner may comprise a barrier layer and / or an adhesion layer and may be titanium nitride or tantalum nitride. In some embodiments, the conductive liner comprises a silicide layer (e.g., titanium silicide, nickel silicide, platinum silicide, cobalt silicide, or any of their ternary silicides) at least at the interface between the backside interconnect 1402 and the source or drain regions 702a and 702c. In some embodiments, the barrier layer is formed on the silicide layer, and the remaining conductive filler is formed on the barrier layer. The conductive filler includes any one of tungsten, molybdenum, ruthenium or cobalt.

[0074] In accordance with some embodiments, backside interconnect 1402 may be a conductive element of a first backside interconnect layer. Additional backside interconnect layers may be formed below backside interconnect 1402 to provide other electrical connections to the backside of other transistor elements (eg, power and ground rails). Figure 15 According to some embodiments Figure 14B The structure shown has an example of a second backside dielectric layer 1502, a third backside dielectric layer 1504, and a backside conductive layer 1506. Each of the second backside dielectric layer 1502 and the third backside dielectric layer 1504 can be any suitable dielectric material and can be the same dielectric material as the backside dielectric layer 1202 and / or dielectric layer 306. The backside conductive layer 1506 can include any suitable conductive material, such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, ruthenium, molybdenum, cobalt, or copper, and a suitable barrier layer. The barrier layer can include tantalum nitride, ruthenium tantalum nitride, or titanium nitride.

[0075] According to some embodiments, backside conductive layer 1506 can be used to provide power or ground rails to the semiconductor device. According to some embodiments, the presence of backside interconnect 1402 relegates backside conductive layer 1506 to a lower position within the backside interconnect region to avoid any short circuits between conductive layers. Any source or drain regions can be coupled to backside conductive layer 1506 using one or more vias passing through the thickness of each of backside dielectric layer 1202 / dielectric layer 306 and second backside dielectric layer 1502.

[0076] Backside interconnects can be used to create cross-coupled backside connections in circuits that require coupling between the gate of one or more transistors and the source or drain regions of one or more different transistors. This occurs for SRAM cells where two cross-coupled connections are used within the circuit. Figure 16A is a circuit diagram of a standard SRAM cell according to some embodiments, and Figure 16B Shows the use can be used to make Figure 16A Layout of transistors connected on the back side of the SRAM cell circuit cross-coupled. As can be seen in this example, the SRAM cell includes six transistors (M1-M6) to provide a 6TSRAM cell, where the four memory transistors are arranged as a trigger divided into two n-type transistors (M1 and M2) and two p-type transistors (M3 and M4), and two n-type access transistors (M5 and M6). In the trigger arrangement, the gates of M1 and M3 are coupled together and are also coupled to the common source / drain terminal between M2 and M4 using a first cross-coupling interconnect 1601a. ​​Similarly, the gates of M2 and M4 are coupled together and are also coupled to the common source / drain terminal between M1 and M3 using a second cross-coupling interconnect 1601b. Access transistor M5 is coupled between the common source / drain terminal between M1 and M3 and the first bit line BL, while access transistor M6 is coupled between the common source / drain terminal between M1 and M3 and the second bit line The gates of each access transistor M5 and M6 are coupled to word line WL. The first cross-coupling interconnect 1601a and the second cross-coupling interconnect 1601b can be complex to arrange using conventional top-side interconnect methods. Therefore, providing these cross-coupling interconnects on the back side of the structure frees up more space for interconnect routing on the top side.

[0077] exist Figure 16B Shown in Figure 16ALayout of an SRAM cell in which six identical transistors M1-M6 are arranged across four gate trenches (1602a-1602d). Note that in this example, M3 and M4 are p-channel transistors, while M1, M2, M5, and M6 are n-channel transistors. The first gate trench 1602a is aligned collinearly with the second gate trench 1602b along the Y direction and is separated from the second gate trench 1602b by a first dielectric gate cut 1604a. The third gate trench 1602c is aligned collinearly with the fourth gate trench 1602d along the Y direction and is separated from the fourth gate trench 1602d by a second dielectric gate cut 1604b. More than one transistor gate can be present in a given gate trench and thus conductively coupled together. In the example shown, the gates of M1 and M3 are coupled together within the first gate trench 1602a, and the gates of M2 and M4 are coupled together within the fourth gate trench 1602d.

[0078] Top side contacts to transistor elements are provided in solid lines, while back side contacts and interconnects to transistor elements are provided in dashed lines. Figure 14A and Figure 14B Back-side "L"-shaped interconnects, such as those described, are used to provide cross-coupling interconnects 1601a and 1601b. First cross-coupling interconnect 1601a contacts the lower side of the source or drain region shared by both M2 and M6, the lower side of the source or drain region of M4, and the lower side of at least a portion of the first gate trench 1602a. Thus, first cross-coupling interconnect 1601a provides connections between the source or drain regions of M2, M4, and M6 and the gates of M1 and M3. Second cross-coupling interconnect 1601b contacts the lower side of the source or drain region shared by both M1 and M5, the lower side of the source or drain region of M3, and the lower side of at least a portion of the fourth gate trench 1602d. Thus, second cross-coupling interconnect 1601b provides connections between the source or drain regions of M1, M3, and M5 and the gates of M2 and M4. Backside power and ground rails may also be provided to another source or drain region of transistors M1, M2, M3, and M4 via backside contacts. Providing cross-coupling connections on the backside frees up more space on the topside for routing bitline and wordline interconnects to other source or drain regions of M5 and M6 and to the topside contacts shown on the gates of M5 and M6.

[0079] Although Figures 16A-16B The examples described herein are with respect to SRAM cells, but the techniques described herein can be readily applied to other memory cell types (e.g., multi-port DRAM cells) or logic cells (e.g., transistor-transistor logic or TTL circuits), or other electronic circuits that include multiple transistors tightly coupled to each other in a functional arrangement in a cell-like manner.

[0080] Figure 17 An example embodiment of a chip package 1700 according to an embodiment of the present disclosure is shown. As can be seen, chip package 1700 includes one or more dies 1702. One or more dies 1702 may include at least one integrated circuit having a semiconductor device, such as any semiconductor device disclosed herein. In some example configurations, one or more dies 1702 may include any other circuitry for interfacing with other devices formed on the die or connected to chip package 1700.

[0081] As can be further seen, chip package 1700 includes a housing 1704 bonded to a package substrate 1706. Housing 1704 can be any standard or specialized housing and can provide, for example, electromagnetic shielding and environmental protection for the components of chip package 1700. One or more dies 1702 can be conductively coupled to package substrate 1706 using connections 1708, which can be implemented using any number of standard or specialized connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire bonds, to name a few. Package substrate 1706 can be any standard or specialized package substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and lines) extending through the dielectric material between faces of package substrate 1706 or between different locations on each face. In some embodiments, package substrate 1706 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 1712 may be provided on the opposite side of the package substrate 1706 for conductively contacting, for example, a printed circuit board (PCB). One or more vias 1710 extend through the thickness of the package substrate 1706 to provide a conductive path between one or more of the connections 1708 and one or more of the contacts 1712. For ease of illustration, the via 1710 is shown as a single straight column extending through the package substrate 1706, but other configurations may be used (e.g., a damascene, dual damascene, through-silicon via, or a via that zigzags through the thickness of the package substrate 1706 to contact one or more interconnect structures located intermediate therein). In other embodiments, the via 1710 is fabricated from multiple smaller stacked vias or staggered at different locations across the package substrate 1706. In the illustrated embodiment, the contacts 1712 are solder balls (e.g., for bump-based connections or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). In some embodiments, solder resist is provided between contacts 1712 to inhibit shorting.

[0082] In some embodiments, molding material 1714 can be disposed around one or more dies 1702 included within housing 1704 (e.g., as an underfill material between die 1702 and package substrate 1706, and as an overfill material between die 1702 and housing 1704). While the size and mass of molding material 1714 can vary from one embodiment to the next, in some embodiments, molding material 1714 has a thickness of less than 1 mm. Example materials that can be used for molding material 1714 include epoxy molding materials, as appropriate. In some cases, in addition to being electrically insulating, molding material 1714 can also be thermally conductive.

[0083] method

[0084] Figure 18 is a flow chart of a method 1800 for forming at least a portion of an integrated circuit according to an embodiment. The various operations of the method 1800 may be performed in Figures 2A-14A and Figures 2B-14B . However, the correlation of the various operations of method 1800 with the specific components shown in the aforementioned figures is not intended to imply any architectural and / or usage limitations. Rather, the aforementioned figures provide an example embodiment of method 1800. Other operations may be performed before, during, or after any operation of method 1800. For example, method 1800 does not explicitly describe various standard processes that are commonly performed to form transistor structures. Some operations of method 1800 may be performed in an order different from that shown.

[0085] According to some embodiments, method 1800 begins with operation 1802, where a plurality of parallel semiconductor fins are formed including at least a first fin and a second fin. The semiconductor material in the fins can be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed from material deposited onto an underlying substrate. In one such example case, a uniform layer of silicon germanium (SiGe) can be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins can be formed in a so-called aspect ratio capture-based process, where the native fins are etched away so as to leave fin-shaped trenches, which can then be filled with an alternative semiconductor material (e.g., a group IV or group III-V material). In other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during the gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region so that a gate-all-around (GAA) process can then be performed. Again, the alternating layers can be deposited in a uniform thickness and then etched into the fins, or deposited into fin-shaped trenches. The fins can also include a cap structure over each fin that is used to define the position of the fin during, for example, an RIE process. The cap structure can be a dielectric material, such as silicon nitride.

[0086] Method 1800 continues with operation 1804, in which a first dielectric layer is formed adjacent to the sub-fin portions of the first fin and the second fin. The dielectric layer may include any suitable dielectric material, such as silicon dioxide, which is deposited and recessed to a final height surrounding the base sub-fin portion of the fin. In the case of a GAA transistor, the sub-fin portion of the fin may be a portion of the substrate located below the alternating layers of semiconductor material.

[0087] Method 1800 is followed by operation 1806, in which a sacrificial gate is formed over the fin. The sacrificial gate can be patterned (e.g., forming a cross-hatched pattern) using a gate mask layer in the form of strips that extend intersectingly and parallel to each other on the fin. The gate mask layer can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate itself can be formed of any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon.

[0088] According to some embodiments, a spacer structure is also formed on at least the sidewalls of the sacrificial gate. The spacer structure can be deposited and then etched back so that the spacer structure remains primarily only on the sidewalls of any exposed structures. In some cases, the spacer structure can also be formed along the sidewalls of the exposed fins extending orthogonally between the strips of the sacrificial gate. According to some embodiments, the spacer structure can be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0089] Method 1800 is followed by operation 1808, in which portions of the fin adjacent to (e.g., not covered by) the sacrificial gate and spacer structures are removed. Any exposed portions of the fin not covered by the sacrificial gate or spacer structures may be removed using any anisotropic etching process (e.g., reactive ion etching (RIE)). In accordance with some embodiments, etching continues beyond the height of the fin into the substrate such that a groove is etched into the substrate between the remaining portions of the fin. The groove may be filled with one or more dielectric materials or sacrificial materials to facilitate formation of backside contacts.

[0090] Method 1800 is followed by operation 1810, in which source or drain regions are formed at the exposed ends of the first fin and the second fin, such as a first source or drain region at the end of the first fin and a second source or drain region at the end of the second fin. The source or drain region may be formed in an area previously occupied by the exposed fin between the spacer structures. According to some embodiments, the source or drain region is epitaxially grown from the exposed semiconductor material of the fin (or nanoribbon, nanowire or nanosheet, as the case may be) along the outer wall of the spacer structure. In some example embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe). A dielectric filler may be formed between and above the source or drain region along a given source / drain trench. The dielectric filler may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler extends over the source or drain region up to and flush with the top surface of the spacer structure. The dielectric filler also acts as an electrical insulator between adjacent source or drain regions, but some adjacent source or drain regions may merge together during their growth.

[0091] Method 1800 is followed by operation 1812, in which a gate structure is formed over the semiconductor material of each semiconductor fin. The sacrificial gate and any sacrificial layers within the exposed fins between the spacer structures are first removed (in the case of a GAA structure). A gate structure may then be formed to replace the sacrificial gate. The gate structures may each include both a gate dielectric and a gate electrode. According to some embodiments, a gate dielectric is first formed over the exposed semiconductor regions between the spacer structures, and then a gate electrode is formed within the remaining portion of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process such as ALD. The gate electrode may include any conductive material, such as a metal, a metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, chemical plating, CVD, ALD, PECVD, or PVD, to name a few.

[0092] According to some embodiments, at least a portion of the dielectric fill within the source / drain trench can be recessed until the top surface of a given source or drain region in the trench is exposed. A front-side conductive contact can be formed within a recess in the source / drain trench such that the front-side conductive contact contacts the top surface of a given source or drain region in the trench. A separate front-side conductive contact can be formed within the trench over the corresponding source or drain region, or the front-side conductive contact can extend within the trench along the second direction to contact any number of source or drain regions. The front-side conductive contact can include any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt.

[0093] Method 1800 continues with operation 1814, in which the substrate is removed from the backside of the structure. The substrate may be removed via any combination of grinding, polishing, and / or etching processes. In some embodiments, the substrate is thinned down at least until the bottom surface of the first dielectric layer is exposed. In some examples, the only portion of semiconductor material from the substrate remaining after the backside polishing process is the sub-fin portion adjacent to the first dielectric layer.

[0094] Method 1800 is followed by operation 1816, in which the sub-fin portion is removed and replaced with a second dielectric layer. The sub-fin portion can be a semiconductor material (e.g., silicon) that is removed using an appropriate isotropic etching process. Once removed, the absence of the sub-fin region leaves a backside recess that can be filled with one or more appropriate dielectric materials to form a second dielectric layer. In some examples, the second dielectric layer is the same dielectric material as the first dielectric layer. The second dielectric layer can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. According to some embodiments, the second dielectric layer is polished after its deposition so that the bottom surface of the second dielectric layer is substantially coplanar with the bottom surface of the first dielectric layer.

[0095] Method 1800 is followed by operation 1818, wherein a backside groove is formed from the back side of the structure through the first dielectric layer and / or the second dielectric layer. The backside groove can be formed using an RIE process to etch away portions of the first dielectric layer and / or the second dielectric layer to expose the underside of each transistor element. According to some embodiments, the bottom surface of the first source or drain region, the bottom surface of the second source or drain region, and the bottom surface of the gate structure above the semiconductor material of the first fin and / or the second fin are exposed within the groove. In some embodiments, the "L" shaped backside groove is used to connect across adjacent transistor elements along the x-direction and the y-direction. The backside groove is formed through the entire thickness of the first dielectric layer and / or the second dielectric layer.

[0096] Method 1800 is followed by operation 1820, in which a backside conductive structure is formed within the backside recess to electrically contact the underside of each transistor element. According to some embodiments, the backside conductive structure electrically connects any number of different source or drain regions and / or gate structures together. The backside conductive structure can be used to provide an electrical connection between two or more transistor element regions that are not aligned along the first direction and not aligned along the second direction. The backside conductive structure may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt. The bottom surface of the backside conductive structure may be polished using any known polishing technique (e.g., chemical mechanical polishing) so that it is substantially coplanar with the bottom surface of the first dielectric layer and / or the second dielectric layer.

[0097] Example System

[0098] Figure 19 1900 is an example computing system implemented using one or more of the integrated circuit structures disclosed herein, according to some embodiments of the present disclosure. As can be seen, computing system 1900 houses a motherboard 1902. Motherboard 1902 may include several components, including but not limited to a processor 1904 and at least one communication chip 1906, each of which may be physically and electrically coupled to motherboard 1902 or otherwise integrated therein. As will be appreciated, motherboard 1902 may be, for example, any printed circuit board (PCB), a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 1900.

[0099] Depending on its application, computing system 1900 may include one or more other components that may or may not be physically and electrically coupled to motherboard 1902. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disc (CD), a digital versatile disc (DVD), etc.). Any of the components included in computing system 1900 may include one or more integrated circuit structures or devices configured according to example embodiments (e.g., a module including an integrated circuit device on a substrate having one or more semiconductor devices including logic connections made through a backside conductive layer). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 1906 may be part of processor 1904 or otherwise integrated into processor 1904).

[0100] The communication chip 1906 implements wireless communication for data transmission to and from the computing system 1900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data by using modulated electromagnetic radiation via a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. The communication chip 1906 can implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing system 1900 may include multiple communication chips 1906. For example, the first communication chip 1906 can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1906 can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0101] The processor 1904 of the computing system 1900 includes an integrated circuit die packaged within the processor 1904. In some embodiments, the integrated circuit die of the processor includes onboard circuitry implemented with one or more semiconductor devices as described in various ways herein. The term "processor" can refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0102] The communication chip 1906 may also include an integrated circuit die packaged within the communication chip 1906. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described in various manners herein. As will be understood in light of this disclosure, it is noted that multi-standard wireless capabilities may be integrated directly into the processor 1904 (e.g., where the functionality of any chip 1906 is integrated into the processor 1904, rather than having a separate communication chip). It is further noted that the processor 1904 may be a chipset that has such wireless capabilities. In short, any number of processors 1904 and / or communication chips 1906 may be used. Likewise, any one chip or chipset may have multiple functionalities integrated therein.

[0103] In various embodiments, computing system 1900 may be a laptop computer, a netbook, a notebook, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

[0104] It will be understood that in some embodiments, the various components of computing system 1900 can be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components can be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0105] Further example embodiments

[0106] The following examples relate to further embodiments from which numerous arrangements and configurations will be apparent.

[0107] Example 1 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; and a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in a second direction. The second source or drain region is spaced apart from the first source or drain region along the second direction. The integrated circuit further comprises a conductive structure on an underside of each of the first source or drain region, the second source or drain region, and the first gate structure.

[0108] Example 2 includes the integrated circuit of Example 1, wherein the second semiconductor device includes a third source or drain region and a frontside contact on a top surface of the third source or drain region.

[0109] Example 3 includes the integrated circuit of Example 1 or 2, further comprising a dielectric layer below the first semiconductor device and the second semiconductor device, such that the conductive structure extends through an entire thickness of the dielectric layer.

[0110] Example 4 includes the integrated circuit of Example 3, wherein the dielectric layer comprises silicon and oxygen.

[0111] Example 5 includes an integrated circuit according to any one of Examples 1-4, wherein the conductive structure includes a first arm extending under both the first source or drain region and the second source or drain region in a second direction, and a second arm extending under both the first source or drain region and the first gate structure in a first direction, the first direction being substantially orthogonal to the second direction.

[0112] Example 6 includes the integrated circuit of any of Examples 1-5, wherein the conductive structure is L-shaped.

[0113] Example 7 includes the integrated circuit of any of Examples 1-6, wherein the conductive structure is one of a power rail, a ground rail, or a control signal conductor.

[0114] Example 8 includes the integrated circuit of any of Examples 1-7, wherein the first source or drain region is a p-type source or drain region and the second source or drain region is an n-type source or drain region.

[0115] Example 9 includes the integrated circuit of any of Examples 1-8, wherein the conductive structure includes a conductive liner and a conductive filler.

[0116] Example 10 includes the integrated circuit of Example 9, wherein the conductive liner comprises titanium and nitrogen, and the conductive fill comprises tungsten.

[0117] Example 11 includes the integrated circuit of any of Examples 1-10, wherein the first semiconductor device and the second semiconductor device are arranged within a static random access memory (SRAM) unit cell.

[0118] Example 12 includes the integrated circuit of any of Examples 1-10, wherein the first semiconductor device and the second semiconductor device are arranged within a memory unit cell.

[0119] Example 13 includes the integrated circuit of any of Examples 1-10, wherein the first semiconductor device and the second semiconductor device are arranged within a logic unit cell.

[0120] Example 14 includes the integrated circuit of any of Examples 1-10, wherein the first semiconductor device and the second semiconductor device are arranged within a multi-transistor unit cell.

[0121] Example 15 is a printed circuit board comprising the integrated circuit according to any one of Examples 1-14.

[0122] Example 16 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies comprises: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in a second direction; and a conductive structure located on an underside of each of the first source or drain region, the second source or drain region, and the first gate structure. The second source or drain region is spaced apart from the first source or drain region along the second direction.

[0123] Example 17 includes the electronic device of Example 16, wherein the second semiconductor device includes a third source or drain region and a frontside contact on a top surface of the third source or drain region.

[0124] Example 18 includes an electronic device according to Example 16 or 17, wherein at least one of the one or more dies further includes a dielectric layer below the first semiconductor device and the second semiconductor device, such that the conductive structure extends through the entire thickness of the dielectric layer.

[0125] Example 19 includes the electronic device of Example 18, wherein the dielectric layer includes silicon and oxygen.

[0126] Example 20 includes an electronic device according to any one of Examples 16-19, wherein the conductive structure includes a first arm extending below both the first source or drain region and the second source or drain region in a second direction, and a second arm extending below both the first source or drain region and the first gate structure in a first direction, the first direction being substantially orthogonal to the second direction.

[0127] Example 21 includes the electronic device of any of Examples 16-20, wherein the first source or drain region is a p-type source or drain region and the second source or drain region is an n-type source or drain region.

[0128] Example 22 includes the electronic device of any of Examples 16-21, wherein the conductive structure includes a conductive liner and a conductive filler.

[0129] Example 23 includes the electronic device of Example 22, wherein the conductive liner includes titanium and nitrogen, and the conductive filler includes tungsten.

[0130] Example 24 includes the electronic device of any of Examples 16-23, wherein the first semiconductor device and the second semiconductor device are arranged within an SRAM unit cell.

[0131] Example 25 includes the electronic device of any of Examples 16-24, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0132] Example 26 is a method of forming an integrated circuit. The method includes: forming a first fin including a first semiconductor region and a second fin including a second semiconductor region extending above a substrate; forming a first dielectric layer adjacent to a sub-fin portion of each of the first fin and the second fin; forming a sacrificial gate and a spacer structure over the first fin and the second fin; removing portions of the first fin and the second fin not covered by the sacrificial gate and the spacer structure; forming a first source or drain region at an exposed end of the first semiconductor region and a second source or drain region at an exposed end of the second semiconductor region; replacing the sacrificial gate with a first gate structure over the first semiconductor region and with a second gate structure over the second semiconductor region; removing the substrate to expose a backside of the first dielectric layer; replacing the sub-fin portion of each of the first fin and the second fin with a second dielectric layer; forming a recess through both the first dielectric layer and the second dielectric layer to expose a bottom surface of the first source or drain region, a bottom surface of the second source or drain region, and a bottom surface of the first gate structure; and forming a conductive structure within the recess.

[0133] Example 27 includes the method of Example 26, wherein forming the recess comprises removing portions of the first dielectric layer and the second dielectric layer using a reactive ion etching (RIE) process.

[0134] Example 28 includes the method of Example 26 or 27, further comprising forming a third source or drain region at the exposed end of the second semiconductor region, and forming a conductive contact on a top surface of the third source or drain region.

[0135] Example 29 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending from the first source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction; a third semiconductor device having a third semiconductor region extending from the second source or drain region in the first direction and a third gate structure extending over the third semiconductor region in the second direction; a fourth semiconductor device having a fourth semiconductor region extending from the third source or drain region in the first direction and a fourth gate structure extending over the fourth semiconductor region in the second direction; a fifth semiconductor device having a fifth semiconductor region extending from the fourth source or drain region in the first direction and a fifth gate structure extending over the fifth semiconductor region in the second direction; and a sixth semiconductor device having a sixth semiconductor region extending from the fourth source or drain region in the first direction and a sixth gate structure extending over the sixth semiconductor region in the second direction. The first gate structure and the third gate structure are coupled together in a first gate trench, and the fourth gate structure and the sixth gate structure are coupled together in a second gate trench parallel to the first gate trench. The integrated circuit also includes a conductive structure on an underside of each of the first source or drain region, the second source or drain region, and the conductive portion of the second gate trench.

[0136] Example 30 includes the integrated circuit of Example 29, wherein the first semiconductor device includes a fifth source or drain region and a backside contact on a bottom surface of the fifth source or drain region.

[0137] Example 31 includes the integrated circuit of Example 29 or 30, further comprising a dielectric layer beneath each of the semiconductor devices, such that the conductive structure extends through the entire thickness of the dielectric layer.

[0138] Example 32 includes the integrated circuit of Example 31, wherein the dielectric layer comprises silicon and oxygen.

[0139] Example 33 includes an integrated circuit according to any one of Examples 29 to 32, wherein the conductive structure includes a first arm extending under both the first source or drain region and the second source or drain region in a second direction, and a second arm extending under both the second source or drain region and the conductive portion of the second gate trench in the first direction, the first direction being substantially orthogonal to the second direction.

[0140] Example 34 includes the integrated circuit of any of Examples 29 to 33, wherein the first source or drain region is an n-type source or drain region and the second source or drain region is a p-type source or drain region.

[0141] Example 35 includes the integrated circuit of any of Examples 29-34, wherein the conductive structure includes a conductive liner and a conductive filler.

[0142] Example 36 includes the integrated circuit of Example 35, wherein the conductive liner comprises titanium and nitrogen, and the conductive fill comprises tungsten.

[0143] Example 37 includes the integrated circuit of any of Examples 29-36, wherein each of the first semiconductor device, the second semiconductor device, the third semiconductor device, the fourth semiconductor device, the fifth semiconductor device, and the sixth semiconductor device is arranged within an SRAM unit cell.

[0144] Example 38 includes an integrated circuit according to any one of Examples 29-37, wherein the conductive structure is a first conductive structure and the integrated circuit further includes a second conductive structure on the underside of each of the third source or drain region, the fourth source or drain region, and the conductive portion of the first gate trench.

[0145] Example 39 includes the integrated circuit of any of Examples 29-37, further comprising a first gate cut extending along the first direction between the second gate structure and the fourth gate structure, and a second gate cut extending along the first direction between the third gate structure and the fifth gate structure.

[0146] Example 40 is a printed circuit board comprising the integrated circuit according to any one of Examples 29-39.

[0147] The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but by the appended claims.

Claims

1. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction, the second source or drain region being spaced apart from the first source or drain region along the second direction; as well as A conductive structure is located on a lower side of each of the first source or drain region, the second source or drain region, and the first gate structure.

2. The integrated circuit according to claim 1, wherein: The second semiconductor device includes a third source or drain region and a frontside contact on a top surface of the third source or drain region. 3 . The integrated circuit of claim 1 , further comprising a dielectric layer beneath the first semiconductor device and the second semiconductor device, such that the conductive structure extends through an entire thickness of the dielectric layer.

4. The integrated circuit according to claim 3, wherein: The dielectric layer includes silicon and oxygen.

5. The integrated circuit according to claim 1, wherein: The conductive structure includes: a first arm extending in the second direction below both the first source or drain region and the second source or drain region; and A second arm extends below both the first source or drain region and the first gate structure in the first direction, the first direction being substantially orthogonal to the second direction.

6. The integrated circuit according to any one of claims 1 to 5, wherein: The conductive structure is L-shaped.

7. The integrated circuit according to any one of claims 1 to 5, wherein: The conductive structure is one of a power rail, a ground rail, or a control signal conductor.

8. The integrated circuit according to any one of claims 1 to 5, wherein: The first source or drain region is a p-type source or drain region, and the second source or drain region is an n-type source or drain region.

9. The integrated circuit according to any one of claims 1 to 5, wherein: The conductive structure includes a conductive liner and a conductive filler.

10. The integrated circuit according to claim 9, wherein: The conductive liner includes titanium and nitrogen, and the conductive filler includes tungsten.

11. The integrated circuit according to any one of claims 1 to 5, wherein: The first semiconductor device and the second semiconductor device are arranged within a static random access memory (SRAM) unit cell.

12. The integrated circuit according to any one of claims 1 to 5, wherein: The first semiconductor device and the second semiconductor device are arranged within a memory unit cell, a logic unit cell, or a multi-transistor unit cell.

13. A printed circuit board comprising the integrated circuit according to any one of claims 1 to 5.

14. An electronic device comprising: A chip package comprising one or more dies, at least one of the one or more dies comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction, the second source or drain region being spaced apart from the first source or drain region along the second direction; and A conductive structure is located on a lower side of each of the first source or drain region, the second source or drain region, and the first gate structure.

15. The electronic device according to claim 14, wherein The at least one of the one or more dies further includes a dielectric layer beneath the first semiconductor device and the second semiconductor device, such that the conductive structure extends through an entire thickness of the dielectric layer.

16. The electronic device according to claim 14 or 15, wherein: The conductive structure includes: a first arm extending in the second direction below both the first source or drain region and the second source or drain region; and A second arm extends below both the first source or drain region and the first gate structure in the first direction, the first direction being substantially orthogonal to the second direction.

17. The electronic device according to claim 14 or 15, wherein: The first source or drain region is a p-type source or drain region, and the second source or drain region is an n-type source or drain region.

18. The electronic device according to claim 14 or 15, wherein: The first semiconductor device and the second semiconductor device are arranged within an SRAM unit cell.

19. The electronic device according to claim 14 or 15, further comprising a printed circuit board, wherein The chip package is coupled to the printed circuit board.

20. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending from the first source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction; a third semiconductor device having a third semiconductor region extending from the second source or drain region in the first direction and a third gate structure extending over the third semiconductor region in the second direction; a fourth semiconductor device having a fourth semiconductor region extending from the third source or drain region in the first direction and a fourth gate structure extending over the fourth semiconductor region in the second direction; a fifth semiconductor device having a fifth semiconductor region extending from a fourth source or drain region in the first direction and a fifth gate structure extending over the fifth semiconductor region in the second direction; a sixth semiconductor device having a sixth semiconductor region extending from the fourth source or drain region in the first direction and a sixth gate structure extending over the sixth semiconductor region in the second direction, wherein the first gate structure and the third gate structure are coupled together in a first gate trench, and the fourth gate structure and the sixth gate structure are coupled together in a second gate trench parallel to the first gate trench; as well as A conductive structure is located on an underside of each of the first source or drain region, the second source or drain region, and the conductive portion of the second gate trench.

21. The integrated circuit of claim 20, further comprising a dielectric layer beneath each of the semiconductor devices, such that the conductive structure extends through the entire thickness of the dielectric layer.

22. The integrated circuit of claim 20, wherein: The conductive structure includes: a first arm extending in the second direction below both the first source or drain region and the second source or drain region; and A second arm extends under both the second source or drain region and the conductive portion of the second gate trench in the first direction, the first direction being substantially orthogonal to the second direction.

23. The integrated circuit of claim 20, wherein: The first source or drain region is an n-type source or drain region, and the second source or drain region is a p-type source or drain region.

24. The integrated circuit of claim 20, wherein: The conductive structure is a first conductive structure, and the integrated circuit further includes a second conductive structure on an underside of each of the third source or drain region, the fourth source or drain region, and the conductive portion of the first gate trench.

25. The integrated circuit according to any one of claims 20 to 24, further comprising: a first gate cutout extending along the first direction between the second gate structure and the fourth gate structure; as well as A second gate cutout extends along the first direction between the third gate structure and the fifth gate structure.

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