Pixel circuit, driving method and display device

Abstract

The invention discloses a pixel circuit, a driving method and a display device. The pixel circuit comprises a light-emitting element (E1), a driving circuit (10), a first control circuit (11), a second control circuit (12) and a third control circuit (13). The second control circuit (12) controls the connection or disconnection between the first node (N1) and the first end of the first control circuit (11) under the control of a first refresh control signal (NG1); the third control circuit (13) controls the connection or disconnection between the first end of the drive circuit (10) and the second end of the first control circuit (11) under the control of a second first refresh control signal (NG2); and the first control circuit (11) controls the connection or disconnection between the first end of the first control circuit (11) and the second end of the first control circuit (11) under the control of the second refresh control signal (CG). The first refresh control signals (NG1 and NG2) are used for controlling row refresh or row holding, the second refresh control signals (CG) are used for controlling column refresh or column holding, updating of local pictures of the screen is achieved, the rest pictures do not need to be charged and discharged for multiple times, and therefore display power consumption is further reduced.

Description

Pixel circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, and a display device. Background Art

[0002] In related technologies, when updating the screen, the display panel still needs to initialize and write all pixel voltages within one frame time. However, in some special screens (such as AOD (always on display) screens, static screens or screens that are updated less frequently, etc.), most of the pixel voltages on the entire screen do not need to be updated, that is, the original display brightness can be maintained through low-leakage transistors. The repeated refresh of these pixels causes a certain amount of power consumption to be wasted.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, comprising a light-emitting element, a driving circuit, a first control circuit, a second control circuit, and a third control circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, and the first terminal of the driving circuit is electrically connected to the light-emitting element, and is used to drive the light-emitting element under the control of the potential of the first node;

[0006] The second control circuit is electrically connected to the first first refresh control terminal, the first node, and the first terminal of the first control circuit, respectively, and is used to control the connection or disconnection between the first node and the first terminal of the first control circuit under the control of the first first refresh control signal of the first first refresh control terminal;

[0007] The third control circuit is electrically connected to the second first refresh control terminal, the first terminal of the driving circuit, and the second terminal of the first control circuit, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the second terminal of the first control circuit under the control of the second first refresh control signal provided by the second first refresh control terminal;

[0008] The control end of the first control circuit is electrically connected to the second refresh control end, and the first control circuit is used to control the connection or disconnection between the first end of the first control circuit and the second end of the first control circuit under the control of a second refresh control signal provided by the second refresh control end.

[0009] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit;

[0010] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second terminal of the driving circuit under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0011] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit;

[0012] The data writing circuit is electrically connected to the writing control terminal, the data line and the second end of the driving circuit respectively, and is used to write the data voltage provided by the data line into the second end of the driving circuit under the control of the writing control signal provided by the writing control terminal.

[0013] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a storage circuit and a second light emitting control circuit;

[0014] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0015] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control terminal;

[0016] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0017] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first reset circuit;

[0018] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first terminal of the driving circuit respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first terminal of the driving circuit under the control of the first reset control signal provided by the first reset control terminal.

[0019] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0020] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0021] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third reset circuit;

[0022] The third reset circuit is electrically connected to the third reset control terminal, the third initial voltage terminal and the second terminal of the driving circuit respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal.

[0023] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third reset circuit;

[0024] The third reset circuit is electrically connected to the third reset control terminal, the third initial voltage terminal and the first terminal of the driving circuit respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal.

[0025] Optionally, the driving circuit includes a driving transistor, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor;

[0026] The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the light emitting element;

[0027] The gate of the second transistor is electrically connected to the first refresh control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first electrode of the first transistor;

[0028] The gate of the third transistor is electrically connected to the second first refresh control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;

[0029] The gate of the first transistor is electrically connected to the second refresh control terminal.

[0030] Optionally, the first transistor, the second transistor and the third transistor are oxide transistors.

[0031] Optionally, the first light emitting control circuit includes a fourth transistor;

[0032] The gate of the fourth transistor is electrically connected to the first light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second terminal of the driving circuit.

[0033] Optionally, the data writing circuit includes a fifth transistor;

[0034] A gate of the fifth transistor is electrically connected to the write control terminal, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit.

[0035] Optionally, the second light emitting control circuit includes a sixth transistor;

[0036] The gate of the sixth transistor is electrically connected to the second light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.

[0037] Optionally, the first reset circuit includes a seventh transistor;

[0038] The gate of the seventh transistor is electrically connected to the first reset control terminal, the first electrode of the seventh transistor is electrically connected to the first initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first terminal of the driving circuit.

[0039] Optionally, the second reset circuit includes an eighth transistor;

[0040] The gate of the eighth transistor is electrically connected to the second reset control terminal, the first electrode of the eighth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

[0041] Optionally, the third reset circuit includes a ninth transistor;

[0042] The gate of the ninth transistor is electrically connected to the third reset control terminal, the first electrode of the ninth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second terminal of the driving circuit.

[0043] Optionally, the third reset circuit includes a ninth transistor;

[0044] The gate of the ninth transistor is electrically connected to the third reset control terminal, the first electrode of the ninth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first terminal of the driving circuit.

[0045] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit. The driving method includes:

[0046] The driving circuit drives the light emitting element under the control of the potential of the first node;

[0047] The second control circuit controls the connection or disconnection between the first node and the first end of the first control circuit under the control of the first refresh control signal;

[0048] Under the control of the second first refresh control signal of the third control circuit, the first end of the driving circuit is controlled to be connected or disconnected with the second end of the first control circuit;

[0049] The first control circuit controls the connection or disconnection between the first end of the first control circuit and the second end of the first control circuit under the control of the second refresh control signal.

[0050] Optionally, the driving method includes:

[0051] In a row refresh frame, the second control circuit controls the first node to be connected to the first end of the first control circuit under the control of a first first refresh control signal; and the third control circuit controls the first end of the driving circuit to be connected to the second end of the first control circuit under the control of a second first refresh control signal.

[0052] In the row hold frame, the second control circuit controls the first node and the first end of the first control circuit to be disconnected under the control of the first first refresh control signal; the third control circuit controls the first end of the driving circuit and the second end of the first control circuit to be disconnected under the control of the second first refresh control signal;

[0053] In a column refresh frame, the second control circuit controls the first node to be connected to the first end of the first control circuit under the control of the first refresh control signal;

[0054] In the column holding frame, the second control circuit controls the first node to be disconnected from the first end of the first control circuit under the control of the first refresh control signal.

[0055] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure;

[0057] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0058] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] FIG5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] FIG6 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 ;

[0062] FIG7 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 ;

[0063] FIG8 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 ;

[0064] FIG9 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 ;

[0065] FIG10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] FIG11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] FIG12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] FIG13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] FIG14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] FIG16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0073] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0074] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0075] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1, a driving circuit 10, a first control circuit 11, a second control circuit 12, and a third control circuit 13;

[0076] The control terminal of the driving circuit 10 is electrically connected to the first node N1, and the first terminal of the driving circuit 10 is electrically connected to the light emitting element E1, for driving the light emitting element E1 under the control of the potential of the first node N1;

[0077] The second control circuit 12 is electrically connected to the first first refresh control terminal NG1, the first node N1, and the first terminal of the first control circuit 11, respectively, and is used to control the connection or disconnection between the first node N1 and the first terminal of the first control circuit 11 under the control of the first first refresh control signal of the first first refresh control terminal NG1;

[0078] The third control circuit 13 is electrically connected to the second first refresh control terminal NG2, the first terminal of the driving circuit 10, and the second terminal of the first control circuit 11, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit 10 and the second terminal of the first control circuit 11 under the control of the second first refresh control signal provided by the second first refresh control terminal NG2;

[0079] The control end of the first control circuit 11 is electrically connected to the second refresh control end CG, and the first control circuit 11 is used to control the connection or disconnection between the first end of the first control circuit 11 and the second end of the first control circuit 11 under the control of the second refresh control signal provided by the second refresh control end CG.

[0080] In the pixel circuit described in the embodiment of the present disclosure, the first first refresh control terminal and the second first refresh control terminal may be row refresh control terminals, and the second refresh control terminal may be a column refresh control terminal.

[0081] In the pixel circuit described in at least one embodiment of the present disclosure, when the transistors included in the second control circuit and the transistors included in the third control circuit are both n-type transistors, or the transistors included in the second control circuit and the transistors included in the third control circuit are both p-type transistors, the first first refresh control terminal and the second first refresh control terminal can be the same first refresh control terminal.

[0082] In the pixel circuit described in at least one embodiment of the present disclosure, the first control circuit is arranged between the second control circuit and the third control circuit, and the potential of the second refresh control signal provided by the second refresh control terminal is switched during the blank time period. This can avoid the potential jump of the second refresh control signal affecting the potential of the first node and the potential of the first end of the driving circuit through the parasitic capacitance of the transistor included in the first control circuit, thereby preventing defects such as multi-pulse split screen and flickering.

[0083] In related technologies, when updating the screen, the display panel still needs to initialize and write all pixel voltages within one frame time. However, in some special screens (such as AOD (always on display) screens, static screens or screens that are updated less frequently, etc.), most of the pixel voltages on the entire screen do not need to be updated, that is, the original display brightness can be maintained through low-leakage transistors. The repeated refresh of these pixels causes a certain amount of power consumption to be wasted.

[0084] The pixel circuit described in the embodiment of the present disclosure can control row refresh or row hold through a first refresh control signal, and control column refresh or column hold through a second refresh control signal, so as to update a local screen image, while the remaining images do not need to be charged and discharged multiple times, thereby further reducing the display power consumption. By partially updating the display image, ultra-low power consumption of wearable display products, mobile display products, NB (notebook) and other display products can be achieved.

[0085] When the pixel circuit described in the embodiment of the present disclosure is in operation,

[0086] When performing row refresh and parallel refresh, during at least a portion of a blank period between two frame times, and during a next frame time adjacent to the blank period, the potential of the second refresh control signal provided by the second refresh control terminal CG is an effective voltage; during the blank period between the two frame times, and during a next frame time adjacent to the blank period, the first control circuit 11 controls the first terminal of the first control circuit 11 to be connected to the second terminal of the first control circuit 11 under the control of the second refresh control signal; during a data writing period included in the next frame time, the second control circuit 12 controls the first node N1 to be connected to the first terminal of the first control circuit 11 under the control of the first first refresh control signal provided by the first first refresh control terminal NG1, and the third control circuit 13 controls the first terminal of the driving circuit 10 to be connected to the second terminal of the first control circuit 11 under the control of the second first refresh control signal provided by the second first refresh control terminal NG2, so as to control the first node N1 to be connected to the first terminal of the driving circuit 10, so as to enable data voltage refresh;

[0087] When performing row hold and parallel refresh, during at least part of a blank period between two frame times, and during a next frame time adjacent to the blank period, the potential of the second refresh control signal provided by the second refresh control terminal CG is an effective voltage; during the blank period between the two frame times, and during a next frame time adjacent to the blank period, the first control circuit 11 controls the first terminal of the first control circuit 11 to be connected to the second terminal of the first control circuit 11 under the control of the second refresh control signal; during a data writing period included in the next frame time, the second control circuit 12 controls the first node N1 to be disconnected from the first terminal of the first control circuit 11 under the control of the first first refresh control signal provided by the first first refresh control terminal NG1, and the third control circuit 13 controls the first terminal of the driving circuit 10 to be disconnected from the second terminal of the first control circuit 11 under the control of the second first refresh control signal provided by the second first refresh control terminal NG2, then during the next frame time, the pixel circuit does not update the data voltage and maintains the display brightness of the previous frame time;

[0088] When performing row refresh and parallel hold, during at least a portion of a blank period between two frame times, and during a next frame time adjacent to the blank period, the potential of the second refresh control signal provided by the second refresh control terminal CG is an invalid voltage, the control terminal of the first control circuit 11 is electrically connected to the second refresh control terminal CG, and the first control circuit 11 controls the first terminal of the first control circuit 11 and the second terminal of the first control circuit 11 to be disconnected under the control of the second refresh control signal; the second control circuit 12 is used to control the first node N1 and the first terminal of the first control circuit 11 to be connected under the control of the first first refresh control signal; the third control circuit 13 controls the first terminal of the driving circuit 10 and the second terminal of the first control circuit 11 to be disconnected under the control of the second first refresh control signal; in the next frame time, the pixel circuit does not update the data voltage and maintains the display brightness of the previous frame time;

[0089] When performing row hold and column hold, during at least part of the blank time period between two frame times, and during the next frame time adjacent to the blank time period, the potential of the second refresh control signal provided by the second refresh control terminal CG is an invalid voltage, the control end of the first control circuit 11 is electrically connected to the second refresh control terminal CG, and the first control circuit 11 controls the first end of the first control circuit 11 and the second end of the first control circuit 11 to be disconnected under the control of the second refresh control signal; the second control circuit 12 is used to control the first node N1 and the first end of the first control circuit 11 to be disconnected under the control of the first first refresh control signal; the third control circuit 13 controls the first end of the driving circuit 10 and the second end of the first control circuit 11 to be disconnected under the control of the second first refresh control signal; in the next frame time, the pixel circuit does not update the data voltage and maintains the display brightness of the previous frame time.

[0090] In at least one embodiment of the present disclosure, when the transistor included in the first control circuit is an n-type transistor, the effective voltage is a high voltage and the invalid voltage is a low voltage; when the transistor included in the first control circuit is a p-type transistor, the effective voltage is a low voltage and the invalid voltage is a high voltage.

[0091] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit;

[0092] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second terminal of the driving circuit under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0093] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, which controls the connection or disconnection between the power supply voltage terminal and the second terminal of the driving circuit under the control of a first light-emitting control signal to perform light-emitting control.

[0094] In at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit;

[0095] The data writing circuit is electrically connected to the writing control terminal, the data line and the second end of the driving circuit respectively, and is used to write the data voltage provided by the data line into the second end of the driving circuit under the control of the writing control signal provided by the writing control terminal.

[0096] In a specific implementation, the pixel circuit may further include a data writing circuit, and the data writing circuit writes the data voltage provided by the data line into the second end of the driving circuit under the control of a writing control signal.

[0097] The pixel circuit according to at least one embodiment of the present disclosure further includes an energy storage circuit and a second light emitting control circuit;

[0098] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0099] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control terminal;

[0100] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0101] Optionally, the first voltage terminal may be a low voltage terminal.

[0102] In a specific implementation, the pixel circuit may further include an energy storage circuit and a second light-emitting control circuit, wherein the energy storage circuit maintains the potential of the first node, and the second light-emitting control circuit controls the connection or disconnection between the first end of the driving circuit and the first pole of the light-emitting element under the control of a second light-emitting control signal to perform light-emitting control.

[0103] In at least one embodiment of the present disclosure, when the transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit are both n-type transistors or both p-type transistors, the first light-emitting control terminal and the second light-emitting control terminal can be the same light-emitting control terminal.

[0104] In at least one embodiment of the present disclosure, the pixel circuit further includes a first reset circuit;

[0105] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first terminal of the driving circuit respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first terminal of the driving circuit under the control of the first reset control signal provided by the first reset control terminal.

[0106] In a specific implementation, the pixel circuit may further include a first reset circuit, which, under the control of a first reset control signal, writes a first initial voltage into the first end of the driving circuit to reset the potential of the first end of the driving circuit, and when the first node is connected to the first end of the driving circuit, resets the potential of the first node.

[0107] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0108] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0109] In a specific implementation, the pixel circuit may further include a second reset circuit, which, under the control of a second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0110] In at least one embodiment of the present disclosure, the second reset control terminal and the write control terminal may be the same control terminal, or the second reset control terminal and the third reset control terminal may be the same control terminal, but the present invention is not limited thereto.

[0111] In at least one embodiment of the present disclosure, the pixel circuit further includes a third reset circuit;

[0112] The third reset circuit is electrically connected to the third reset control terminal, the third initial voltage terminal and the second terminal of the driving circuit respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal.

[0113] In a specific implementation, the pixel circuit may further include a third reset circuit, and the third reset circuit writes a third initial voltage into the second end of the driving circuit under the control of a third reset control signal.

[0114] In at least one embodiment of the present disclosure, the pixel circuit further includes a third reset circuit;

[0115] The third reset circuit is electrically connected to the third reset control terminal, the third initial voltage terminal and the first terminal of the driving circuit respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal.

[0116] In a specific implementation, the pixel circuit may further include a third reset circuit, and the third reset circuit writes a third initial voltage into the first end of the driving circuit under the control of a third reset control signal.

[0117] In at least one embodiment of the present disclosure, the second reset control terminal and the third reset control terminal may be the same control terminal, but the present invention is not limited thereto.

[0118] As shown in FIG2 , based on the embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 21 ;

[0119] The first light emitting control circuit 21 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal ELVDD, and the second terminal of the driving circuit 10, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second terminal of the driving circuit 10 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0120] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 22;

[0121] The data writing circuit 22 is electrically connected to the write control terminal PG, the data line DT and the second end of the driving circuit 10 respectively, and is used to write the data voltage provided by the data line DT into the second end of the driving circuit 10 under the control of the write control signal provided by the write control terminal PG;

[0122] The pixel circuit according to at least one embodiment of the present disclosure further includes a storage circuit 20 and a second light emitting control circuit 23;

[0123] The energy storage circuit 20 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0124] The second light emitting control circuit 23 is electrically connected to the light emitting control terminal EM, the first terminal of the driving circuit 10, and the first electrode of the light emitting element E1, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit 10 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0125] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0126] The pixel circuit according to at least one embodiment of the present disclosure further includes a first reset circuit 24;

[0127] The first reset circuit 24 is electrically connected to the first reset control terminal PR, the first initial voltage terminal I1, and the first terminal of the driving circuit 10, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first terminal of the driving circuit 10 under the control of the first reset control signal provided by the first reset control terminal PR;

[0128] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit 25;

[0129] The second reset circuit 25 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the first electrode of the light-emitting element E1, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal R2.

[0130] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third reset circuit 31 ;

[0131] The third reset circuit 31 is electrically connected to the third reset control terminal HR, the third initial voltage terminal I3 and the second terminal of the driving circuit 10, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the second terminal of the driving circuit 10 under the control of the third reset control signal provided by the third reset control terminal HR.

[0132] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third reset circuit 31 ;

[0133] The third reset circuit 31 is electrically connected to the third reset control terminal HR, the third initial voltage terminal I3 and the first terminal of the driving circuit 10, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first terminal of the driving circuit 10 under the control of the third reset control signal provided by the third reset control terminal HR.

[0134] Optionally, the driving circuit includes a driving transistor, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor;

[0135] The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the light emitting element;

[0136] The gate of the second transistor is electrically connected to the first refresh control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first electrode of the first transistor;

[0137] The gate of the third transistor is electrically connected to the second first refresh control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;

[0138] The gate of the first transistor is electrically connected to the second refresh control terminal.

[0139] In at least one embodiment of the present disclosure, the first transistor, the second transistor, and the third transistor are oxide transistors.

[0140] In a specific implementation, the first transistor, the second transistor and the third transistor can all be oxide transistors. The oxide transistor has low leakage. During low-frequency display, the oxide transistor can ensure that the voltage maintained by the energy storage circuit is maintained for a longer period of time, thereby reducing repeated charging and discharging of the data line and reducing power consumption.

[0141] Optionally, the oxide transistor may be an IGZO (Indium Gallium Zinc Oxide) transistor, but is not limited thereto.

[0142] Optionally, the first light emitting control circuit includes a fourth transistor;

[0143] The gate of the fourth transistor is electrically connected to the first light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second terminal of the driving circuit.

[0144] Optionally, the data writing circuit includes a fifth transistor;

[0145] A gate of the fifth transistor is electrically connected to the write control terminal, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit.

[0146] Optionally, the second light emitting control circuit includes a sixth transistor;

[0147] The gate of the sixth transistor is electrically connected to the second light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.

[0148] Optionally, the first reset circuit includes a seventh transistor;

[0149] The gate of the seventh transistor is electrically connected to the first reset control terminal, the first electrode of the seventh transistor is electrically connected to the first initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first terminal of the driving circuit.

[0150] Optionally, the second reset circuit includes an eighth transistor;

[0151] The gate of the eighth transistor is electrically connected to the second reset control terminal, the first electrode of the eighth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

[0152] Optionally, the third reset circuit includes a ninth transistor;

[0153] The gate of the ninth transistor is electrically connected to the third reset control terminal, the first electrode of the ninth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the second terminal of the driving circuit.

[0154] Optionally, the third reset circuit includes a ninth transistor;

[0155] The gate of the ninth transistor is electrically connected to the third reset control terminal, the first electrode of the ninth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first terminal of the driving circuit.

[0156] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG4 , the light emitting element is an organic light emitting diode O1 ; the energy storage circuit includes a storage capacitor Cst;

[0157] The driving circuit includes a driving transistor T0, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the third control circuit includes a third transistor T3;

[0158] The gate of the driving transistor T0 is electrically connected to the first node N1;

[0159] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0160] The gate of the second transistor T2 is electrically connected to the first refresh control terminal NG, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the source of the first transistor T1;

[0161] The gate of the third transistor T3 is electrically connected to the first refresh control terminal NG, the source of the third transistor T3 is electrically connected to the drain of the first transistor T1, and the drain of the third transistor T3 is electrically connected to the drain of the driving transistor T0;

[0162] The gate of the first transistor T1 is electrically connected to the second refresh control terminal CG;

[0163] The first light emitting control circuit includes a fourth transistor T4;

[0164] The gate of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the source of the driving transistor T0;

[0165] The data writing circuit includes a fifth transistor T5;

[0166] The gate of the fifth transistor T5 is electrically connected to the write control terminal PG, the source of the fifth transistor T5 is electrically connected to the data line DT, and the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;

[0167] The second light emitting control circuit includes a sixth transistor T6;

[0168] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;

[0169] The first reset circuit includes a seventh transistor T7;

[0170] The gate of the seventh transistor T7 is electrically connected to the first reset control terminal PR, the source of the seventh transistor T7 is electrically connected to the first initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the drain of the driving transistor T0; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0171] The second reset circuit includes an eighth transistor T8;

[0172] The gate of the eighth transistor T8 is electrically connected to the third reset control terminal HR, the source of the eighth transistor T8 is electrically connected to the second initial voltage terminal I2, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0173] The third reset circuit includes a ninth transistor T9;

[0174] The gate of the ninth transistor T9 is electrically connected to the third reset control terminal HR, the source of the ninth transistor T9 is electrically connected to the third initial voltage terminal I3, and the drain of the ninth transistor T9 is electrically connected to the source of the driving transistor T0; the third initial voltage terminal I3 is used to provide a third initial voltage Vi3.

[0175] In FIG. 5 , the second node N2 is electrically connected to the source of T0 , the third node N3 is electrically connected to the drain of T0 , and the fourth node N4 is electrically connected to the anode of O1 .

[0176] In at least one embodiment of the pixel circuit shown in FIG. 5 , the second reset control terminal and the third reset control terminal HR are the same control terminal.

[0177] In at least one embodiment of the pixel circuit shown in FIG. 5 , T1 , T2 , and T3 are all IGZO TFTs (thin film transistors).

[0178] In at least one embodiment of the pixel circuit shown in FIG. 5 , T1 , T2 , and T3 are all n-type transistors, and T4 - T9 are all p-type transistors.

[0179] In at least one embodiment of the pixel circuit shown in Figure 5, T1, T2 and T3 use IGZO TFTs that greatly reduce leakage. During low-frequency display, the IGZO TFT can ensure that the potential of the first node N1 is maintained for a long time, thereby reducing the repeated charging and discharging of the data line and reducing power consumption. The write control terminal PG is responsible for writing the data voltage, the first refresh control terminal NG is responsible for resetting Cst, extracting the threshold voltage and writing the data voltage to the first node N1, the third reset control terminal HR is responsible for resetting the potential of the second node N2 and the potential of the anode of O1, and the first reset control terminal PR is responsible for resetting the potential of the first node N1 and the potential of the third node N3.

[0180] In at least one embodiment of the pixel circuit shown in Figure 5, T1 is set between T2 and T3, and the potential of the second refresh control signal provided by the second refresh control terminal CG is switched during the blank time period. This can avoid the potential jump of the second refresh control signal affecting the potential of N1 and the potential of N3 through the parasitic capacitance of T1, thereby preventing the occurrence of multi-pulse split screen, flickering and other defects.

[0181] When at least one embodiment of the pixel circuit shown in Figure 5 is in operation, the high-frequency refresh and low-frequency refresh in the row direction are controlled by the first refresh control terminal NG, and the high-frequency refresh and low-frequency refresh in the column direction are controlled by the second refresh control terminal CG. Through the combination of high-frequency and low-frequency refresh of rows and columns, different refresh rates can be achieved in different display areas, thereby minimizing power consumption.

[0182] At least one embodiment of the pixel circuit shown in FIG5 of the present disclosure is in operation.

[0183] When performing row refresh and parallel refresh, the voltage of the second refresh control terminal CG is switched to a high voltage during the blank period and maintained for the entire frame time. In the effective display area, the pixel circuits of each row are scanned row by row. For a certain row of pixel circuits, first, the light-emitting control terminal EM closes T4 and T5, the first refresh control terminal NG opens T2 and T3, and PR opens T7 to write the data voltage Vdata and compensate the threshold voltage. Finally, the potential of N1 is Vdata+Vth, where Vth is the threshold voltage of T0. After that, NG is closed, HR controls to open T8 and T9, and resets the potentials of N2 and N4. Finally, EM is turned on, and O1 emits light.

[0184] When performing row hold and parallel refresh, the voltage of the second refresh control terminal CG switches to a high voltage during the blank period and maintains it for the entire frame time. In the effective display area, the pixel circuits of each row are scanned row by row. In the next frame time, NG provides a low voltage signal, T2 and T3 are turned off, the pixel circuit does not update the data voltage, and the display brightness of the previous frame is maintained;

[0185] When performing row refresh and column hold, the voltage of the second refresh control terminal CG switches to a low voltage during the blank period and maintains it for the entire frame time. T1 is turned off, and the pixel circuit does not update the data voltage, maintaining the display brightness of the previous frame.

[0186] When row hold and column hold are performed, the voltage of the second refresh control terminal CG is switched to a low voltage during the blank period and maintained for the entire frame time. T1 is turned off, the pixel circuit does not update the data voltage, and maintains the display brightness of the previous frame.

[0187] FIG6 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 when performing row refresh and column refresh;

[0188] FIG7 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 when performing row refresh and column hold;

[0189] FIG8 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 during row hold and column refresh;

[0190] FIG. 9 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 5 when performing row hold and column hold.

[0191] In FIG6 to FIG9 , the blank period is labeled TB, and the one-frame period is labeled TZ after the blank period TB.

[0192] As shown in FIG6 , in at least one embodiment of the pixel circuit shown in FIG5 , when performing row and column refresh, TZ includes a first reset period S1 , a data writing period S2 , a second reset period S3 and a light emitting period S4 that are sequentially set;

[0193] During the blank period TB, the potential of CG jumps from low voltage to high voltage; during TZ, the potential of CG remains high voltage; when the potential of CG is high voltage, T1 is turned on;

[0194] In the first reset period S1, PR provides a low voltage signal, NG provides a high voltage signal, PG provides a high voltage signal, HR provides a high voltage signal, EM provides a high voltage signal, T1, T2 and T3 are turned on, T7 is turned on, and I1 provides a first initial voltage Vi1 to N3 and N1, so that T0 can be turned on when the data writing period S2 begins;

[0195] In the data writing period S2, CG and NG provide high voltage signals, PG provides a low voltage signal, HR provides a high voltage signal, EM provides a high voltage signal, T1, T2 and T3 are turned on, T5 is turned on, and the data voltage Vdata provided by DT is written into N2;

[0196] At the beginning of the data writing period S2, T0 is turned on and Vdata charges Cst until the potential of N1 becomes Vdata+Vth, and T0 is turned off;

[0197] In the second reset period S3, CG provides a high voltage signal, NG provides a low voltage signal, PR provides a high voltage signal, PG provides a high voltage signal, HR provides a low voltage signal, EM provides a high voltage signal, T8 and T9 are turned on, I2 provides Vi2 to N4, and I3 provides Vi3 to N2 to clear the residual charge on the anode of O1 and reset the potential of N2 to improve the hysteresis phenomenon;

[0198] In the light-emitting period S4, CG provides a high voltage signal, NG provides a low voltage signal, PR provides a high voltage signal, PG provides a high voltage signal, HR provides a high voltage signal, EM provides a low voltage signal, T4 and T6 are turned on, and T0 drives O1 to emit light.

[0199] The difference between at least one embodiment of the pixel circuit shown in FIG. 10 and at least one embodiment of the pixel circuit shown in FIG. 5 is that T1 , T2 and T3 are p-type transistors.

[0200] At least one embodiment of the pixel circuit shown in FIG. 10 is applicable to a pure PMOS (P-type metal-oxide-semiconductor) low-frequency display.

[0201] The difference between at least one embodiment of the pixel circuit shown in FIG. 11 and at least one embodiment of the pixel circuit shown in FIG. 5 is that T1 is a p-type transistor.

[0202] The difference between at least one embodiment of the pixel circuit shown in FIG12 and at least one embodiment of the pixel circuit shown in FIG5 is that: T1 and T3 are p-type transistors;

[0203] The gate of T2 is electrically connected to the first first refresh control terminal NG1 , and the gate of T3 is electrically connected to the second first refresh control terminal NG2 .

[0204] The difference between at least one embodiment of the pixel circuit shown in FIG. 13 and at least one embodiment of the pixel circuit shown in FIG. 5 is that T9 is not included.

[0205] The difference between at least one embodiment of the pixel circuit shown in FIG. 14 and at least one embodiment of the pixel circuit shown in FIG. 13 is that T1 , T2 , and T3 are all p-type transistors.

[0206] At least one embodiment of the pixel circuit shown in FIG. 14 is suitable for pure PMOS low-frequency display.

[0207] The difference between at least one embodiment of the pixel circuit shown in FIG. 15 and at least one embodiment of the pixel circuit shown in FIG. 5 is that the drain of T9 is electrically connected to the drain of the driving transistor T0 .

[0208] The difference between at least one embodiment of the pixel circuit shown in FIG. 16 and at least one embodiment of the pixel circuit shown in FIG. 15 is that T1 , T2 , and T3 are all p-type transistors.

[0209] At least one embodiment of the pixel circuit shown in FIG. 16 is suitable for pure PMOS low-frequency display.

[0210] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0211] The driving circuit drives the light emitting element under the control of the potential of the first node;

[0212] The second control circuit controls the connection or disconnection between the first node and the first end of the first control circuit under the control of the first refresh control signal;

[0213] Under the control of the second first refresh control signal of the third control circuit, the first end of the control driving circuit is controlled to be connected or disconnected with the second end of the first control circuit;

[0214] The first control circuit controls the connection or disconnection between the first end of the first control circuit and the second end of the first control circuit under the control of the second refresh control signal.

[0215] In at least one embodiment of the present disclosure, the driving method includes:

[0216] In a row refresh frame, the second control circuit controls the first node to be connected to the first end of the first control circuit under the control of a first first refresh control signal; and the third control circuit controls the first end of the driving circuit to be connected to the second end of the first control circuit under the control of a second first refresh control signal.

[0217] In the row hold frame, the second control circuit controls the first node and the first end of the first control circuit to be disconnected under the control of the first first refresh control signal; the third control circuit controls the first end of the driving circuit and the second end of the first control circuit to be disconnected under the control of the second first refresh control signal;

[0218] In a column refresh frame, the second control circuit controls the first node to be connected to the first end of the first control circuit under the control of the first refresh control signal;

[0219] In the column holding frame, the second control circuit controls the first node to be disconnected from the first terminal of the first control circuit under the control of the first refresh control signal.

[0220] In at least one embodiment of the present disclosure, row refresh is performed in a row refresh frame; row hold is performed in a row hold frame; column refresh is performed in a column refresh frame; and column hold is performed in a column hold frame.

[0221] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0222] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a driving circuit, a first control circuit, a second control circuit, and a third control circuit; A control terminal of the driving circuit is electrically connected to a first node, and a first end of the driving circuit is electrically connected to the light-emitting element, and is configured to drive the light-emitting element under the control of the potential of the first node; The second control circuit is respectively electrically connected to a first first refresh control terminal, the first node, and a first end of the first control circuit, and is configured to control the connection or disconnection between the first node and the first end of the first control circuit under the control of a first first refresh control signal provided by the first first refresh control terminal; The third control circuit is respectively electrically connected to a second first refresh control terminal, a first end of the driving circuit, and a second end of the first control circuit, and is configured to control the connection or disconnection between the first end of the driving circuit and the second end of the first control circuit under the control of a second first refresh control signal provided by the second first refresh control terminal; A control terminal of the first control circuit is electrically connected to a second refresh control terminal, and the first control circuit is configured to control the connection or disconnection between a first end of the first control circuit and a second end of the first control circuit under the control of a second refresh control signal provided by the second refresh control terminal.

2. The pixel circuit according to claim 1, wherein It further comprises a first light-emitting control circuit; The first light-emitting control circuit is respectively electrically connected to a first light-emitting control terminal, a power supply voltage terminal, and a second end of the driving circuit, and is configured to control the connection or disconnection between the power supply voltage terminal and the second end of the driving circuit under the control of a first light-emitting control signal provided by the first light-emitting control terminal.

3. The pixel circuit according to claim 2, wherein, It further comprises a data writing circuit; The data writing circuit is respectively electrically connected to a writing control terminal, a data line, and a second end of the driving circuit, and is configured to write a data voltage provided by the data line into the second end of the driving circuit under the control of a writing control signal provided by the writing control terminal.

4. The pixel circuit according to claim 1, wherein It further comprises an energy storage circuit and a second light-emitting control circuit; The energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node; The second light-emitting control circuit is respectively electrically connected to a second light-emitting control terminal, a first end of the driving circuit and a first pole of the light-emitting element, and is configured to control the connection or disconnection between the first end of the driving circuit and the first pole of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control terminal; A second pole of the light-emitting element is electrically connected to a first voltage terminal.

5. The pixel circuit according to claim 4, wherein, It further comprises a first reset circuit; The first reset circuit is respectively electrically connected to a first reset control terminal, a first initial voltage terminal, and a first end of the driving circuit, and is configured to write a first initial voltage provided by the first initial voltage terminal into the first end of the driving circuit under the control of a first reset control signal provided by the first reset control terminal.

6. The pixel circuit according to claim 4, wherein, It further comprises a second reset circuit; The second reset circuit is respectively electrically connected to the second reset control terminal, the second initial voltage terminal, and the first pole of the light-emitting element, and is configured to write the second initial voltage provided by the second initial voltage terminal into the first pole of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

7. The pixel circuit according to claim 2, wherein, It further includes a third reset circuit; The third reset circuit is respectively electrically connected to a third reset control terminal, a third initial voltage terminal, and a second terminal of the driving circuit, and is configured to write the third initial voltage provided by the third initial voltage terminal into the second terminal of the driving circuit under the control of a third reset control signal provided by the third reset control terminal.

8. The pixel circuit according to claim 4, wherein, It further includes a third reset circuit; The third reset circuit is respectively electrically connected to a third reset control terminal, a third initial voltage terminal, and a first terminal of the driving circuit, and is configured to write the third initial voltage provided by the third initial voltage terminal into the first terminal of the driving circuit under the control of a third reset control signal provided by the third reset control terminal.

9. The pixel circuit according to claim 1, wherein, The driving circuit includes a driving transistor, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; The gate of the driving transistor is electrically connected to the first node, and the first pole of the driving transistor is electrically connected to the light-emitting element; The gate of the second transistor is electrically connected to the first first refresh control terminal, the first pole of the second transistor is electrically connected to the first node, and the second pole of the second transistor is electrically connected to the first pole of the first transistor; The gate of the third transistor is electrically connected to the second first refresh control terminal, the first pole of the third transistor is electrically connected to the second pole of the first transistor, and the second pole of the third transistor is electrically connected to the first pole of the driving transistor; The gate of the first transistor is electrically connected to the second refresh control terminal.

10. The pixel circuit according to claim 9, wherein, The first transistor, the second transistor, and the third transistor are oxide transistors.

11. The pixel circuit according to claim 2, wherein, The first light-emitting control circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the first light-emitting control terminal, the first pole of the fourth transistor is electrically connected to the power supply voltage terminal, and the second pole of the fourth transistor is electrically connected to the second terminal of the driving circuit.

11. The pixel circuit according to claim 3, wherein the data writing circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the writing control terminal, the first pole of the fifth transistor is electrically connected to the data line, and the second pole of the fifth transistor is electrically connected to the second terminal of the driving circuit.

12. The pixel circuit according to claim 4, wherein, The second light-emitting control circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first pole of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second pole of the sixth transistor is electrically connected to the first pole of the light-emitting element.

13. The pixel circuit according to claim 5, wherein, The first reset circuit includes a seventh transistor; The gate of the seventh transistor is electrically connected to the first reset control terminal, a first pole of the seventh transistor is electrically connected to the first initial voltage terminal, and a second pole of the seventh transistor is electrically connected to a first end of the driving circuit.

14. The pixel circuit according to claim 6, wherein, The second reset circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the second reset control terminal, a first pole of the eighth transistor is electrically connected to the second initial voltage terminal, and a second pole of the eighth transistor is electrically connected to a first pole of the light-emitting element.

15. The pixel circuit according to claim 7, wherein, The third reset circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the third reset control terminal, a first pole of the ninth transistor is electrically connected to the third initial voltage terminal, and a second pole of the ninth transistor is electrically connected to a second end of the driving circuit.

16. The pixel circuit according to claim 8, wherein, The third reset circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the third reset control terminal, a first pole of the ninth transistor is electrically connected to the third initial voltage terminal, and a second pole of the ninth transistor is electrically connected to a first end of the driving circuit.

17. A driving method, applied to the pixel circuit according to any one of claims 1 to 16, the driving method comprising: The driving circuit drives the light-emitting element under the control of the potential of the first node; The second control circuit controls the connection or disconnection between the first node and a first end of the first control circuit under the control of the first first refresh control signal; The third control circuit controls the connection or disconnection between the first end of the driving circuit and a second end of the first control circuit under the control of the second first refresh control signal; The first control circuit controls the connection or disconnection between the first end and the second end of the first control circuit under the control of the second refresh control signal.

18. The driving method according to claim 17, wherein, The driving method includes: In a row refresh frame, the second control circuit controls the connection between the first node and the first end of the first control circuit under the control of the first first refresh control signal; the third control circuit controls the connection between the first end of the driving circuit and the second end of the first control circuit under the control of the second first refresh control signal; In a row hold frame, the second control circuit controls the disconnection between the first node and the first end of the first control circuit under the control of the first first refresh control signal; the third control circuit controls the disconnection between the first end of the driving circuit and the second end of the first control circuit under the control of the second first refresh control signal; In a column refresh frame, the second control circuit controls the connection between the first node and the first end of the first control circuit under the control of the first first refresh control signal; In a column hold frame, the second control circuit controls the disconnection between the first node and the first end of the first control circuit under the control of the first first refresh control signal.

19. A display device, comprising the pixel circuit according to any one of claims 1 to 16.

Images