Semiconductor device, circuit board and method for manufacturing circuit board

Abstract

A semiconductor device according to an embodiment includes a first surface facing a first side and a second surface facing a second side opposite to the first side. A semiconductor device according to an embodiment includes: a semiconductor device body; a lead frame electrically connected to the semiconductor device body; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; and a resin portion covering and holding at least a portion of the semiconductor device main body and at least a portion of the lead frame. At least a portion of the conductive bump portion is exposed outside the resin portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, a circuit substrate, and a method for manufacturing the circuit substrate.

[0002] This application claims priority based on Japanese Patent Application No. 2023-124558 filed in Japan on July 31, 2023, the contents of which are incorporated herein by reference. Background Art

[0003] Thinner semiconductor devices are desirable. However, thinning semiconductor devices reduces their operability. Consequently, the productivity of products incorporating semiconductor devices may decrease due to factors such as reduced yields of products incorporating semiconductor devices and restrictions on mounting methods.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-25143 Summary of the Invention

[0007] Technical problem to be solved by the invention

[0008] The technical problem to be solved by the present invention is to provide a semiconductor device capable of improving operability, a circuit board including such a semiconductor device, and a method for manufacturing such a circuit board.

[0009] Means for solving technical problems

[0010] A semiconductor device according to an embodiment includes a first surface facing a first side and a second surface facing a second side opposite to the first side. The semiconductor device according to an embodiment includes: a semiconductor device body; a lead frame electrically connected to the semiconductor device body; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; and a resin portion covering and retaining at least a portion of the semiconductor device body and at least a portion of the lead frame. At least a portion of the conductive bump portion is exposed outside the resin portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a cross-sectional view showing a portion of the circuit board according to the first embodiment.

[0012] Figure 2 It is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0013] Figure 3 It is a plan view showing the semiconductor device according to the first embodiment.

[0014] Figure 4 1 is a cross-sectional view showing a stud bump for forming the conductive bump portion according to the first embodiment.

[0015] Figure 5 This is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 6A It is a cross-sectional view showing the first housing portion forming step in the first embodiment.

[0017] Figure 6B It is a cross-sectional view showing the chip fixing step of the first embodiment.

[0018] Figure 6C It is a cross-sectional view showing the stud bump forming step of the first embodiment.

[0019] Figure 6D It is a cross-sectional view showing a state after the stud bump forming step according to the first embodiment.

[0020] Figure 6E This is a cross-sectional view showing a state after the molding step according to the first embodiment.

[0021] Figure 6F This is a cross-sectional view showing a state after the grinding step according to the first embodiment.

[0022] Figure 7 This is a plan view showing a base material of the lead frame according to the first embodiment.

[0023] Figure 8 This is a flowchart showing the method for manufacturing the circuit board according to the first embodiment.

[0024] Figure 9A It is a cross-sectional view showing the semiconductor device housing step according to the first embodiment.

[0025] Figure 9B It is a cross-sectional view showing a state after the sealing step according to the first embodiment.

[0026] Figure 9C It is a cross-sectional view showing the laser processing step of the first embodiment.

[0027] Figure 9D This is a cross-sectional view showing a state after the laser processing step according to the first embodiment.

[0028] Figure 10 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0029] Figure 11 It is a plan view showing a semiconductor device according to a second embodiment.

[0030] Figure 12 It is a cross-sectional view showing a semiconductor device according to a third embodiment.

[0031] Figure 13 It is a plan view showing a semiconductor device according to a third embodiment.

[0032] Figure 14 It is a cross-sectional view showing a semiconductor device according to a fourth embodiment.

[0033] Figure 15 This is a flowchart showing a method for manufacturing a semiconductor device according to a fourth embodiment.

[0034] Figure 16A It is a cross-sectional view showing a chip fixing step according to the fourth embodiment.

[0035] Figure 16B 4 is a cross-sectional view showing a stud bump forming step and a vertical wire forming step according to the fourth embodiment.

[0036] Figure 16C It is a cross-sectional view showing a state after the stud bump forming step and the vertical wire forming step according to the fourth embodiment.

[0037] Figure 16D It is a cross-sectional view showing a state after the molding step according to the fourth embodiment.

[0038] Figure 16E It is a cross-sectional view showing a state after the grinding step according to the fourth embodiment.

[0039] Figure 17 It is a cross-sectional view showing a portion of a circuit board according to a fifth embodiment.

[0040] Figure 18 It is a cross-sectional view showing a portion of a circuit board according to a sixth embodiment. DETAILED DESCRIPTION

[0041] Hereinafter, a semiconductor device, a circuit board, and a method for manufacturing the circuit board according to embodiments will be described with reference to the drawings.

[0042] In the accompanying drawings, the thickness direction of the circuit substrate of the embodiment is appropriately represented by the Z-axis direction, a direction perpendicular to the thickness direction of the circuit substrate is represented by the X-axis direction, and a direction perpendicular to both the Z-axis direction and the X-axis direction is represented by the Y-axis direction. In the following description, the X-axis direction is referred to as the "first direction X", the Y-axis direction is referred to as the "second direction Y", and the Z-axis direction is referred to as the "thickness direction Z". In addition, the side to which the arrow of the Z-axis in the thickness direction Z points (the +Z side) is referred to as the "upper side", and the side opposite to the side to which the arrow of the Z-axis in the thickness direction Z points (the -Z side) is referred to as the "lower side". In addition, in the following embodiments, the upper side is equivalent to the "first side", and the lower side is equivalent to the "second side" on the side opposite to the first side.

[0043] (First embodiment)

[0044] Figure 1 1 is a cross-sectional view showing a portion of the circuit board 100 according to the first embodiment. Figure 1 As shown, in the first embodiment, the circuit substrate 100 is a circuit substrate having a built-in semiconductor device 20. The circuit substrate 100 includes a substrate body 10, the semiconductor device 20, and a wiring portion 40. The substrate body 10 is in the form of a plate with its surface facing the thickness direction Z. The semiconductor device 20 is mounted on the substrate body 10. The substrate body 10 includes a plate-shaped base portion 11, a resin layer 12 laminated on the upper surface of the base portion 11, a resin layer 13 laminated on the lower surface of the base portion 11, and a sealing resin portion 30.

[0045] The base member 11 includes a second housing portion 14 for housing the semiconductor device 20. In the first embodiment, the second housing portion 14 is a hole that penetrates the base member 11 in the thickness direction Z. The upper opening of the second housing portion 14 is blocked by the resin layer 12. The lower opening of the second housing portion 14 is blocked by the resin layer 13. The interior of the second housing portion 14, except for the portion where the semiconductor device 20 is located, is filled with a sealing resin portion 30.

[0046] Figure 2 1 is a cross-sectional view showing a semiconductor device 20 according to the first embodiment. Figure 3 1 is a top view of a semiconductor device 20 according to the first embodiment. In the first embodiment, the semiconductor device 20 is, for example, a vertical field effect transistor (FET). The semiconductor device 20 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Figure 2 and Figure 3As shown, the semiconductor device 20 is in the shape of a plate that is relatively thin in the thickness direction Z. Figure 3 As shown, the semiconductor device 20 is substantially square in shape with sides along the first direction X and the second direction Y when viewed in the thickness direction Z. Figure 2 As shown, the semiconductor device 20 includes a semiconductor device body 50 , a lead frame 60 , a conductive bump portion 80 , and a resin portion 70 .

[0047] In the first embodiment, the semiconductor device body 50 is a semiconductor chip on which electrodes of a field effect transistor are formed. The semiconductor device body 50 is housed in a first housing portion 63 (described later) of a lead frame 60. The semiconductor device body 50 includes a substrate 51, a first metal film 52a, a second metal film 52b, and a third metal film 52c. Figure 2 and Figure 3 As shown, the substrate portion 51 is plate-shaped with its surface facing the thickness direction Z. The substrate portion 51 is rectangular when viewed along the thickness direction Z. The substrate portion 51 is made of a semiconductor material. Examples of the material making up the substrate portion 51 include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and the like.

[0048] The first metal film 52a and the second metal film 52b are formed on the upper surface of the substrate portion 51. The third metal film 52c is formed on the lower surface of the substrate portion 51. Figure 3 As shown, the first metal film 52a is formed at one corner of the upper surface of the substrate portion 51. The first metal film 52a is roughly square when viewed in the thickness direction Z. The second metal film 52b is formed across the remaining three corners of the upper surface of the substrate portion 51. The second metal film 52b is roughly L-shaped when viewed in the thickness direction Z. The second metal film 52b has a portion adjacent to the first metal film 52a in the first direction X and a portion adjacent to the first metal film 52a in the second direction Y. Figure 2 As shown, the third metal film 52 c is formed on the entire lower surface of the substrate portion 51 .

[0049] The first metal film 52a, the second metal film 52b, and the third metal film 52c are formed, for example, by sputtering. The material constituting the first metal film 52a and the material constituting the second metal film 52b are, for example, the same. The material constituting the first metal film 52a and the material constituting the second metal film 52b are not particularly limited as long as they are conductive, and may be, for example, aluminum. The material constituting the third metal film 52c is not particularly limited as long as it is conductive, and may be, for example, a material containing one or more of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and the like. The third metal film 52c is, for example, a Ti / Ni / Au stacked film or a Ti / Ni / Ag stacked film.

[0050] In the first embodiment, the first metal film 52a serves as a gate electrode. The second metal film 52b serves as a source electrode. The third metal film 52c serves as a drain electrode. Alternatively, each metal film may serve as any electrode. Furthermore, the third metal film 52c may not be an electrode. In this case, three metal films may be formed on the upper surface of the substrate 51, with these three metal films corresponding to the gate electrode, source electrode, and drain electrode, respectively.

[0051] The semiconductor device body 50 is electrically connected to the lead frame 60. The lead frame 60 is a conductive component made of metal. The material constituting the lead frame 60 is not particularly limited as long as it is conductive, and an example thereof is copper (Cu). Although not shown in the figure, a silver (Ag) coating is formed on the surface of the lead frame 60 to prevent oxidation. However, this coating does not need to be formed. The lead frame 60 includes a support portion 61 that supports the semiconductor device body 50 from the bottom, a frame portion 62 that protrudes upward from the support portion 61, and a protrusion 64 that protrudes from the support portion 61 in a direction perpendicular to the thickness direction Z.

[0052] The semiconductor device body 50 is bonded to the upper surface of the support portion 61 via a bonding portion 53. The bonding portion 53 is conductive and can be made of, for example, solder or metal paste. In the first embodiment, the bonding portion 53 electrically connects the upper surface of the support portion 61 to the third metal film 52c.

[0053] like Figure 3 As shown in FIG. 1 , in the first embodiment, the frame portion 62 is in the shape of a rectangular frame. The frame portion 62 surrounds the semiconductor device body 50. Figure 2 As shown, the upper surface of the frame portion 62 is arranged at the same position as the upper surface of the semiconductor device body 50 in the thickness direction Z. The upper surface of the frame portion 62 may be located above or below the upper surface of the semiconductor device body 50.

[0054] The support portion 61 and the frame portion 62 form a first receiving portion 63 that opens upward. In the first embodiment, the upper surface of the frame portion 62 forms the opening periphery of the first receiving portion 63 on the upper surface of the lead frame 60. A protrusion 64 is connected to the support portion 61. Multiple protrusions 64 are provided. These multiple protrusions 64 include a protrusion 64 that protrudes from the support portion 61 in the first direction X and a protrusion 64 that protrudes from the support portion 61 in the second direction Y.

[0055] The conductive bump portion 80 is a bump having conductivity. In addition, in this specification, the so-called "conductive bump portion" is, for example, a portion having a conductive material formed into a block having a certain degree of thickness. "A certain degree of thickness" refers to, for example, a thickness that is greater than the thickness of a film usually formed by sputtering and the thickness of a film usually formed by plating. In the first embodiment, the dimension of the conductive bump portion 80 in the thickness direction Z is greater than 4 μm. As an example, the dimension of the conductive bump portion 80 in the thickness direction Z is about 10 μm or more and 50 μm or less. The dimension of the conductive bump portion 80 in the thickness direction Z is not particularly limited.

[0056] In the first embodiment, the conductive bump portion 80 is formed of a stud bump. The stud bump is formed by cutting the bonding wire after ball bonding. Figure 4 This is a cross-sectional view of a stud bump 180 used to form the conductive bump portion 80. Stud bump 180 has a generally conical shape, with the outer diameter decreasing as it moves upward. Stud bump 180 includes a base portion 181 for bonding to an object to be connected to stud bump 180, and a reduced diameter portion 182 protruding from base portion 181. The outer diameter of reduced diameter portion 182 decreases as it moves away from base portion 181.

[0057] Figure 4 The outer diameter D1 shown is the outer diameter of the bonding wire. For example, the outer diameter of a portion of the upper portion of the reduced diameter portion 182 is equal to the outer diameter D1 of the bonding wire. The outer diameter D1 of the bonding wire is not particularly limited, and is, for example, about 20 μm or more and 100 μm or less. The outer diameter D2 of the base portion 181 is, for example, about 2 times or more and 3 times or less of the outer diameter D1 of the bonding wire. The height H2 of the base portion 181 is, for example, about 1 / 5 of the outer diameter D2 of the base portion 181. The height H1 of the columnar bump 180 can be arbitrarily increased by overlapping ball welding. The conductive bump portion 80 of the first embodiment is formed by cutting a portion of the reduced diameter portion 182 of the columnar bump 180. Specifically, for example, by cutting along Figure 4 The imaginary line CL shown cuts a portion of the reduced diameter portion 182 of the stud bump 180 to form the conductive bump portion 80. Figure 4 In the example, the imaginary line CL is located at a portion of the reduced diameter portion 182 having an outer diameter larger than the outer diameter D1 of the bonding wire. Therefore, the outer diameter D3 of the upper end of the conductive bump portion 80 is smaller than the outer diameter D2 of the base portion 181 and larger than the outer diameter D1 of the bonding wire.

[0058] Since a portion of the upper portion of the columnar bump 180 is cut to form the conductive bump portion 80, the conductive bump portion 80 is roughly truncated cone-shaped with an outer diameter that decreases as it moves upward. The upper end face of the conductive bump portion 80 is a flat surface that is orthogonal to the thickness direction Z. The material constituting the conductive bump portion 80 is not particularly limited as long as it has conductivity, and examples include gold (Au), silver (Ag), copper (Cu), etc. From the perspective of ease of manufacturing the columnar bump 180, for example, gold (Au) is preferably selected as the material constituting the conductive bump portion 80. From the perspective of reducing manufacturing costs, for example, copper (Cu) is preferably selected as the material constituting the conductive bump portion 80.

[0059] like Figure 2 As shown, the conductive bump portion 80 includes a first conductive bump portion 81 and a second conductive bump portion 82. The first conductive bump portion 81 is electrically connected to the semiconductor device body 50. More specifically, the first conductive bump portion 81 is connected to the upper surface of the semiconductor device body 50. A plurality of first conductive bump portions 81 are provided. The plurality of first conductive bump portions 81 include a first conductive bump portion 81 electrically connected to the first metal film 52a and a first conductive bump portion 81 electrically connected to the second metal film 52b. Figure 3 As shown, for example, only one first conductive bump portion 81 is provided that is electrically connected to the first metal film 52a. Alternatively, two or more first conductive bump portions 81 may be provided that are electrically connected to the first metal film 52a. A plurality of first conductive bump portions 81 are provided that are electrically connected to the second metal film 52b. The plurality of first conductive bump portions 81 that are electrically connected to the second metal film 52b are arranged in the first direction X and the second direction Y so as to completely cover the substantially L-shaped second metal film 52b.

[0060] like Figure 2 As shown, the second conductive bump portion 82 is electrically connected to the lead frame 60. In the first embodiment, the second conductive bump portion 82 is electrically connected to the upper surface of the frame portion 62. In other words, the second conductive bump portion 82 is connected to the opening peripheral portion of the first receiving portion 63 in the upper surface of the lead frame 60. The second conductive bump portion 82 is electrically connected to the third metal film 52c via the lead frame 60 and the bonding portion 53. A plurality of second conductive bump portions 82 are provided. As shown in FIG. Figure 3 As shown in FIG. 1 , in the first embodiment, the plurality of second conductive bump portions 82 are arranged in a rectangular frame shape along the frame portion 62. When viewed from above, the plurality of second conductive bump portions 82 are arranged to surround the first conductive bump portion 81.

[0061] In the first embodiment, the first conductive bump portion 81 and the second conductive bump portion 82 are made of the same material. In the first embodiment, the first conductive bump portion 81 and the second conductive bump portion 82 are made of a material different from that of the lead frame 60 .

[0062] like Figure 2 As shown, the resin portion 70 covers and retains at least a portion of the semiconductor device body 50 and at least a portion of the lead frame 60. In the first embodiment, the resin portion 70 covers the entire semiconductor device body 50, the entire lead frame 60 except for the front end surface of the protrusion 64, and the entire conductive bump portion 80 except for the upper end surface. In the first embodiment, the semiconductor device body 50, the lead frame 60, and the conductive bump portion 80 are embedded in and retained by the resin portion 70. In the first embodiment, the resin portion 70 is formed by resin molding using a mold.

[0063] The upper surface of the resin portion 70 constitutes a portion of the first surface 20a facing upward in the semiconductor device 20. The resin portion 70 covers the entire lower surface of the lead frame 60. The lower surface of the resin portion 70 constitutes the second surface 20b facing downward in the semiconductor device 20. At least a portion of the conductive bump portion 80 is exposed to the outside of the resin portion 70. In the first embodiment, the upper end surfaces of the plurality of conductive bump portions 80 are exposed to the outside of the resin portion 70. More specifically, the upper end surfaces of the plurality of conductive bump portions 80 are exposed to the first surface 20a of the semiconductor device 20. In the first embodiment, the first surface 20a is formed by the upper surface of the resin portion 70 and the upper end surfaces of the plurality of conductive bump portions 80. The material constituting the resin portion 70 is not particularly limited as long as it is an insulating resin. The material constituting the resin portion 70 may be a molding resin or an interlayer insulating material.

[0064] In the first embodiment, the upper end surface of the first conductive bump portion 81 and the upper end surface of the second conductive bump portion 82 are exposed on the first surface 20a. That is, the end surface of the first conductive bump portion 81 and the end surface of the second conductive bump portion 82 are exposed on the same surface of the semiconductor device 20. Figure 3As shown, in the first embodiment, the upper end surfaces of the first conductive bump portion 81 and the upper end surfaces of the second conductive bump portion 82 are circular. The first conductive bump portion 81, which is connected to the first metal film 52a, is exposed outside the resin portion 70 at its upper end surface, thereby functioning as a gate electrode of the semiconductor device 20. The first conductive bump portion 81, which is connected to the second metal film 52b, is exposed outside the resin portion 70 at its upper end surface, thereby functioning as a source electrode of the semiconductor device 20. The second conductive bump portion 82, which is electrically connected to the third metal film 52c via the lead frame 60 and the bonding portion 53, is exposed outside the resin portion 70 at its upper end surface, thereby functioning as a drain electrode of the semiconductor device 20.

[0065] like Figure 1 As shown, semiconductor device 20 is housed within second housing portion 14 of substrate main body 10 and is embedded in substrate main body 10. Second surface 20b of semiconductor device 20 contacts the upper surface of resin layer 13. First surface 20a of semiconductor device 20 is positioned downwardly away from the lower surface of resin layer 12. A portion of sealing resin portion 30 is interposed between first surface 20a and resin layer 12 in thickness direction Z.

[0066] The wiring portion 40 forms at least a portion of the circuit pattern formed on the circuit substrate 100. The wiring portion 40 includes a first wiring pattern 41 formed on the upper surface of the substrate body 10 and a second wiring pattern 42 formed on the lower surface of the substrate body 10. The wiring portion 40 is electrically connected to the portion of the conductive bump portion 80 exposed to the outside of the resin portion 70 via a hole 15 formed in the substrate body 10. The hole 15 extends from the outer surface of the substrate body 10 to the portion of the conductive bump portion 80 exposed to the outside of the resin portion 70. In the first embodiment, the hole 15 is a hole recessed downward from the upper surface of the substrate body 10. The hole 15 penetrates the resin layer 12 and the portion of the sealing resin portion 30 located above the semiconductor device 20 in the thickness direction Z. The inner diameter of the hole 15 decreases downward, for example. The hole 15 is formed by laser drilling. A plurality of holes 15 are formed. The plurality of holes 15 are respectively located above the plurality of conductive bumps 80. At the lower end of each hole 15, the upper end surface of each conductive bump 80 is exposed.

[0067] The wiring portion 40 includes a connection wiring portion 43 formed inside the hole portion 15. The connection wiring portion 43 is provided in each of the plurality of hole portions 15. The connection wiring portion 43 is electrically connected to the conductive bump portion 80. More specifically, the lower end portion of each connection wiring portion 43 is electrically connected to the upper end surface of each conductive bump portion 80 exposed in each hole portion 15. The upper end portion of each connection wiring portion 43 is connected to the first wiring pattern 41. In the first embodiment, the connection wiring portion 43 fills the hole portion 15. Alternatively, the connection wiring portion 43 may be a conductive film formed on the inner circumferential surface of the hole portion 15.

[0068] The wiring portion 40 includes a connecting wiring portion 44 that connects the first wiring pattern 41 and the second wiring pattern 42. The connecting wiring portion 44 is formed in a through-hole 16 that penetrates the substrate body 10 in the thickness direction Z. In the first embodiment, the connecting wiring portion 44 fills the through-hole 16. Alternatively, the connecting wiring portion 44 may be a conductive film formed on the inner circumferential surface of the through-hole 16.

[0069] Figure 5 FIG. 1 is a flowchart showing a method for manufacturing the semiconductor device 20 according to the first embodiment. Figure 5 As shown, the method for manufacturing the semiconductor device 20 includes a first receiving portion forming step S11 , a chip fixing step S12 , a stud bump forming step S13 , a molding step S14 , a grinding step S15 , and a singulation step S16 . Figure 6A It is a cross-sectional view showing the first housing portion forming step S11. Figure 6B It is a cross-sectional view showing the chip fixing step S12. Figure 6C 3 is a cross-sectional view showing the stud bump forming step S13 . Figure 6D It is a cross-sectional view showing a state after the stud bump forming step S13 is performed. Figure 6E It is a cross-sectional view showing a state after the molding step S14 is performed. Figure 6F It is a cross-sectional view showing a state after the grinding step S15 is performed.

[0070] like Figure 6A As shown, the first housing portion forming step S11 is a step of forming the first housing portion 63 on the base material 160 for forming the lead frame 60 . Figure 7 1 is a top view of a base material 160. The base material 160 has a plurality of frame main bodies 161. The plurality of frame main bodies 161 are arranged in a matrix. Adjacent frame main bodies 161 are connected to each other by two connecting parts 162. Figure 6AAs shown, the dimension of the thickness direction Z of the connecting portion 162 is smaller than the dimension of the thickness direction Z of the frame main body 161. The connecting portion 162 is connected to the lower end of the frame main body 161. In the first receiving portion forming step S11 of the first embodiment, a first receiving portion 63 recessed downward is formed on each frame main body 161 by etching. Figure 6B As shown, by forming the first receiving portion 63 , the support portion 61 and the frame portion 62 are formed in each frame body portion 161 .

[0071] The chip fixing step S12 is a step of fixing the semiconductor device body 50 in the first receiving portion 63. Figure 6B and Figure 6C As shown, in the chip fixing step S12, the semiconductor device body 50 is received in the first receiving portion 63 from above and fixed to the support portion 61 via the bonding portion 53. In the chip fixing step S12, one semiconductor device body 50 is fixed in each first receiving portion 63 formed in each frame body portion 161 of the base material 160.

[0072] like Figure 6C and Figure 6D As shown, stud bump forming step S13 is a step of forming a plurality of stud bumps 180 on the upper surface of the semiconductor device body 50 and the upper surface of the frame portion 62. As described above, stud bumps 180 are formed by cutting the bonding wire after ball bonding. Stud bumps 180 formed on the upper surface of the semiconductor device body 50 form the first conductive bump portion 81. Stud bumps 180 formed on the upper surface of the frame portion 62 form the second conductive bump portion 82.

[0073] The molding step S14 is a step of insert molding the base material 160 in a state where the semiconductor device body 50 is fixed and the stud bumps 180 are formed as an insert component. Figure 6E As shown, the molding step S14 forms the resin portion 170 in which the base material 160 , the semiconductor device body 50 , and the stud bumps 180 are embedded.

[0074] The grinding step S15 is a step of grinding the resin portion 170 from the upper side to reduce the size of the resin portion 170 in the thickness direction Z. In the grinding step S15, the resin portion 170 is ground until the size of the resin portion 170 in the thickness direction Z becomes the size of the semiconductor device 20 in the thickness direction Z. Figure 6FAs shown, in the grinding step S15, the resin portion 170 is ground from the upper side, thereby exposing the stud bumps 180 on the upper surface of the resin portion 170. In the grinding step S15, the upper portion of the stud bumps 180 is also ground together with the resin portion 170. In the grinding step S15, the upper portion of the stud bumps 180 is ground and removed, and each stud bump 180 becomes a conductive bump portion 80.

[0075] The singulation step S16 is a step of cutting the resin portion 170 and the base material 160 into individual frame body portions 161. In the singulation step S16, each connection portion 162 is cut and the base material 160 is singulated. In this way, a plurality of semiconductor devices 20 are manufactured.

[0076] Figure 8 FIG. 1 is a flowchart showing a method for manufacturing the circuit substrate 100 according to the first embodiment. Figure 8 As shown, the method for manufacturing the circuit substrate 100 includes a support substrate fixing step S21 , a semiconductor device housing step S22 , a sealing step S23 , a support substrate removing step S24 , a resin layer forming step S25 , a laser processing step S26 , and a wiring portion forming step S27 . Figure 9A It is a cross-sectional view showing the semiconductor device housing step S22. Figure 9B It is a cross-sectional view showing a state after the sealing step S23 is performed. Figure 9C It is a cross-sectional view showing the laser processing step S26. Figure 9D It is a cross-sectional view showing a state after the laser processing step S26 is performed.

[0077] The support substrate fixing process S21 is a process of fixing the support substrate 90 to the base material portion 11 formed with the second receiving portion 14. The support substrate 90 is in the shape of a plate with the plate surface facing the thickness direction Z. The support substrate 90 is made of stainless steel, for example. In addition, the material constituting the support substrate 90 is not particularly limited. Although not shown in the figure, an adhesive layer is formed on the upper surface of the support substrate 90. In the support substrate fixing process S21, the support substrate 90 is fixed to the lower surface of the base material portion 11 by means of the adhesive layer. Thus, as Figure 9A As shown, the lower opening of the second housing portion 14 is blocked by the support substrate 90 .

[0078] The semiconductor device housing step S22 is a step of housing the semiconductor device 20 in the second housing portion 14. Figure 9A As shown, in the semiconductor device housing step S22, the semiconductor device 20 is inserted into the second housing portion 14 through the upper opening of the second housing portion 14. Figure 9BAs shown, the semiconductor device 20 inserted into the second housing portion 14 is placed on the upper surface of the support substrate 90 and fixed to the support substrate 90 via an adhesive layer formed on the support substrate 90 .

[0079] The sealing step S23 is a step of sealing the interior of the second housing portion 14 with resin. In the sealing step S23, resin is poured into the second housing portion 14, which houses the semiconductor device 20, to form a sealing resin portion 30. Formation of the sealing resin portion 30 embeds the semiconductor device 20 within the sealing resin portion 30 and secures the semiconductor device 20 to the base portion 11 via the sealing resin portion 30. The support substrate removal step S24 is a step of removing the support substrate 90 from the base portion 11. The method for removing the support substrate 90 in the support substrate removal step S24 is not particularly limited.

[0080] The resin layer forming step S25 is a step of forming a pair of resin layers 12 and 13. In the resin layer forming step S25, the formation of the pair of resin layers 12 and 13 is performed simultaneously. In addition, in the resin layer forming step S25, the pair of resin layers 12 and 13 can also be formed sequentially. Figure 9C As shown, the resin layer 12 is formed on the upper surface of the base member 11 , and the resin layer 13 is formed on the lower surface of the base member 11 .

[0081] The laser processing step S26 is a step of forming the hole portion 15 and the through hole 16 by irradiating the laser beam LB. Figure 9C As shown, in the laser processing step S26, the resin layer 12 is irradiated with laser LB from the upper side to the lower side. The laser LB that forms the hole portion 15 is irradiated toward the conductive bump portion 80. The laser LB irradiated from the upper side of the resin layer 12 toward the conductive bump portion 80 penetrates the resin layer 12 and the portion of the sealing resin portion 30 located on the upper side of the conductive bump portion 80 and irradiates the conductive bump portion 80. The laser LB is blocked by the conductive bump portion 80. In the first embodiment, the conductive bump portion 80 functions as an absorption layer for the laser LB. Thus, a hole portion 15 is formed that reaches the conductive bump portion 80 from the upper surface of the resin layer 12. The laser LB that forms the through hole 16 is irradiated to a position that does not overlap with the second receiving portion 14 in the thickness direction Z. The laser LB that forms the through hole 16 penetrates the resin layer 12, the base material portion 11 and the resin layer 13 in the thickness direction Z to form the through hole 16. Through the laser processing step S26, as Figure 9D As shown, a plurality of holes 15 and a plurality of through holes 16 are formed. In addition, the through holes 16 may be formed using a drill instead of the laser LB. In this case, the shape of the through holes 16 becomes a straight line shape with a substantially uniform inner diameter.

[0082] The wiring portion forming step S27 is a step of forming the wiring portion 40. In the wiring portion forming step S27, a metal layer is formed on the upper surface of the resin layer 12, the lower surface of the resin layer 13, the inside of the hole 15, and the inside of the through hole 16 by plating, thereby forming the wiring portion 40. Through the above steps, the wiring portion 40 is manufactured. Figure 1 The circuit board 100 of the first embodiment is shown.

[0083] According to the first embodiment, a semiconductor device 20 has a first surface 20a facing upward and a second surface 20b facing downward. The semiconductor device 20 includes: a semiconductor device body 50; a leadframe 60 electrically connected to the semiconductor device body 50; conductive bump portions 80 electrically connected to the semiconductor device body 50 or the leadframe 60; and a resin portion 70 covering and retaining at least a portion of the semiconductor device body 50 and at least a portion of the leadframe 60. At least a portion of the conductive bump portions 80 is exposed outside the resin portion 70. Therefore, even when the semiconductor device body 50 is covered by the resin portion 70, the semiconductor device body 50 can be electrically connected to other components via the conductive bump portions 80 exposed outside the resin portion 70. Consequently, the semiconductor device 20 can be packaged by covering the semiconductor device body 50 secured to the leadframe 60 with the resin portion 70. Since the semiconductor device 20 can be packaged, including not only the semiconductor device body 50 but also the lead frame 60 and the resin portion 70, the semiconductor device 20 can be easily handled even when the semiconductor device body 50 is thinned. Consequently, the handleability of the semiconductor device 20 can be improved. This can improve the yield rate of products incorporating the semiconductor device 20, and thus the productivity of products incorporating the semiconductor device 20 can be improved. In the first embodiment, the yield rate when manufacturing the circuit board 100 by mounting the semiconductor device 20 on the substrate body 10 can be improved, and thus the productivity of the circuit board 100 can be improved.

[0084] Furthermore, by electrically connecting the leadframe 60 to the electrodes of the semiconductor device body 50, the positions of the electrodes connected to the external terminals in the semiconductor device 20 can be freely designed. Specifically, for example, in the first embodiment, the leadframe 60 is connected to the third metal film 52c, which serves as the drain electrode, provided on the lower surface of the semiconductor device body 50. The second conductive bump portion 82 connected to the leadframe 60 is exposed on the upper first surface 20a. This allows the drain electrode of the semiconductor device 20 to be arranged on the upper surface of the semiconductor device 20. This allows the gate electrode, source electrode, and drain electrode to be provided on the upper surface of the semiconductor device 20. Consequently, the semiconductor device body 50 can be configured as a field-effect transistor with a vertical structure, while the semiconductor device 20 as a whole can be treated as a field-effect transistor with a horizontal structure. This increases the degree of freedom in the placement of the electrodes connected to the external terminals in the semiconductor device 20, facilitating the adoption of a mounting method suitable for the product in which the semiconductor device 20 is to be mounted, thereby further improving the productivity of the products in which the semiconductor device 20 is to be mounted. In the first embodiment, the productivity of the circuit substrate 100 with built-in semiconductor devices 20 can be further improved.

[0085] Furthermore, heat from the semiconductor device body 50 can be easily released to the outside via the lead frame 60. Consequently, the heat dissipation performance of the semiconductor device 20 can be improved. Furthermore, the conductive bump portion 80 has a larger dimension in the thickness direction Z and a larger heat capacity than, for example, a conductive film formed by plating. Therefore, by connecting the conductive bump portion 80 to the semiconductor device body 50, heat can be more easily transferred from the semiconductor device body 50 to the conductive bump portion 80, compared to, for example, providing a conductive film formed by plating on the semiconductor device body 50 instead of the conductive bump portion 80. Consequently, heat from the semiconductor device body 50 can be easily released to the outside, further improving the heat dissipation performance of the semiconductor device 20.

[0086] Furthermore, when forming a conductive film on the lower surface of the thin semiconductor device body 50 by plating, the use of plating not only complicates the process but is also technically difficult. In contrast, in the first embodiment, the lead frame 60 can be fixed to the lower surface of the semiconductor device body 50, eliminating the need to form a conductive film on the lower surface of the semiconductor device body 50 by plating.

[0087] Furthermore, according to the first embodiment, the conductive bump portion 80 includes a first conductive bump portion 81 electrically connected to the semiconductor device body 50 and a second conductive bump portion 82 electrically connected to the lead frame 60. Therefore, it is possible to easily electrically connect other components to the semiconductor device body 50 and the lead frame 60 from outside the semiconductor device 20 via the first conductive bump portion 81 and the second conductive bump portion 82.

[0088] Furthermore, according to the first embodiment, the end faces of the first conductive bump portion 81 and the end faces of the second conductive bump portion 82 are exposed on the same surface of the semiconductor device 20. Therefore, compared to a case where the first conductive bump portion 81 and the second conductive bump portion 82 are exposed on different surfaces of the semiconductor device 20, it is easier to electrically connect the first conductive bump portion 81 and the second conductive bump portion 82 to other components. This further improves the productivity of products incorporating the semiconductor device 20. Furthermore, since the first conductive bump portion 81 and the second conductive bump portion 82 can be formed from the same side, the number of steps required to manufacture the semiconductor device 20 can be reduced. This improves the productivity of the semiconductor device 20.

[0089] Furthermore, according to the first embodiment, the first conductive bump portion 81 is connected to the upper surface of the semiconductor device body 50. The lead frame 60 has a first housing portion 63 that opens upward. The semiconductor device body 50 is housed within the first housing portion 63. The second conductive bump portion 82 is connected to the periphery of the opening of the first housing portion 63 on the upper surface of the lead frame 60. The upper end surface of the first conductive bump portion 81 and the upper end surface of the second conductive bump portion 82 are exposed on the first surface 20a. This makes it easy to align the upper surface of the semiconductor device body 50 with the periphery of the opening of the first housing portion 63 on the upper surface of the lead frame 60 in the thickness direction Z, making it easy to manufacture the first conductive bump portion 81 and the second conductive bump portion 82 using the same method. Specifically, in the first embodiment, the first conductive bump portion 81 and the second conductive bump portion 82 can be formed by forming the same stud bump 180. Thus, the first conductive bump portion 81 and the second conductive bump portion 82 can be easily manufactured.

[0090] Furthermore, according to the first embodiment, the conductive bump portion 80 is formed of a stud bump. In other words, the first conductive bump portion 81 and the second conductive bump portion 82 are formed of a stud bump. Therefore, the first conductive bump portion 81 and the second conductive bump portion 82 can be easily formed by ball bonding using a bonding wire. This reduces the number of steps required to form the conductive portion electrically connected to the semiconductor device body 50 or the lead frame 60, compared to forming a conductive film by plating instead of the conductive bump portion 80. Consequently, the manufacturing cost of the semiconductor device 20 can be reduced.

[0091] Furthermore, according to the first embodiment, a plurality of second conductive bump portions 82 are provided, and when viewed from above, the plurality of second conductive bump portions 82 are arranged to surround the first conductive bump portion 81. Therefore, external terminals and the like can be easily connected to the second conductive bump portions 82. Furthermore, this allows heat from the third metal film 52c, which serves as the drain electrode, to be efficiently released over a large area toward the side (upper side) where the semiconductor device 20 is mounted.

[0092] Furthermore, according to the first embodiment, the material constituting the first conductive bump portion 81 and the material constituting the second conductive bump portion 82 are the same, but different from the material constituting the lead frame 60. For example, a configuration is also conceivable in which the conductive bump portion 80 is not connected to the lead frame 60, and the lead frame 60 itself is exposed outside the resin portion 70 to serve as a terminal portion of the semiconductor device 20. In this case, in the grinding step S15 described above, when the resin portion 170 is ground, a portion of the conductive bump portion 80 and a portion of the lead frame 60 are ground together with the resin portion 170, so that a portion of the conductive bump portion 80 and a portion of the lead frame 60 are exposed outside the resin portion 70. In this case, if the material constituting the conductive bump portion 80 and the material constituting the lead frame 60 are different, it is necessary to grind three different materials for the resin portion 170, which may make the grinding process difficult. In contrast, in the first embodiment, by providing a second conductive bump portion 82 connected to the lead frame 60 and forming the second conductive bump portion 82 from the same material as the first conductive bump portion 81, the other material to be ground when grinding the resin portion 170 in the grinding step S15 can be a single material. Therefore, the grinding process can be easily performed in the grinding step S15. Furthermore, by making the first conductive bump portion 81 and the second conductive bump portion 82 from the same material, a plurality of conductive bump portions 80 can be easily manufactured.

[0093] Furthermore, according to the first embodiment, the semiconductor device 20 is embedded within the substrate main portion 10. Therefore, compared to mounting the semiconductor device 20 on the surface of the substrate main portion 10 and connecting the electrodes of the semiconductor device 20 to the wiring patterns formed on the substrate main portion 10 through wire bonding or the like, the length of the wiring connecting the electrodes of the semiconductor device 20 to the wiring patterns formed on the substrate main portion 10 can be shortened. This easily reduces the resistance between the electrodes of the semiconductor device 20 and the wiring patterns formed on the substrate main portion 10, facilitating the flow of current between the electrodes of the semiconductor device 20 and the wiring patterns formed on the substrate main portion 10. Consequently, it is easy to configure the circuit substrate 100 as a circuit substrate capable of high-speed communications, such as those involving the flow of high-frequency electrical signals. Furthermore, compared to mounting the semiconductor device 20 on the surface of the substrate main portion 10 and connecting the electrodes of the semiconductor device 20 to the wiring patterns formed on the substrate main portion 10 through wire bonding or the like, it is easier to miniaturize the circuit substrate 100. Furthermore, it is also possible to form additional layers and mount other components along the thickness direction Z of the portion of the substrate main portion 10 where the semiconductor device 20 is embedded. This can improve the degree of freedom in designing the circuit board 100 .

[0094] Furthermore, according to the first embodiment, the substrate body 10 includes a second housing portion 14 that houses the semiconductor device 20. A hole 15 is formed in the substrate body 10, extending from the outer surface of the substrate body 10 to the portion of the conductive bump 80 exposed outside the resin portion 70. A connection wiring portion 43 is formed within the hole 15, electrically connected to the conductive bump 80. To form this hole 15, the substrate body 10 is machined, for example, using the aforementioned laser processing. To prevent laser beam LB from damaging the semiconductor device body 50 and the like, an absorption layer that receives the laser beam LB is provided on the upper surface of the semiconductor device body 50 and the like. If this absorption layer is a thin film formed, for example, by sputtering, there is a risk that the laser beam LB will penetrate the thin film and damage the semiconductor device body 50 and the like. In contrast, in the first embodiment, the conductive bump 80, which can be increased in thickness direction Z to a certain extent, can serve as an absorption layer for the laser beam LB. Therefore, when the hole 15 is formed by laser processing, the laser beam LB can be appropriately received by the conductive bump portion 80 , and damage to the semiconductor device main body 50 and the like can be suppressed.

[0095] Alternatively, for example, a conductive film having a somewhat larger dimension in the thickness direction Z may be formed on the semiconductor device body 50 by plating or the like, and this conductive film may be used as an absorption layer for the laser beam LB when the hole 15 is formed. However, the process of forming the conductive film by plating tends to require more man-hours, and the manufacturing cost of the semiconductor device 20 tends to increase. In addition, the conductive film formed by plating sometimes does not have a sufficient thickness to serve as an absorption layer. In contrast, in the first embodiment, instead of the conductive film formed by plating, a conductive bump portion 80 is formed that is easily formed thicker than the conductive film. The man-hours required to form the conductive bump portion 80 are easily less than the man-hours required to form the conductive film by plating. Therefore, the increase in the manufacturing cost of the semiconductor device 20 can be suppressed. In addition, the conductive bump portion 80 easily makes it possible to obtain a sufficient thickness to serve as an absorption layer.

[0096] Furthermore, according to the first embodiment, the method for manufacturing the circuit substrate 100 includes the step of forming the hole 15 by irradiating the conductive bump portion 80 with laser light LB. Therefore, as described above, the conductive bump portion 80 can be used as an absorption layer, and the laser light LB can be appropriately prevented from penetrating the conductive bump portion 80. Consequently, damage to the semiconductor device body 50 and the like due to the laser light LB can be appropriately prevented.

[0097] (Second embodiment)

[0098] The second embodiment differs from the first embodiment in the number of second conductive bump portions 82. In the following description, the same configurations as those in the above-described embodiment are appropriately denoted by the same reference numerals and the description thereof may be omitted.

[0099] Figure 10 2 is a cross-sectional view showing a semiconductor device 220 according to the second embodiment. Figure 11 FIG is a top view showing a semiconductor device 220 according to the second embodiment. Figure 10 and Figure 11 As shown in FIG. 2 , the semiconductor device 220 has a smaller number of second conductive bumps 82 than the semiconductor device 20 of the first embodiment. Figure 11As shown, multiple second conductive bumps 82 are arranged in an L-shape along both sides of the rectangular frame portion 62. In other words, no second conductive bumps 82 are provided on the other two sides of the rectangular frame portion 62. Thus, by not arranging the multiple second conductive bumps 82 in a frame shape and not providing second conductive bumps 82 on one or more of the four sides of the frame portion 62, it is possible to prevent the second conductive bumps 82 from interfering with the routing of wiring on the circuit substrate on which the semiconductor device 220 is mounted. Consequently, the degree of freedom in routing wiring on the circuit substrate on which the semiconductor device 220 is mounted can be increased. The remaining structure of the semiconductor device 220 is the same as that of the semiconductor device 20 of the first embodiment.

[0100] (Third embodiment)

[0101] The third embodiment differs from the first embodiment in that the second conductive bump portion 82 is not provided. In the following description, the same configurations as those in the above-described embodiment are sometimes omitted by appropriately assigning the same reference numerals.

[0102] Figure 12 It is a cross-sectional view showing a semiconductor device 320 according to the third embodiment. Figure 13 FIG is a top view showing a semiconductor device 320 according to the third embodiment. Figure 12 and Figure 13 As shown, the semiconductor device 320 is different from the semiconductor device 20 of the first embodiment and does not have the second conductive bump portion 82 connected to the lead frame 360. Figure 12 As shown, the upper end surface of the frame portion 362 in the lead frame 360 ​​is located above the upper surface of the semiconductor device body 50. The upper end surface of the frame portion 362 is exposed on the upper first surface 320a of the semiconductor device 320. In the third embodiment, the first surface 320a is composed of the upper surface of the resin portion 70, the upper end surface of the first conductive bump portion 81, and the upper end surface of the frame portion 362. In the third embodiment, the upper end surface of the frame portion 362 can be used as an absorption layer during the laser processing step S26.

[0103] In the third embodiment, the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 are the same. Therefore, when performing the grinding step S15, it is possible to grind only one material outside the resin portion 70, and the grinding process can be easily performed. When the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 are the same, for example, from the perspective of manufacturing cost, it is preferable that the material is copper (Cu). In addition, in the third embodiment, the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 may also be different from each other. The other structures of the semiconductor device 320 are the same as those of the semiconductor device 20 of the first embodiment.

[0104] (Fourth embodiment)

[0105] The fourth embodiment differs from the first embodiment in the shape of the second conductive bump portion 482. In the following description, the same configurations as those in the above-described embodiment are appropriately denoted by the same reference numerals and their description may be omitted.

[0106] Figure 14 4 is a cross-sectional view showing a semiconductor device 420 according to a fourth embodiment. Figure 14 As shown, in the semiconductor device 420, the first receiving portion 63 is not formed in the lead frame 460. The lead frame 460 is in the shape of a flat plate with its plate surface facing in the thickness direction Z.

[0107] In the fourth embodiment, the second conductive bump portion 482 is formed by a vertical wire 480a. The vertical wire 480a is formed by performing ball bonding using a bonding wire, extending the bonding wire vertically from the stud bump formed by ball bonding, and then cutting the bonding wire to a certain length. The second conductive bump portion 482 is connected to the upper surface of the lead frame 460.

[0108] The second conductive bump portion 482 includes a stud bump portion 482a connected to the lead frame 460 and a wire portion 482b extending upward from the stud bump portion 482a. The stud bump portion 482a is formed of a stud bump. The stud bump portion 482a has the same shape as the stud bump 180 described in the first embodiment. The stud bump portion 482a is connected to the upper surface of the lead frame 460. In the fourth embodiment, the stud bump portion 482a and the semiconductor device body 50 are fixed to the same surface of the lead frame 460. In other words, the second conductive bump portion 482 and the semiconductor device body 50 are fixed to the same surface of the lead frame 460. The wire portion 482b is formed of a bonding wire. The upper end surface of the wire portion 482b is exposed on the first surface 420a. The rest of the structure of the semiconductor device 420 is the same as that of the semiconductor device 20 in the first embodiment.

[0109] Figure 15 FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device 420 according to a fourth embodiment. Figure 15 As shown, the manufacturing method of the semiconductor device 420 includes a chip mounting step S31 , a stud bump forming step S32 , a vertical wire forming step S33 , a molding step S34 , a grinding step S35 , and a singulation step S36 . Figure 16A It is a cross-sectional view showing the chip fixing step S31. Figure 16B 3 is a cross-sectional view showing the stud bump forming step S32 and the vertical wire forming step S33 . Figure 16C It is a cross-sectional view showing a state after the stud bump forming step S32 and the vertical wire forming step S33 are performed. Figure 16D It is a cross-sectional view showing a state after the molding step S34 is performed. Figure 16E It is a cross-sectional view showing a state after the grinding step S35 is performed.

[0110] like Figure 16A As shown, the chip fixing step S31 is a step of fixing the semiconductor device body 50 to the base material 460a of the lead frame 460. The base material 460a is identical to the base material 160 of the first embodiment, except that the dimensions in the thickness direction Z are generally the same. Alternatively, the base material 460a may be the same base material as the base material 160 of the first embodiment. In the chip fixing step S31, the semiconductor device body 50 is fixed to the upper surface of the base material 460a via the bonding portion 53. In the chip fixing step S31, one semiconductor device body 50 is fixed to each of the multiple frame body portions formed on the base material 460a.

[0111] The stud bump forming step S32 is the same as the stud bump forming step S13 in the first embodiment except that only the first conductive bump portion 81 is formed. Figure 16B and Figure 16C As shown, the vertical wire forming step S33 is a step of forming a vertical wire 480a on the base material 460a of the lead frame 460. As described above, the vertical wire 480a is formed by performing ball bonding using a bonding wire, extending the bonding wire vertically from the stud bump formed by ball bonding, and then cutting the bonding wire to a certain length.

[0112] In addition, Figure 16B , the stud bump forming step S32 and the vertical wire forming step S33 are performed simultaneously, but the present invention is not limited thereto. The vertical wire forming step S33 may be performed after the stud bump forming step S32, or after the vertical wire forming step S33, or the stud bump forming step S32 and the vertical wire forming step S33 may be performed simultaneously.

[0113] The molding step S34 is a step of insert molding the mother material 460a in a state where the semiconductor device body 50 is fixed and the stud bumps 180 and the vertical wires 480a are formed as an insert component. Figure 16D As shown, the molding step S34 forms the resin portion 170 in which the base material 460 a , the semiconductor device body 50 , the stud bumps 180 , and the vertical wires 480 a are embedded.

[0114] The grinding step S35 is a step of grinding the resin portion 170 from the upper side to reduce the size of the resin portion 170 in the thickness direction Z. In the grinding step S35, the resin portion 170 is ground until the size of the resin portion 170 in the thickness direction Z becomes the size of the semiconductor device 420 in the thickness direction Z. Figure 16E As shown, the resin portion 170 is ground from the top in the grinding step S35, thereby exposing the stud bumps 180 and the vertical wires 480a on the top surface of the resin portion 170. In the grinding step S35, the top portions of the stud bumps 180 and the top portions of the wire portions of the vertical wires 480a are also ground away along with the resin portion 170. In the grinding step S35, the top portions of the stud bumps 180 are removed by grinding, and each stud bump 180 becomes a first conductive bump portion 81. In the grinding step S35, the top portions of the wire portions of the vertical wires 480a are removed by grinding, and each vertical wire 480a becomes a second conductive bump portion 482.

[0115] The singulation step S36 is the same as the singulation step S16 of the first embodiment. The singulation step S36 forms a plurality of semiconductor devices 420. The remaining steps in the method of manufacturing the semiconductor device 420 are the same as the remaining steps in the method of manufacturing the semiconductor device 20 of the first embodiment.

[0116] According to the fourth embodiment, the second conductive bump portion 482 includes a columnar bump portion 482a connected to the lead frame 460 and a wire portion 482b extending upward from the columnar bump portion 482a. The upper end surface of the wire portion 482b is exposed on the first surface 420a. Thus, by configuring the second conductive bump portion 482 to be formed from the vertical wire 480a, the first receiving portion 63 can be omitted from the lead frame 460. Instead, the upper end of the second conductive bump portion 482 connected to the lead frame 460 can be positioned at the same position as the upper end of the first conductive bump portion 81. Consequently, the number of steps required to process the lead frame 460 can be reduced.

[0117] (Fifth embodiment)

[0118] The fifth embodiment differs from the first embodiment in the shape of the wiring portion 540. In the following description, the same configurations as those in the above-described embodiment are appropriately denoted by the same reference numerals and the like, and the description thereof may be omitted.

[0119] Figure 17 FIG is a cross-sectional view showing a portion of a circuit substrate 500 according to the fifth embodiment. Figure 17 As shown, the through-hole 16 is not formed in the substrate body 510 of the circuit substrate 500. The wiring portion 540 in the circuit substrate 500 does not include the second wiring pattern 42 and the connecting wiring portion 44 formed in the through-hole 16. The remaining structure of the wiring portion 540 is the same as that of the wiring portion 40 in the first embodiment. The remaining structure of the circuit substrate 500 is the same as that of the circuit substrate 100 in the first embodiment.

[0120] (Sixth embodiment)

[0121] The sixth embodiment differs from the first embodiment in that the circuit substrate 600 does not have a built-in semiconductor device 20. In the following description, the same configurations as those in the above-mentioned embodiments are sometimes omitted by appropriately assigning the same reference numerals.

[0122] Figure 18 FIG is a cross-sectional view showing a portion of a circuit substrate 600 according to the sixth embodiment. Figure 18 As shown, in the sixth embodiment, the semiconductor device 20 is mounted on one surface of a substrate main body 610. The semiconductor device 20 is mounted on the substrate main body 610 by flip-chip mounting. The first conductive bump portion 81 and the second conductive bump portion 82 of the semiconductor device 20 are electrically connected to a wiring pattern (not shown) on the substrate main body 610 via bumps 691 formed of solder or the like. An adhesive layer 692 is formed between the semiconductor device 20 and the substrate main body 610 to bond the semiconductor device 20 to the substrate main body 610. A plurality of bumps 691 are embedded in the adhesive layer 692.

[0123] According to the sixth embodiment, the semiconductor device 20 is mounted on one surface of the substrate body 610. Therefore, the structure of the substrate body 610 can be simplified compared to a case where the semiconductor device 20 is built into the substrate body 610.

[0124] Furthermore, thinning the semiconductor device body 50 reduces its operability, making it difficult to mount the semiconductor device body 50 on the substrate body 610 via flip-chip mounting. Furthermore, flip-chip mounting also imposes structural constraints, such as requiring the semiconductor device body 50 to be a horizontal field-effect transistor. In contrast, encapsulating the semiconductor device 20 by covering the semiconductor device body 50 and the lead frame 60 with a resin portion 70 improves the operability of the semiconductor device 20, making it easier to mount the semiconductor device 20 on the substrate body 610 via flip-chip mounting. Furthermore, even if the semiconductor device body 50 is a vertical field-effect transistor, the gate electrode, source electrode, and drain electrode of the semiconductor device 20 can be arranged on the same surface via the lead frame 60. Therefore, flip-chip mounting can be used as the mounting method for the semiconductor device 20 regardless of the structure of the semiconductor device body 50.

[0125] According to at least one embodiment described above, a semiconductor device includes a first surface facing a first side and a second surface facing a second side opposite the first side. The semiconductor device includes a semiconductor device body, a lead frame electrically connected to the semiconductor device body, a conductive bump portion electrically connected to the semiconductor device body or the lead frame, and a resin portion covering and retaining at least a portion of the semiconductor device body and at least a portion of the lead frame. At least a portion of the conductive bump portion is exposed outside the resin portion. This improves the operability of the semiconductor device.

[0126] The conductive bump portion is not limited to the above-mentioned conductive bump portion formed by the columnar bump or the conductive bump portion formed by the vertical wire. The method for forming the conductive bump portion is not particularly limited. The conductive bump portion can be formed by a metal bump formed by screen printing or by inkjet printing. The conductive bump portion can also be entirely exposed outside the resin portion.

[0127] As the conductive bump portion, only the first conductive bump portion may be provided, or only the second conductive bump portion may be provided. The number of conductive bump portions is not particularly limited as long as it is at least one. The surface of the semiconductor device on which the first conductive bump portion is exposed and the surface of the semiconductor device on which the second conductive bump portion is exposed may also be different surfaces. In the case of providing a plurality of first conductive bump portions, the plurality of first conductive bump portions may also include two or more first conductive bump portions exposed on different surfaces of the semiconductor device. In the case of providing a plurality of second conductive bump portions, the plurality of second conductive bump portions may also include two or more second conductive bump portions exposed on different surfaces of the semiconductor device. The material constituting the first conductive bump portion and the material constituting the second conductive bump portion may also be different from each other.

[0128] The structure of the circuit substrate having the semiconductor device is not particularly limited. The circuit substrate may also be a multilayer substrate. The number of semiconductor devices on the circuit substrate is not particularly limited, as long as it is one or more. The holes formed in the circuit substrate may also be formed by methods other than laser processing. Even in this case, by forming the conductive bump portion with a certain thickness, damage to the semiconductor device body and the like can be suppressed.

[0129] The semiconductor device, the circuit board, and the method for manufacturing the circuit board according to the embodiment include the following additional aspects.

[0130] (Note 1)

[0131] A semiconductor device having a first surface facing a first side and a second surface facing a second side opposite to the first side, wherein the semiconductor device is characterized by:

[0132] a semiconductor device body;

[0133] a lead frame electrically connected to the semiconductor device body;

[0134] a conductive bump portion electrically connected to the semiconductor device body or the lead frame; and

[0135] a resin portion that covers and holds at least a portion of the semiconductor device body and at least a portion of the lead frame,

[0136] At least a portion of the conductive bump portion is exposed outside the resin portion.

[0137] (Note 2)

[0138] The semiconductor device according to Supplementary Note 1, wherein the conductive bump portion includes:

[0139] a first conductive bump portion electrically connected to the semiconductor device body; and

[0140] A second conductive bump portion is electrically connected to the lead frame.

[0141] (Note 3)

[0142] The semiconductor device according to Supplementary Note 2 is characterized in that an end surface of the first conductive bump portion and an end surface of the second conductive bump portion are exposed on the same surface of the semiconductor device.

[0143] (Note 4)

[0144] The semiconductor device according to Supplementary Note 3 is characterized in that:

[0145] The first conductive bump portion is connected to the first side surface of the semiconductor device body.

[0146] The lead frame has a first receiving portion opened at the first side,

[0147] The semiconductor device body is housed in the first housing portion.

[0148] The second conductive bump portion is connected to the opening peripheral edge portion of the first receiving portion on the first side surface of the lead frame.

[0149] The end surface of the first conductive bump portion on the first side and the end surface of the second conductive bump portion on the first side are exposed on the first surface.

[0150] (Note 5)

[0151] The semiconductor device according to Supplementary Note 4 is characterized in that the first conductive bump portion and the second conductive bump portion are formed of stud bumps.

[0152] (Note 6)

[0153] The semiconductor device according to Appendix 3, wherein:

[0154] The first conductive bump portion is connected to the first side surface of the semiconductor device body.

[0155] The second conductive bump portion is connected to the first side surface of the lead frame,

[0156] The first conductive bump portion is formed by a pillar-shaped bump,

[0157] The second conductive bump portion has:

[0158] a stud bump portion connected to the lead frame; and

[0159] a lead portion extending from the stud bump portion toward the first side,

[0160] The end surface of the first conductive bump portion on the first side and the end surface of the lead portion on the first side are exposed on the first surface.

[0161] (Note 7)

[0162] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the conductive bump portion is formed of a stud bump.

[0163] (Note 8)

[0164] The semiconductor device according to any one of Supplementary Notes 4 to 6, characterized in that:

[0165] The second conductive bump portion is provided with a plurality of

[0166] The plurality of second conductive bump portions are arranged to surround the first conductive bump portion when viewed from the first side.

[0167] (Note 9)

[0168] The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein a material constituting the first conductive bump portion and a material constituting the second conductive bump portion are the same as each other and different from a material constituting the lead frame.

[0169] (Note 10)

[0170] A circuit substrate, characterized by comprising:

[0171] The semiconductor device according to any one of Supplementary Notes 1 to 9; and

[0172] A substrate main body portion is provided with the semiconductor device mounted thereon.

[0173] (Note 11)

[0174] The circuit substrate according to Supplementary Note 10 is characterized in that the semiconductor device is built into the substrate main body.

[0175] (Note 12)

[0176] The circuit substrate according to Appendix 11, wherein:

[0177] The substrate main body has a second housing portion for housing the semiconductor device therein.

[0178] The substrate body portion includes a hole portion extending from an outer surface of the substrate body portion to a portion of the conductive bump portion exposed to the outside of the resin portion.

[0179] A connection wiring portion electrically connected to the conductive bump portion is formed inside the hole portion.

[0180] (Note 13)

[0181] The circuit substrate according to Supplementary Note 10 is characterized in that the semiconductor device is mounted on one surface of the substrate main body.

[0182] (Note 14)

[0183] A method for manufacturing a circuit substrate, comprising:

[0184] The method includes forming the hole portion by irradiating the conductive bump portion with a laser.

[0185] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention, and are also intended to be within the scope of the invention set forth in the claims and their equivalents.

[0186] Description of Reference Numerals

[0187] 10, 510, 610…substrate main body, 14…second housing portion, 15…hole portion, 20, 220, 320, 420…semiconductor device, 20a, 320a, 420a…first surface, 20b…second surface, 40, 540…wiring portion, 43…connecting wiring portion, 50…semiconductor device main body, 60, 360, 460…lead frame, 63…first housing portion, 70…resin portion, 80…conductive bump portion, 81…first conductive bump portion, 82, 482…second conductive bump portion, 100, 500, 600…circuit substrate, 180…columnar bump, 482a…columnar bump portion, 482b…wire portion, LB…laser

Claims

1. A semiconductor device comprising a first surface facing a first side and a second surface facing a second side opposite to the first side, the semiconductor device comprising: a semiconductor device body; a lead frame electrically connected to the semiconductor device body; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; and a resin portion that covers and holds at least a portion of the semiconductor device body and at least a portion of the lead frame, At least a portion of the conductive bump portion is exposed outside the resin portion.

2. The semiconductor device according to claim 1, wherein: The conductive bump portion includes: a first conductive bump portion electrically connected to the semiconductor device body; and A second conductive bump portion is electrically connected to the lead frame.

3. The semiconductor device according to claim 2, wherein: An end surface of the first conductive bump portion and an end surface of the second conductive bump portion are exposed on the same surface of the semiconductor device.

4. The semiconductor device according to claim 3, wherein: The first conductive bump portion is connected to the first side surface of the semiconductor device body. The lead frame has a first receiving portion opened at the first side, The semiconductor device body is housed in the first housing portion. The second conductive bump portion is connected to the opening peripheral edge portion of the first receiving portion on the first side surface of the lead frame. The end surface of the first conductive bump portion on the first side and the end surface of the second conductive bump portion on the first side are exposed on the first surface.

5. The semiconductor device according to claim 4, wherein: The first conductive bump portion and the second conductive bump portion are formed of stud bumps.

6. The semiconductor device according to claim 3, wherein: The first conductive bump portion is connected to the first side surface of the semiconductor device body. The second conductive bump portion is connected to the first side surface of the lead frame, The first conductive bump portion is formed by a pillar-shaped bump, The second conductive bump portion has: a stud bump portion connected to the lead frame; and a lead portion extending from the stud bump portion toward the first side, The end surface of the first conductive bump portion on the first side and the end surface of the lead portion on the first side are exposed on the first surface.

7. The semiconductor device according to claim 1, wherein: The conductive bump portion is formed of a stud bump.

8. The semiconductor device according to claim 4, wherein: The second conductive bump portion is provided with a plurality of The plurality of second conductive bump portions are arranged to surround the first conductive bump portion when viewed from the first side.

9. The semiconductor device according to claim 2, wherein: A material constituting the first conductive bump portion and a material constituting the second conductive bump portion are the same as each other and different from a material constituting the lead frame.

10. A circuit substrate, characterized in that: have: The semiconductor device according to any one of claims 1 to 9; and A substrate main body portion is provided with the semiconductor device mounted thereon.

11. The circuit substrate according to claim 10, wherein: The semiconductor device is built into the substrate main body.

12. The circuit substrate according to claim 11, wherein: The substrate main body has a second housing portion for housing the semiconductor device therein. The substrate body portion includes a hole portion extending from an outer surface of the substrate body portion to a portion of the conductive bump portion exposed to the outside of the resin portion. A connection wiring portion electrically connected to the conductive bump portion is formed inside the hole portion.

13. The circuit substrate according to claim 10, wherein: The semiconductor device is mounted on one surface of the substrate main body.

14. A method for manufacturing a circuit substrate, for manufacturing the circuit substrate according to claim 12, characterized in that: The method includes forming the hole by irradiating the conductive bump portion with laser light.

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