Electrical switching device for generating current control electrical signal

Abstract

There is described an electrical switching device for generating a current control electrical signal in a controlled cascode current mirror manner for functional in vivo stimulation, comprising first, second, third and fourth transistors, each transistor having associated source, drain and gate terminals, the second and fourth transistors are connected in an output cascode structure such that a source terminal of the fourth transistor is connected to a drain terminal of the second transistor and a drain terminal of the fourth transistor is connected to an output contact associated with the electrical switching device, a voltage potential associated with the current control electrical signal can be acquired at the output contact. The invention is characterized in that the gate terminal of the fourth transistor is connected in a switchable manner to at least one constant specifiable voltage potential.

Description

Technical Field

[0001] The present invention relates to an electrical switching device for generating a current-controlled electrical signal in a controlled cascode current mirror manner for achieving functional in vivo stimulation, comprising first, second, third and fourth transistors, each transistor having associated source, drain and gate terminals, wherein the gate terminals of the first and second transistors are connected to each other in order to form a current mirror, wherein the third and first transistors are connected in an input cascode configuration, wherein the drain terminal of the third transistor is connected to the gate terminals of the first and second transistors, the source terminal of the third transistor is connected to the drain terminal of the first transistor, and the gate terminal of the third transistor is connected to the output of an operational amplifier having at least two inputs, wherein one input of the operational amplifier is connected to the drain terminal of the second transistor, and the other input of the operational amplifier is connected to the source terminal of the third transistor, which is at the same potential as the drain terminal of the first transistor, and wherein the second and fourth transistors are connected in an output cascode configuration in such a way that the source terminal of the fourth transistor is connected to the drain terminal of the second transistor, and the drain terminal of the fourth transistor is connected to an output contact associated with the electrical switching device, at which a voltage potential associated with the current-controlled electrical signal is accessible. Background Art

[0002] Functional electrical stimulation or neurostimulation (FES / FNS) is a method of treating various neurological disorders by stimulating nerves with electrical charges. Applications range from cardiac pacemakers and corneal implants to peripheral nerve stimulators.

[0003] A known medical implant, which is the subject of publication EP 3 204 105 B1, is used for site-selective recording of neural electrical signals propagating along at least one nerve fiber and for selective electrical stimulation of at least one nerve fiber. The medical implant utilizes an electrode arrangement designed in the form of a sleeve to achieve electrical signal transmission between the nerve fiber and the implant. The electrode arrangement comprises a plurality of electrode contacts that are in direct contact with the epineurium of a nerve fiber bundle (preferably the vagus nerve). This involves mutually coordinated electrical polarization or activation of each individual electrode contact, depending on the medical treatment or analysis goal. To this end, the electrode contacts are each electrically connected to at least one stimulation channel, wherein each individual stimulation channel can be accessed at a separate output contact of an electrical switching device arranged on the implant side.

[0004] In principle, there are three possibilities for polarizing stimulation channels and the associated individual electrodes: via voltage-, charge-, or current-based stimulation. These methods are physically related but describe different ways of achieving charge release: controlled by a voltage source, discharged via a capacitor, or achieved via a current source. However, the following describes the principle of charge release using a current source, known as "current-controlled stimulation" (CCS).

[0005] Therefore, it is crucial to control the amount of charge applied locally to the epineurium via the electrode contacts, because on the epineurium the metal electrode contact / electrolyte interface is characterized by a maximum allowable amount of charge that can be transferred from the respective electrode contacts to the biological tissue.

[0006] Therefore, with current-controlled stimulation, the pulse width t_w and the stimulation current amplitude l_stim can be controlled independently of impedance fluctuations. Furthermore, when using right-angle stimulation, charge and current are directly linked via Q = l_stim * t_w. However, with current-controlled stimulation, it must be considered that high voltages are required to achieve specific current levels in the presence of high load impedances. This necessitates high-voltage CMOS processes when developing application-specific ICs (ASICs).

[0007] As the current source for each stimulation channel, a current mirror was used to form a controllable current source with the highest possible output resistance.

[0008] A possible architecture of such a current mirror is described in the document "Ultra high-compliance cmos current mirrors for low voltage charge pumps and references" by O. Charlon and W. Redman-White, Sept. 2004, pp. 227-230. In addition to a series of current mirrors that differ in complexity, Figure 1 A known regulated cascode current mirror disclosed in this document is shown, comprising first, second, third and fourth transistors (T1, T2, T3, T4), each transistor having associated source, drain and gate terminals, wherein, in order to form the current mirror, the gate terminals of the first and second transistors (T1, T2) are connected to each other and to an input potential (V in ), wherein the third and first transistors (T3, T1) are connected in an input cascode configuration. To this end, the drain terminal of the third transistor (T3) is connected to the input potential (V in), the source terminal of the third transistor (T3) is connected to the drain terminal of the first transistor (T1), and the gate terminal of the third transistor (T3) is connected to the output terminal (A) of the operational amplifier (OPA). The operational amplifier (OPA) has two input terminals, wherein one input terminal (+) of the operational amplifier (OPA) is connected to the drain terminal of the second transistor (T2), and the other input terminal (-) of the operational amplifier (OPA) is connected to the source terminal of the third transistor (T3) and the drain terminal of the first transistor (T1) at the same potential (Va). In addition, the source terminal of the fourth transistor (T4) is connected to the drain terminal of the second transistor (T2), and the gate terminal of the fourth transistor (T4) is connected to the input potential (V in ), the drain terminal of the fourth transistor (T4) is connected to an output contact (out) associated with the electrical switching device, at which a voltage potential (V out ). Summary of the Invention

[0009] The object of the present invention is to further develop an electrical switching device for generating current-controlled electrical signals in the manner of a controlled cascode current mirror for functional in vivo stimulation, such that the quality of the stimulation channels that can be obtained in the form of current-controlled electrical signals at at least one output contact is improved compared to known switching topologies. Furthermore, the circuit structure needs to be designed to be as compact as possible, i.e., space-saving, with regard to scalability of the number of stimulation channels and their combinability, while being diverse in terms of the different switchable connection possibilities between the stimulation channels and the output contacts connected to the electrode contacts.

[0010] The solution to the object underlying the invention is set forth in claim 1. Advantageous features of the inventive concept form the subject matter of the dependent claims and of the further description with reference to the drawings.

[0011] The electrical switching device according to the invention for generating a current-controlled electrical signal in a controlled cascode current level manner for achieving functional in vivo stimulation has the features according to the preamble of claim 1, characterized in that the gate terminal of the fourth transistor is connected in a switchable manner to a constant, prescribable voltage potential.

[0012] Compared to the known switching device described initially (where the gate voltage of the fourth transistor is also controlled by the gate voltages of the first and second transistors, see Figure 1 ), according to this solution the fourth transistor is constantly biased with a voltage which preferably originates from an external supply voltage source.

[0013] Basically, for a current source, the higher the output resistance of the current source, the better the current source. According to this solution, the fourth transistor is not controlled, so that the switching topology is similar to the topology of an input-controlled current mirror, but the output resistance is significantly increased because the output resistance increases with the inherent gain of the fourth transistor. The output resistance achieved at the drain terminal of the fourth transistor using the switching topology according to the present invention is significantly higher than the output resistance of the fourth transistor in the prior art when it is controlled, see Figure 1 The gate terminal of the controlled fourth transistor is connected to the gate terminals of the first and second transistors, thereby reducing the electrical polarity of the drain terminal of the second transistor to an extent that causes the second transistor to change its operating region (i.e., from a saturation region to a linear region), wherein the output resistance of the transistor in the linear region is much lower than its output resistance in the saturation region.

[0014] A further advantage of the switching topology according to this solution is improved robustness against possible drain voltage fluctuations, since, on the one hand, the first and second transistors operate in a strong inversion region instead of a linear region; on the other hand, the fourth transistor (whose gate voltage is now constant and is separated from the control circuit) acts as a buffer, so that undesirable voltage fluctuations (in particular voltage fluctuations at the drain terminal of the fourth transistor which is directly connected to the electrode contact) are no longer directly reflected in the current amplitude.

[0015] Furthermore, the fourth transistor acts as a static switch and thus has a switching function. During operation, for example, a supply voltage of 1.8 V is applied to the gate terminal. Depending on the switch position, a control or supply voltage of 0 V or 1.8 V is thus present at the fourth transistor.

[0016] If it is necessary to generate particularly high stimulus currents, for example 2 mA and above, the maximum gate-source voltage is advantageous. Even in the smallest dimension design for forming the fourth transistor (preferably with the smallest width / length dimensions B / L=1-3 μm / 500 nm–1.3 μm), the maximum gate-source current still enables the fourth transistor to be fully turned on.

[0017] Preferably, in order to protect the electrical switching device as a whole from external high voltage, a high-voltage protection transistor is arranged in series between the output contact and the fourth transistor, and the high-voltage protection transistor is connected in series with the source-drain section of the fourth transistor. This makes it possible to design all other transistors (i.e. the first, second, third and fourth transistors) as low-voltage transistors, which can be controlled with a voltage of a maximum of ±1.8V, while according to the present invention, the high-voltage transistor can be operated with a maximum control voltage of ±20V (but preferably ±18V). The size of the low-voltage transistor can be smaller than that of the high-voltage transistor, thereby opening up the possibility of further miniaturization of the entire electrical switching device.

[0018] In addition to the first electrical switching device, a second switching device is provided that is opposite to the first switching device and is capable of generating a current control signal that is opposite to the current control signal of the first switching device. Similar to the first switching device, the second switching device also includes a fourth transistor connected to the output contact of the first switching device.

[0019] The switching topology of the two switching devices is opposite to each other, with one switching device acting as a current source for the positive stimulation path and the other switching device acting as a current sink for the negative stimulation path. To this end, the two switching devices have the same structure but are implemented using opposite transistor types (n-MOS and p-MOS).

[0020] Preferably, the current mirror formed by the first and second transistors in the electrical switching device designed according to this solution is configured as an n-bit digital-analog converter (preferably a 5-bit digital-analog converter) and has 2 n -1 second transistor. n -1 The drain terminals of the second transistors are connected to 2 n - a source terminal of a fourth transistor, the drain terminals of which are respectively connected to an output contact of the electrical switching device.

[0021] In another preferred embodiment, the 2 n The drain terminals of the -1 second transistors are also connected or can be connected to each other, so that those bits that are activated are always transmitted via the appropriately connected drain terminals.

[0022] In another preferred embodiment, it is possible to switch each stimulation channel separately to a different or multiple output contacts and electrode contacts connected thereto (e.g., directly in contact with the vagus nerve). For this purpose, a switching matrix is ​​used, which connects, on the one hand, the drain terminal of at least one fourth transistor of the electrical switching device and, on the other hand, the m output contacts. For protection against destructive power surges and for reasons of reducing component size, an additional high-voltage transistor is provided between each of the m output contacts and the corresponding fourth transistor as part of the switching matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be described below by way of example with reference to the accompanying drawings, without limiting the general inventive concept.

[0024] Figure 1 shows the switching topology of a known current mirror device,

[0025] Figure 2 The switching device designed according to the solution is shown.

[0026] Figure 3 Another switching device is shown, and

[0027] Figure 4 A switching matrix is ​​shown schematically. DETAILED DESCRIPTION

[0028] To explain Figure 1 Please refer to the above description for the conventional current mirror switching device shown in FIG. This switching device can be found in FIG. 9 of the reference by O. Charlon et al. mentioned in the introduction.

[0029] Figure 2 The illustrated electrical switching device according to this solution also has the aforementioned first, second, third and fourth transistors T1, T2, T3, T4, wherein the series-connected first and third transistors T1 and T3 are wired as a controlled input cascode structure, and the first and second transistors T1 and T2 are wired as a current mirror. To this end, the respective gate terminals of the first and second transistors T1, T2 are not only connected to one another but also to the input potential V applied to the input contact (in) of the switching device. in In addition, a fourth transistor T4 is provided as an output cascode structure, wherein the source-drain section of the fourth transistor T4 is connected in series with the source-drain section of the second transistor T2. The fourth transistor T4 is supplied with a constant supply voltage V DD And used as a switch. Supply voltage V DD Typically 1.8 V, which is applied in a switchable manner at the gate terminal of the fourth transistor T4 .

[0030] The basic current I is provided by the reference current source ref , the basic current I ref The scaling is performed by means of the switching device according to this solution and can be obtained at the output out of said switching device.

[0031] like Figure 1 As shown in the circuit diagram, the third transistor T3 is connected to the output terminal A of the operational amplifier OPA, and the output voltage V c The operational amplifier OPA has two input terminals, wherein the positive input terminal "+" is connected to the voltage potential V applied between the second and fourth transistors T2 and T4 connected in series. b The negative input terminal "-" of the operational amplifier OPA is connected to the voltage potential V applied between the first and third transistors T1 and T3 connected in series. a .

[0032] By controlling the third transistor T3 with the aid of the operational amplifier OPA, two control paths R1 and R2 can be distinguished within the switching device: the first control path R1 corresponds to the source voltage V applied to the third transistor T3 via the negative input terminal “-” of the operational amplifier OPA. a The second control path R2 involves positive feedback via the positive input terminal "+" of the operational amplifier OPA, through the third, first and second transistors T3, T1 and T2. It is this concept of controlled input common source common gate structure that enables the output current I out It has higher mirroring accuracy.

[0033] Due to the additional amplification effect brought about by the operational amplifier OPA, the output resistance R out For the output resistance R out , the following formula applies: R out =A·R ds2 ·g m4 ·R ds4 , where A: amplification factor of operational amplifier OPA, R ds2 = the small signal resistance between the drain and source terminals of the second transistor, g m4 = small signal transconductance of T4, R ds4 =The small signal resistance between the drain and source terminals of the fourth transistor.

[0034] Furthermore, the dimensions of the third transistor T3 can be smaller, in particular can be designed to be smaller than the dimensions of the fourth transistor T4, whereby the requirements placed on the operational amplifier OPA for controlling the third transistor T3 are much lower than in the case of known switching concepts with a controlled output stage (i.e. with a controlled fourth transistor T4), see Figure 1 Switching device in.

[0035] Figure 2 A further development of the electrical switching device shown in FIG is an optional, additional monitoring switching component CM, also called a compliance monitoring component, in FIG. Figure 2 The monitoring switching component CM detects abnormal operating conditions of the electrical switching device, which are characterized by irregular voltage potentials that can form at certain nodes of the switching device. For example, if the voltage potential V out If the potential drops to the lowest level within the switching device, it indicates that an abnormal state has occurred, wherein a potential crossing phenomenon called "crossing" will occur within the switching device, which phenomenon needs to be detected.

[0036] Figure 2 The monitoring switching component CM shown in FIG is a comparator K having two comparator inputs Ke1, Ke2 and a comparator output Ka. The comparator input Ke1 is connected to the gate terminals of the first and second transistors (T1, T2) and thereby to the input contact (in) of the switching device, at which the input potential V in In contrast, the comparator input Ke2 is connected to the potential Vc applied to the output (A) of the operational amplifier (OPA).

[0037] In a preferred application of a switching device for generating a current-controlled electrical signal to achieve functional in vivo stimulation, the voltage potential within the switching device is selected such that, in normal operation, the input potential V in is always smaller than the amplified voltage potential Vc selected by the operational amplifier OPA. In addition, in normal operation, all potentials on the switching nodes of the switching device are ideally kept constant at their operating points.

[0038] However, if a potential deviation from the normal state occurs at the operating point and the deviation is greater than the initially set potential difference Vc-V in , then the switching device will no longer be able to operate in a reliable and correct manner. in = Vc, the voltage will be the same or the voltage will cross, which is a very suitable detection feature. Through circuit design, it can be selected according to the V inThe magnitude of the initial potential difference with Vc determines in a deterministic manner the moment at which the voltage crossover or "crossover" phenomenon occurs.

[0039] According to the input potential V in The comparator K generates a signal S from the potential difference between the potential Vc present at the output of the operational amplifier OPA, which serves as a warning signal as soon as a critical operating state occurs as described above.

[0040] The warning signal S can be used as a criterion for stopping the switching operation of the switching device, or as a regulation or control parameter to adjust the supply voltage V DD With the necessary output voltage V out The switching device's supply voltage V DD It should always be slightly larger than the output voltage V that can be obtained at the output terminal out out However, the voltage potential V DD and V out The choices of should not differ too much in order to keep the power dissipation generated in the circuit to a minimum. Therefore, so-called compliance monitoring is advantageous.

[0041] Figure 3 An advantageous extended switching device is shown, comprising a first switching device I and a second switching device II which are mirror images of each other and are connected to one another only via a respective fourth transistor T4 to at least one output contact.

[0042] Assume that the first switching device I functions as a current sink to generate a negative stimulation channel, while the second switching device II functions as a current source to generate a positive stimulation channel. The two switching devices I and II are configured as mirror images, but each has opposite transistor types: n-MOS transistors (T1, T2, T3, T4) in the case of the first switching device I, and p-MOS transistors (T1*, T2*, T3*, T4*) in the case of the second switching device II. The first switching device I operates in a lower voltage domain than the second switching device II, that is, between voltage potentials vlvo and vlvi, while the second switching device II operates between voltage potentials vhvo and vhvi.

[0043] Since the fourth transistors T4 and T4* act as switches, the two switching devices can preferably occupy at least one output contact out synchronously with each other to output a positive or negative stimulation signal. To this end, the corresponding fourth transistors T4 and T4* are switched by the static switching signal en bit_x Control or switch.

[0044] The first and second transistors T1 or T1* and T2 or T2* are wired as current mirrors IDAC,N, IDAC,P, respectively, which form a stimulation channel and are implemented in the form of a 5-bit digital-to-analog converter (DAC). In this case, the first transistor T1 or T1* is connected to 2 5 - 1 second transistor T2 or T2*.

[0045] For the purpose of high voltage protection, a high voltage transistor T is connected between the fourth transistor T4 or T4* and the output contact out. HV or T HV *, to protect the switching device from external power surges. In this way, all other transistors can be designed as low-voltage transistors, the size of which can be significantly smaller than that of the high-voltage transistors, thereby enabling the entire switching device to be further miniaturized. High-voltage transistor T HV or T HV *Also via static switching signal en E_x Switch, where en bit_x with en E_x Independent of each other. Switching signal en bit_x Determines the current amplitude at the output end out, and the switching signal en E_x Select the electrode to be connected to the output terminal out.

[0046] In a preferred and optional embodiment of the switching devices I and II, the first transistor T1 or T1* is respectively connected to the dynamic switch S en Connected to the corresponding second transistor T2 or T2*. When the switch S en When closed, a source-drain current of 20 μA flows through the corresponding second transistor T2 or T2*. In addition, another second transistor T2 is provided. hc or T2 hc *, which can be switched as needed via switch S hc If the switch S hc Closed, 30μA source-drain current flows through the corresponding other second transistor T2 hc or T2 hc *, so that when the switch S en and S hc When closed at the same time, the two other second transistors T2 / T2 hc or T2* / T2 hc * A total of 50 μA of current can be obtained at the drain output of each. By combining all current paths in the 5-bit current mirror IDAC,P and IDAC,N, up to (2 5-1) ·50 μA = 1.55 mA stimulation current.

[0047] Additional high-dynamic switches S that result in faster or shorter switching times hs This constitutes a further option for expanding the functionality of the switching device, by which a steeper rising edge of the stimulation current can be achieved. hs and S hc When both switches are closed, the switches S hs Make sure to compensate for at least the number of transistors (T2+T2 hc or T2*+T2 hc *) causes a slowdown in the current rise time.

[0048] For the sake of completeness, it is pointed out that in the switching devices I and II, for the purpose of monitoring, additional Figure 2 Related discussion of the monitoring switching component CM.

[0049] In order to switch the stimulation current available at the output out jointly or individually to a plurality of or different output contacts and ultimately to the electrode contacts, the switching device has a switching matrix sw_matrix, which is shown schematically and in more detail in Figure 4 middle.

[0050] Figure 4 A switching matrix sw_matrix is ​​shown, which connects a number k=8 stimulation channels to a number m of output contacts, at which each stimulation channel can be accessed and applied directly to the organic structure (for example to the vagus nerve) via electrode contacts.

[0051] To display and implement the stimulus channel, Figure 3 The switching device shown is composed of switching devices I and II.

[0052] Figure 4 The switching matrix shown in FIG is capable of electrically connecting m=12 output contacts out to k=8 stimulation channels. For each individual stimulation channel k in each of the first and second switching devices I and II, k first and third transistors T1, T3 and k·(2 n -1) second transistors, where n=5 (i.e., 5 bits). Figure 4 In the diagram, since the structure of the switching device II is exactly the same as that of the switching device I, the schematic diagram of each stimulation channel k in the switching device II is omitted. In order to realize the additional activatable connection of k=8 stimulation channels and m=12 output connectors, k·(2 n -1) second transistors T2 are connected to m=12 output contacts out, that is, m·k·(2 n-1) fourth transistors T4, each of which establishes a switchable connection with the m=12 output contacts. The drain terminals of all fourth transistors T4 are connected in an orderly manner to an electrical drain, which is connected to one of the m=12 output channels. To ensure the high voltage protection against external power surges mentioned above, a high voltage transistor T is arranged along each individual electrical drain. HV , that is, each switching device I or II only needs m = 12 high-voltage transistors T HV This protects all other transistors from power surges. HV In comparison, the other transistors can be much smaller in size, so that the entire switching device can be designed in a miniaturized manner.

[0053] Reference Signs List

[0054] T1, T2, T3, T4 first, second, third and fourth transistors

[0055] T1*, T2*, T3*, T4* first, second, third and fourth transistors

[0056] in input contact

[0057] out output contact

[0058] OPA Operational Amplifier

[0059] V DD Supply voltage

[0060] V in Input potential

[0061] m Number of output contacts

[0062] k is the number of stimulation channels

[0063] n-bit DAC

[0064] T hc The second transistor

[0065] T HV High-voltage transistors

[0066] S hc switch

[0067] S en switch

[0068] A Output of the operational amplifier

[0069] CM monitoring switching component

[0070] K Comparator

[0071] Ke1 comparator input

[0072] Ke2 comparator input

[0073] Ka comparator output

[0074] S signal

Claims

1. An electrical switching device for generating a current-controlled electrical signal in a controlled cascode current mirror manner to achieve functional in vivo stimulation, comprising first, second, third and fourth transistors (T1, T2, T3, T4), each transistor having associated source, drain and gate terminals, wherein: In order to form a current mirror, the gate terminals of the first and second transistors (T1, T2) are connected to each other, wherein the third and first transistors (T3, T1) are connected in an input cascode structure, wherein the drain terminal of the third transistor (T3) is connected to the gate terminals of the first and second transistors (T1, T2), the source terminal of the third transistor (T3) is connected to the drain terminal of the first transistor (T1), and the gate terminal of the third transistor (T3) is connected to the output terminal (A) of an operational amplifier (OPA) having at least two input terminals, wherein one input terminal (+) of the operational amplifier (OPA) is connected to the drain terminal of the second transistor (T2), and the operational amplifier (OPA) has a gate terminal connected to the output terminal (A) of the second transistor (T2). The other input terminal (-) of the amplifier (OPA) is connected to the source terminal of the third transistor and the drain terminal of the first transistor (T1), the source terminal of the third transistor and the drain terminal of the first transistor (T1) are at the same potential (Va), and the second and fourth transistors (T2, T4) are connected in an output cascode structure in such a way that the source terminal of the fourth transistor (T4) is connected to the drain terminal of the second transistor (T2), and the drain terminal of the fourth transistor (T4) is connected to an output contact (out) associated with the electrical switching device, at which a voltage potential (V) associated with the current control electrical signal can be obtained. out ), It is characterized in that the gate terminal of the fourth transistor (T4) is connected in a switchable manner to at least one constant prescribable voltage potential.

2. The electrical switching device according to claim 1, It is characterized by: The constant prescribable voltage potential on the gate terminal of the fourth transistor (T4) is derived from an external supply voltage source (V DD ), or corresponds to the voltage potential (VSS) at the source terminals of the first and second transistors (T1, T2), respectively.

3. The electrical switching device according to claim 1 or 2, It is characterized by: A high voltage protection transistor (T HV ), the high voltage protection transistor (T HV ) is connected in series with the source-drain section of the fourth transistor (T4), wherein, With the high voltage protection transistor (T HV ), the fourth transistor (T4) is in the form of a low-voltage transistor.

4. The electrical switching device according to claim 3, It is characterized by: The low voltage transistor (T4) is designed for a maximum drain voltage of ±2V, and the high voltage transistor (T HV ) are designed for drain voltages up to ±18V.

5. The electrical switching device according to claim 4, It is characterized by: The first, second and third transistors are all designed as low voltage transistors.

6. The electrical switching device according to any one of claims 1 to 5, It is characterized by: The current mirror formed by the first and second transistors (T1, T2) is constructed as an n-bit digital-to-analog converter and has 2 n - 1 second transistor (T2), Among them, the 2 n -1 second transistor (T2) drain terminals are connected to 2 n - a source terminal connection of one of a fourth transistor (T4), the drain terminal of which is respectively connected or connectable to an output contact (out) of the electrical switching device.

7. The electrical switching device according to any one of claims 1 to 6, characterized in that: The output contact portion (out) is connected to the drain terminal of another fourth transistor (T4*), which is part of another electrical switching device (II), and the other electrical switching device (II) is the same as the first electrical switching device (I) according to any one of claims 1 to 6, and wherein the other electrical switching device (II) is capable of generating a current control electrical signal that is opposite to the current control electrical signal of the first electrical switching device (I).

8. An electrical switching device having a plurality of k stimulation channels, each stimulation channel carrying a current-controlled electrical signal for performing functional in vivo stimulation, the electrical switching device comprising k electrical switching devices according to any one of claims 1 to 7, characterized in that: The drain terminal of each fourth transistor (T4) is connected to m output contacts (out) via the switching matrix.

9. The electrical switching device according to claim 8, It is characterized by: In the switching matrix, m output contacts (out) are connected via high voltage transistors (T HV ) is connected to the drain connection of the corresponding fourth transistor (T4).

10. The electrical switching device according to any one of claims 1 to 9, characterized in that: The electrical switching device is provided with a monitoring switching component which generates a signal by detecting only an internal switching potential of the electrical switching device when the electrical switching device is in a non-permitted operating state.

11. The electrical switching device according to claim 10, It is characterized by: The monitoring switching component is in the form of a comparator having two comparator inputs and a comparator output at which a signal can be acquired, and wherein: The potential to the gate terminals of the first and second transistors (T1, T2) is applied to one of the two comparator inputs, while the potential at the output (A) of the operational amplifier (OPA) is applied to the other of the two comparator inputs.

12. The electrical switching device according to any one of claims 1 to 11, characterized in that: The gate terminals of the first and second transistors (T1, T2) are connected to each other and to the input potential (V in ).

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