Image sensor for event detection

Abstract

An image sensor (80) includes a pixel array (10) having pixel circuits (100), where each pixel circuit (100) outputs a request signal REQ in response to a predefined illumination change. Each pixel circuit (100) includes a floating node (121) configured to temporarily store a charge that varies with an illumination condition. Each pixel circuit (100) includes a reset switch (126) to set the floating node (121) to a predefined initial potential in response to a reset ramp signal REFR. The ramp signal circuit (20) outputs a reset ramp signal REFR for at least a first group of pixel circuits (100).

Description

[0001] The present disclosure relates to image sensors and solid-state imaging devices. More particularly, the present disclosure relates to the field of event detection sensors that respond to changes in light intensity, such as dynamic vision sensors (DVS) and event-based vision sensors (EVS) with continuous asynchronous detection of events. Background Art

[0002] Event-detecting image sensors (such as DVS and EVS) only transmit information about the locations of changes in the imaged scene. Unlike image sensors that transmit large amounts of image information per frame, information about pixels that do not change can be omitted, resulting in a type of intra-pixel data compression. Intra-pixel data compression removes data redundancy and promotes high temporal resolution, low latency, low power consumption, high dynamic range, and minimal motion blur.

[0003] Each DVS or EVS pixel temporarily stores an event indicating an increase or decrease in detected light intensity compared to the previous readout until the next readout of that pixel. Each readout of a pixel clears the event.

[0004] In an image sensor for synchronous event detection, a readout circuit reads out the pixel array row by row.

[0005] In an image sensor designed for continuous asynchronous event detection, each pixel that detects an event indicates the event by outputting a request signal to the readout circuit. In the readout circuit, the request signal triggers the compilation of event information. The event information includes the pixel address, which identifies the pixel's location in the pixel array, the sign of the light intensity change, and a timestamp. The readout circuit passes the event information to the image processor and confirms to the pixel that it has received the event. Upon receiving the confirmation, the pixel deletes the event.

[0006] The clearing event typically includes an auto-zeroing process ("auto-zeroing process", "auto-zeroing") that resets the voltage in the input path of the comparator stage to an initial value. Summary of the Invention

[0007] During the duration of the auto-zero process, the pixel cannot process another event. Therefore, the auto-zero process defines a dead time, during which a previously read pixel is blocked before it can detect the next event. The dead time is sensitive to manufacturing-related variations between pixels in the pixel array and is therefore pixel-specific.

[0008] The present technology has been made in view of this situation, and aims to improve the sensing performance of an image sensor for asynchronous event detection.

[0009] In this regard, the present disclosure relates to an image sensor having a pixel array including pixel circuits. Each pixel circuit is configured to output a request signal in response to a predefined change in illumination. Each pixel circuit includes a floating node configured to temporarily store charge that varies with illumination conditions; and a reset switch configured to set the potential of the floating node to a predefined initial potential in response to a reset ramp signal. The image sensor also includes a ramp signal circuit configured to output a reset ramp signal for at least a first group of the pixel circuits. The first group includes more than one pixel circuit.

[0010] The ramp signal circuit is shared by at least one group of pixel circuits and can be implemented in the peripheral portion of the image sensor and / or in the signal processing layer. The ramp signal circuit can be implemented outside the pixel array and thus has fewer area constraints. Compared to a case where each pixel circuit includes its own ramp signal circuit, dead time variation between pixel circuits receiving reset ramp signals from multiple ramp signal circuits is smaller.

[0011] For asynchronous image sensors with separate ramp signal circuits for each pixel circuit, the dead time is typically extended to such an extent that the impact of manufacturing-related variations between individual pixels on the response to the auto-zero process is reduced. The dead time can be as high as hundreds of microseconds, and each pixel circuit requires a bias source and appropriately sized capacitors to generate the reset ramp signal. In this regard, the asynchronous image sensor with a shared ramp signal circuit according to this embodiment allows for shorter dead time and exhibits less dead time variation. This can increase temporal resolution and, therefore, improve sensing performance.

[0012] The described embodiments and further advantages will be best understood by referring to the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram illustrating a configuration example of an imaging apparatus as an electronic device according to an embodiment, the imaging apparatus including a solid-state imaging device having an image sensor.

[0014] Figure 2 is a simplified block diagram showing a configuration example of a solid-state imaging device having an image sensor for discontinuous asynchronous readout and sharing a reset ramp signal according to an embodiment.

[0015] Figure 3 is a schematic diagram illustrating an embodiment in which a solid-state imaging device has a two-layer structure in a stacked CIS configuration.

[0016] Figure 4is a simplified block diagram illustrating an example configuration of a group of pixels sharing the same reset ramp signal according to an embodiment.

[0017] Figure 5 is a simplified block diagram showing a configuration example of a pixel circuit according to an embodiment.

[0018] Figure 6 is a simplified block diagram illustrating a configuration example of an image sensor related to a global reset ramp signal according to an embodiment.

[0019] Figure 7 is a timing diagram for illustrating a method of operating an image sensor using a global reset ramp signal according to an embodiment.

[0020] Figure 8 is a simplified block diagram illustrating a configuration example of a pixel circuit related to a global reset ramp signal according to an embodiment.

[0021] Figure 9 is a simplified block diagram showing a configuration example of a pixel circuit having a latch that generates a pixel internal control signal to process a global reset ramp signal according to an embodiment.

[0022] Figure 10 is a state diagram for illustrating a method of operating an image sensor using a global reset ramp signal according to an embodiment.

[0023] Figure 11 is a simplified block diagram illustrating a configuration example of an image sensor using a row reset ramp signal according to an embodiment.

[0024] Figure 12 is a simplified block diagram illustrating a configuration example of a pixel circuit related to a row reset ramp signal according to an embodiment.

[0025] Figure 13 is a simplified block diagram illustrating a configuration example of a pixel circuit that processes a row reset ramp signal using a reset latch signal according to an embodiment.

[0026] Figure 14 is a timing chart for illustrating a method of operating an image sensor using a row reset ramp signal.

[0027] Figure 15 is a state diagram for illustrating a method of operating an image sensor using a row reset ramp signal according to an embodiment.

[0028] Figure 16 is a circuit diagram of a radiation sensitive circuit in a pixel circuit of an image sensor according to an embodiment.

[0029] Figure 17is a circuit diagram of a capacitive amplifier circuit and a pixel comparator circuit in a pixel circuit of an image sensor according to an embodiment.

[0030] Figure 18 is a circuit diagram of an auto-zero enabling switch in a pixel circuit of an image sensor according to an embodiment.

[0031] Figure 19 is a simplified block diagram illustrating a row arbiter interface associated with a row reset ramp signal according to an embodiment.

[0032] Figure 20 is used to illustrate the operation according to one embodiment Figure 19 Timing diagram for the methods in the row arbiter interface.

[0033] Figure 21 is used to illustrate the operation according to one embodiment Figure 19 State diagram for the methods in the row arbitrator interface.

[0034] Figure 22 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0035] Figure 23 It is an auxiliary explanation Figure 22 A diagram showing an example of installation positions of a vehicle exterior information detection portion and an imaging portion of a vehicle control system. DETAILED DESCRIPTION

[0036] The following drawings will be used to describe in detail embodiments of the technology for implementing the present disclosure. The technology of the present disclosure is not limited to the described embodiments, and the various numerical values ​​and the like in the embodiments are merely illustrative. The same elements or elements having the same functions are represented by the same reference numerals. Repeated descriptions are omitted.

[0037] The connected electronic components can be electrically connected via a direct and permanent low-resistance connection (e.g., via a conductive wire). The terms "electrically connected" and "signal connected" may also include connections through other provided electronic components suitable for permanent and / or temporary signal transmission and / or energy transmission. For example, electronic components can be electrically connected or signal connected via resistors, capacitors, and electronic switches (such as transistors or transistor circuits, e.g., MOSFETs, transmission gates, and others).

[0038] The load path of a transistor is the controlled path of the transistor. For example, a voltage applied to the gate of a field effect transistor (FET) controls the flow of current through the load path between the source and drain of the FET through the field effect.

[0039] exist Figure 1, the imaging apparatus 1 includes an optical system 91, a solid-state imaging device 90, a storage unit 92, and a control unit 93. The optical system 91 includes one or more lenses and various mechanisms such as an autofocus mechanism and an aperture mechanism, and guides light from a subject to a light receiving surface of the solid-state imaging device 90.

[0040] Solid-state imaging device 90 includes an image sensor having a plurality of pixel circuits. Each pixel circuit includes a radiation-sensitive element that converts incident radiation into an electrical signal through photoelectric conversion and outputs the electrical signal. Solid-state imaging device 90 also includes a signal processing unit that performs predetermined signal processing on the electrical signal output from the pixel circuit and outputs image data based on the electrical signal.

[0041] The storage unit 92 stores the image data output from the solid-state imaging device 90 in a storage medium. The storage medium may include a volatile storage medium and / or a non-volatile storage medium. The non-volatile storage medium may be or include a flash memory or a hard disk drive. The non-volatile storage medium may be or include a dynamic random access memory (DRAM).

[0042] The control unit 93 controls the solid-state imaging device 90 so that the solid-state imaging device 90 performs an imaging operation. The imaging operation includes capturing an image of a subject or a scene and outputting image data including image information about the subject or the scene.

[0043] Figure 2 1 is a block diagram showing a configuration of an example of a solid-state imaging device 90 having an image sensor 80 applicable to an embodiment. The solid-state imaging device 90 includes the image sensor 80 and a signal processing unit 60. The image sensor 80 includes a pixel array 10, a ramp signal circuit 20, a row arbiter 30, a column readout circuit 40, and a sensor control circuit 50.

[0044] In the pixel array 10, a plurality of pixel circuits 100 are arranged in a two-dimensional matrix into pixel rows and pixel columns. For simplicity, the pixel circuits 100 belonging to the same pixel row are arranged along Figure 2 The pixel circuits 100 belonging to the same pixel column are arranged along the horizontal line in Figure 2 The vertical line arrangement in .

[0045] Each pixel circuit 100 includes a radiation-sensitive circuit, an event detection circuit, and a pixel logic circuit. The radiation-sensitive circuit outputs a voltage corresponding to the intensity of the received radiation. The event detection circuit detects an event based on the magnitude of the change in the voltage received from the radiation-sensitive circuit. The event detection circuit can be reset to an initial state by temporarily turning on a reset switch. The pixel logic circuit controls the output of event data from the pixel circuit 100 and the self-zeroing of the event detection circuit.

[0046] The event data may indicate that the intensity of the received radiation has decreased by more than a certain value compared to the previous event readout (an "OFF event"). Alternatively, the event data may indicate that the intensity of the received radiation has increased by more than a certain magnitude compared to the magnitude at the previous event readout (an "ON event"). The event data is transmitted on the event data bus 41.

[0047] The control bus 31 connects the pixel circuits 100 to the row arbiter 30. Each control bus 31 connects a group of pixel circuits 100 to the row arbiter 30. Each control bus 31 may include a request line for transmitting a request signal from the pixel circuits 100 of the pixel group to the row arbiter 30. The control bus 31 may include an answer line for transmitting a group selection signal from the row arbiter 30 to the pixel circuits 100 of the pixel group.

[0048] For each pixel circuit 100 that detects an event, the pixel logic circuit of the pixel circuit 100 concerned outputs a request to the row arbiter 30 via the control bus 31. To transmit a request, a request signal transmitted on the request signal line has an active level.

[0049] The row arbiter 30 performs arbitration based on pending valid requests output from the pixel circuits 100 of the pixel array 10. The row arbiter 30 selects a request received from a specific pixel group and acknowledges the request by outputting an acknowledgement on the control bus 31, and then transmits the corresponding row address to the column readout circuit 40. To transmit the acknowledgement, the group select signal transmitted on the response signal line has an active level.

[0050] In response to the acknowledgement, all pixel circuits 100 in which an event has been detected apply event data on respective event data buses 41. Each event data bus may be connected to some or all pixel circuits 100 of the same pixel column, or to all pixel circuits 100 of more than one pixel column.

[0051] The event data bus 41 may include a shared data line for transmitting ON events and OFF events using different signal levels or in a time-division multiplexing scheme. In the illustrated embodiment, the event data bus 41 includes a first data line 42 for transmitting ON events and a second data line 43 for transmitting OFF events. To transmit an ON event, the ON event signal transmitted on the first data line 42 has an active level. To transmit an OFF event, the OFF event signal transmitted on the second data line 43 has an active level.

[0052] The column readout circuit 40 receives event data from all pixel circuits 100 of the selected pixel group via the event data bus 41, along with the row address of the selected pixel group from which the received event data originates. Based on the row address and identifier of the event data bus 41 that transmits the event data, the column readout circuit 40 compiles a digital address event representation (AER) for each event. The AER includes the row address, a column address derived from the identifier of the event data bus that transmits the event, the event data, and, if applicable, a timestamp. The column readout circuit 40 outputs the AER to the signal processing unit 60.

[0053] The ramp signal circuit 20 outputs at least one reset ramp signal REFR and transmits the reset ramp signal REFR to a group of pixel circuits 100 via a ramp control bus, for example, to some or all pixel circuits 100 in a pixel row, or to pixel circuits 100 in more than one pixel row. For each pixel circuit 100, the pixel logic circuit controls the resetting of the event detection circuit by passing the reset ramp signal REFR to the gate of the reset switch only when a predefined condition is met. The ramp control bus 21 includes at least a ramp signal line for transmitting the reset ramp signal. The ramp control bus 21 may include other lines for transmitting other control signals from the ramp signal circuit 20 to the pixel circuit 100.

[0054] The sensor control circuit 50 may control the timing of the ramp signal circuit 20 and / or the communication between the column readout circuit 40 and the signal processing unit 60 .

[0055] The signal processing unit 60 receives the AER. The signal processing unit 60 may perform signal processing such as image recognition processing based on the received AER. The signal processing unit 60 may output the processed image data, for example, to Figure 1 The data is output to the storage unit 92 in the memory and / or via a wired or wireless electronic interface.

[0056] By providing the reset ramp signal REFR from a single source external to the pixel array 10 to the electrically connected plurality of pixel circuits 100 for output requests, the image sensor 80 provides asynchronous readout that can operate with a relatively short dead time.

[0057] As reference Figure 2 The solid-state imaging device 90 described may be provided as a stacked contact image sensor (CIS) formed by stacking a plurality of semiconductor chips, for example. As an example, the solid-state imaging device 90 may be formed of a two-layer structure in which semiconductor chips are stacked in two layers.

[0058] Figure 3 It shows that Figure 21 is a diagram showing an example of a solid-state imaging device 90 formed of a stacked CIS having a two-layer structure having a radiation receiving chip 910 and a processing chip 920. The radiation receiving chip 910 includes at least a radiation sensitive element, such as a complete radiation sensitive circuit, or a complete radiation sensitive circuit and other elements of a pixel circuit. The processing chip 920 includes other elements of the pixel circuit 100, such as an event detection circuit and a pixel logic circuit. Figure 3 As shown on the right side of , the solid-state imaging device 90 is formed as a sensor by bonding a first-layer semiconductor chip and a second-layer semiconductor chip while electrically contacting contact pads on the radiation receiving chip 910 with corresponding contact pads on the processing chip 920.

[0059] Figure 4 An image sensor including a pixel array 10 and a ramp signal circuit 20 is shown. Pixel array 10 includes pixel circuits 100. Each pixel circuit 100 outputs a request signal REQ in response to a predefined change in illumination. Each pixel circuit 100 includes a floating node 121 configured to temporarily store charge that varies with illumination conditions, and a reset switch 126 configured to set the floating node 121 to a predefined initial potential in response to a reset ramp signal REFR. The ramp signal circuit 20 outputs a reset ramp signal REFR for at least a first group of pixel circuits 100.

[0060] The pixel circuit 100 outputs a request signal REQ on the request signal line 32. The generated voltage of the floating node 121 is related to the illuminance intensity variation. The illuminance variation is the difference in light intensity between the current time and the previous time.

[0061] The amount of charge stored on the floating node 121 corresponds to a change in brightness detected by the pixel circuit 100 between the currently detected brightness and the brightness evaluated at a previous point in time (e.g., during a previous readout of the pixel circuit 100). The predefined brightness change corresponds to a predefined amount of charge stored on the floating node 121 and a predefined voltage between the floating node 121 and the reference potential VSS. The reset switch 126 switches the floating node 121 to a predefined initial potential during the auto-zero period. For example, the reset switch 126 can temporarily connect the floating node 121 to a predefined potential (e.g., to the reference potential VSS of the pixel array 10), or can temporarily short-circuit a feedback element of an amplifier circuit whose input is connected to the floating node 121.

[0062] Hereinafter, for ease of reading, the process of initializing the potential at the floating node 121 will be referred to as the auto-zero process. The auto-zero process includes partially or completely discharging the floating node 121. When the potential at the floating node 121 reaches the initial potential, the groove switch 126 is turned off. Turning off the groove switch 126 too quickly may cause a large amount of charge to be injected into the floating node 121.

[0063] Applying a relatively slowly varying reset ramp signal to the gate of the notch switch 126 to turn off the notch switch 126 avoids turning off the notch switch 126 too quickly and mitigates the resulting problems.

[0064] If the notch switch 126 is an n-channel FET controlled by a reset ramp signal REFR that varies between an inactive low level and an active high level, the notch switch 126 is turned on with a leading edge in the notch ramp signal REFR and is turned off with a trailing edge in the notch ramp signal REFR. The trailing edge of the reset ramp signal REFR is significantly flatter (less steep) and falls or rises at a significantly slower rate, for example, at least an order of magnitude slower than other signals that control or are output by the pixel circuit 100. For example, the trailing edge of the reset ramp signal REFR can be significantly flatter and falls or rises at a significantly slower rate, for example, at least an order of magnitude slower than the rising edge of the reset ramp signal REFR. For example, the trailing edge of the reset ramp signal REFR can take several microseconds, corresponding to a slope in the range of 0.1 V / μs to 1 V / μs. The leading edge of the reset ramp signal REFR and / or other control signals typically take 100 ns or less to transition. The slope of the trailing edge can be fixed. Alternatively, the slope may be programmable. For example, the ramp signal circuit 20 includes a register whose output affects the slope of the ramp, wherein the register may be programmed by Figure 2 The sensor control circuit 50 and / or Figure 1 The control unit 93 and / or the sensor control circuit 50 may change the register settings in response to user settings, changes in sensor internal conditions and / or illumination conditions.

[0065] The ramp signal circuit 20 generates a reset ramp signal REFR having a gentle trailing edge and applies the reset ramp signal REFR to the pixel array 10. The output of the ramp signal circuit 20 is electrically connected to each pixel circuit 100 in a first group of pixel circuits 100 in the pixel array 10. The first group of pixel circuits 100 may include some or all of the pixel circuits 100 in one pixel row, some or all of the pixel circuits 100 in a plurality of adjacent pixel rows, some or all of the pixel circuits 100 in a plurality of non-adjacent pixel rows, or all of the pixel circuits 100 in the pixel array 10.

[0066] There will be no mismatch between the pixel circuits 100 in the same group regarding the length of the self-zero period. Otherwise, such mismatch must be addressed by an appropriate safety margin for the length of the self-zero period to ensure that each pixel circuit 100 is correctly reset after each event. With these embodiments, such a safety margin becomes obsolete or can be significantly reduced. The dead time during which the pixel circuit does not detect illumination changes can be correspondingly reduced.

[0067] The pixel circuit 100 can be configured such that for each pixel circuit 100, the reset ramp signal REFR is passed to the reset switch 126 only within a time period after a predefined illumination change in the pixel circuit 100 is detected and before the initial potential at the setting floating node 121 ends (for example, from the detection of the predefined illumination change until the initial potential at the setting floating node 121 ends).

[0068] The pixel circuit 100 is reset only if the pixel circuit 100 has detected and output an event since the last readout. For example, the reset switch 126 may be or include a FET. The analog switch may pass the reset ramp signal REFR to the gate of the reset switch 126 only during the period from detecting a predefined illumination change to setting the initial potential at the floating node 121.

[0069] More specifically, each pixel circuit 100 may include an auto-zero enable switch 150 for temporarily disconnecting the gate of the reset switch 126 from the reset ramp signal REFR. The auto-zero signal AZ controls the auto-zero enable switch 150. The auto-zero signal AZ may be a binary signal that varies between an active level and an inactive level. The active level turns on the auto-zero enable switch 150. The inactive level turns off the auto-zero enable switch 150. The auto-zero signal AZ may image the internal state of the pixel circuit 100 and allow a conditional auto-zero process.

[0070] During the period from when the pixel circuit 100 outputs an event to when the self-zero period ends, the self-zero signal AZ may be active and the self-zero enable switch 150 may be on. During the remaining time, the self-zero signal AZ may be inactive and the self-zero enable switch 150 may be off.

[0071] Figure 5 Shown for Figure 2 A block diagram of a pixel circuit 100 of an asynchronous image sensor 80 is shown.

[0072] The radiation-sensing circuit 110 outputs a pixel voltage signal VPR proportional to the intensity of incident light. The event detection circuit includes a capacitive amplifier circuit 120 and a pixel comparator circuit 130. Capacitive amplifier circuit 120 generates an amplified voltage signal VBF. Pixel comparator circuit 130 compares amplified voltage signal VBF with an upper reference voltage VTH and a lower reference voltage VTL. Pixel logic circuit 140 outputs pixel event signals (ON and OFF) based on the comparison results of amplified voltage signal VBF with upper reference voltage VTH and lower reference voltage VTL.

[0073] The radiation sensitive circuit 110 includes a photoelectric conversion element 111 and outputs a pixel voltage signal VPR. The voltage level of the pixel voltage signal VPR depends on the photodetector current generated by the photoelectric conversion element 111.

[0074] More specifically, radiation-sensitive circuit 110 includes a photoelectric conversion element 111 and a photoreceptor circuit 112. Photoelectric conversion element 111 may include or be formed of a photodiode, which converts electromagnetic radiation incident on a detection surface into a photodetector current via the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation, and / or ultraviolet radiation. The amplitude of the photodetector current corresponds to the intensity of the incident electromagnetic radiation, wherein, within a range of intensity of interest, the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0075] The photoreceptor circuit 112 converts the photodetector current into a pixel voltage signal VPR. The voltage of the pixel voltage signal VPR is related to the photodetector current, wherein, within a voltage range of interest, the voltage amplitude of the current photoreceptor signal VPR increases as the photodetector current increases. For example, the voltage of the pixel voltage signal VPR increases logarithmically with the photodetector current.

[0076] The capacitive amplifier circuit 120 obtains the floating voltage VSF by subtracting the previously evaluated photoreceptor voltage VPT from the current pixel voltage signal VPR. The amplified voltage signal VBF represents the amplified difference between the previously evaluated photoreceptor voltage VPT and the current voltage of the pixel voltage signal VPR.

[0077] The pixel comparator circuit 130 receives the amplified voltage signal VBF from the capacitive amplifier circuit 120 and compares the amplified voltage signal VBF with an upper reference voltage VTH and a lower reference voltage VTL.

[0078] In the illustrated embodiment, the pixel comparator circuit 130 includes two comparators 131 , 132 for simultaneously comparing the output signal of the amplifier circuit 123 with an upper voltage threshold VTH and a lower voltage threshold VTL.

[0079] The first comparator 131 outputs a first comparator output signal VC1 that varies between an active level and an inactive level. The first comparator 131 outputs an active level (a valid first comparator output signal) only when the output signal of the capacitor amplifier circuit 120 exceeds the upper voltage threshold VTH. The second comparator 132 outputs a binary second comparator output signal VC2 that varies between an active level and an inactive level. The second comparator 132 outputs an active level (a valid first comparator output signal) only when the output signal of the capacitor amplifier circuit 120 falls below the lower voltage threshold VTL.

[0080] According to another example, the pixel comparator circuit 130 includes a three-stage comparator that outputs a combined comparator output signal that varies between two different active and inactive levels. The three-stage comparator outputs a first active level when the amplified voltage signal VBF received from the capacitor amplifier circuit 120 exceeds an upper voltage threshold VTH, outputs a second active level when the output signal of the capacitor amplifier circuit 120 falls below a lower voltage threshold VTL, and otherwise outputs an inactive level.

[0081] According to another example, the pixel comparator circuit 130 includes a single comparator that sequentially compares the amplified voltage signal VBF with an upper voltage threshold VTH and a lower voltage threshold VTL. The single comparator outputs a valid level in a first phase when the amplified voltage signal VBF exceeds the upper voltage threshold VTH, outputs a valid level in a subsequent second phase when the amplified voltage signal VBF drops below the lower voltage threshold VTL, and otherwise outputs a non-valid level.

[0082] The pixel logic circuit 140 receives the comparator output signal from the pixel comparator circuit 130 and receives the control signal from outside the pixel array 10. Based on the comparator output signal, the pixel logic circuit 140 generates and outputs a control signal for the pixel array 10 to pass. Figure 2 The row arbiter 30 in the pixel logic circuit 140 registers the request signal REQ of the event readout. The pixel logic circuit 140 outputs the request signal REQ to the request signal line through the request signal output RQO. The request signal output RQO can be an open collector output or any other output type that allows multiple pixel circuits 100 to be connected to the same request signal line.

[0083] The pixel logic circuit 140 generates event data signals EVP, EVN based on the comparator output signal and transmits the event data signals EVP, EVN to the CMOS circuit in response to a valid acknowledge signal ACK received through the acknowledge input ACI. Figure 2Column readout circuit in. Further based on the comparator output signal, the pixel logic circuit 140 generates a valid signal AZ in response to the received acknowledge signal ACK and outputs a valid auto-zero signal to the auto-zero enable switch 150, as long as the pixel circuit 100 has detected an event since the last readout. The valid auto-zero signal turns on the auto-zero enable switch 150 during the auto-zero period, so that the voltage at the floating node 121 can be reset to the initial voltage using the next valid ramp signal.

[0084] Figure 6 An embodiment of an image sensor 80 is shown having use of a global reset ramp signal REFR.

[0085] The row arbiter 30 receives a group request signal REQ from any pixel circuit 100 in the first group of pixel circuits 100. <x>, the group selection signal SEL <x>Output to the first group.

[0086] Each group of pixel circuits 100 may include some or all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. In the embodiment shown, each pixel group includes all pixel circuits 100 of the same pixel row.

[0087] In response to the group selection signal SEL <x>, each pixel circuit 100 in the selected group of pixel circuits 100 that has detected an event outputs event data and initiates self-zeroing.

[0088] The ramp signal circuit 20 is configured to output a reset ramp signal REFR for each pixel circuit 100 of the pixel array 10 .

[0089] The ramp signal circuit 20 outputs a single reset ramp signal REFR. Each pixel circuit 100 receives the same reset ramp signal REFR or a signal derived from the same reset ramp signal REFR. The ramp signal circuit 20 may include a buffer (not shown) to distribute the reset ramp signal REFR across the pixel array 10. For example, the ramp signal circuit 20 may include a buffer circuit for every n pixel rows, such as one row buffer circuit for each single pixel row. All row buffer circuits receive the same original reset ramp signal, and each pixel circuit 100 in a pixel row receives a buffered reset ramp signal from the row buffer circuit.

[0090] The ramp signal circuit 20 transmits the same reset ramp signal REFR to all pixel circuits 100 of the pixel array 10 so that mismatch regarding the length of the auto-zero period does not occur between the pixel circuits of the pixel array 10 .

[0091] The ramp signal circuit 20 may be configured to output the reset ramp signal REFR at regular time intervals.

[0092] The reset ramp signal REFR is a periodic signal. The regular time intervals have the same length. The ramp signal circuit 20 can operate asynchronously with respect to the control signals output by the pixel array 10 and the row arbiter 30. Alternatively, the ramp signal circuit 20 and the row arbiter 30 can share a common clock signal or a common source for the control signals transmitted to the pixel circuit 100 on the control bus 31.

[0093] Figure 7 Two cycles of the global reset ramp signal REFR are shown. One cycle of the reset ramp signal REFR defines a self-zero interval with an interval length trmp. Each pixel circuit 100 applies the reset ramp signal REFR to Figure 6 The gate of the reset switch 126 in the reset state is connected to the reset state. In each auto-zero interval, the reset ramp signal REFR changes between a low level and a high level once, and changes between a high level and a low level once. Figure 6 The reset switch 126 in the reset ramp signal REFR is turned on and can be relatively steep. The reset ramp signal REFR can maintain the level reached for a certain time. Compared with the leading edge, the trailing edge is usually less steep and makes Figure 6 The reset switch 126 in is turned off.

[0094] In the embodiment shown, Figure 6 The reset switch 126 in FIG is an NFET (n-channel field effect transistor). The leading edge of the reset ramp signal REFR is a rising edge, and the trailing edge is a falling edge. Figure 6 If the reset switch 126 in the embodiment is a PFET (p-channel field effect transistor), the leading edge of the reset ramp signal REFR can be a falling edge, while the trailing edge is a rising edge. The reset ramp signal REFR reaches a low level and remains at a low level for the remainder of the auto-zero interval. The trailing edge changes at a significantly lower rate, for example, at least one order of magnitude slower than other signals that control the pixel circuit 100 or are output by the pixel circuit 100. For example, the trailing edge of the reset ramp signal REFR can be significantly flatter and can change at a significantly lower rate, for example, at least one order of magnitude slower than the leading edge.

[0095] In each pixel row x, the first pixel circuit 100 that detects an event sends a row request signal REQ on the request signal line 32. <x>If the request signal line 32 is connected to the pull-up structure, the effective level is low. Figure 7 In the figure, for better readability, high level indicates valid level.

[0096] Figure 6 The row arbiter 30 in the embodiment selects one of the pixel rows having a valid request for readout and sets the group selection signal SEL <x>Set to active level to trigger the readout of the selected pixel row. In this case, the group selection signal SEL <x>is a row selection signal. For each pixel row, an acknowledge signal is transmitted on the acknowledge signal line 33. In the embodiment shown, the active level is a high level. The signals on the request signal line 32 and the acknowledge signal line 33 are asynchronous with respect to the reset ramp signal REFR. All pixel circuits 100 in the selected pixel row that have detected an event are read out synchronously.

[0097] Figure 8 FIG1 shows details of a configuration example of a pixel circuit 100 for an image sensor using a global reset ramp signal REFR. The pixel circuit 100 includes a radiation sensitive circuit 110, a capacitor amplifier circuit 120, and a pixel comparator circuit 130. The pixel comparator circuit outputs pixel event signals ON and OFF, as shown in FIG1. Figure 5 described.

[0098] Each pixel circuit 100 includes a reset latch circuit 180 configured to suppress output of the request signal REQ for a period starting after information on a predefined illumination variation has been read out until the end of the next full cycle of the reset ramp signal REFR.

[0099] The reset latch circuit 180 is as shown in FIG. Figure 4 and Figure 5 A portion of the pixel logic circuit 140 is depicted. A cycle of the reset ramp signal REFR includes a transition from an inactive level to an active level and a subsequent transition from an active level to an inactive level. The next full cycle may be the next full cycle in which only a small number of pixel rows detect an event per auto-zero interval. The next full cycle may be another cycle in which a large number of pixel rows detect an event per auto-zero interval.

[0100] That is, after detecting an event, the pixel circuit 100 requests a readout. Upon receiving confirmation from the row arbiter, the pixel circuit 100 outputs an ON signal or an OFF signal on the event data bus 41, and then waits until the floating node 121 is reset to the initial potential. For this purpose, the pixel circuit 100 applies the reset ramp signal REFR to the gate of the reset switch 126 within the next full cycle of the reset ramp signal REFR or within another subsequent cycle of the reset ramp signal REFR. The waiting time ends with the end of the cycle of the reset ramp signal REFR. Starting from the end of the waiting time, the pixel circuit 100 can request the next readout. In order to temporarily suppress the output request signal, the reset latch circuit 180 can receive other control signals via the control bus 31 and / or via the ramp control bus 21.

[0101] The reset latch circuit 180 may also be configured to inhibit further output of event data for a period starting after the information about the predefined illumination change has been read out and ending at the end of the next full cycle of the reset ramp signal REFR. The next full cycle may be the next full cycle or another cycle in the following cycles.

[0102] For example, the first output of the pixel comparator circuit 130 will indicate an ON event and control the ON signal output of the first output switch 191. The controlled path of the first output switch 191 is located between the first data signal line 42 and the common data node. The second output of the pixel comparator circuit 130 will indicate an OFF event and control the OFF signal output of the second output switch 192. The controlled path of the second output switch 192 is located between the second data signal line 43 and the common data node. The row select signal SEL <x>The third output switch 193 is controlled to have a controlled path between the common data node and the reference potential VSS. The reset latch circuit 180 can temporarily suppress the output of event data by interrupting the connection between the third output switch 193 and the reference potential VSS.

[0103] Specifically, the reset latch circuit 180 may be configured to output a read completion signal RDDN indicating that the pixel circuit 100 has detected a predefined illumination change and information about the predefined change has been read out from the pixel circuit 100 .

[0104] The read completion signal RDDN may be used to suppress the output of the request signal REQ and / or generate other signals indicating an auto-zero period.

[0105] Additionally, the reset latch circuit 180 may be configured to output an auto-zero signal AZ that indicates the start and end of a complete cycle of the reset ramp signal REFR after a predefined illumination change of the pixel circuit 100 is detected.

[0106] The start and end of the active auto-zero signal AZ define an auto-zero interval. From the start of the auto-zero interval until the end of the auto-zero interval, the reset ramp signal REFR is applied to the gate of the reset switch 126. The auto-zero signal AZ can be used to suppress the output of the request signal during the auto-zero interval and / or suppress the output of the event data ON, OFF during the auto-zero interval. In other words, once the pixel circuit 100 has detected an event by detecting a predefined illumination change and has been read out, the read completion signal RDDN and the auto-zero signal AZ can be used to prevent the pixel circuit 100 from outputting a valid request signal during a period starting from the pixel readout and ending at the end of the auto-zero interval for auto-zeroing the pixel circuit 100.

[0107] exist Figure 9 In the embodiment of the present invention, the reset latch circuit 180 receives the latch signal LAT and the reset latch signal RLAT to generate the read completion signal RDDN and the auto-zero signal AZ. The active level of the reset latch signal RLAT follows the active level of the latch signal LAT. The leading edge of the reset ramp signal REFR follows the active reset latch signal RLAT. The latch signal LAT and the reset latch signal RLAT can be global signals that are synchronously applied to all pixel circuits 100. Alternatively, the reset latch signal RLAT can be obtained by delaying the latch signal LAT in each pixel circuit 100.

[0108] The ramp control bus 21 or the control bus 31 transmits a latch signal LAT on the latch signal line 23 and a reset latch signal RLAT on the reset latch signal line 23. The latch signal LAT and the reset latch signal RLAT are synchronized with respect to the reset ramp signal REFR.

[0109] Reference again Figure 7 , the latch signal LAT may be active between t=t0 and t=t1. Compared to the latch signal LAT, the reset latch signal RLAT becomes active slightly later, for example, between t=t1 and t=t2. The leading edge of the reset ramp signal REFR does not precede t=t2. The trailing edge begins at t=t3 and ends at t=t4. The auto-zero interval begins at t=t0 and ends at t=t0 of the next auto-zero interval.

[0110] Reference again Figure 9 , the reset latch circuit 180 generates an event signal EVT, which indicates that an ON event or an OFF event is detected. For example, the OR gate 181 can combine the ON signal and the OFF signal into the event signal EVT.

[0111] The reset latch circuit 180 includes an edge-sensitive (clock-controlled) master-slave FF (flip-flop) 182 having a set input S, a reset input R, a clock input, and a non-inverting output Q. The event signal EVT indicates a predefined increase or decrease in illumination and is applied to the set input S. The row select signal SEL <x>is applied to the clock input. At the same time, the row select signal SEL <x>This enables event data to be output on the event data lines 42, 43. At the non-inverting output, the master-slave FF 182 outputs a read completion signal RDDN. The read completion signal RDDN changes between an inactive state and an active state. The active state of the read completion signal RDDN indicates that the pixel circuit 100 has received the row select signal ACK. <x>, and the pixel circuit 100 receives the row selection signal ACK <x>The event has been detected before, and the auto-zero has not yet ended. The inverter 184 generates the inverted read completion signal XRDN by inverting the read completion signal RDDN. Alternatively, the inverted read completion signal can come from the inverted output of the master-slave FF 182.

[0112] The reset latch circuit 180 may further include a level-sensitive D-FF 183 having a data input D, a clock input, a non-inverting output Q, and / or an inverting output / Q. The level-sensitive D-FF 183 is controlled by the voltage level at the clock input. A read completion signal RDDN is applied to the data input D. A latch signal LAT is applied to the clock input. The D-FF 183 outputs an auto-zero signal AZ at its non-inverting output Q. The D-FF 183 outputs an inverted auto-zero signal XAZ at its inverting output / Q. The auto-zero signal AZ varies between an inactive level and an active level. The inverted auto-zero signal XAZ varies between an active level and an inactive level.

[0113] The rising edge of the latch signal LAT indicates the start of the auto-zero interval.Shortly after the latch signal LAT has become active, the reset latch signal RLAT may become active and may reset the master-slave FF 182.

[0114] The auto-zero signal AZ and / or the inverted auto-zero signal XAZ controls the auto-zero enable switch 150. When the auto-zero signal AZ is active and / or the inverted auto-zero signal XAZ is inactive, the auto-zero enable switch 150 passes the reset ramp signal REFR to the control electrode of the reset switch 126. The reset switch 126 may be an NFET, and the control electrode is the gate of the NFET.

[0115] The active level of the auto-zero signal AZ indicates that auto-zeroing is in progress for the pixel circuit 100 that has detected an event and has been read out.

[0116] The reset latch circuit 180 further includes a switch circuit 185 configured to disable the request signal REQ when the auto-zero signal AZ and / or the read completion signal RDDN are valid. For example, when at least one of the auto-zero signal AZ and the read completion signal RDDN is valid, the switch circuit 185 disables the request signal REQ from being transmitted from the pixel circuit 100 to the row arbiter.

[0117] Event signal EVT is applied to the gate of request output transistor 194. The controlled path of request output transistor 194 is located between request signal line 32 and first controllable path 185a of switch circuit 185. A pull-up resistor (not shown) terminates request signal line 32. First controllable path 185a of switch circuit 185 is electrically connected between request output transistor 194 and reference potential VSS. First controllable path 185a of switch circuit 185 can be controlled to avoid requests during auto-zeroing.

[0118] The second controllable path 185b of the switch circuit 185 can be used to avoid a second readout before auto-zeroing is complete.

[0119] exist Figure 9 In FIG. 1 , a first controllable path 185 a of the switch circuit 185 includes a first NFET 186 a and a second NFET 187 a. The load paths of the first NFET 186 a and the second NFET 187 a are electrically connected in series between the controlled path of the request output transistor 194 and the reference potential VSS. An inverted read completion signal XRDDN is applied to the gate of the first NFET 186 a and controls the first NFET 186 a. An inverted auto-zero signal XAZ is applied to the gate of the second NFET 187 a and controls the second NFET 187 a.

[0120] Both the inverted auto-zero signal XAZ and the inverted read completion signal XRDDN must be active (and both the auto-zero signal AZ and the read completion signal RDDN are inactive) to enable the output of the request signal REQ.

[0121] The second controllable path 185b of the switch circuit 185 includes a third NFET 186b and a fourth NFET 187b. The load paths of the third NFET 186b and the fourth NFET 187b are electrically connected in series between the controlled path of the third output switch 193 and the reference potential VSS. The inverted read completion signal XRDDN is applied to the gate of the third NFET 186b and controls the third NFET 186b. The inverted auto-zero signal XAZ is applied to the gate of the fourth NFET 187b and controls the fourth NFET 187b.

[0122] Both the inverted auto-zero signal XAZ and the inverted read completion signal XRDDN must be active (and both the auto-zero signal AZ and the read completion signal RDDN inactive) to enable output of event data.

[0123] Figure 10 Shown Figure 9 The state diagram of the pixel circuit 100 shown in FIG. In the idle state, the pixel circuit 100 waits for an event. When the voltage at the input of the pixel comparator circuit exceeds the upper or lower threshold, the pixel circuit applies a valid group request signal to the control bus. When the pixel circuit detects that the group select signal on the control bus has become valid, the pixel circuit applies an ON signal or an OFF signal to the event data bus. When the group select signal becomes inactive, the pixel circuit stops outputting the ON and OFF signals, sets the read completion signal RDDN to an active level, and waits for a valid latch signal. The active latch signal indicates the start of the next auto-zero interval. When the pixel circuit receives the active latch signal, the pixel circuit sets the auto-zero signal AZ to an active level, turns the reset switch on and off, and waits for a valid reset latch signal. When the pixel circuit receives the active reset latch signal, the pixel circuit sets the read completion signal RDDN to an inactive level and waits for the next active latch signal. When the pixel circuit receives the next active latch signal, the reset switch has already smoothly opened. The pixel circuit sets the auto-zero signal AZ to an inactive level and returns to the idle state.

[0124] Figure 11 1 shows an image sensor comprising a plurality of groups of pixel circuits 100, wherein the pixel circuits 100 of each group share a common group ramp signal REFR. <x>.

[0125] The row arbiter 30 receives a group request signal REQ from any pixel circuit 100 in the first group of pixel circuits 100. <x>, the group selection signal SEL <x>Output to the first group.

[0126] That is, for each group of pixel circuits 100, the row arbiter 30 may receive the group request signal REQ from any pixel circuit 100 in the group. <x>, and in response to the received group request signal REQ <x>, the row arbiter 30 sets the group selection signal SEL <x>Outputs to each pixel circuit 100 in the group involved. Each group of pixel circuits 100 may include some or all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row.

[0127] The ramp signal circuit 20 responds to the group selection signal SEL for the first group of pixel circuits 100. <x>, outputs a reset ramp signal REFR for the first group of pixel circuits 100 <x>.

[0128] The reset ramp signal REFR for the first group of pixel circuits 100 <x>is the group-specific reset ramp signal ("group reset ramp signal") REFR <x>. Group selection signal SEL <x>and group reset ramp signal REFR <x>have a fixed time relationship with each other, wherein the group selection signal SEL <x>Trigger group reset ramp signal REFR <x>.

[0129] When the pixel circuits 100 are allocated to pixel rows and pixel columns, the first group of pixel circuits 100 may be allocated to one of the pixel rows or one of the pixel columns.

[0130] Each pixel logic circuit 140 includes a reset latch circuit 180 that resets the latch circuit based on the group selection signal SEL <x>and group reset ramp signal REFR <x>To control the auto-zero process.

[0131] In the embodiment shown, each pixel group includes all pixel circuits 100 of the same pixel row. Accordingly, the group selection signal SEL <x>Named as row selection signal SEL <x>, group request signal REQ <x>Named as line request signal REQ <x>, and the group reset ramp signal REFR <x>The row reset ramp signal REFR is named <x>.

[0132] Figure 12 Shown suitable for Figure 11 The pixel circuit 100 of the image sensor has a reset latch circuit 180.

[0133] The reset latch circuit 180 outputs the auto-zero signal AZ indicating that the pixel circuit 100 has detected a predefined illuminance change, information about the predefined illuminance change has been read out, and initialization of the floating node 121 is not completed.

[0134] The auto-zero signal AZ can be used to selectively pass the reset ramp signal REFR to the reset switch 126 only when the pixel circuit 100 has detected a predefined illumination change. The reset ramp signal REFR is not passed to the reset switch 126 of such pixel circuits 100 in the same group that have not detected the predefined illumination change. The pixel circuits 100 in the same group that have not detected the predefined illumination change remain unaffected by the readout and auto-zeroing of the pixel circuits 100 that have requested event data readout.

[0135] In addition to the auto-zero signal AZ, the reset latch circuit 180 may also output an inverted auto-zero signal XAZ, which may be used to control the reset ramp signal REFR from the ramp signal line 22 to the control input of the reset switch 126 .

[0136] exist Figure 13 In FIG. 1 , the reset latch circuit 180 includes an OR gate 188 and an edge-sensitive master-slave FF 189 .

[0137] A first output of the pixel comparator circuit 130 is connected to a first input of an OR gate 188. A second output of the pixel comparator circuit 130 is connected to a second input of the OR gate 188. The OR gate 188 combines the ON signal and the OFF signal and outputs an event signal EVT. When at least one of the ON signal and the OFF signal is valid, the event signal EVT is valid.

[0138] The output of the OR gate 188 is connected to the gate of the request output transistor 194 and the set input of the master-slave FF 189. The valid event signal EVT turns on the request output transistor 194 and can set the master-slave FF 189. The response line 33 is connected to the clock input of the master-slave FF 189. With the valid row select signal SEL <x>The master-slave FF 189 captures the signal at the set input S at the leading edge of 100V. The reset latch line 24 is connected to the reset input R. The valid reset latch signal RLAT transmitted on the reset latch line 24 <x>Resets the master-slave FF 189. The non-inverting output Q outputs the auto-zero signal AZ. The inverting output / Q outputs the inverted auto-zero signal AZ.

[0139] That is, each pixel circuit 100 includes a reset latch circuit 180 that outputs an auto-zero signal AZ in response to a predefined illumination change. Each pixel circuit 100 also includes an auto-zero enable switch 150 that transmits a reset ramp signal REFR to the reset switch 126 in response to the auto-zero signal AZ. The auto-zero signal AZ can be used to control the auto-zero enable switch 150.

[0140] For example, the auto-zero enable switch 150 receives the reset ramp signal REFR and outputs the auto-zero switch signal AZSW obtained by gating the reset ramp signal REFR with the auto-zero signal AZ. The auto-zero switch signal AZSW is applied to the gate of the reset transistor 126 .

[0141] Figure 14 A timing diagram for event data readout and subsequent auto-zero interval is shown. At t=t0, one of the pixel circuits in a group of pixel circuits asserts the active group request signal REQ <x>(For simplicity, it is shown as active high level.) At t=t1, the row arbiter sets the group selection signal SEL of the group involved to <x>Set to active level. In response to the active group selection signal SEL <x>, the reset latch circuit 180 resets the group request signal REQ <x>After the event data is read out, the row arbiter switches the group selection signal SEL to the inactive level at t=t2. <x>Switches to an inactive level. At t = t2 or later, the auto-zero interval begins by setting the reset ramp signal to an active level. The reset switch turns on, and the floating node is set to an initial potential. Starting at t = t3, the reset ramp signal decreases at a relatively low rate and reaches an inactive level at t = t4.

[0142] While the leading edge of the reset ramp signal REFR can be as fast as the technology used for the image sensor allows, the slope of the trailing edge is controlled and is longer (e.g., at least an order of magnitude longer) than the minimum length given by the technology limitations. The duration of the trailing edge can be controllable by device settings.

[0143] With the group selection signal SEL <x>Compared to the leading edge of the reset ramp signal REFR, the trailing edge of the reset ramp signal REFR changes at a rate at least ten times slower.

[0144] For example, with the group selection signal SEL <x>Compared to the leading edge of the reset ramp signal REFR, the trailing edge changes at a rate at least twenty, fifty, or one hundred times slower. The slow change at the gate allows the reset switch to be turned off smoothly. At t=t4 or later, the row arbiter sets the group reset latch signal RLAT. <x>Changes to active level to reset the master-slave FF 189. When the group reset latch signal RLAT <x>When it returns to the inactive level at t=t6, the auto-zero interval ends.

[0145] Figure 15 Shown Figure 13 The state diagram of the pixel circuit 100 is shown in FIG. In the idle state, the pixel circuit 100 waits for an event. When the voltage at the input of the pixel comparator circuit exceeds the upper or lower threshold, the pixel circuit applies the valid group request signal to the control bus. When the pixel circuit detects the group select signal SEL on the control bus <x>When the group selection signal SEL is active, the pixel circuit applies an ON signal or an OFF signal to the event data bus. <x>When it becomes inactive, the pixel circuit stops outputting the ON and OFF signals, sets the auto-zero signal AZ to an active level, and waits for an active reset latch signal. The active auto-zero signal indicates the start of the auto-zero interval. When the pixel circuit receives the active reset latch signal, the reset switch has already smoothly turned off. The pixel circuit sets the auto-zero signal AZ to an inactive level and returns to the idle state.

[0146] Figure 16 There is shown a configuration example of a radiation sensitive circuit 110 including a photoelectric conversion element 111 , a multi-transistor feedback logarithmic amplifier circuit (LAC), and a source follower.

[0147] The anode of the photoelectric conversion element 111 is electrically connected to a reference potential VSS. The LAC includes a first amplifier NFET 115 and a second amplifier NFET 113 electrically connected in series between a positive power supply potential VDD and the cathode of the photoelectric conversion element 111. A pull-up PFET (p-channel FET) 117 with a constantly biased gate, a third amplifier NFET 116, and a fourth amplifier NFET 114 are electrically connected in series between the positive power supply potential VDD and the reference potential VSS. The gate of the fourth amplifier NFET 114 is connected to the cathode of the photoelectric conversion element 111. The gate of the second amplifier NFET 113 is connected to a node between the third amplifier NFET 116 and the fourth amplifier NFET 114. The gate of the third amplifier NFET 116 is connected to a node between the first amplifier NFET 115 and the second amplifier NFET 113. The gate of the first amplifier NFET 115 is connected to the LAC output node between the pull-up PFET 117 and the third amplifier NFET 116.

[0148] The source follower includes a source follower NFET 119 and a load NFET 118, wherein the load NFET has a constantly biased gate electrically connected in series between a positive power supply potential VDD and a reference potential VSS. The LAC output node is electrically connected to the gate of source follower NFET 119. The source follower outputs a pixel voltage signal VPR. The source follower forms a near-unity-gain voltage buffer that isolates the LAC from the capacitive amplifier circuit 120.

[0149] As reference Figure 3 As mentioned, the image sensor may include a radiation receiving chip 910 and a processing chip 920. The radiation receiving chip 910 may include a photoelectric conversion element 111 and an NFET of a logarithmic amplifier. The processing chip 920 may include a pull-up PFET 117 and a source follower. A through-contact via 915 in each pixel circuit transmits a signal from the radiation receiving chip 910 to the processing chip 920.

[0150] Other examples of radiation-sensitive circuit 110 can be based on the basic configuration of a logarithmic amplifier, which has an inverting amplifier and a feedback element with a logarithmic current-to-voltage relationship connected between the input and output of the inverting amplifier. The inverting amplifier ensures that the voltage across the photoelectric conversion element 111 is approximately constant. The pixel voltage signal VPR exhibits a logarithmic dependence on the photocurrent of the photoelectric conversion element 111.

[0151] Figure 17 A configuration example of a combination of the capacitive amplifier circuit 120 and the pixel comparator circuit 130 is shown.

[0152] The capacitance amplifier circuit 120 includes a switched capacitor amplifier including a storage capacitor 122, a feedback capacitor 125, a reset switch 126, and an inverting amplifier circuit. Figure 5 1. The inverting amplifier circuit includes a first PFET 129 and a first load NFET 128, wherein the load paths of the first PFET 129 and the first load NFET 128 are electrically connected in series between a positive power supply potential VDD and a reference potential VSS. The gate of the first PFET 129 is connected to the floating node 121. The gate of the first load NFET 128 receives a constant bias voltage bias1. The inverting amplifier circuit outputs an amplified signal at a node between the first PFET 129 and the first load NFET 128. The voltage gain of the inverting amplifier circuit is substantially greater than the ratio of the capacitance of the storage capacitor 122 to the capacitance of the feedback capacitor 125.

[0153] The pixel comparator circuit 130 includes a first comparator 131 , a second comparator 132 , and an inverter circuit 139 .

[0154] The first comparator 131 includes a first comparator PFET 134 and a first threshold NFET 133, wherein the load paths of the first comparator PFET 134 and the first threshold NFET 133 are electrically connected in series between a positive power supply potential VDD and a reference potential VSS. The gate of the first comparator PFET 134 receives the output signal of the capacitor amplifier circuit 120. A constant second bias voltage bias2 is applied to the gate of the first threshold NFET 133.

[0155] The second comparator 132 includes a second comparator PFET 136 and a second threshold NFET 135, wherein the load paths of the second comparator PFET 136 and the second threshold NFET 135 are electrically connected in series between the positive power supply potential VDD and the reference potential VSS. The gate of the second comparator PFET 136 receives the output signal of the capacitor amplifier circuit 120. A constant third bias voltage bias3 is applied to the gate of the second threshold NFET 135.

[0156] The channel widths of the first comparator PFET 134 and the first threshold NFET 133 can be selected so that when the output signal of the capacitor amplifier circuit 120 rises above a certain threshold, the first comparator 131 outputs an active ON signal at a high voltage level at the first output node between the first comparator PFET 134 and the first threshold NFET 133. Otherwise, the first comparator 131 outputs a low voltage level at the first output node. The channel widths of the second comparator PFET 136 and the second threshold NFET 135 can be selected so that when the output signal of the capacitor amplifier circuit 120 falls below a certain threshold, the second comparator 132 outputs a low voltage signal at the internal output node between the second comparator PFET 136 and the second threshold NFET 135. Otherwise, the second comparator 132 outputs a high voltage level at the internal output node.

[0157] Alternatively, the channel widths of first comparator PFET 134 and second comparator PFET 136 may be equal, and the channel widths of first threshold NFET 133 and second threshold NFET 135 may be equal, and biases bias2 and bias3 on the gates of first threshold NFET 133 and second threshold NFET 135 may be selected so that: when the output signal of capacitor amplifier circuit 120 rises above a certain threshold, first comparator 131 outputs an active ON signal of a high voltage level at a first output node between first comparator PFET 134 and first threshold NFET 133, and when the output signal of capacitor amplifier circuit 120 falls below a certain threshold, second comparator 132 outputs a low voltage signal at an internal output node between second comparator PFET 136 and second threshold NFET 135. First PFET 129 may have the same channel width as first comparator PFET 134 and second comparator PFET 136.

[0158] The inverter circuit 139 inverts the signal at the internal output node so that the second comparator 132 outputs an active high voltage level OFF signal when the output signal of the capacitive amplifier circuit 120 falls below a certain threshold.

[0159] Figure 18 An example of the configuration of the auto-zero enabling switch 150 is shown.

[0160] The auto-zero enabling switch 150 includes an NFET 155 and a PFET 153 electrically connected in parallel between the output of the ramp signal circuit 20 and the control input of the reset switch 126 .

[0161] More specifically, the controlled load paths between the source and drain of NFET 155 and between the source and drain of PFET 153 are electrically connected in parallel. NFET 155 and PFET 153 are configured as transmission gates operating as an analog switch. The body of PFET 153 can be connected to a positive potential. The body of NFET 155 can be connected to a reference potential, VSS.

[0162] The auto-zero signal AZ is applied to the gate of NFET 155. For example, Figure 13 The non-inverting output Q of the master-slave FF 189 in the MOSFET is connected to the gate of the NFET 155. The inverted auto-zero signal XAZ is applied to the gate of the PFET 153. For example, Figure 13 The inverting output / Q of the master-slave FF 189 in the master-slave FF is connected to the gate of the PFET 153. On the first side of the parallel load path, the group reset ramp signal REFR is applied. <x>On a second side of the parallel load path, an auto-zero switching signal is obtained, which is applied to a control electrode of a reset switch in the pixel circuit.

[0163] The controlled load path of the auxiliary NFET 154 can be connected between the control input terminal of the reset switch 126 and the reference potential VSS. The inverted auto-zero signal XAZ is applied to the gate of the auxiliary NFET 154. When the auto-zero signal AZ has a low level and the inverted auto-zero signal XAZ has a high level, the auxiliary NFET 154 fixes the auto-zero switch signal AZSW at the reference potential VSS and prevents the reset switch 126 from being accidentally turned on.

[0164] Figure 19 The row arbiter 30 is shown to include an arbitration circuit 300 and a plurality of arbiter interface circuits 310, wherein each arbiter interface circuit 310 is assigned to a group of pixel circuits 100, for example, all pixel circuits 100 of a pixel row. A group of pixel circuits 100 and associated arbiter interface circuits 310 form an interface pixel group 390.

[0165] The arbiter interface circuit 310 includes an inverter circuit 312 and a request pull-up transistor 311, which is connected to the request signal line 32. The request signal line 32 transmits the low-level active group request signal XRQY from the pixel circuit 100. <m>The inverter circuit 312 converts the low-level active group request signal XRQY into <m>Converts to a high-level active group request signal RQY <m>The group interface circuit 315 receives the high-level active group request signal RQY <m>And the group request signal REQ <m>Delivered to arbitration circuit 300.

[0166] The arbitration circuit 300 transmits the group acknowledgement signal ACK in an order generated from a predefined priority scheme. <m>, to request the signal REQ for each group <m>Respond.

[0167] In response to the received acknowledgement signal ACK <m>, the group interface circuit 315 generates an unbuffered group select signal SEL <m>, unbuffered group reset latch signal <m>And the group auto-zero start signal AZP <m>.

[0168] The first buffer circuit 313 receives the unbuffered group selection signal SEL <m>, and outputs the buffered group selection signal SELB on the response signal line 33 <m>The second buffer circuit 314 receives the unbuffered group reset latch signal RLAT. <m>, and outputs the buffered group reset latch signal RLTB on the reset latch signal line 24 <m>AZP group auto-zero start signal <m>The control ramp signal circuit 20 starts to output the group reset ramp signal REFR on the ramp signal line 22 <m>.

[0169] Figure 20 Shown for Figure 19 The group request signal REQ may be defined in the group interface circuit 315. <m>The leading edge of the group selection signal SEL <m>A minimum read waiting period Δt1 is set between the leading edges of Δt1 to give other pixel circuits 100 in the same group a chance to detect the predefined illumination change. More pixel circuits 100 can then be read out in the same readout.

[0170] At t=t1, the group interface circuit 315 can send the group request signal REQ <m>With the group selection signal SEL <m>At the same time, it is set to an inactive level, as long as the high level active group request signal RQY at the input of the group interface circuit 315 <m>With low level.

[0171] The period Δt2 shows an example where the group interface circuit 315 ignores the active high group request signal RQY <m>, until the ongoing auto-zero is completed (as indicated by the group reset latch signal RLAT <m>The trailing edge of the valid pulse is indicated).

[0172] Group auto-zero start pulse AZP <m>The trailing edge of the group reset latch signal RLAT <m>The period Δt3 between the leading edges of Δt and Δt can be configured. <m>, group selection signal SEL <m>and group auto-zero signal AZP <m>The width of the active pulse may be configurable in the group interface circuit 315 .

[0173] Finally, the timing diagram shows that during the self-zeroing of pixel group m in period Δt4 , pixel group m+1 can be read out.

[0174] Figure 21 Shown for Figure 19 An exemplary state diagram of the operation of group interface circuit 315 is shown.

[0175] The group interface circuit receives the high-level active group request signal RQY <m>The group interface circuit will activate the group request signal REQ <m>Output to the arbitration circuit and start the read wait timer. When the read wait timer expires and the group response signal ACK is received <m>When the group interface circuit 315 sets the group selection signal SEL <m>Set to active level, start the selection timer, and wait for the high level active group request signal RQY <m>When the selection timer expires, the group interface circuit 315 sets the group selection signal SEL <m>Set to invalid.

[0176] When the timer is selected, the group request signal RQY is active at high level <m>When the time expires before the active high group request signal RQY <m>When it becomes invalid, the setting group auto-zero start signal AZP <m>.

[0177] When the timer is selected, the group request signal RQY is active at high level <m>When the group interface circuit 315 expires after becoming inactive, it starts the auto-zero pulse timer and sets the group auto-zero start signal AZP when the selection timer expires. <m>.

[0178] When the auto-zero pulse timer expires, the group interface circuit 315 sends the group auto-zero start signal AZP <m>Set to inactive and start the reset latch delay timer.

[0179] When the reset latch delay timer expires, the group interface circuit 315 asserts the group reset latch signal RLAT. <m>Set to active and start the reset latch pulse width timer.

[0180] When the reset latch pulse width timer expires, the group interface circuit 315 asserts the group reset latch signal RLAT. <m>Set to inactive and return to idle state.

[0181] Figure 22 is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a system to which the technology according to the embodiment of the present disclosure can be applied.

[0182] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 22 In the example depicted in FIG, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output portion 12052, and an in-vehicle network interface 12053 are shown as the functional configuration of the integrated control unit 12050.

[0183] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for the following: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the vehicle's drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; a braking device for generating the vehicle's braking force; and the like.

[0184] The body system control unit 12020 controls the operation of various devices provided to the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the keyless entry system, the smart key system, the power window system, or various lights (such as the headlights, backup lights, brake lights, turn signals, fog lights, etc.). In this case, radio waves transmitted from a mobile device as a replacement for the key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power window system, lights, etc.

[0185] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can detect an object (such as a person, vehicle, obstacle, sign, or text on the road) or detect the distance thereto.

[0186] The imaging portion 12031 may be or may include an image sensor according to an embodiment of the present disclosure or a solid-state imaging device having an image sensor. The light received by the imaging portion 12031 may be visible light, or may be invisible light (such as infrared rays, etc.).

[0187] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle and may be or may include an image sensor according to an embodiment of the present disclosure or a solid-state imaging device having an image sensor. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection portion 12041 that detects the state of the driver. For example, the driver state detection portion 12041 includes a camera that includes a solid-state imaging device and focuses on the driver. Based on the detection information input from the driver state detection portion 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0188] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle (this information is obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040), and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS), such as collision avoidance or shock absorption for the vehicle, follow-up driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, lane departure warning, and the like.

[0189] In addition, the microcomputer 12051 can perform collaborative control intended for autonomous driving, which controls the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle (the information is obtained by the outside information detection unit 12030 or the inside information detection unit 12040), so that the vehicle can travel autonomously without relying on the driver's operation.

[0190] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle, which information is obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0191] The sound / image output portion 12052 transmits an output signal of at least one of sound or image to an output device that can visually or auditorily notify information to a passenger of the vehicle or the outside of the vehicle. Figure 22 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display or a head-up display.

[0192] Figure 23 12101 , 12102 , 12103 , 12104 , and 12105 .

[0193] For example, imaging sections 12101, 12102, 12103, 12104, and 12105 are provided at locations on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100, as well as at locations on the upper portion of the windshield inside the vehicle. Imaging section 12101 provided to the front nose and imaging section 12105 provided to the upper portion of the windshield inside the vehicle primarily obtain images of the front of the vehicle 12100. Imaging sections 12102 and 12103 provided to the side mirrors primarily obtain images of the sides of the vehicle 12100. Imaging section 12104 provided to the rear bumper or rear door primarily obtains images of the rear of the vehicle 12100. Imaging section 12105 provided to the upper portion of the windshield inside the vehicle is primarily used to detect preceding vehicles, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0194] Incidentally, Figure 23 The following diagram illustrates examples of the imaging ranges of imaging sections 12101 through 12104. Imaging range 12111 represents the imaging range of imaging section 12101 positioned on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging sections 12102 and 12103, respectively, positioned on the side mirrors. Imaging range 12114 represents the imaging range of imaging section 12104 positioned on the rear bumper or rear door. For example, by superimposing image data captured by imaging sections 12101 through 12104, a bird's-eye view image of vehicle 12100 viewed from above can be obtained.

[0195] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, an imaging element having pixels for phase difference detection, or a ToF module including an image sensor according to an embodiment of the present disclosure, or a solid-state imaging device including an image sensor according to an embodiment of the present disclosure.

[0196] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, and thereby extract the closest three-dimensional object as the preceding vehicle, specifically one that is located on the travel path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. Furthermore, the microcomputer 12051 can set in advance a following distance to be maintained ahead of the preceding vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, it is possible to execute cooperative control intended for autonomous driving, which enables the vehicle to travel autonomously without relying on the operation of the driver or the like.

[0197] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data regarding 3D objects into 3D object data for two-wheeled vehicles, standard-sized vehicles, large-sized vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that are visually recognizable by the driver of the vehicle 12100 and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and executes forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0198] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed by a program that extracts feature points from the images captured by the imaging units 12101 to 12104, which function as infrared cameras, and a program that determines whether the object is a pedestrian by performing pattern matching on a series of feature points representing the object's outline. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline for emphasis, superimposed on the identified pedestrian. The audio / video output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0199] An example of a vehicle control system to which the technology according to an embodiment of the present disclosure is applied has been described above. By applying an image sensor according to an embodiment of the present disclosure or a solid-state imaging device having an image sensor, the sensor has improved temporal resolution and sensing performance.

[0200] In addition, the embodiment of the present technology is not limited to the above-described embodiment, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0201] The image sensor according to the present disclosure may be any device for analyzing and / or processing radiation (such as visible light, infrared light, ultraviolet light, and X-rays). For example, a solid-state imaging device including an image sensor according to an embodiment may be any electronic device in the fields of transportation, home appliances, medicine and healthcare, security, beauty, sports, agriculture, image reproduction, etc.

[0202] Specifically, in the field of image reproduction, a solid-state imaging device including an image sensor according to an embodiment can be a device for capturing images to be provided for viewing, such as a digital camera, a smartphone, or a mobile phone device with a camera function. In the field of transportation, for example, a solid-state imaging device including an image sensor according to an embodiment can be integrated into an in-vehicle sensor (which captures the front, rear, periphery, interior, etc. of a vehicle for safe driving, such as automatic parking, recognition of the driver's status, etc.), integrated into a monitoring camera that monitors traveling vehicles and roads, or integrated into a distance measurement sensor that measures the distance between vehicles, etc.

[0203] In the field of home appliances, the image sensor according to the embodiment can be integrated into any type of sensor that can be used in a device provided for home appliances (such as television receivers, refrigerators, and air conditioners) to capture a user's gestures and perform device operations based on the gestures. Accordingly, the image sensor according to the embodiment can be integrated into home appliances such as television receivers, refrigerators, and air conditioners and / or devices for controlling home appliances. In addition, in the field of medicine and healthcare, the image sensor according to the embodiment can be integrated into any type of sensor, for example, a solid-state imaging device provided for use in medicine and healthcare, such as an endoscope or a device for performing angiography by receiving infrared light.

[0204] In the field of security, the image sensor according to the embodiment can be integrated into a device provided for use in security, such as a surveillance camera for crime prevention or a camera for personnel authentication. In addition, in the field of beauty, the image sensor according to the embodiment can be used in a device provided for use in beauty, such as a skin measurement instrument that captures the skin or a microscope that captures a probe. In the field of sports, the image sensor according to the embodiment can be integrated into a device provided for use in sports, such as a sports camera or a wearable camera for sports use. In addition, in the field of agriculture, the image sensor can be used in a device provided for use in agriculture, such as a camera for monitoring the conditions of fields and crops.

[0205] This technology can also be configured as follows:

[0206] [1] An image sensor (80) comprising: a pixel array (10) including pixel circuits (100), wherein each pixel circuit (100) is configured to output a request signal in response to a predefined illumination change, wherein each pixel circuit (100) includes a floating node (121) configured to temporarily store a charge that varies with illumination conditions, and wherein each pixel circuit (100) includes a reset switch (126) configured to set the floating node (121) to a predefined initial potential in response to a reset ramp signal; and a ramp signal circuit (20) configured to output a reset ramp signal for at least a first group of pixel circuits (100).

[0207] [2] An image sensor according to [1], wherein the pixel circuit (100) is configured so that, for each pixel circuit (100), the reset ramp signal is passed to the reset switch (126) only within a time period after a predefined illumination change in the pixel circuit (100) is detected and before the initial potential of the floating node (121) is set.

[0208] [3] The image sensor according to any one of [1] and [2], wherein the ramp signal circuit (20) is configured to output the reset ramp signal at regular time intervals.

[0209] [4] An image sensor according to any one of [1] to [3], wherein the ramp signal circuit (20) is configured to output a reset ramp signal for each pixel circuit (100) of the pixel array (10).

[0210] [5] An image sensor according to any one of [1] to [4], wherein each pixel circuit (100) includes a reset latch circuit (180) configured to suppress the output of the request signal during a period starting after information about a predefined illumination change is read out until the end of the next full cycle of the reset ramp signal.

[0211] [6] The image sensor according to [5], wherein the reset latch circuit (180) is configured to output a read completion signal indicating that the pixel circuit (100) detects a predefined illumination change and reads out information about the predefined illumination change from the pixel circuit (100).

[0212] [7] An image sensor according to any one of [5] and [6], wherein the reset latch circuit (180) is configured to output an auto-zero signal after detecting a predefined illumination change of the pixel circuit (100), the auto-zero signal indicating the beginning and end of a complete cycle of the reset ramp signal.

[0213] [8] An image sensor according to any one of [6] to [7], wherein each pixel circuit (100) includes a switch circuit (185) configured to disable the request signal when the read completion signal and / or the auto-zero signal is valid.

[0214] [9] The image sensor according to [1] further includes: a row arbiter circuit (30) configured to output a group selection signal for the first group of pixel circuits (100) in response to a group request signal received from any pixel circuit (100) in the first group of pixel circuits (100).

[0215]

[10] The image sensor according to [9], wherein the ramp signal circuit (20) is configured to output a reset ramp signal for the first group of pixel circuits (100) in response to a group selection signal for the first group of pixel circuits (100).

[0216]

[11] An image sensor according to any one of [9] and

[10] , wherein the pixel circuits (100) are assigned to pixel rows and pixel columns, and wherein the first group of pixel circuits (100) are assigned to one pixel row or one pixel column.

[0217]

[12] An image sensor according to any one of [9] to

[11] , wherein the reset latch circuit (180) is configured to output an auto-zero signal indicating that the pixel circuit (100) detects a predefined illumination change, reads out information about the predefined illumination change, and does not complete initialization of the floating node (121).

[0218]

[13] An image sensor according to any one of [9] to

[12] , wherein the trailing edge of the reset ramp signal changes at a rate at least ten times slower than the leading edge of the group select signal.

[0219]

[14] An image sensor according to any one of [1] to

[13] , wherein each pixel circuit (100) further includes a reset latch circuit (180) and an auto-zero enable switch (150), wherein the auto-zero enable switch (150) is configured to pass the reset ramp signal to the reset switch (126) in response to the auto-zero signal, and wherein the reset latch circuit (180) is configured to output the auto-zero signal in response to a predefined illumination change.

[0220]

[15] The image sensor according to

[14] , wherein the self-zeroing enable switch (150) includes an NFET (151) and a PFET (152) electrically connected in parallel between the output of the ramp signal circuit (20) and the control input of the reset switch (126).< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. An image sensor, comprising: a pixel array comprising pixel circuits, wherein each pixel circuit is configured to output a request signal in response to a predefined illumination change, wherein each pixel circuit includes a floating node configured to temporarily store charge that varies with illumination conditions, and wherein each pixel circuit includes a reset switch configured to set the floating node to a predefined initial potential in response to a reset ramp signal; and The ramp signal circuit is configured to output the reset ramp signal to at least a first group of the pixel circuits.

2. The image sensor according to claim 1, in, The pixel circuits are configured such that, for each pixel circuit, the reset ramp signal is passed to the reset switch only during a period after a predefined illumination change in the pixel circuit is detected and before setting the initial potential of the floating node ends.

3. The image sensor according to claim 1, in, The ramp signal circuit is configured to output the reset ramp signal at regular time intervals.

4. The image sensor according to claim 1, in, The ramp signal circuit is configured to output the reset ramp signal for each pixel circuit of the pixel array.

5. The image sensor according to claim 3, in, Each of the pixel circuits includes a reset latch circuit configured to suppress output of the request signal during a period starting after the information on the predefined illumination variation is read out until the end of a next full cycle of the reset ramp signal.

6. The image sensor according to claim 5, in, The reset latch circuit is configured to output a read completion signal indicating that the pixel circuit detects a predefined illumination change and to read out information about the predefined illumination change from the pixel circuit.

7. The image sensor according to claim 5, in, The reset latch circuit is configured to output an auto-zero signal after detecting a predefined illumination change of the pixel circuit, the auto-zero signal indicating the beginning and end of a complete cycle of the reset ramp signal.

8. The image sensor according to claim 5, in, Each pixel circuit includes a switch circuit configured to disable the request signal if the read completion signal and / or the auto-zero signal is valid.

9. The image sensor according to claim 1, further comprising: The row arbiter circuit is configured to output a group selection signal for the first group of pixel circuits in response to a group request signal received from any pixel circuit in the first group of pixel circuits.

10. The image sensor according to claim 9, in, The ramp signal circuit is configured to output the reset ramp signal for a first group of the pixel circuits in response to the group selection signal for the first group of the pixel circuits.

11. The image sensor according to claim 9, in, The pixel circuits are assigned to pixel rows and pixel columns, and wherein a first group of the pixel circuits is assigned to one pixel row or one pixel column.

12. The image sensor according to claim 9, in, The reset latch circuit is configured to output an auto-zero signal indicating that the pixel circuit detects a predefined illumination change, reads out information about the predefined illumination change, and does not complete initialization of the floating node.

13. The image sensor according to claim 9, in, The trailing edge of the reset ramp signal changes at a rate at least ten times slower than the leading edge of the group select signal.

14. The image sensor according to claim 1, in, Each pixel circuit further includes a reset latch circuit and an auto-zero enable switch, wherein the auto-zero enable switch is configured to pass the reset ramp signal to the reset switch in response to an auto-zero signal, and wherein the reset latch circuit is configured to output the auto-zero signal in response to the predefined illumination change.

15. The image sensor according to claim 14, in, The auto-zero enabling switch includes an NFET and a PFET electrically connected in parallel between an output of the ramp signal circuit and a control input of the reset switch.

Images