Transistor on-resistance high-precision comparison method

Abstract

The invention belongs to the technical field of power electronics and semiconductor devices, and provides a transistor on-resistance high-precision comparison method, which comprises the following steps of: generating and outputting a direct-current voltage # imgabs0 # which can quickly adjust a numerical value and has load capacity through a direct-current voltage adjusting module; the grid driving module generates and outputs a pulse signal # imgabs3 # of which the voltage can be quickly adjusted based on the direct-current voltage # imgabs1 # and the pulse voltage # imgabs2 #; applying a pulse signal # imgabs4 # to the transistor to be measured through the power module, and measuring the on-resistance of the transistor to be measured under the gate driving voltage; and switching the gate driving voltage in the microsecond-to-nanosecond magnitude delay, and measuring the on-resistance of the transistor to be measured under the switching gate driving voltage based on the pulse signal # imgabs5 #. According to the method, the on-resistance of the transistor to be tested under different gate driving voltages can be tested in the pulse circuit, the measurement delay is shortened to several nanoseconds from several minutes of a traditional double-pulse circuit, and the performance of the transistor reliability evaluation circuit is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics and semiconductor devices, and in particular to a high-precision comparison method for transistor on-resistance. Background Art

[0002] The semiconductor field has experienced rapid development in recent years. A variety of new materials and structures have emerged based on traditional silicon (Si)-based field-effect transistors (MOSFETs), improving transistor characteristics in certain key areas. For example, materials such as gallium nitride (GaN), silicon carbide (SiC), gallium oxide (Ga2O3), and aluminum nitride (AlN) possess higher electron mobility and bandgap widths, resulting in transistors with higher switching frequencies and excellent high-voltage resistance. The "p-type GaN gate high-electron-mobility transistor structure," "Schottky-Ohm hybrid gate structure," and "p-FET junction high-electron-mobility transistor structure" have further enhanced transistor performance, and related achievements have gradually moved from laboratory research to practical applications in society.

[0003] Before transistors made of various new materials and structures are used in large quantities, they need to undergo "reliability characterization" to verify their ability to work normally in various working environments. According to the different stages of transistor preparation to application, reliability characterization can be divided into "wafer-level reliability characterization", "device-level reliability characterization", and "circuit-level reliability characterization". As the names suggest, they respectively refer to the quality assessment during the wafer preparation process, the quality assessment after the transistor structure is prepared, and the quality assessment during actual application in the circuit (with certain voltage and current stress). Among them, the test conditions of circuit-level reliability characterization are closest to the real scenarios of actual application of transistors, and its data also has great reference value.

[0004] The dual-pulse circuit is a commonly used circuit in "circuit-level reliability characterization." It consists of a high-voltage power supply, a voltage-stabilizing capacitor, a power inductor, a freewheeling diode, and a transistor under test. Dual-pulse testing is performed by applying a dual-pulse waveform to the gate of the transistor under test. It can test the switching characteristics and on-resistance of the transistor under test under certain gate drive voltages, drain voltage stresses, and load currents. Experiments have found that when comparing transistor on-resistances under different drive conditions (gate drive voltages), using traditional "dual-pulse circuits" makes it difficult to adjust the drive voltage in a short period of time. This results in long delays between sets of test data, making the reliability of the data comparisons low. Summary of the Invention

[0005] Therefore, one object of the present invention is to provide a high-precision comparison method for transistor on-resistance to solve the problems mentioned in the background art and overcome the deficiencies in the prior art.

[0006] In order to achieve the above object, the present invention provides a high-precision comparison method for transistor on-resistance, comprising: The DC voltage adjustment module generates and outputs a DC voltage that can quickly adjust the value and has load capacity. ; The gate drive module is based on the DC voltage and pulse voltage Generate and output pulse signals with rapidly adjustable voltage ; Apply a pulse signal to the transistor under test through the power module , and based on the pulse signal Measure the on-resistance of the transistor under test under gate drive voltage; Switching the gate drive voltage within a microsecond to nanosecond delay based on the pulse signal Measure the on-resistance of the transistor under test under switching gate drive voltage, and achieve high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages.

[0007] As an advantage, the DC voltage adjustment module includes a digital-to-analog conversion chip and an operational amplifier, wherein the digital-to-analog conversion chip and the operational amplifier are connected via a DC voltage. The output end of the digital-to-analog conversion chip is connected to the operational amplifier, and the output end of the operational amplifier is connected to the gate driving module.

[0008] Preferably, the gate drive module includes a first CMOS inverter and a second CMOS inverter, the output end of the operational amplifier is connected to the power pin of the first CMOS inverter and the power pin of the second CMOS inverter, and the input pin of the first CMOS inverter is connected to the pulse voltage The output pin of the first CMOS inverter is connected to the input pin of the second CMOS inverter, the ground pin of the first CMOS inverter and the ground pin of the second CMOS inverter are both grounded, and the output pin of the second CMOS inverter is connected to the power module.

[0009] Preferably, the power module includes a freewheeling diode and a power inductor, the gate of the transistor to be tested is connected to the output pin of the second CMOS inverter, the drain of the transistor to be tested is respectively connected to the positive electrode of the freewheeling diode and one end of the power inductor, the negative electrode of the freewheeling diode and the other end of the power inductor are connected to the positive electrode of the high-voltage power supply, the source of the transistor to be tested and the negative electrode of the high-voltage power supply are grounded, and the high-voltage power supply is connected in parallel with a voltage-stabilizing capacitor.

[0010] Preferably, the digital-to-analog conversion chip of the DC voltage adjustment module is controlled by a digital signal to generate and output a high-speed adjustable DC voltage, and then the operational amplifier is operated in a voltage follower mode to convert the DC signal output by the digital-to-analog conversion chip into a DC voltage that can carry a load. .

[0011] As an advantage, the first CMOS inverter and the second CMOS inverter of the gate driving module form a push-pull output structure, and the adjustable DC voltage output by the DC voltage adjustment module is Power supply, through pulse voltage Control the opening and closing of the gate drive module voltage output, and adjust the DC voltage and pulse voltage A pulse signal that controls the gate drive module output voltage and can quickly adjust .

[0012] Preferably, the switching gate drive voltage is based on the pulse signal Measuring the on-resistance of transistors under switching gate drive voltages to achieve high-precision comparison of transistor on-resistances under different gate drive voltages includes: switching the gate drive voltage of the transistor to be tested multiple times under a fixed drain voltage stress, and Real-time monitoring of the change data and change curve of the on-resistance of the transistor under test that has not yet degraded to a steady state under different gate drive voltages.

[0013] Preferably, the multiple switching of the gate drive voltage of the transistor under test includes periodically switching the gate drive voltage of the transistor under test, incrementally switching the gate drive voltage of the transistor under test, or decrementally switching the gate drive voltage of the transistor under test.

[0014] Preferably, in the push-pull output structure formed by the first CMOS inverter and the second CMOS inverter of the gate driving module, the lower tubes of the first CMOS inverter and the second CMOS inverter are silicon-based field effect transistors or gallium nitride-based N-channel enhancement mode transistors.

[0015] Preferably, when the lower tubes of the first CMOS inverter and the second CMOS inverter are silicon-based field effect transistors, their threshold voltages are 2 to 4 V, and the pulse voltage The high level of the first CMOS inverter and the second CMOS inverter is about 5V; when the lower tube of the first CMOS inverter and the second CMOS inverter is a gallium nitride-based N-channel enhancement transistor, its threshold voltage is 1 to 2V, and the pulse voltage The high level is about 3.3V.

[0016] Compared with the prior art, the present invention has the following advantages and beneficial effects: The high-precision transistor on-resistance comparison method of the present invention forms a new transistor on-resistance comparison system through the close coordination of circuit architecture, timing control and comparison method, achieving a breakthrough improvement in the accuracy and timeliness of transistor on-resistance comparison under different gate drive voltages, and realizing high-precision comparison of transistor on-resistance.

[0017] At the circuit architecture level, the DC voltage adjustment module and the gate drive module form the circuit foundation that can switch the transistor gate drive voltage at the microsecond to nanosecond level; at the timing control level, based on the real-time voltage adjustment capability of the digital-to-analog conversion chip of the DC voltage adjustment module and the precise timing of the gate drive module control signal, multiple groups of different drive voltages are quickly switched during the pulse test, so that different drive voltages act on transistors that have not yet degenerated to a steady state, thereby realizing on-resistance measurement; at the comparison method level, by synchronizing the voltage switching with microsecond to nanosecond delay and the pulse window, the interval of traditional batch testing is compressed from minutes to nanoseconds, ultimately achieving a breakthrough improvement in the accuracy and timeliness of on-resistance comparison, thereby improving the credibility of data comparison.

[0018] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which: Figure 1 It is a circuit diagram of each stage of the traditional double pulse circuit; Figure 2 This is a typical test waveform of a traditional double-pulse circuit (including a drain clamp module); Figure 3 It is the on-resistance of the GaN transistor after being subjected to different drain voltage stress durations; Figure 4 It is the on-resistance of the GaN transistor after being subjected to different drive voltages and drain voltage stresses; Figure 5 This is a flow chart of a method according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a new test waveform designed in an embodiment of the present invention; Figure 7 This is a schematic diagram of a novel test circuit designed in accordance with an embodiment of the present invention; Figure 8 This is a schematic diagram of the circuit principle of the digital-to-analog conversion chip according to an embodiment of the present invention; Figure 9 This is a flow chart of a novel testing method designed in accordance with an embodiment of the present invention; Figure 10This is a diagram illustrating a method for implementing a novel test waveform designed in an embodiment of the present invention.

[0020] In the figure: 1. DC voltage adjustment module; 2. Gate drive module; 3. Power module. DETAILED DESCRIPTION

[0021] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0022] Figure 1 This is a schematic diagram of the various stages of a traditional double-pulse circuit. It consists of a high-voltage power supply, a voltage-stabilizing capacitor, a power inductor, a freewheeling diode, and a transistor under test. A double-pulse (two consecutive switching cycles) test is performed by applying a double-pulse waveform to the gate of the transistor under test. This test measures the switching characteristics and on-resistance of the transistor under test under certain gate drive voltages, drain voltage stresses, and load currents. Figures (a) through (f) illustrate the circuit states at different stages. The dashed line (Q) of the transistor under test indicates the transistor is off, while the solid line (Q) indicates the transistor is on. The dashed arcs represent the voltage stress path, and the solid arcs represent the current loop path. (a) shows the first stage, when the transistor under test is not on and is experiencing drain voltage stress. (b) shows the second stage, when the transistor under test is turned on for the first time, and the charge from the voltage-stabilizing capacitor flows through the transistor under test to charge the power inductor. (c) shows the third stage, when the transistor under test is turned off for the first time. The power inductor current cannot change suddenly and is freewheeling through the Schottky diode, while the drain of the transistor under test is experiencing drain voltage stress. (d) represents the fourth stage, during which the transistor under test is turned on for the second time. The charge on the voltage-stabilizing capacitor flows through the transistor under test to charge the power inductor. (e) represents the fifth stage, during which the transistor under test is turned off for the second time. The power inductor current cannot change suddenly and is freewheeling through the Schottky diode. The drain of the transistor under test is subjected to drain voltage stress. (f) represents the sixth stage, during which the inductor current gradually decreases to zero during the freewheeling process. At this point, no current flows through the power inductor, and the drain of the transistor under test is subjected to drain voltage stress.

[0023] Figure 2 This is a typical test waveform for a traditional double-pulse circuit (including a drain clamp module). The horizontal axis represents time, and the double-pulse waveform test time is generally several microseconds. A breakpoint is set before time 0 on the horizontal axis, indicating that the drain of the transistor under test has begun to withstand voltage stress from the high-voltage power supply for a certain period of time (microseconds to several hours) before the double-pulse test is carried out. Figure 1 (a), ~ correspond Figure 1 (b) ~ correspond Figure 1 (c), ~ correspond Figure 1 (d), after time T4, contains Figure 1 (e), (f), where (e) and (f) are not Figure 2 It will be described in detail in the text. The vertical axis represents the gate (drive) voltage, drain voltage, (drain) clamping voltage, and drain-source current from top to bottom. The gate voltage is used as a control signal, and the drain voltage, clamping voltage, and drain-source current are used as signals measured by the oscilloscope. When the gate voltage is low, the transistor to be tested is turned off. At this time, the drain voltage of the transistor to be tested is high, and the drain-source current is 0A. When the gate voltage is high, the transistor to be tested is turned on. At this time, the drain voltage of the transistor to be tested is low, and the drain-source current gradually increases. The (drain) clamping voltage represents the drain voltage of the transistor to be tested tested by the drain clamping module in the dual-pulse circuit. The drain clamping module is added to improve the accuracy of the drain voltage test when the transistor to be tested is turned on. Because the drain clamping module is not the focus of this study, it is not included in the text. Figure 1 The circuit schematic is shown in the figure.

[0024] Figure 3 The on-resistance of a GaN transistor after being subjected to different drain voltage stress durations is measured. The improvement of the present invention lies in the combination of circuit innovation and test method innovation. The focus is not on the transistor under test; the GaN transistor is used here as an example only. Figure 3 The on-resistance of the transistor under test was measured at room temperature using a conventional double-pulse test circuit with a fixed gate drive voltage of 6V. The data shows the change in on-resistance of the transistor under test under different drain voltage stress durations. As the drain voltage stress duration increases, the on-resistance initially increases and then stabilizes.

[0025] Figure 4 It is the on-resistance of the GaN transistor after being subjected to different driving voltages and drain voltage stresses. The on-resistance of the transistor under test under different driving voltages was experimentally studied and it was found that increasing the driving voltage can suppress the degradation of the on-resistance of the transistor under test. Figure 3 It has been shown that the on-resistance shows the characteristic of "increasing first and then stabilizing" as the drain voltage stress duration changes. Figure 4The experimental data tests the on-resistance of the transistor under test in a stable state after being subjected to a "long-term" drain voltage stress. Although the data of the transistor under test in a stable state can be tested in the early stages of the experiment, and the on-resistance of the transistor under test under different drive voltages can be compared, the traditional dual-pulse circuit has a major shortcoming in terms of reliability assessment, real-time monitoring of on-resistance, and degradation mechanism analysis of the transistor under test: it is impossible to quickly adjust the gate drive voltage under a short measurement delay (nanosecond delay), and therefore it is impossible to compare the on-resistance of the transistor under test under different drive voltages during drain voltage stress of any duration (at which time the transistor under test may not have degraded to a steady state).

[0026] Based on this, a high-precision comparison method of transistor on-resistance according to an embodiment of the present invention is as follows: Figure 5 As shown, including: Step S1: Generate and output a DC voltage that can quickly adjust the value and has load capacity through the DC voltage adjustment module 1 ; Step S2: The gate driving module 2 generates a voltage based on the DC voltage. and pulse voltage Generate and output pulse signals with rapidly adjustable voltage ; Step S3: Apply a pulse signal to the transistor to be tested through the power module 3 , and based on the pulse signal Measure the on-resistance of the transistor under test under gate drive voltage; Step S4: Switching the gate drive voltage within a microsecond to nanosecond delay based on the pulse signal Measure the on-resistance of the transistor under test under switching gate drive voltage, and achieve high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages.

[0027] The high-precision transistor on-resistance comparison method of the present invention forms a new transistor on-resistance comparison system through the close coordination of circuit architecture, timing control and comparison method, achieving a breakthrough improvement in the accuracy and timeliness of transistor on-resistance comparison under different gate drive voltages, and realizing high-precision comparison of transistor on-resistance.

[0028] At the circuit architecture level, the DC voltage adjustment module 1 and the gate drive module 2 form the circuit basis for switching the transistor gate drive voltage at the microsecond to nanosecond level; at the timing control level, based on the real-time voltage adjustment capability of the digital-to-analog conversion chip of the DC voltage adjustment module 1 and the precise timing of the control signal of the gate drive module 2, multiple sets of different drive voltages are quickly switched during the pulse test, so that different drive voltages act on transistors that have not yet degenerated to a steady state, thereby realizing on-resistance measurement; at the comparison method level, by synchronizing the voltage switching with microsecond to nanosecond delay and the pulse window, the interval of traditional batch testing is compressed from minutes to nanoseconds, ultimately achieving a breakthrough improvement in the accuracy and timeliness of on-resistance comparison, thereby improving the credibility of data comparison.

[0029] It is understandable that the pulse signal of the present invention It can be a double pulse signal in a traditional double pulse test, or a single pulse signal or a multi-pulse signal, that is, the present invention can implement testing of the gate of the transistor to be tested by applying any number of pulse signal waveforms with different gate drive voltages.

[0030] Figure 6 It is a schematic diagram of a new test waveform designed in an embodiment of the present invention. The horizontal axis is time, and the vertical axes are "gate voltage 1", "gate voltage 2", "gate voltage 3", "gate voltage 4", and "gate voltage 5" from top to bottom, indicating five possible gate voltage control waveforms. Gate voltage 1 represents a typical waveform when comparing the on-resistance of the transistor to be tested under different gate drive voltages in a traditional double-pulse test circuit. Gate voltage 2 and gate voltage 3 represent the gate drive waveforms when the drive voltage needs to be changed once and the on-resistance of the transistor to be tested needs to be compared. Gate voltage 4 and gate voltage 5 represent the gate drive waveforms when the drive voltage needs to be changed multiple times and the on-resistance of the transistor to be tested needs to be compared. The figure only plots the waveforms when the drive voltage is changed twice, and the waveforms of the drive voltage that changes multiple times are the same as the waveforms when the drive voltage is changed twice, and they are no longer plotted one by one in the figure. The shaded areas are the parts that the oscilloscope needs to focus on and read the data. The oscilloscope tests the drain voltage and drain-source current data of the transistor to be tested in the shaded area time period, and then obtains the on-resistance of the transistor to be tested at this time. Gate voltage 1 represents the test of different gate drive voltages ( , ) waveform when the transistor characteristics are under test. When testing different gate drive voltages, it is generally necessary to manually adjust the external voltage divider module. This process generally takes several minutes. The longer time delay in the middle is represented by the "breakpoint" on the coordinate axis. Gate voltage 2 is one of the optimization solutions proposed by the present invention. In the second pulse voltage The value applied after several microseconds is The pulse voltage of this solution has moderate requirements on circuit performance and cost. Gate voltage 3 is a further optimization solution proposed by the present invention. After a nanosecond delay, the value is This solution has high requirements on circuit performance and cost, but the measurement delay is shortened to the nanosecond level, which can achieve high-precision comparison of on-resistance. Gate voltage 4 is a waveform diagram when the gate drive voltage needs to be changed multiple times. In the second pulse voltage The value applied after several microseconds is The pulse voltage is then applied after a microsecond delay. The gate voltage 5 is a further optimization solution proposed by the present invention for the gate voltage 4. After a nanosecond delay, the value is A pulse voltage of , followed by a delay of several nanoseconds and a value of It is worth noting that the voltage values ​​that can be applied in Gate Voltage 4 and Gate Voltage 5 are not limited to three values. Multiple voltage values ​​can also be set according to experimental needs. , , This is for illustration purposes only.

[0031] As an implementation method, Figure 7 As shown, the DC voltage adjustment module 1 includes a digital-to-analog conversion chip and an operational amplifier. The digital-to-analog conversion chip and the operational amplifier are connected via a DC voltage. The output end of the digital-to-analog conversion chip is connected to the operational amplifier, and the output end of the operational amplifier is connected to the gate driving module 2.

[0032] As an implementation method, Figure 7 As shown, the gate drive module 2 includes a first CMOS inverter and a second CMOS inverter, the output end of the operational amplifier is connected to the power pin of the first CMOS inverter and the power pin of the second CMOS inverter, and the input pin of the first CMOS inverter is connected to the pulse voltage The output pin of the first CMOS inverter is connected to the input pin of the second CMOS inverter, the ground pin of the first CMOS inverter and the ground pin of the second CMOS inverter are both grounded, and the output pin of the second CMOS inverter is connected to the power module 3.

[0033] like Figure 7As shown, it can be understood that the first CMOS inverter and the second CMOS inverter are both composed of two enhancement mode field effect transistors, one is an NMOS field effect transistor and the other is a PMOS field effect transistor.

[0034] As an implementation method, Figure 7 As shown, the power module 3 includes a freewheeling diode D and a power inductor L, the gate of the transistor to be tested Q is connected to the output pin of the second CMOS inverter, the drain of the transistor to be tested Q is connected to the positive electrode of the freewheeling diode D and one end of the power inductor L, and the negative electrode of the freewheeling diode D and the other end of the power inductor L are connected to the high voltage power supply. The positive electrode of the transistor to be tested is connected to the source of the high voltage power supply The negative pole of is grounded, and the high voltage power supply is connected in parallel with a voltage stabilizing capacitor C.

[0035] Figure 7 This is a schematic diagram of a novel test circuit designed by the present invention. Figure 7 This is the macro structure of a transistor on-resistance high-precision comparison circuit. The transistor on-resistance high-precision comparison circuit includes three modules: a DC voltage adjustment module 1, a gate drive module 2, and a power module 3. The DC voltage adjustment module 1 is used to provide rapidly changing DC power; the gate drive module 2 uses a pulse control signal and a rapidly changing DC output level that can rapidly change the pulse signal; the power module 3 is used to perform pulse testing on the transistor to be tested and obtain the on-resistance of the transistor to be tested. The DC voltage adjustment module 1 uses a digital-to-analog conversion chip to generate a high-speed adjustable DC power. Then the operational amplifier is operated in voltage follower mode to convert the DC signal output by the digital-to-analog converter chip Converted into DC power that can carry a load (output a certain current) DC voltage Power the digital-to-analog conversion chip and the operational amplifier chip. The gate drive module 2 includes two CMOS inverter modules to form a push-pull output. The gate drive module 2 uses the adjustable DC voltage output by the DC voltage adjustment module 1. Power supply. Pulse voltage It is a control signal used to control whether the gate drive module 2 outputs voltage. With adjustable DC , and finally output a "pulse with rapidly adjustable voltage" waveform signal Power module 3 uses a pulse waveform signal with rapidly adjustable voltage Drive the transistor under test and extract the on-resistance of the transistor under test from the test waveform for comparative analysis. Figure 8The example of the high-speed digital-to-analog conversion chip of the embodiment of the present invention is DAC08 produced by ADI. The analog signal settling time output by the digital-to-analog conversion chip DAC08 is 85ns. The digital-to-analog conversion chip DAC08 includes 8 digital signal control bits. Figure 8 After the circuit diagram is connected, a high-frequency analog voltage can be output at the IOUT pin. This solution has been experimentally proven that the digital-to-analog conversion chip can indeed switch and output different DC values ​​in nanoseconds.

[0036] More specifically, Figure 8 As shown, the V+ pin of the digital-to-analog conversion chip DAC08 is connected to a 15V DC power supply, the VREF+ pin of the digital-to-analog conversion chip DAC08 is connected to a 10V reference DC power supply via a resistor R1, the VREF- pin of the digital-to-analog conversion chip DAC08 is grounded via a resistor R2, the COMP pin of the digital-to-analog conversion chip DAC08 is connected to a -15V DC power supply via a capacitor C1, the VLC pin of the digital-to-analog conversion chip DAC08 is grounded, the IOUT- pin of the digital-to-analog conversion chip DAC08 is connected to a 10V DC power supply via a resistor R3, the V- pin of the digital-to-analog conversion chip DAC08 is connected to a -15V DC power supply, the IOUT pin of the digital-to-analog conversion chip DAC08 is connected to a 10V DC power supply via a resistor R4, and the IOUT pin of the digital-to-analog conversion chip DAC08 outputs a DC power supply. , the B1-B8 pins of the digital-to-analog converter chip DAC08 are connected to the corresponding digital input voltage source through resistors R12-R5. - .

[0037] As an embodiment, the digital-to-analog conversion chip of the DC voltage adjustment module 1 is controlled by a digital signal to generate and output a high-speed adjustable DC voltage, and then the operational amplifier is operated in a voltage follower mode to convert the DC signal output by the digital-to-analog conversion chip into a DC voltage that can carry a load. .

[0038] As an embodiment, the first CMOS inverter and the second CMOS inverter of the gate driving module 2 form a push-pull output structure, and the adjustable DC voltage output by the DC voltage adjustment module 1 is Power supply, through pulse voltage Controls the opening and closing of the voltage output of the gate drive module 2, and can adjust the DC voltage and pulse voltage Control gate drive module 2 output voltage can quickly adjust the pulse signal .

[0039] Figure 9This is a flow chart of the new test method designed by the present invention. First, according to the experimental needs, a digital signal is input to the digital-to-analog conversion chip. At this time, the digital-to-analog conversion chip can generate a DC power that can be quickly adjusted, and combined with the operational amplifier, the DC power has a load-carrying capacity, and a DC voltage that can carry a load and can quickly adjust the voltage is obtained. The DC power supply is then used to power the gate drive module 2, and a control signal is used to determine the time range of the output voltage of the gate drive module 2. Finally, the "rapidly adjustable, load-carrying pulse voltage" is used to drive the gate of the transistor to be tested to perform a double pulse test under different driving voltages based on a short measurement delay. At this time, the on-resistance of the transistor to be tested under different driving voltages based on a short measurement delay can be obtained.

[0040] As an embodiment, the switching gate drive voltage is based on the pulse signal Measuring the on-resistance of transistors under switching gate drive voltages to achieve high-precision comparison of transistor on-resistances under different gate drive voltages includes: switching the gate drive voltage of the transistor to be tested multiple times under a fixed drain voltage stress, and Real-time monitoring of the change data and change curve of the on-resistance of the transistor under test that has not yet degraded to a steady state under different gate drive voltages.

[0041] As an embodiment, the multiple switching of the gate drive voltage of the transistor under test includes periodically switching the gate drive voltage of the transistor under test, incrementally switching the gate drive voltage of the transistor under test, or decrementally switching the gate drive voltage of the transistor under test.

[0042] It can be understood that the gate drive voltage of the transistor to be tested is switched multiple times, wherein the multiple times is specifically greater than or equal to 1.

[0043] In one embodiment, the multiple switching of the gate drive voltage of the transistor under test is specifically: periodically switching the gate drive voltage of the transistor under test, for example, switching the gate drive voltage of the transistor under test according to 5V-6V-5V-6V, with a switching time interval of 100 nanoseconds.

[0044] In one embodiment, the multiple switching of the gate drive voltage of the transistor under test is specifically: periodically switching the gate drive voltage of the transistor under test, for example, switching the gate drive voltage of the transistor under test according to 5V-6V-7V-5V-6V-7V, with a switching time interval of 100 nanoseconds.

[0045] In one embodiment, the multiple switching of the gate drive voltage of the transistor under test is specifically: incrementally switching the gate drive voltage of the transistor under test, for example, switching the gate drive voltage of the transistor under test according to 5V-6V-7V-8V, with a switching time interval of 200 nanoseconds.

[0046] In one embodiment, the multiple switching of the gate drive voltage of the transistor under test is specifically: switching the gate drive voltage of the transistor under test in a decreasing manner, for example, switching the gate drive voltage of the transistor under test according to 7V-6V-5V, with a switching time interval of 10 microseconds.

[0047] It can be understood that the above-mentioned switching of the gate drive voltage of the transistor to be tested is exemplary, and the gate drive voltage of the switching of the transistor to be tested of the present invention, including the voltage size, voltage interval, switching times, and switching time interval, are not limited to this. Any switching of the gate drive voltage of the transistor to be tested that can achieve high-precision comparison of the on-resistance of the transistor to be tested under different gate drive voltages through the high-precision comparison method of the transistor on-resistance of the present invention is within the protection scope of the present invention.

[0048] As an embodiment, in the push-pull output structure formed by the first CMOS inverter and the second CMOS inverter of the gate driving module 2, the lower tubes of the first CMOS inverter and the second CMOS inverter are silicon-based field effect transistors or gallium nitride-based N-channel enhancement transistors.

[0049] As an embodiment, when the lower tubes of the first CMOS inverter and the second CMOS inverter are silicon-based field effect transistors, their threshold voltages are 2 to 4 V, and the pulse voltage The high level of the first CMOS inverter and the second CMOS inverter is about 5V; when the lower tube of the first CMOS inverter and the second CMOS inverter is a gallium nitride-based N-channel enhancement transistor, its threshold voltage is 1 to 2V, and the pulse voltage The high level is about 3.3V.

[0050] Figure 10 This is a diagram illustrating a method for implementing a novel test waveform designed by the present invention. Figure 10 (a) is an illustration of a method for generating gate voltage 2; Figure 10 (b) is an illustration of a method for generating the gate voltage 3; Figure 10 (c) is an explanation of the method for generating the gate voltage 4; Figure 10 (d) is an explanation of the method for generating the gate voltage 5. For the convenience of explanation, Figure 10 Replace with 5V Figure 6 in , Figure 10 Replace with 6V Figure 6 in , Figure 10 Replace with 7V Figure 6 in DC voltage Power the digital-to-analog converter chip and the operational amplifier chip, using 10V as an example. This is the "quickly adjustable" voltage output by the digital-to-analog converter chip and followed by the voltage of the operational amplifier. The shaded area in the diagram illustrates the time window for the voltage to switch from 5V to 6V and from 6V to 7V. It is the control signal output by the microcontroller, which is used to control the time range of the output voltage of the gate drive module 2. When the voltage is high at 3.3V, the gate drive module 2 is turned on. The level is equal to Level; when When the voltage is low 0V, the gate drive module 2 is turned off. The voltage level is 0V or negative voltage, which is represented by 0V in this embodiment. Depend on and It is worth mentioning that when the push-pull circuit bottom tube of the CMOS structure in the gate drive module 2 uses a silicon-based field-effect transistor, its threshold voltage is generally 2 to 4V, so the control signal A voltage of around 5V is required to fully activate the lower transistor. Gallium nitride-based N-channel enhancement-mode transistors can also be used for the lower transistor, which typically has a threshold voltage of 1 to 2V. Using the 3.3V output from the microcontroller can fully activate the lower transistor.

[0051] The present invention relates to a high-precision comparison method and circuit for transistor on-resistance, which can output a pulse signal with rapidly adjustable voltage and test the transistor on-resistance based on a pulse circuit, ultimately achieving high-precision comparison of transistor on-resistance under different gate drive voltages with a delay time of nanoseconds.

[0052] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0053] Those skilled in the art will readily understand that the present invention encompasses any combination of the components described in the Summary and Detailed Description of the Invention and the accompanying drawings. Due to space limitations and for the sake of clarity, not all of the various solutions resulting from these combinations are described. Any modifications, equivalent substitutions, and improvements within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0054] Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments without departing from the principles and intent of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision comparison method for transistor on-resistance, characterized in that: include: The DC voltage adjustment module generates and outputs a DC voltage that can quickly adjust the value and has load capacity. ; The gate drive module is based on the DC voltage and pulse voltage Generate and output pulse signals with rapidly adjustable voltage ; Apply a pulse signal to the transistor under test through the power module , and based on the pulse signal Measure the on-resistance of the transistor under test under gate drive voltage; Switching the gate drive voltage within a microsecond to nanosecond delay based on the pulse signal Measure the on-resistance of the transistor under test under switching gate drive voltage, and achieve high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages.

2. The high-precision comparison method for transistor on-resistance according to claim 1, wherein: The DC voltage adjustment module includes a digital-to-analog conversion chip and an operational amplifier. The digital-to-analog conversion chip and the operational amplifier are connected by a DC voltage. The output end of the digital-to-analog conversion chip is connected to the operational amplifier, and the output end of the operational amplifier is connected to the gate driving module.

3. The high-precision comparison method for transistor on-resistance according to claim 2, wherein: The gate drive module includes a first CMOS inverter and a second CMOS inverter. The output end of the operational amplifier is connected to the power pin of the first CMOS inverter and the power pin of the second CMOS inverter. The input pin of the first CMOS inverter is connected to a pulse voltage. The output pin of the first CMOS inverter is connected to the input pin of the second CMOS inverter, the ground pin of the first CMOS inverter and the ground pin of the second CMOS inverter are both grounded, and the output pin of the second CMOS inverter is connected to the power module.

4. The high-precision comparison method for transistor on-resistance according to claim 3, wherein: The power module includes a freewheeling diode and a power inductor. The gate of the transistor to be tested is connected to the output pin of the second CMOS inverter. The drain of the transistor to be tested is respectively connected to the positive electrode of the freewheeling diode and one end of the power inductor. The negative electrode of the freewheeling diode and the other end of the power inductor are connected to the positive electrode of the high-voltage power supply. The source of the transistor to be tested and the negative electrode of the high-voltage power supply are grounded. A voltage-stabilizing capacitor is connected in parallel to the high-voltage power supply.

5. The high-precision comparison method for transistor on-resistance according to claim 1 or 2, characterized in that: The digital-to-analog conversion chip of the DC voltage adjustment module is controlled by digital signals to generate and output a high-speed adjustable DC voltage. Subsequently, the operational amplifier is operated in voltage follower mode to convert the DC signal output by the digital-to-analog conversion chip into a DC voltage that can carry a load. .

6. The high-precision comparison method for transistor on-resistance according to claim 1 or 3, characterized in that: The first CMOS inverter and the second CMOS inverter of the gate driving module form a push-pull output structure, and the adjustable DC voltage output by the DC voltage adjustment module is Power supply, through pulse voltage Control the opening and closing of the gate drive module voltage output, and adjust the DC voltage and pulse voltage A pulse signal that controls the gate drive module output voltage and can quickly adjust .

7. The high-precision comparison method for transistor on-resistance according to claim 6, wherein: The switching gate drive voltage is based on the pulse signal Measuring the on-resistance of transistors under switching gate drive voltages to achieve high-precision comparison of transistor on-resistances under different gate drive voltages includes: switching the gate drive voltage of the transistor to be tested multiple times under a fixed drain voltage stress, and Real-time monitoring of the change data and change curve of the on-resistance of the transistor under test that has not yet degraded to a steady state under different gate drive voltages.

8. The high-precision comparison method for transistor on-resistance according to claim 7, wherein: The multiple switching of the gate driving voltage of the transistor under test includes periodically switching the gate driving voltage of the transistor under test, incrementally switching the gate driving voltage of the transistor under test, or decrementally switching the gate driving voltage of the transistor under test.

9. The high-precision comparison method for transistor on-resistance according to claim 3, wherein: In the gate driving module, the first CMOS inverter and the second CMOS inverter form a push-pull output structure, and the lower transistors of the first CMOS inverter and the second CMOS inverter are silicon-based field effect transistors or gallium nitride-based N-channel enhancement transistors.

10. The high-precision comparison method for transistor on-resistance according to claim 9, wherein: When the lower tubes of the first CMOS inverter and the second CMOS inverter are silicon-based field effect transistors, their threshold voltages are 2 to 4V, and the pulse voltage The high level is about 5V; when the lower tubes of the first CMOS inverter and the second CMOS inverter are gallium nitride-based N-channel enhancement transistors, their threshold voltages are 1 to 2V, and the pulse voltage The high level is about 3.3V.

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