Test mode control circuit, method and chip

Abstract

The invention belongs to the field of chip testing, and provides a test mode control circuit and method and a chip. The circuit comprises a data clock width identification module, a data time sequence generation module and a test control module, wherein the data time sequence generation module is respectively connected with the data clock width identification module and the test control module. The data clock width identification module receives test mode data and a clock single-line signal through an input / output pin of the chip, and processes the test mode data and the clock single-line signal to obtain a first signal; the data time sequence generation module receives test mode data and a clock single-line signal through an input / output pin of the chip, and processes the first signal according to the test mode data and the clock single-line signal to obtain a second signal; and the test control module detects the second signal, and if the second signal is matched with a preset signal, the chip enters a test mode. According to the invention, through a single-line transmission technology, the chip can enter a test mode only by multiplexing one input / output pin of the chip.

Description

Technical Field

[0001] The present application belongs to the field of chip testing technology, and in particular relates to a test mode control circuit, method and chip. Background Art

[0002] As integrated circuits (ICs) continue to increase in complexity and integration, design for testability (DFT) has become an essential component of modern chip design processes during automated test equipment (ATE) testing. Effective DFT techniques, particularly access and control of internal chip functional modules, rely heavily on the ability to reliably and efficiently place the chip into specific test modes.

[0003] Currently, the industry's commonly adopted solution for entering test mode is to reuse multiple functional input / output (I / O) pins on a chip and configure these pins as "test mode entry control pins" under specific conditions (such as during the power-on reset phase or a specific signal sequence combination). However, entering test mode by reusing multiple functional I / O pins has a series of significant and difficult-to-overcome disadvantages, such as increased test complexity and cost, higher ATE costs, increased test fixture complexity and cost, longer test times, increased debugging difficulty, and reliability risks. These issues seriously restrict chip design efficiency, test cost control, and the competitiveness of the final product.

[0004] Therefore, the solution of entering test mode by multiplexing multiple functional I / O pins has become a key bottleneck restricting the improvement of chip integration, test cost optimization and system reliability, and a better solution is urgently needed. Summary of the Invention

[0005] The embodiments of the present application provide a test mode control circuit, method and chip that can solve a series of problems existing in the solution of implementing the test mode by multiplexing multiple functional I / O pins, thereby breaking through the constraints on chip integration, test cost and system reliability.

[0006] In a first aspect, an embodiment of the present application provides a test mode control circuit, comprising a data clock width detection module, a data timing generation module, and a test control module, wherein the data timing generation module is connected to the data clock width detection module and the test control module respectively; The data clock width detection module is used to receive test mode data and a single-line clock signal through an input / output pin of the chip, and process the test mode data and the single-line clock signal to obtain a first signal; the data timing generation module is used to receive test mode data and a single-line clock signal through an input / output pin of the chip, and process the first signal according to the test mode data and the single-line clock signal to obtain a second signal; the test control module is used to detect the second signal. If the second signal matches the preset signal, it indicates that the chip has entered the test mode.

[0007] In a possible implementation of the first aspect, the test mode control circuit further includes a signal gating module, the test control module is connected to the signal gating module, and the test control module and the signal gating module are respectively used to connect to a plurality of circuits to be tested; After the chip enters the test mode, the data clock width detection module is also used to receive test data and a single-line clock signal through an input and output pin of the chip, and process the test data and the single-line clock signal to obtain multiple third signals; the data timing generation module is also used to receive test data and a single-line clock signal through an input and output pin of the chip, and process the multiple third signals in sequence according to the test data and the single-line clock signal to obtain multiple fourth signals; the test control module is also used to generate an enable signal and a selection signal according to the multiple fourth signals, the enable signal is used to control the operation of all circuits to be tested, and the selection signal is used to control multiple circuits to be tested to output the signals to be tested in sequence; the signal selection module is used to output the multiple signals to be tested in sequence according to the enable signal and the selection signal.

[0008] In a possible implementation of the first aspect, the data clock width detection module includes a signal edge detection unit, a pulse width measurement unit, and a pulse width threshold judgment unit, wherein the pulse width measurement unit is connected to the signal edge detection unit and the pulse width threshold judgment unit, respectively, and the pulse width threshold judgment unit is connected to the data timing generation module; The signal edge detection unit is used to receive an input signal through an input / output pin of the chip, detect the rising edge and falling edge of the input signal, output a first detection signal when each rising edge of the input signal is detected, and output a second detection signal when each falling edge of the input signal is detected; wherein, the input signal is test mode data and a single-line clock signal or test data and a single-line clock signal; the pulse width measurement unit is used to start counting in sequence according to each of the first detection signals, and stop counting according to each corresponding second detection signal to obtain multiple pulse width values; the pulse width threshold judgment unit is used to judge each of the pulse width values, and output "1" when the pulse width value is greater than the first threshold, and output "0" when the pulse width value is less than the second threshold.

[0009] In a possible implementation of the first aspect, the data clock width detection module further includes a noise filtering unit, and the noise filtering unit is connected to the signal edge detection unit; The noise filtering unit is used to receive an input signal through an input / output pin of the chip and perform noise filtering on the input signal.

[0010] In a possible implementation of the first aspect, the data timing generation module includes multiple D flip-flops, the clock input end of each D flip-flop receives an input signal through an input / output pin of a chip, the inverting output end of each D flip-flop is respectively connected to the test control module, the data input end of the first D flip-flop is connected to the data clock width detection module, and the positive output end of each D flip-flop is respectively connected to the data input end of the next D flip-flop and the test control module, wherein the input signal is a single-line signal of test mode data and clock or a single-line signal of test data and clock.

[0011] In a possible implementation of the first aspect, the test control module includes a data decoding unit and a data conversion unit; the data decoding unit is connected to the data timing generation module and the data conversion unit respectively; The data decoding unit is configured to receive a second signal, decode the second signal to obtain a first decoded signal, and detect the first decoded signal. If the first decoded signal matches the preset signal, it indicates that the chip has entered a test mode. After the chip enters the test mode, the data decoding unit is further used to receive multiple fourth signals, and decode the multiple fourth signals in sequence to obtain multiple second decoding signals; the data conversion unit is used to convert the multiple second decoding signals in sequence, and output enable signals and selection signals according to the first-in-first-out principle.

[0012] In a possible implementation of the first aspect, the signal selection module includes a first switch unit and multiple second switch units, the control end of the first switch unit is connected to the test control module to receive the enable signal, the first end of the first switch unit is used to connect to the automatic test equipment through another input and output pin of the chip, the second end of the first switch unit is connected to the first ends of multiple second switch units, the control end of each second switch unit is connected to the test control module to receive the selection signal, and the second ends of the multiple second switch units are connected one-to-one with the multiple circuits to be tested.

[0013] In a second aspect, an embodiment of the present application provides a test mode control method, applied to the test mode control circuit according to any one of the first aspects, comprising: The data clock width detection module receives the test mode data and the clock single-line signal through an input / output pin of the chip, and processes the test mode data and the clock single-line signal to obtain a first signal, where the first signal is a serial signal; The data timing generation module receives test mode data and a clock single-line signal through an input / output pin of the chip, processes the first signal according to the test mode data and the clock single-line signal, and obtains a second signal, where the second signal is a parallel signal; The test control module detects the second signal, and if the second signal matches a preset signal, it indicates that the chip enters the test mode.

[0014] In a possible implementation of the second aspect, the method further includes: After the chip enters the test mode, the data clock width detection module further receives test data and a clock single-line signal through an input / output pin of the chip, and processes the test data and the clock single-line signal to obtain a plurality of third signals, where the third signals are serial signals; The data timing generation module further receives test data and a clock single-line signal through an input / output pin of the chip, and processes the plurality of third signals in sequence according to the test data and the clock single-line signal to obtain a plurality of fourth signals, wherein the fourth signals are parallel signals; The test control module generates an enable signal and a strobe signal according to the plurality of fourth signals, wherein the enable signal is used to control the operation of all circuits under test, and the strobe signal is used to control the plurality of circuits under test to sequentially output signals under test, and the strobe signal is a parallel signal; The signal gating module outputs a plurality of signals to be tested in sequence according to the enable signal and the gating signal.

[0015] In a third aspect, an embodiment of the present application provides a chip comprising the test mode control circuit described in any one of the first aspects.

[0016] Compared with the prior art, the embodiments of the present application have the following beneficial effects: An embodiment of the present application provides a test mode control circuit, including a data clock width detection module, a data timing generation module and a test control module, wherein the data timing generation module is connected to the data clock width detection module and the test control module respectively.

[0017] The data clock width detection module is used to receive test mode data and a single-line clock signal through an input / output pin of the chip, and process the test mode data and the single-line clock signal to obtain a first signal; the data timing generation module is used to receive test mode data and a single-line clock signal through an input / output pin of the chip, and process the first signal according to the test mode data and the single-line clock signal to obtain a second signal; the test control module is used to detect the second signal. If the second signal matches the preset signal, it indicates that the chip has entered the test mode.

[0018] The test mode control circuit proposed in this application uses single-line transmission technology to reliably enter the DFT test mode by reusing only one of the chip's input and output pins. This eliminates the need for a dedicated test port, significantly reducing the number of ports. This reduces chip size and design costs, making the chip more versatile and adaptable. Compared to traditional multi-pin multiplexing solutions, this application uses single-line transmission technology to reuse only one of the chip's input and output pins, reducing test complexity, ATE costs, and test fixture complexity. It also shortens test time, reduces debugging difficulty, and reduces reliability risks, thereby breaking through the constraints on chip integration, test costs, and system reliability.

[0019] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a principle block diagram of a test mode control circuit provided in one embodiment of the present application; Figure 2 is a principle block diagram of a test mode control circuit provided by another embodiment of the present application; Figure 3 is a principle block diagram of a test mode control circuit provided by another embodiment of the present application; Figure 4 is a principle block diagram of a test mode control circuit provided by another embodiment of the present application; Figure 5 1 is a circuit connection diagram of a test mode control circuit provided in one embodiment of the present application; Figure 6 is a principle block diagram of a test mode control circuit provided by another embodiment of the present application; Figure 7 is a principle block diagram of a test mode control circuit provided by another embodiment of the present application; Figure 8 is a signal waveform diagram of a test mode control circuit provided by an embodiment of the present application; Figure 9 is a signal waveform diagram of a test mode control circuit provided by another embodiment of the present application; Figure 10 This is a flow chart of a test mode control method provided by an embodiment of the present application; Figure 11 It is a flowchart of a test mode control method provided in another embodiment of the present application.

[0022] In the figure: 10, data clock width detection module; 11, signal edge detection unit; 12, pulse width measurement unit; 13, pulse width threshold judgment unit; 14, noise filtering unit; 20, data timing generation module; 30, test control module; 31, data decoding unit; 32, data conversion unit; 40, signal selection module; 41, first switch unit; 42, second switch unit; 50, circuit to be tested; 60, automatic test equipment. DETAILED DESCRIPTION

[0023] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0024] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0025] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0026] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0027] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Currently, the industry's commonly used solution for entering test mode is to reuse multiple functional I / O pins on the chip and configure them as "test mode entry control pins" under specific conditions. However, entering test mode by reused multiple functional I / O pins has a series of significant and difficult-to-overcome drawbacks, such as: (1) Increased test complexity and cost: The voltage levels or timing sequences of multiple functional I / O pins must be precisely controlled simultaneously to reliably trigger the test mode, which is more difficult to achieve when the chip has fewer pins. (2) Increase ATE cost: The number of drive / compare channels required by ATE is significantly increased, which in turn increases the expensive ATE resource usage cost; (3) Increased complexity and cost of test fixtures: The design, manufacturing, and maintenance costs of test boards and probe cards increase significantly due to the need to ensure the integrity of multiple signal paths (signal quality, timing synchronization), and complex multi-signal wiring also increases the failure rate of the fixture; (4) Extended test time and increased debugging difficulty: Establishing, maintaining, and verifying multi-signal combinations requires longer test time, and diagnosing the cause of failure (for example, determining which pin signal does not meet the requirements) is also more complex and time-consuming; (5) Reliability risk: The specific multi-pin combination used to enter the test mode may be triggered by unexpected signal noise, interference, or a specific operation sequence when the chip is operating normally, causing the chip to enter the test mode unexpectedly, which in turn may cause system dysfunction, data errors, and even security risks. To avoid such combination conflicts, additional design constraints and stricter verification are required, which will increase the design burden. The above problems seriously restrict the chip design efficiency, test cost control, and the competitiveness of the final product.

[0030] Therefore, the solution of entering test mode by multiplexing multiple functional I / O pins has become a key bottleneck restricting the improvement of chip integration, test cost optimization and system reliability, and a better solution is urgently needed.

[0031] In view of the above problems, the present invention provides a test mode control circuit for use in a chip, such as Figure 1 As shown, the test mode control circuit includes a data clock width detection module 10, a data timing generation module 20 and a test control module 30. The data timing generation module 20 is connected to the data clock width detection module 10 and the test control module 30 respectively.

[0032] Specifically, the data clock width detection module 10 is used to receive test mode data and a single-line clock signal via a chip input / output pin (I / O pin), and processes the test mode data and the single-line clock signal by identifying the width of the high level and converting it to "1" or "0" to obtain a first signal, which is a serial signal. The data timing generation module 20 is used to receive test mode data and a single-line clock signal via a chip input / output pin, and processes the first signal based on the test mode data and the single-line clock signal to obtain a second signal, which is a parallel signal. The data timing generation module 20 thus achieves the conversion from serial to parallel signals. The test control module 30 is used to detect the second signal. If the second signal matches a preset signal, it indicates that the chip has entered test mode. The preset signal is manually set and can be adjusted according to actual needs.

[0033] The test mode control circuit proposed in this application uses single-line transmission technology to reliably enter the DFT test mode by reusing only one of the chip's input and output pins. This eliminates the need for a dedicated test port, significantly reducing the number of ports. This reduces chip size and design costs, making the chip more versatile and adaptable. Compared to traditional multi-pin multiplexing solutions, this application uses single-line transmission technology to reuse only one of the chip's input and output pins, reducing test complexity, ATE costs, and test fixture complexity. It also shortens test time, reduces debugging difficulty, and reduces reliability risks, thereby breaking through the constraints on chip integration, test costs, and system reliability.

[0034] In some embodiments, as Figure 2 As shown, the test mode control circuit also includes a signal gating module 40, the test control module 30 is connected to the signal gating module 40, the test control module 30 and the signal gating module 40 are respectively used to connect to multiple circuits under test 50, and the signal gating module 40 is also used to connect to an automatic test equipment 60 through another input and output pin (I / O pin) of the chip.

[0035] Specifically, after the chip enters test mode, the data clock width detection module 10 is further configured to receive test data and a single-line clock signal via one of the chip's input / output pins and process the test data and single-line clock signals by identifying the width of the high-level signals and converting them to "1" or "0," thereby generating multiple third signals, which are serial signals. Since the test data and single-line clock signals contain multiple selection signals corresponding to the circuits under test 50 after the chip enters test mode, the data clock width detection module 10 outputs multiple third signals after processing. The data timing generation module 20 is further configured to receive test data and a single-line clock signal via one of the chip's input / output pins and sequentially process the multiple third signals based on the test data and the single-line clock signal to generate multiple fourth signals, which are parallel signals. The data timing generation module 20 thereby achieves serial-to-parallel conversion. The test control module 30 is further configured to generate an enable signal test_enable and a strobe signal test_ctrl[n:0] based on the multiple fourth signals, where n is a natural number greater than 0. The enable signal test_enable is used to control the operation of all circuits under test 50. The number of bits of the strobe signal test_ctrl[n:0] is related to the number of circuits under test 50. For example, when the number of circuits under test 50 is 16, the number of bits of the strobe signal test_ctrl[n:0] is 4. This strobe signal test_ctrl[n:0] is used to control the multiple circuits under test 50 to sequentially output the test signals. The signal strobe module 40 is used to sequentially output the multiple test signals based on the enable signal test_enable and the strobe signal test_ctrl[n:0], so that the automatic test equipment 60 can test the multiple circuits under test 50 in sequence.

[0036] In some embodiments, as Figure 3 As shown, the data clock width detection module 10 includes a signal edge detection unit 11, a pulse width measurement unit 12 and a pulse width threshold judgment unit 13. The pulse width measurement unit 12 is connected to the signal edge detection unit 11 and the pulse width threshold judgment unit 13 respectively, and the pulse width threshold judgment unit 13 is connected to the data timing generation module 20.

[0037] Specifically, the signal edge detection unit 11 is used to receive an input signal through an input / output pin of the chip, detect the rising and falling edges of the input signal, output a first detection signal when each rising edge of the input signal is detected, and output a second detection signal when each falling edge of the input signal is detected; wherein the input signal is a test mode data and a single-line clock signal or a test data and a single-line clock signal. The pulse width measurement unit 12 is used to start counting in sequence according to each first detection signal and stop counting according to each corresponding second detection signal to obtain multiple pulse width values. The pulse width threshold judgment unit 13 is used to judge each pulse width value, output "1" when the pulse width value is greater than the first threshold, and output "0" when the pulse width value is less than the second threshold, and finally output a serial signal consisting of "0" and "1". wherein the first threshold and the second threshold are set internally by the chip.

[0038] In some embodiments, as Figure 4 As shown, the data clock width detection module 10 further includes a noise filtering unit 14 , which is connected to the signal edge detection unit 11 .

[0039] Specifically, the noise filtering unit 14 is used to receive an input signal through an input / output pin of the chip and perform noise filtering on the input signal to ensure the accuracy of the input signal.

[0040] In some embodiments, as Figure 5 As shown, the data timing generation module 20 includes a plurality of D flip-flops. The number of D flip-flops is related to the number of circuits to be tested 50. For example, when the number of circuits to be tested 50 is 16, the number of D flip-flops is 5. The clock input terminal CLK of each D flip-flop receives an input signal through an input / output pin of the chip. The inverting output terminal of each D flip-flop They are respectively connected to the test control module 30, the data input terminal D of the first D flip-flop is connected to the data clock width detection module 10, and the positive phase output terminal Q of each D flip-flop is respectively connected to the data input terminal D of the next D flip-flop and the test control module 30, wherein the input signal is a single-line signal of test mode data and clock or a single-line signal of test data and clock.

[0041] Specifically, the data timing generation module 20 converts the serial signal output by the data clock width detection module 10 into a parallel signal through a plurality of D flip-flops. The parallel signal includes Q[n+1:0] and QN[n+1:0].

[0042] In some embodiments, as Figure 6 As shown, the test control module 30 includes a data decoding unit 31 and a data conversion unit 32; the data decoding unit 31 is connected to the data timing generation module 20 and the data conversion unit 32 respectively.

[0043] Specifically, the data decoding unit 31 is used to receive a second signal, the second signal includes Q[n+1:0] and QN[n+1:0], and decode the second signal (Q[n+1:0] in the second signal) to obtain a first decoded signal, and detect the first decoded signal. If the first decoded signal matches the preset signal, it indicates that the chip has entered the test mode.

[0044] After the chip enters test mode, the data decoding unit 31 is further configured to receive multiple fourth signals, including Q[n+1:0] and QN[n+1:0], and sequentially decode the multiple fourth signals (including Q[n+1:0] and QN[n+1:0] in the multiple fourth signals) to obtain multiple second decoded signals. The data conversion unit 32 is configured to sequentially convert the multiple second decoded signals and output an enable signal test_enable and a select signal test_ctrl[n:0] according to a first-in, first-out (FIFO) principle.

[0045] In some embodiments, as Figure 7 As shown, the signal selection module 40 includes a first switch unit 41 and multiple second switch units 42. The control end of the first switch unit 41 is connected to the test control module 30 and receives the enable signal test_enable. The first end of the first switch unit 41 is used to connect to the automatic test equipment 60 through another input and output pin of the chip. The second end of the first switch unit 41 is connected to the first ends of the multiple second switch units 42. The control end of each second switch unit 42 is connected to the test control module 30 and receives the selection signal test_ctrl[n:0]. The second ends of the multiple second switch units 42 are connected one-to-one with the multiple circuits to be tested 50.

[0046] Specifically, after the chip enters the test mode, the test control module 30 outputs an enable signal test_enable and a selection signal test_ctrl[n:0]. The enable signal test_enable controls the first switch unit 41 to be turned on, and the second switch unit 42 is controlled by the selection signal test_ctrl[n:0]. When the selection signal test_ctrl[n:0] controls the first circuit under test 50 to output a test signal, the second switch unit 42 corresponding to the first circuit under test 50 is turned on according to the selection signal test_ctrl[n:0], so that the test signal output by the first circuit under test 50 is transmitted to the automatic test equipment 60, so that the automatic test equipment 60 tests the first circuit under test 50. The selection principle of the remaining circuits under test 50 is the same as above.

[0047] Example 1 Assuming that the number of circuits under test 50 is 16, the number of D flip-flops in the data timing generation module 20 is 5, and the number of bits of the selection signal test_ctrl[n:0] output by the test control module 30 is 4 bits, namely test_ctrl[3:0].

[0048] The data clock width detection module 10 receives the test mode data and the clock single-line signal through an input and output pin of the chip. The waveforms of the test mode data and the clock single-line signal are as follows: Figure 8 As shown, it consists of wide high-level pulses numbered 1, 3, and 5, and narrow high-level pulses numbered 2 and 4. The data clock width detection module 10 processes the test mode data and the single-line clock signal by identifying the width of the high-level pulses and converting them to "1" or "0" to generate a first signal. The data timing generation module 20 receives the test mode data and the single-line clock signal via an input / output pin of the chip and processes the first signal based on the test mode data and the single-line clock signal to generate a second signal, which includes Q[4:0] and QN[4:0]. The test control module 30 detects the second signal. The specific detection process is as follows: the data decoding unit 31 decodes the second signal (only Q[4:0] in the second signal) to obtain 10101. The last digit "1" indicates that the test mode data and the single-line clock signal have been transmitted. 10101 is then tested. If 10101 matches the preset signal, the chip enters test mode.

[0049] After the chip enters the test mode, the data clock width detection module 10 receives the test data and the clock single-line signal through an input and output pin of the chip. The waveforms of the test data and the clock single-line signal are as follows: Figure 9As shown, it includes 16 groups of selection signals. The first group of selection signals consists of a wide high-level pulse, numbered 10, and narrow high-level pulses, numbered 6, 7, 8, and 9. Test data and a single-line clock signal are processed by identifying the width of the high-level pulses and converting them to "1" or "0," generating 16 third signals. The data timing generation module 20 receives test data and a single-line clock signal via an input / output pin of the chip. Based on the test data and the single-line clock signal, it sequentially processes the 16 third signals to generate 16 fourth signals, including Q[4:0] and QN[4:0]. The test control module 30 generates an enable signal test_enable and a selection signal test_ctrl[3:0] according to the 16 fourth signals. The specific processing process is: first, the 16 fourth signals (Q[4:0] and QN[4:0] in the 16 fourth signals) are decoded in sequence by the data decoding unit 31 to obtain 16 second decoded signals, and then the 16 second decoded signals are converted in sequence by the data conversion unit 32, and the enable signal test_enable and the selection signal test_ctrl[3:0] are output according to the FIFO principle.

[0050] For the first set of selection signals, after processing, the selection signal test_ctrl[3:0] is 0000, which is used to select the first circuit under test 50, and the enable signal test_enable becomes high, which is used to enable all circuits under test 50. Similarly, by changing the combination of wide pulse high level and narrow pulse high level, a total of 16 digital signals from 0000 to 1111 can be generated, namely the selection signal test_ctrl[3:0], which is used to select 16 circuits under test in sequence. Finally, the 16 test signals are output in sequence through the signal selection module 40, so that the automatic test equipment 60 can test the 16 circuits under test 50 in sequence. It should be noted that the last digit corresponding to each set of selection signals is "1", indicating that the selection signal has been sent.

[0051] If more or fewer circuits under test 50 need to be tested, this can be achieved by increasing or decreasing the number of D flip-flops in the data timing generation module 20 .

[0052] The present application also provides a test mode control method, such as Figure 10 As shown, the test mode control method includes S1-S3.

[0053] S1. The data clock width detection module receives test mode data and a clock single-line signal through an input / output pin of the chip, processes the test mode data and the clock single-line signal, and obtains a first signal, which is a serial signal.

[0054] Specifically, the data clock width detection module detects the width of the high level in the test mode data and the clock single-line signal, and converts it into "1" or "0" to obtain the first signal.

[0055] S2. The data timing generation module receives the test mode data and the clock single-line signal through an input / output pin of the chip, processes the first signal according to the test mode data and the clock single-line signal, and obtains a second signal, which is a parallel signal.

[0056] Specifically, the data timing generation module converts the serial signal output by the data clock width detection module into a parallel signal according to the test mode data and the clock single-line signal.

[0057] S3. The test control module detects the second signal. If the second signal matches a preset signal, it indicates that the chip has entered the test mode. The preset signal is manually set and can be adjusted according to actual needs.

[0058] Specifically, the test control module determines whether the chip enters the test mode by detecting the second signal: when the second signal matches the preset signal, it indicates that the chip enters the test mode.

[0059] The test mode control method proposed in this application uses single-line transmission technology to reliably enter the DFT test mode by reusing only one of the chip's input and output pins. This eliminates the need for a dedicated test port, significantly reducing the number of ports and thus reducing chip size and design costs, making the chip more adaptable and versatile. Compared to traditional multi-pin multiplexing solutions, this application uses single-line transmission technology to reuse only one of the chip's input and output pins, reducing not only test complexity, ATE costs, and test fixture complexity, but also test time, debugging difficulty, and reliability risks, thereby breaking through the constraints on chip integration, test costs, and system reliability.

[0060] In some embodiments, as Figure 11 As shown, the test mode control method further includes S4-S7.

[0061] S4. After the chip enters the test mode, the data clock width detection module also receives test data and a clock single-line signal through an input and output pin of the chip, and processes the test data and the clock single-line signal to obtain multiple third signals, which are serial signals.

[0062] Specifically, after the chip enters test mode, the test data and clock single-line signal contains multiple selection signals that correspond one-to-one to the circuits under test. The data clock width detection module identifies the width of the high level in this signal and converts it to "1" or "0," thereby generating a third signal that corresponds one-to-one to the selection signal.

[0063] S5. The data timing generation module also receives test data and a single-line clock signal through an input / output pin of the chip, and processes the multiple third signals in sequence according to the test data and the single-line clock signal to obtain multiple fourth signals, which are parallel signals.

[0064] Specifically, the data timing generation module converts the multiple serial signals output by the data clock width detection module into parallel signals in sequence according to the test data and the clock single-line signal.

[0065] S6. The test control module generates an enable signal and a strobe signal according to the multiple fourth signals. The enable signal is used to control the operation of all circuits under test. The strobe signal is used to control the multiple circuits under test to output the test signals in sequence. The strobe signal is a parallel signal.

[0066] Specifically, after the chip enters the test mode, the test control module generates an enable signal based on multiple fourth signals, which controls all circuits to be tested to enter the working state; it also generates a selection signal, the number of bits of the selection signal is related to the number of circuits to be tested, and through different high and low level combinations, controls multiple circuits to be tested to output the test signals in sequence.

[0067] S7. The signal gating module outputs the multiple signals to be tested in sequence according to the enable signal and the gating signal.

[0068] Specifically, the signal gating module starts working under the control of the enable signal, and outputs multiple test signals in sequence according to the timing logic of the gating signal, so that the automatic test equipment can test the multiple test circuits one by one.

[0069] The present application also provides a chip including the test mode control circuit described above. Since the chip provided in the present application adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0070] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0071] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A test mode control circuit, characterized in that: It includes a data clock width detection module, a data timing generation module and a test control module, wherein the data timing generation module is connected to the data clock width detection module and the test control module respectively; The data clock width detection module is used to receive test mode data and a single-line clock signal through an input / output pin of the chip, and process the test mode data and the single-line clock signal to obtain a first signal; the data timing generation module is used to receive test mode data and a single-line clock signal through an input / output pin of the chip, and process the first signal according to the test mode data and the single-line clock signal to obtain a second signal; the test control module is used to detect the second signal. If the second signal matches the preset signal, it indicates that the chip has entered the test mode.

2. The test mode control circuit according to claim 1, wherein: The test mode control circuit further includes a signal gating module, the test control module is connected to the signal gating module, and the test control module and the signal gating module are respectively used to connect to a plurality of circuits to be tested; After the chip enters the test mode, the data clock width detection module is also used to receive test data and a single-line clock signal through an input and output pin of the chip, and process the test data and the single-line clock signal to obtain multiple third signals; the data timing generation module is also used to receive test data and a single-line clock signal through an input and output pin of the chip, and process the multiple third signals in sequence according to the test data and the single-line clock signal to obtain multiple fourth signals; the test control module is also used to generate an enable signal and a selection signal according to the multiple fourth signals, the enable signal is used to control the operation of all circuits to be tested, and the selection signal is used to control multiple circuits to be tested to output the signals to be tested in sequence; the signal selection module is used to output the multiple signals to be tested in sequence according to the enable signal and the selection signal.

3. The test mode control circuit according to claim 1 or 2, characterized in that: The data clock width detection module includes a signal edge detection unit, a pulse width measurement unit and a pulse width threshold judgment unit, wherein the pulse width measurement unit is connected to the signal edge detection unit and the pulse width threshold judgment unit respectively, and the pulse width threshold judgment unit is connected to the data timing generation module; The signal edge detection unit is used to receive an input signal through an input / output pin of the chip, detect the rising edge and falling edge of the input signal, output a first detection signal when each rising edge of the input signal is detected, and output a second detection signal when each falling edge of the input signal is detected; wherein, the input signal is test mode data and a single-line clock signal or test data and a single-line clock signal; the pulse width measurement unit is used to start counting in sequence according to each first detection signal, and stop counting according to each corresponding second detection signal to obtain multiple pulse width values; the pulse width threshold judgment unit is used to judge each of the pulse width values, and output "1" when the pulse width value is greater than the first threshold, and output "0" when the pulse width value is less than the second threshold.

4. The test mode control circuit according to claim 3, wherein: The data clock width detection module further includes a noise filtering unit, and the noise filtering unit is connected to the signal edge detection unit; The noise filtering unit is used to receive an input signal through an input / output pin of the chip and perform noise filtering on the input signal.

5. The test mode control circuit according to claim 1 or 2, characterized in that: The data timing generation module includes multiple D flip-flops, the clock input end of each D flip-flop receives an input signal through an input / output pin of the chip, the inverting output end of each D flip-flop is respectively connected to the test control module, the data input end of the first D flip-flop is connected to the data clock width detection module, and the positive output end of each D flip-flop is respectively connected to the data input end of the next D flip-flop and the test control module, wherein the input signal is a single-line signal of test mode data and clock or a single-line signal of test data and clock.

6. The test mode control circuit according to claim 2, wherein: The test control module includes a data decoding unit and a data conversion unit; the data decoding unit is connected to the data timing generation module and the data conversion unit respectively; The data decoding unit is configured to receive a second signal, decode the second signal to obtain a first decoded signal, and detect the first decoded signal. If the first decoded signal matches the preset signal, it indicates that the chip has entered a test mode. After the chip enters the test mode, the data decoding unit is further used to receive multiple fourth signals, and decode the multiple fourth signals in sequence to obtain multiple second decoding signals; the data conversion unit is used to convert the multiple second decoding signals in sequence, and output enable signals and selection signals according to the first-in-first-out principle.

7. The test mode control circuit according to claim 2, wherein: The signal selection module includes a first switch unit and multiple second switch units. The control end of the first switch unit is connected to the test control module to receive the enable signal. The first end of the first switch unit is used to connect to the automatic test equipment through another input and output pin of the chip. The second end of the first switch unit is connected to the first ends of multiple second switch units. The control end of each second switch unit is connected to the test control module to receive the selection signal. The second ends of the multiple second switch units are connected one-to-one with the multiple circuits to be tested.

8. A test mode control method, applied to the test mode control circuit according to any one of claims 1 to 7, characterized in that: include: The data clock width detection module receives the test mode data and the clock single-line signal through an input / output pin of the chip, and processes the test mode data and the clock single-line signal to obtain a first signal, where the first signal is a serial signal; The data timing generation module receives test mode data and a clock single-line signal through an input / output pin of the chip, processes the first signal according to the test mode data and the clock single-line signal, and obtains a second signal, where the second signal is a parallel signal; The test control module detects the second signal, and if the second signal matches a preset signal, it indicates that the chip enters the test mode.

9. The test mode control method according to claim 8, wherein: The method further comprises: After the chip enters the test mode, the data clock width detection module further receives test data and a clock single-line signal through an input / output pin of the chip, and processes the test data and the clock single-line signal to obtain a plurality of third signals, where the third signals are serial signals; The data timing generation module further receives test data and a clock single-line signal through an input / output pin of the chip, and processes the plurality of third signals in sequence according to the test data and the clock single-line signal to obtain a plurality of fourth signals, wherein the fourth signals are parallel signals; The test control module generates an enable signal and a strobe signal according to the plurality of fourth signals, wherein the enable signal is used to control the operation of all circuits under test, and the strobe signal is used to control the plurality of circuits under test to sequentially output signals under test, and the strobe signal is a parallel signal; The signal gating module outputs a plurality of signals to be tested in sequence according to the enable signal and the gating signal.

10. A chip, characterized in that: The test mode control circuit comprises the test mode control circuit according to any one of claims 1 to 7.

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