Photonic device with extended metal layer and method

Abstract

The invention relates to a photonic device with an extended metal layer and a method. The photonic device includes a substrate, photonic integrated circuit structures on the substrate, and a redistribution structure over and coupled to the one or more photonic integrated circuit structures. The redistribution structure includes one or more metal layers and one or more dielectric layers. A first one of the one or more metal layers is exposed on a top side of the redistribution structure through a pad of the first one of the one or more dielectric layers and an edge connection opening. The edge connection opening is positioned such that at least a portion of the periphery of the photonic device is closer to the edge connection opening than the pad opening. The edge connection opening may be diced and an electrical connection is formed via the first metal layer and / or a diced portion along a sidewall of the photonic device.

Description

Technical Field

[0001] Aspects of the present disclosure relate to photonic integrated circuit (PIC) devices and methods of fabricating photonic integrated circuit (PIC) devices. Background Art

[0002] Silicon photonic integrated circuits (Siph PICs) are typically manufactured using silicon-on-insulator (SOI) wafers that are, for example, approximately 750 micrometers (μm) thick. In such wafers, the functional devices of the Siph PIC (e.g., optical and electronic devices) are located within a few micrometers (μm) from the top surface of the Siph PIC, which may include semiconductor layers (Si, Ge, etc.), metal layers, and dielectric layers. The semiconductor layers, metal layers, and dielectric layers may form various photonic and / or electronic integrated circuit structures. In addition, the metal and dielectric layers may provide electrical paths for the photonic and / or electronic integrated circuit structures. The remaining micrometers below the above layers (e.g., the remaining >95% of the wafer) may not include metal layers, thereby limiting the opportunity to provide electrical connections for the functional devices of the Siph PIC device.

[0003] Further limitations and disadvantages of conventional and traditional approaches will become apparent to those skilled in the art by comparing such a system with certain aspects of the present disclosure as set forth in the remainder of this application with reference to the accompanying figures. Summary of the Invention

[0004] Shown in at least one of the accompanying drawings and / or described in conjunction with at least one of the accompanying drawings, and more fully set forth in the claims, are photonic devices and associated processes for fabricating the photonic devices. Conventional photonic devices may provide electrical connections only through pads along the front side of the photonic device using wire bonding or flip chip bonding. Various embodiments of the present disclosure may allow for electrical connections along the sidewalls and / or backside of the photonic device via metal or other conductive materials.

[0005] For example, a photonic device according to some embodiments of the present disclosure may include one or more metal layers extending to at least a scribe groove of a wafer of the photonic device. In order to separate or cut apart the photonic devices from one another, cutting or cutting apart such a wafer along the scribe groove may expose one or more metal layers along the sidewalls of the photonic device. Such exposed metal layers may enable electrical connections to be formed via at least one sidewall of the scribed photonic device, and / or may enable external electrical connections to be provided to the photonic device with better electrical characteristics, such as greater current capacity, greater current stability, greater voltage capacity, lower resistance, etc., compared to conventional techniques.

[0006] These and other advantages, aspects and novel features of the present disclosure, as well as details of illustrated embodiments thereof, will be more fully understood from the following description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various features and advantages of the present disclosure may be more readily understood by reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like structural elements.

[0008] Figure 1 A wafer including photonic devices is depicted prior to dicing and separation of the photonic devices.

[0009] Figure 2A Depicts the wafer before dicing Figure 1 Plan view of the wafer with photonic devices.

[0010] Figure 2B Depicts the wafer after dicing Figure 2A Plan view of the photonic device.

[0011] Figure 3A Depicts the area before cutting Figure 2A Cross-section of the peripheral portion of the photonic device.

[0012] Figure 3B Depicts the Figure 3A Cross section of the peripheral portion.

[0013] Figure 3C Depicted after extending the metal layer along the sidewalls of the photonic device Figure 3B Cross section of the peripheral portion.

[0014] Figure 3D Depicted after extending the metal layer along the bottom side of the photonic device Figure 3C Cross section of the peripheral portion.

[0015] Figure 4 Describes the Figures 3A to 3D Flowchart of the process for manufacturing photonic devices.

[0016] Figure 5A Depicted is a cross-section of the perimeter portion of two adjacent photonic devices during wafer fabrication.

[0017] Figure 5B Depicts the process after trench formation along the scribe groove between adjacent photonic devices. Figure 5A Cross section of the peripheral portion.

[0018] Figure 5C Depicts the metal layer after it is deposited and patterned via a lift-off process. Figure 5B Cross section of the peripheral portion.

[0019] Figure 5D Depicts the Figure 5C Cross section of the peripheral part.

[0020] Figure 5E Depicts the process after extending the metal layer along the sidewalls of the photonic device. Figure 5D Cross section of the peripheral portion.

[0021] Figure 5F Depicts the metal layer after extending it along the bottom side of the photonic device. Figure 5E Cross section of the peripheral portion.

[0022] Figure 6 Describes the Figures 5A to 5F Flowchart of the process for manufacturing photonic devices. DETAILED DESCRIPTION

[0023] The following discussion provides various examples of photonic integrated circuit (PIC) devices, silicon photonic integrated circuit (Siph PIC) devices, and associated processes for fabricating photonic devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0024] The accompanying drawings illustrate a general manner of construction. Descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the accompanying drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the examples discussed in this disclosure. The same reference numerals in different figures represent the same elements.

[0025] The term "and / or" means any one or more of the items in a list connected by "and / or". As an example, "x and / or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z".

[0026] The terms “comprises,” “comprising,” and / or “includes” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0027] The terms "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in this disclosure could be referred to as a second element without departing from the teachings of this disclosure.

[0028] Unless otherwise specified, the term "coupled" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A can be directly in contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "over" or "above" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0029] Now go to Figure 1 , a wafer 10 is shown including several photonic devices 20 (e.g., photonic integrated circuit (PIC) devices, silicon photonic integrated circuit (Siph PIC) devices, etc.). In order not to distract attention from other features of the disclosed embodiments, Figure 1 The wafer 10 is not drawn to scale and does not depict various features, such as process control monitoring (PCM) areas, fiducial marks between reticles, etc. As shown, the photonic devices 20 can be arranged in an array of rows and columns separated by scribe grooves 30. However, in other embodiments, the wafer 10 can arrange the photonic devices 20 in a different manner. In some embodiments, each photonic device 20 includes a Siph PIC device. However, aspects of the present disclosure can also be applied to PIC devices and their manufacture. Thus, the wafer 10 can include Siph PIC devices, PIC devices, or a combination of Siph PIC devices and PIC devices.

[0030] exist Figure 2A and Figure 2B Depicted in Figure 1 In particular, Figure 2A A plan view of the photonic device 20 is depicted before the wafer 10 is diced. Figure 2B The process of dicing the wafer 10 and Figure 1 After the photonic device 20 is separated from other photonic devices on the wafer 10 Figure 2A Plan view of the photonic device.

[0031] As shown, the photonic device 20 may include a photonic and / or electronic integrated circuit structure 40, a pad 60, and an edge connection 70. The photonic and / or electronic integrated circuit structure 40 may include at least one or more passive photonic structures or devices (such as gratings, waveguides, etc.), and / or one or more active photonic structures or devices 50 (for example, lasers, polarizers, phase shifters, photodetectors (PDs) that generate, detect, transmit, and process photons (i.e., light). The photonic and / or electronic integrated circuit structure 40 may also include one or more electronic integrated circuit structures that generally operate based on electron flow (such as transistors, diodes, resistors, capacitors, etc.).

[0032] like Figure 2A and Figure 2B As further shown in FIG, the top side of the photonic device 20 may include a pad 60 and / or a photonic integrated circuit structure that provides an electronic interface for operably coupling the electronic integrated circuit structure, the electronic interface of the photonic integrated circuit structure, to other electronic components such as a printed circuit board, an interposer, an integrated circuit (IC) chip, etc. To this end, the pad 60 may be implemented as a wire bonding pad through which a wire bond may be operably coupled or bonded to the photonic device 20 to the other electronic components. Such a wire bonding pad may be provided by forming a hole or opening through one or more top dielectric layers of the photonic device 20 so as to expose the underlying metal layer of the photonic device 20. In some embodiments, the pad 60 may include a solder pad, a bump, an under-bump metallization (UBM) layer, and / or other conductive interconnect that allows the electronic components of the photonic device 20 to be operably coupled to other electronic components.

[0033] Also like Figure 2A and Figure 2B As shown, the top side of the photonic device 20 can include edge connections 70 along the perimeter or sidewalls of the photonic device 20. The edge connections 70 can be formed in a similar manner to the pads 60. In addition, the edge connections 70 can be formed closer to the perimeter or sidewalls of the photonic device 20 than the pads 60. As explained in more detail below, one or more metal layers of the photonic device 20 can extend toward and / or beyond the scribe grooves 30. As a result of extending the one or more metal layers beyond the scribe grooves 30 and exposing the one or more metal layers from the top side in a manner similar to the pads 60, dicing the photonic device 20 from the wafer 10 can expose the one or more metal layers along the top side and sidewalls of the photonic device 20. In this manner, dicing of the wafer 10 can provide the photonic device 20 with additional and / or alternative electrical connections along the sidewalls of the photonic device 20.

[0034] Such electrical connections can improve the quality of the electrical connections of the photonic device 20. For example, such electrical connections can be used to provide a better ground connection for a shielding component 52 (e.g., a metal layer) that wraps around or at least partially surrounds the photodetector 50 and / or other photonic integrated circuit structures to prevent and / or reduce crosstalk between such components. Similarly, such electrical connections can be used to ground a metal layer that provides an internal EMI shielding component between the photonic integrated circuit structures and / or electronic integrated circuit structures of the photonic device 20. Such electrical connections can also be used to ground an external EMI shielding component of the photonic device 20 to shield the photonic circuit components and / or electronic circuit components of the photonic device 20 from components external to the photonic device 20.

[0035] Will refer to Figures 3A to 3D The cross section and Figure 4 Aspects of the exemplary manufacturing method 400 are described with reference to a flowchart of FIG. At 410, the manufacturing method 400 may include providing a wafer 10 having a photonic device 20. The photonic device 20 may be as shown in FIG. Figure 1 The array shown is arranged on a wafer 10. In addition, the photonic device 20 of the provided wafer 10 may include a photonic and / or electronic integrated circuit structure 40. The photonic and / or electronic integrated circuit structure 40 may be formed from one or more semiconductor layers, one or more metal layers 16, and one or more dielectric layers 18. Specifically, the top metal layer 16a of the one or more metal layers 16 may traverse the scribe groove 30, as shown in FIG. Figure 3A shown.

[0036] The wafer 10 can be provided via a variety of different techniques. In some embodiments, the manufacturing method 400 at 410 can perform all aspects of manufacturing the photonic and / or electronic integrated circuit structure 40 on the substrate 12 (e.g., a silicon-on-insulator substrate) (such as one or more semiconductor layers 15, one or more metal layers 16, and / or one or more dielectric layers 18 thereof) to obtain the wafer 10 having the photonic device 20 as shown. In other embodiments, the wafer 10 can be received at various stages of manufacturing (e.g., with one or more layers of the photonic and / or electronic integrated circuit structure 40 already formed), and the manufacturing method 400 at 410 can include completing the remaining manufacturing steps to obtain the wafer 10 as shown.

[0037] like Figures 3A to 3D As shown, the wafer 10 provided at 410 may include a substrate 12 having a top side, a bottom side opposite the top side, and sidewalls between the substrate top side and the substrate bottom side. In various embodiments, the substrate 12 includes a silicon-on-insulator substrate on which various layers of the photonic and / or electronic integrated circuit structure 40 (e.g., semiconductor layer 15, metal layer 16, dielectric layer 18, etc.) may be disposed.

[0038] As further shown, the photonic and / or electronic integrated circuit structure 40 may also include a redistribution structure 14. The redistribution structure 14 may include a top side, a bottom side opposite the top side, and sidewalls between the redistribution structure top side and the redistribution structure bottom side. In some embodiments, the redistribution structure 14 may be a stacked redistribution structure including alternating metal layers 16 and dielectric layers 18. The metal layers 16 may include conductive traces that conduct electrical signals for the electronic and / or photonic active devices 50. To this end, the redistribution structure 14 may also include conductive vias 17 that extend through one or more dielectric layers 18 and couple one metal layer 16 to another metal layer 16.

[0039] At 420 , the fabrication method 400 may include creating an opening in the top dielectric layer 18 a of the redistribution structure 14 , such as Figure 3A As shown. Specifically, the manufacturing method 400 can generate a pad opening 62 that exposes the pad 60 of the top metal layer 16a of the redistribution structure 14. In addition, the manufacturing method 400 can generate an edge connection opening 72 that exposes the edge connection 70 of the top metal layer 16a of the redistribution structure 14. To do this, the manufacturing method 400 can use photolithography techniques to develop a mask on the top dielectric layer 18a and etch the top dielectric layer 18a through the openings in the mask to form the pad opening 62 and the edge connection opening 72. In other embodiments, the manufacturing method 400 can use other techniques, such as laser ablation, to form the openings 62, 72 in the dielectric layer 18a.

[0040] The manufacturing method 400 may scribe the wafer 10 along the scribe grooves 30 at 430. Figure 3B As shown, such scribing can cut through the top metal layer 16a and expose the top metal layer 16a at the redistribution structure sidewalls. Various scribing techniques, such as blade scribing, laser ablation scribing, and / or scribing, can be used to separate the PIC device 20 from the wafer 10. As a result of such scribing, the sidewalls of the top metal layer 16a can be coplanar with the sidewalls of the substrate 12. In addition, the metal layer sidewalls 19 can include a scribed surface having different surface characteristics (e.g., rougher, knife marks, etc.) compared to one or more other surfaces of the top metal layer 16a. The scribing can also provide a sidewall facet through which one or more photonic integrated circuit structures (e.g., photodetectors 50) of the photonic and / or electronic integrated circuit structure 40 can send and / or receive photons.

[0041] At 440, the manufacturing method 400 may provide a sidewall metal layer 84 along the sidewalls of the photonic device 20. Figure 3CAs shown, the sidewall metal layer 84 can cover and contact the metal layer sidewalls 19 and the substrate sidewalls. In this way, the sidewall metal layer 84 can effectively extend the top metal layer 16a along the sidewalls of the photonic device from the top side of the redistribution structure to the bottom side of the substrate. To this end, the manufacturing method 400 can use various techniques to provide the sidewall metal layer 84, such as applying a conductive epoxy along the sidewalls of the photonic device, applying a metal coating along the sidewalls of the photonic device, etc. In this way, the sidewall metal layer 84 can allow electrical connections to active devices and / or shielding components of the photonic device 20 via the sidewalls of the photonic device.

[0042] Similarly, at 450, the manufacturing method 400 can provide a bottom side metal layer 86 along a portion of the bottom side of the substrate. Specifically, the bottom side metal layer 86 can cover and contact the bottom side of the sidewall metal layer 84. In this way, the bottom side metal layer 86 and the sidewall metal layer 84 can effectively extend the top metal layer 16a of the redistribution structure 14 to one or more portions of the bottom side of the photonic device. To this end, the manufacturing method 400 can use various techniques to provide the bottom side metal layer 86, such as applying a conductive epoxy along the bottom side of the substrate, applying a metal coating along the bottom side of the substrate, or applying the bottom side metal layer 86 from the bottom side of the substrate via wafer-level sputtering, provided that the sidewall metal layer 84 is created using the methods described in the previous section. In this way, the bottom side metal layer 86 can allow electrical connections to active devices and / or shielding components of the photonic device 20 to be provided via the bottom side of the photonic device.

[0043] Will refer to Figures 5A to 5F The cross section and Figure 6 6. The flowchart of FIG. 6 is used to describe aspects of another exemplary manufacturing method 600. At 610, the manufacturing method 600 may include providing a wafer 10 having a photonic device 20. The photonic device 20 may be as shown in FIG. Figure 1 The array shown is arranged on a wafer 10. In addition, the photonic device 20 of the wafer 10 is provided to include a photonic and / or electronic integrated circuit structure 40. Figure 5A As shown, the provided wafer 10 may include a top metal layer 16 a extending pad 60 toward the scribe line 30 .

[0044] The wafer 10 can be provided via a variety of different techniques. In some embodiments, at 610, the manufacturing method 600 can perform all aspects of manufacturing the photonic and / or electronic structure 40 (such as one or more semiconductor layers 15, one or more metal layers 16, and / or one or more dielectric layers 18 thereof) on the substrate 12 (e.g., a silicon-on-insulator substrate) to obtain the wafer 10 having the photonic device 20 as shown. In other embodiments, the wafer 10 can be received at various stages of manufacturing (e.g., with one or more layers of the photonic and / or electronic integrated circuit structure 40 already formed), and the manufacturing method 600 at 610 can include completing the remaining manufacturing steps to obtain the wafer 10 as shown.

[0045] like Figures 5A to 5F As shown, at 610, a wafer 10 is provided that may include a substrate 12 having a top side, a bottom side opposite the top side, and sidewalls between the substrate top side and the substrate bottom side. In various embodiments, the substrate 12 includes a silicon-on-insulator substrate on which various layers (e.g., semiconductor layers, dielectric layers, etc.) of a photonic and / or electronic integrated circuit structure 40 may be disposed.

[0046] As further shown, the photonic and / or electronic integrated circuit structure 40 can also include a redistribution structure 14. The redistribution structure 14 can include a top side, a bottom side opposite the top side, and sidewalls between the redistribution structure top side and the redistribution structure bottom side. In some embodiments, the redistribution structure 14 can be a stacked redistribution structure including alternating metal layers 16 and dielectric layers 18. The metal layers can include conductive traces that conduct electrical signals for the electronic devices and / or photonic active devices 50. To this end, the redistribution structure 14 can also include conductive vias 17 that extend through one or more dielectric layers 18 and couple one metal layer 16 to another metal layer 16.

[0047] like Figure 5AAs shown, the manufacturing method 600 may include, at 620, creating openings in the top dielectric layer 18a of the redistribution structure 14. Specifically, the manufacturing method 600 may generate a pad opening 62 that exposes the pad 60 of the top metal layer 16a of the redistribution structure 14. Additionally, the manufacturing method 600 may generate an edge connection opening 72 that exposes the edge connection 70 of the top metal layer 16a of the redistribution structure 14. The manufacturing method 600 may also generate a trench opening 92 that exposes one or more layers of the redistribution structure 14. To do this, the manufacturing method 600 may use photolithography techniques to develop a mask on the top dielectric layer 18a and etch the top dielectric layer 18a through the openings in the mask to form the pad opening 62, the edge connection opening 72, and the trench opening 92. In other embodiments, the manufacturing method 600 may use other techniques, such as laser ablation, to form the openings 62, 72, 92 in the dielectric layer 18a. Furthermore, in some embodiments, the manufacturing method 600 may precede the formation of the trench opening 92 and simply form the trench 100 as discussed below at 630 without first creating the trench opening 92 .

[0048] The manufacturing method 600 may form a trench 100 along one or more scribe grooves 30 at 630. Specifically, the trench 100 may extend through one or more metal layers 16 and / or dielectric layers 18 of the redistribution structure 14. In some embodiments, the trench 100 may extend into the top side of the substrate 12, such as Figure 5B To this end, the manufacturing method 600 may perform a deep etching process to undercut the silicon of the silicon-on-insulator substrate 12. In some embodiments, the deep etching process may extend the trench 100 to a depth of 100 μm or more.

[0049] At 640 , the manufacturing method 600 may provide a trench sidewall metal layer 104 along the sidewalls of the trench 100 , such as Figure 5C As shown. Specifically, the trench sidewall metal layer 104 can extend to and contact at least a portion of the top metal layer 16a exposed by the edge connection opening 72. To this end, the manufacturing method 600 can use various techniques to provide the trench sidewall metal layer 104, such as wafer-level metal deposition or wafer-level sputtering from the top side. In this way, the trench sidewall metal layer 104 can effectively extend the top metal layer 16a to at least a portion of the sidewall of the photonic device and extend along this portion. In this way, the trench sidewall metal layer 104 can allow electrical connections to active devices and / or shielding components of the photonic device 20 to be provided via the sidewall of the photonic device.

[0050] At 650, the manufacturing method 600 may scribe the wafer 10 along the scribe lines 30. Figure 5DAs shown, such scribing can cut through the trench sidewall metal layer 104 and expose the metal layer 104 at the sidewalls of the photonic device 20. Various scribing techniques such as blade scribing, laser ablation scribing, and / or scribe line scribing can be used to separate the photonic device 20 from the wafer 10. As a result of such scribing, the trench sidewall metal layer 104 can include a scribed surface having different surface characteristics (e.g., roughness, knife marks, etc.) than one or more other surfaces of the trench sidewall metal layer 104. In addition, scribing can provide a sidewall facet through which one or more photonic integrated circuit structures (e.g., photodetector 50) of the photonic and / or electronic integrated circuit structure 40 can transmit and / or receive photons.

[0051] The manufacturing method 600 may optionally provide a sidewall metal layer 106 along the sidewalls of the photonic device 20 at 660. Specifically, the sidewall metal layer 106 may cover and contact a portion of the trench sidewall metal layer 104 and a portion of the substrate sidewall, such as Figure 5E As shown. To this end, the manufacturing method 600 can use various techniques to provide the bottom side metal layer 86, such as applying a conductive epoxy along the sidewalls of the photonic device, applying a metal coating along the sidewalls of the photonic device, or applying a sidewall metal layer 106 from the bottom side of the substrate via wafer-level sputtering. In this way, the trench sidewall metal layer 104 and the sidewall metal layer 106 can effectively extend the top metal layer 16a to the bottom side of the photonic device 20. In this way, the trench sidewall metal layer 106 can allow electrical connections to active devices and / or shielding components of the photonic device 20 to be provided via the sidewalls of the photonic device.

[0052] At 670, the manufacturing method 600 can optionally provide a bottom side metal layer 86 along a portion of the bottom side of the substrate. Specifically, the bottom side metal layer 86 can cover and contact the bottom side of the sidewall metal layer 106. To this end, the manufacturing method 600 can use various techniques to provide the bottom side metal layer 86, such as applying a conductive epoxy along the bottom side of the substrate, applying a metal coating along the bottom side of the substrate, or applying the bottom side metal layer 86 from the bottom side of the substrate via wafer-level sputtering. In this way, the trench sidewall metal layer 104, the sidewall metal layer 106, and the bottom side metal layer 86 can effectively extend the top metal layer 16a of the redistribution structure 14 to one or more portions of the bottom side of the photonic device. In this way, the bottom side metal layer 86 can allow electrical connections to active devices and / or shielding components of the photonic device 20 to be provided via the bottom side of the photonic device.

[0053] This disclosure includes references to certain examples, however, those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the scope of this disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that the disclosure is not limited to the disclosed examples, but rather that the disclosure will include all examples that fall within the scope of the appended claims.

Claims

1. A photonic device comprising: a substrate comprising a substrate top side, a substrate bottom side, and a substrate sidewall between the substrate top side and the substrate bottom side; one or more photonic integrated circuit structures on the top side of the substrate, wherein the photonic integrated circuit structures include one or more photonic active devices and a redistribution structure, and wherein the redistribution structure includes one or more dielectric layers and one or more metal layers coupled to the one or more photonic active devices; a pad opening through a first dielectric layer of the one or more dielectric layers, wherein the pad opening exposes a first metal layer of the one or more metal layers at a top side of the redistribution structure; and An edge connection opening through the first dielectric layer, wherein the edge connection opening is positioned such that at least a portion of a perimeter of the first dielectric layer is closer to the edge connection opening than the pad opening, and wherein the edge connection opening exposes the first metal layer at a top side of the redistribution structure.

2. The photonic device according to claim 1, wherein: The first metal layer includes a first metal layer sidewall; and The edge connection opening exposes a sidewall of the first metal layer at a sidewall of the redistribution structure. 3 . The photonic device according to claim 2 , comprising a sidewall metal layer covering and contacting at least a portion of a sidewall of the redistribution structure and a portion of a sidewall of the first metal layer.

4. The photonic device according to claim 3, wherein The sidewall metal layer covers and contacts at least a portion of the substrate sidewall.

5. The photonic device according to claim 3, wherein The sidewall metal layer extends from a top side of the redistribution structure to a bottom side of the substrate. 6 . The photonic device of claim 5 , comprising a bottom side metal layer covering and contacting at least a portion of the substrate bottom side and a portion of the sidewall metal layer.

7. The photonic device according to claim 1, comprising: a trench along a peripheral edge of the redistribution structure, wherein the trench includes trench sidewalls extending from a top side of the redistribution structure toward a top side of the substrate; and A trench sidewall metal layer covers and contacts at least a portion of the trench sidewall, wherein the trench sidewall metal layer extends to and contacts the first metal layer via one or more edge connection openings. 8 . The photonic device according to claim 7 , comprising a sidewall metal layer covering and contacting at least a portion of a sidewall of the redistribution structure and a portion of the trench sidewall metal layer.

9. The photonic device according to claim 8, wherein: The sidewall metal layer covers and contacts at least a portion of the substrate sidewall.

10. The photonic device according to claim 9, wherein The sidewall metal layer extends from the trench sidewall metal layer to the substrate bottom side.

11. The photonic device of claim 10, comprising a bottom side metal layer covering and contacting at least a portion of the substrate bottom side and a portion of the sidewall metal layer.

12. The photonic device according to claim 1, comprising: a shielding component coupled to the first metal layer; and The shielding component reduces crosstalk between a first photonic active device and a second photonic active device among the one or more active photonic devices.

13. The photonic device of claim 1, comprising an electromagnetic interference (EMI) shield at least partially surrounding a photonic active device of the one or more photonic active devices.

14. A method for manufacturing a photonic device, the method comprising: providing a wafer comprising a substrate, one or more photonic active devices on the substrate, and a redistribution structure coupled to the one or more photonic active devices; providing a pad opening and an edge connection opening through the dielectric layer of the redistribution structure to expose the metal layer of the redistribution structure; Slicing along scribe lines through the substrate and the redistribution structure to separate the photonic device from the wafer; as well as A sidewall metal layer is formed on the photonic device such that the sidewall metal layer contacts the metal layer exposed through one or more of the edge connection openings.

15. The method according to claim 14, wherein: Each of the edge connection openings traverses a scribe slot in the scribe slot; as well as Dicing along the dicing grooves includes dicing through the metal layer and forming diced sidewalls of the metal layer at sidewalls of the redistribution structure. 16 . The method of claim 14 , comprising forming a trench along one or more of the scribe lines before scribing along the scribe lines.

17. The method according to claim 16, wherein Forming the sidewall metal layer includes forming the sidewall metal layer so that the sidewall metal layer covers and contacts a portion of a trench sidewall of the redistribution structure and an exposed portion of the metal layer.

18. The method of claim 14, comprising forming a bottom side metal layer on at least a portion of a bottom side of the photonic device such that the bottom side metal layer contacts the sidewall metal layer.

19. The method according to claim 14, wherein The metal layer is coupled to a shielding component of the photonic device.

20. The method according to claim 14, wherein Providing the wafer includes providing an electromagnetic interference (EMI) shield at least partially surrounding a photonic active device of the one or more photonic active devices.

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