Mask layout method and related product

Abstract

The invention provides a mask layout method and a related product. The layout method comprises the steps that a mask plate is divided into a plurality of chip frame areas, each chip frame area is used for setting a chip layout of a corresponding chip, and cutting channels are formed between the chip frame areas; a measurement layout framework is constructed, the measurement layout framework is used for setting one or more measurement link labels, each measurement link label corresponds to a measurement graph, and the measurement graphs are used for reflecting corresponding process indexes of the mask plate in the chip manufacturing process; and one or more measurement layout frames are respectively arranged in the one or more cutting channels. Compared with multi-time iteration layout through a parameterization tool, the method has the advantages that the layout frequency of the mask plate is reduced, and the typesetting efficiency of the measured graph is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a mask layout method, a computer-readable storage medium, a computer program product, and a computer device. Background Art

[0002] The photomask is a key carrier for transferring photolithographic patterns during semiconductor integrated circuit manufacturing. Mask layout design refers to the arrangement of the chip layout and metrology patterns (also known as metrology marks) on the mask. The proper placement of chips and metrology patterns is crucial to the efficiency, accuracy, and reliability of the semiconductor manufacturing process, directly impacting the efficiency and accuracy of wafer exposure. Proper placement of chips and metrology patterns on the mask not only helps reduce costs and increase yields, but also ensures high quality standards for the final product.

[0003] There may be many types of measurement patterns. Taking the measurement pattern used to measure exposure accuracy as an example, the exposure accuracy of the upper and lower layers can be measured by the exposure condition of the exposure accuracy measurement pattern on each mask on the wafer. If the exposure accuracy is not enough, the subsequent process deviation will become larger and larger, and there is a greater risk that the final wafer will be scrapped. Therefore, after the exposure of each layer is completed, it is necessary to use the exposure accuracy measurement pattern on the wafer to determine whether the current process meets the requirements, and the exposure condition of the exposure accuracy measurement pattern can be used to indirectly reflect the actual exposure condition of the chip, which can effectively save the chip detection time and resource costs. In particular, in the multi-project wafer mode (MPW), multiple chips need to share the same mask and the same wafer. Efficient and accurate layout of each chip and its corresponding measurement pattern is an important link in achieving low-cost, high-integration tape-out.

[0004] In the related art, parameterized tools (such as CSV format configuration files) are usually used to arrange chips and measurement graphics. Specifically, it is usually necessary to rely on manual experience to first set the initial coordinates and other parameters of the measurement graphic file corresponding to each measurement graphic in the layout information file, and then execute the layout tool to check whether the position of the chip and measurement graphic in the mask achieves the expected effect through the layout results of the layout tool. When there is a deviation from the expected effect, it is necessary to re-modify the abnormal parameters in the layout information file, and then execute the layout tool again and check the results. In practice, multiple iterations are usually required to obtain a mask that meets the expected effect. The layout efficiency of chips and measurement graphics in this way is relatively low. Summary of the Invention

[0005] An object of the present invention is to provide a mask layout method, a computer-readable storage medium, a computer program product, and a computer device to improve the layout efficiency of measurement patterns in a mask.

[0006] Specifically, according to one aspect of the present invention, the present invention provides a mask layout method, comprising:

[0007] Dividing the mask into a plurality of chip frame areas, each of which is used to set a chip layout of a corresponding chip, and having cutting lanes between the chip frame areas;

[0008] Constructing a measurement layout framework, wherein the measurement layout framework is used to set one or more measurement link tags, each of which corresponds to a measurement pattern, and the measurement pattern is used to reflect the corresponding process indicators of the mask in the chip manufacturing process;

[0009] One or more measurement layout frames are respectively set in one or more cutting streets.

[0010] Optionally, the step of constructing the measurement link tag includes:

[0011] Based on the process nodes of the corresponding chips in the chip frame regions of the mask, and / or the process indicators of the mask during chip manufacturing, constructing a plurality of the measurement patterns, and generating a measurement pattern file for each of the measurement patterns;

[0012] For each of the measurement graphic files, a measurement link tag is constructed respectively.

[0013] Optionally, the step of constructing the measurement layout framework includes:

[0014] Acquiring layout-related features of each of the cutting lines in the mask, wherein the layout-related features of the cutting lines include the size of the cutting lines and the light transmittance category of the cutting lines on each layer;

[0015] Determining layout-related features of each of the measurement link tags preset on the mask, wherein the layout-related features of the measurement link tags include the type and quantity of the measurement link tags;

[0016] A plurality of measurement layout frameworks are constructed according to the layout-related features of the scribe lines and the layout-related features of the measurement link tags.

[0017] Optionally, constructing a plurality of measurement layout frameworks according to the layout-related features of the dicing lanes and the layout-related features of the measurement link tags includes:

[0018] Determining layout-related features of each of the measurement layout frames according to the layout-related features of the dicing lanes and the layout-related features of the measurement link tags, wherein the layout-related features of the measurement layout frames include a size of the measurement layout frame and a process node to which it belongs;

[0019] sequentially arranging a preset number of label placement areas in each measurement layout frame, and determining the spacing between adjacent label placement areas; and

[0020] The measurement link labels of corresponding types are respectively arranged in one or more label arrangement areas in each of the measurement layout frames.

[0021] Optionally, before the step of respectively setting one or more measurement layout frames in one or more cutting lanes, the method further includes:

[0022] A plurality of the measurement layout frames are displayed in a visual interface, and each of the measurement layout frames is arranged in a corresponding cutting lane by obtaining a drag operation on the measurement layout frame display area.

[0023] Optionally, after the step of respectively setting one or more measurement layout frames in one or more cutting lanes, the method further includes:

[0024] Generating configuration information for recording the layout of each chip frame area, each dicing street, each measurement layout frame, and each measurement link label in the mask; and

[0025] The configuration information is changed to change the layout of the mask.

[0026] Optionally, the configuration information includes: size and coordinate information of each chip frame area; size and coordinate information of each cutting road; size and coordinate information of each measurement layout frame; and type and position information of each measurement link tag in each measurement layout frame.

[0027] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned mask layout methods are implemented.

[0028] According to yet another aspect of the present invention, a computer program product is provided, comprising a computer program, which implements the steps of any one of the above-mentioned mask layout methods when executed by a processor.

[0029] According to another aspect of the present invention, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any one of the above-mentioned mask layout methods.

[0030] The present reticle layout method constructs a measurement layout framework with one or more measurement link tags, and then places each measurement layout framework within the corresponding dicing lane as needed. This makes the measurement pattern layout process more intuitive and easier to achieve the desired effect. Compared to multiple iterative layouts using parametric tools, this method reduces the number of reticle layouts and improves the efficiency of measurement pattern layout.

[0031] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0033] Figure 1 is a schematic flow chart of a layout method according to an embodiment of the present invention;

[0034] Figure 2 is a schematic diagram of a flow chart of constructing a measurement link tag in a layout method according to an embodiment of the present invention;

[0035] Figure 3 is a schematic diagram of a flow chart of constructing a measurement layout framework according to a layout method of an embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of a process for constructing a plurality of measurement layout frameworks according to a layout method of an embodiment of the present invention;

[0037] Figure 5 is a schematic diagram of a process of changing a mask layout according to a layout method of an embodiment of the present invention;

[0038] Figure 6 is a schematic flow chart of a layout method according to another embodiment of the present invention;

[0039] Figure 7 is a schematic diagram of a computer program product according to one embodiment of the present invention;

[0040] Figure 8 is a schematic diagram of a computer-readable storage medium according to one embodiment of the present invention; and

[0041] Figure 9 is a schematic diagram of a computer device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0042] The purpose of the mask layout method of this embodiment is to improve the layout efficiency of the measurement pattern in the mask.

[0043] Figure 1 FIG. 1 is a flow chart of a method for layout of a mask according to an embodiment of the present invention. The method may generally include:

[0044] S100, dividing a plurality of chip frame areas on a mask, each chip frame area being used to set a chip layout of a corresponding chip, with cutting lanes being provided between the chip frame areas;

[0045] S200, constructing a measurement layout framework, the measurement layout framework is used to set one or more measurement link labels, each measurement link label corresponds to a measurement pattern, and the measurement pattern is used to reflect the corresponding process indicators of the mask in the chip manufacturing process;

[0046] S300: setting one or more measurement layout frames in one or more cutting lanes.

[0047] In the semiconductor integrated circuit manufacturing process, taking the Multi-Project Wafer (MPW) mode as an example, multiple chips need to share the same mask and the same wafer. A wafer can be divided into multiple exposure areas (shots), and multiple chips are arranged in each exposure area. Correspondingly, a mask can be set for each exposure area, and the chip layout is laid out on the mask. In order to facilitate the cutting of each chip on the wafer, a cutting path with a certain width is also set on the mask between each chip layout and on the outside of each chip layout at the edge of the exposure area. Measurement graphics can be laid out in the cutting path. Layout design is the process of arranging chip layouts and measurement graphics on the mask.

[0048] The chip frame area may be a polygon, such as a rectangle. Each chip frame area is used to set the chip layout of the corresponding chip, and the chip layout includes the chip graphics of the chip. The size and shape of the chip frame area should be consistent with the outer contour of the chip layout of the chip. In some embodiments, in order to save computing resources and improve layout efficiency, it is not necessary to set the chip graphics in the chip frame area during the layout design stage, and only the border of the frame (such as a rectangular border) is retained. Among them, each chip corresponds to a chip layout file (such as a GDS or OAS format file), that is, each chip frame area is linked to a chip layout file. It should be understood that multiple identical chips can be arranged on a mask, and different chip frame areas can be linked to the same chip layout file.

[0049] In this embodiment, the measurement layout framework is a framework mark with preset attribute parameters (such as size, process node, etc.), and one or more measurement link tags can be set in the measurement layout framework. A variety of measurement layout frameworks can be constructed as needed, and each measurement layout framework can have different preset attribute parameters and / or be arranged with different combinations of measurement link tags. The measurement link tag is a label mark with preset attribute parameters (such as process node, light transmittance category, etc.). Each measurement link tag corresponds to a measurement graphic (also called a measurement tag) and is linked to a measurement graphic file (such as a GDS or OAS format file). By packing multiple measurement link tags into a measurement layout framework and laying out a measurement layout framework, it is possible to layout multiple measurement graphics, which can reduce the number of layout operations and improve layout efficiency.

[0050] Depending on the type of process indicator used for measurement, the measurement pattern may include alignment marks used to align the mask during the exposure process, overlay marks used to align multi-layer masks, critical dimension bars (CD-bars) used to measure critical dimensions, optical critical dimension marks (OCDs) used to measure critical dimensions using optical methods, film thickness marks (THKs) used to measure film thickness, measurement patterns used to measure exposure accuracy, etc.

[0051] After constructing the various metrology layout frames required for the reticle, each metrology layout frame can be placed within the corresponding scribe lanes. In some embodiments of the present invention, an automatic layout algorithm can be used to determine the corresponding position coordinates of each metrology layout frame, and then each metrology layout frame can be placed within the corresponding scribe lanes. In other embodiments, each metrology layout frame can be placed within the corresponding scribe lanes manually. For example, the reticle layout method can be applied to a server, which presents a visual interface during the layout process. The visual interface can display the exposure area, the chip frame areas after preliminary layout, and each scribe lane. The user can place each metrology layout frame within the corresponding scribe lane as needed, and each metrology layout frame can be displayed within each scribe lane. The user can intuitively view the layout of each metrology layout frame in the reticle. In yet other embodiments, after the metrology layout frames are laid out using the automatic layout algorithm and displayed in the visual interface, the server can also accept manual user instructions to adjust the type and position of each metrology layout frame to change the layout of the measurement pattern.

[0052] After completing the layout, the server can generate a configuration file (e.g., a CSV file) that records the details of each element in the mask. This configuration file can include the type, size, and coordinates of each chip frame area, each scribe line, and each measurement layout frame in the mask, as well as the corresponding chip layout file and measurement pattern file.

[0053] The present reticle layout method constructs a measurement layout framework with one or more measurement link tags, and then places each measurement layout framework within the corresponding dicing lane as needed. This makes the measurement pattern layout process more intuitive and easier to achieve the desired effect. Compared to multiple iterative layouts using parametric tools, this method reduces the number of reticle layouts and improves the efficiency of measurement pattern layout.

[0054] In some embodiments of the layout method of the present invention, as Figure 2 As shown, the steps for constructing the measurement link label include:

[0055] S211, constructing multiple measurement patterns based on the process nodes of the corresponding chips in the chip frame areas of the mask and / or the process indicators of the mask during the chip manufacturing process, and generating a measurement pattern file for each measurement pattern;

[0056] S213: Construct a measurement link tag for each measurement graphic file.

[0057] In this embodiment, each combination of process node (also known as process technology) and process index corresponds to a measurement pattern. For example, a critical dimension bar with a process node of 130 nanometers corresponds to a measurement pattern, a film thickness mark with a process node of 130 nanometers corresponds to another measurement pattern, and a critical dimension bar with a process node of 200 nanometers corresponds to another measurement pattern. Generally, each chip in the same mask uses the same process node, while different masks may use different process nodes. In actual use, measurement patterns of multiple process nodes and process index combinations can be constructed in advance, and one-to-one corresponding measurement link labels and measurement pattern files can be generated for selection during layout design. In some embodiments, all possible measurement link labels can also be combined into a measurement link label library, and a measurement link label table can be generated for users to use during layout design.

[0058] In some embodiments of the layout method of the present invention, as Figure 3 As shown, the steps for building the measurement layout framework include:

[0059] S221, obtaining layout-related features of each cutting line in the mask, wherein the layout-related features of the cutting line include the size of the cutting line and the light transmittance type of the cutting line on each layer;

[0060] S223, determining layout-related features of each measurement link tag preset on the mask, where the layout-related features of the measurement link tag include the type and quantity of the measurement link tag;

[0061] S225 , constructing multiple measurement layout frameworks according to the layout-related features of each cutting lane and the layout-related features of each measurement link tag.

[0062] A mask typically consists of multiple layers. The same chip frame area can have different chip patterns on each layer, and the same scribe line can have different light transmittance categories on each layer. Light transmittance categories typically include clear tone and dark tone. By obtaining the dimensions and light transmittance category of each scribe line, you can specifically set the dimensions, light transmittance category, and other attribute parameters of the corresponding measurement link tag. This ensures that the layout measurement pattern achieves the desired effect and improves the measurement performance of the measurement pattern.

[0063] After determining some attribute parameters of the metrology link tag based on the layout-related characteristics of the scribe lines, it is also necessary to determine the types and quantities of all required metrology patterns based on the manufacturing requirements of each chip in the entire reticle (the reticle may use the same metrology pattern in multiple locations) to meet the metrology requirements of various process indicators during chip manufacturing. Based on these layout-related characteristics, corresponding metrology link tags are constructed or selected. In some embodiments, after determining the types of pre-set metrology patterns, a metrology pattern library is also constructed to prepare for combining to form a metrology layout framework.

[0064] Next, the measurement link tags need to be combined, and multiple measurement link tags of measurement graphics that are suitable for being placed together are placed into the same measurement layout frame, thereby constructing multiple measurement layout frames.

[0065] In particular, in some embodiments, each metrology layout frame can include multiple layers corresponding to the layers of the reticle. The multiple layers of each metrology layout frame can use different metrology link tag combinations. This can further reduce the number of layout operations and improve the layout efficiency of the metrology pattern.

[0066] In some embodiments of the layout method of the present invention, as Figure 4 As shown, based on the layout-related features of each cutting lane and the layout-related features of the measurement link label, multiple measurement layout frameworks are constructed, including:

[0067] S251, determining layout-related features of each measurement layout frame based on layout-related features of the dicing lanes and layout-related features of the measurement link tags, wherein the layout-related features of the measurement layout frame include a size of the measurement layout frame and a process node to which it belongs;

[0068] S253, sequentially and spaced apart in each measurement layout frame a preset number of label placement areas, and determining the spacing between adjacent label placement areas; and

[0069] S255 , respectively setting corresponding types of measurement link labels in one or more label layout areas in each measurement layout frame.

[0070] The measurement layout frame may be rectangular, with a width smaller than the width of the corresponding cutting street, so as to prevent the measurement pattern of the final layout from exceeding the range of the cutting street.

[0071] The measurement layout frame may be provided with a plurality of label layout areas adjacent to or spaced apart in its length direction, and each label layout area is used to place a measurement link label. For example, the measurement layout frame may be provided with 4 label layout areas, and they are represented by codes such as #1, #2, #3 and #4 respectively. By linking each code to the corresponding measurement link label, it is possible to conveniently set the measurement link label at the corresponding position within the measurement layout frame. It should be understood that in the above embodiment, a maximum of 4 measurement link labels can be set in a measurement layout frame, a minimum of 1 measurement link label can be set, and a light-transmitting area or a light-impermeable area can be set in the label layout area where the measurement link label is not set. A plurality of identical measurement link labels can be set in a measurement layout frame, or different measurement link labels can be set. There is no restriction here, and they can be set as needed.

[0072] The spacing between label layout areas can be set according to process requirements, measurement link label types, etc. to prevent interference between adjacent measurement graphics.

[0073] In this embodiment, by setting multiple label layout areas in the measurement layout framework, and setting corresponding types of measurement link labels in one or more label layout areas, the measurement layout framework can flexibly select the required measurement link labels, thereby improving the applicability of using the measurement layout framework to layout measurement graphics.

[0074] In some embodiments of the layout method of the present invention, before or after the step of respectively setting one or more measurement layout frames in one or more scribe lines, the method further includes:

[0075] A plurality of measurement layout frames are displayed in a visual interface, and each measurement layout frame is arranged in a corresponding cutting lane by obtaining a drag operation on a display area of ​​the measurement layout frame.

[0076] In this embodiment, the reticle layout method can be applied to a server, which presents a visual interface during the layout process. For example, the visual interface can be configured with a drawing area and a frame area. The drawing area is initially a blank canvas, which is used to subsequently display elements such as the reticle exposure area, the die frame area for the exposure area layout, dicing lanes, and metrology layout frames. The frame area can be used to display various constructed metrology layout frames, such as their names, icons, and thumbnails.

[0077] The drawing area of ​​the visual interface can display the automatic layout process of each element. The user can also manually select the required measurement layout frame from the frame area and then drag it to the appropriate cutting path. Of course, the user can also delete the existing measurement layout frame in the cutting path and replace it with the measurement layout frame selected in the frame area. Compared with using parametric tools for blind layout, this method can effectively reduce the complexity of user parameter settings, making it easier to achieve the expected layout effect, thereby reducing the number of iterative layouts. When there are abnormal situations, users can more intuitively and flexibly check, modify and adjust the layout of each element in the mask on the visual interface, thereby improving the layout efficiency of chips and measurement graphics, reducing the error rate, and making the layout process easier to maintain.

[0078] In some embodiments of the layout method of the present invention, as Figure 5 As shown, after the step of respectively setting one or more measurement layout frames in one or more cutting lanes, the method further includes:

[0079] S500, generating configuration information for recording the layout of each chip frame area, each dicing street, each measurement layout frame, and each measurement link label in the mask; and

[0080] S600: Change the configuration information to change the layout of the mask.

[0081] In this embodiment, after completing the preliminary layout of the mask, a configuration file (such as a CSV format file) is generated to record the configuration information of each element in the mask. The configuration file records in detail the layout of each chip frame area, each cutting lane, each measurement layout frame and each measurement link label.

[0082] If the measurement pattern layout does not meet expectations or anomalies are detected, the user can directly modify the relevant parameters in the configuration file, save the configuration file, and reload it to generate an updated mask. The chip frame area, each dicing lane, each measurement layout frame, and each measurement link label in the mask will be rearranged accordingly (for example, the screen in the frame area will be refreshed), achieving the purpose of modifying the mask layout.

[0083] In some embodiments of the layout method of the present invention, the configuration information includes: the dimensions and coordinates of each chip frame area; the dimensions and coordinates of each dicing street; the dimensions and coordinates of each measurement layout frame; and the type and location of each measurement link tag within each measurement layout frame. This configuration information fully reflects the layout of each element in the reticle, facilitating its use in subsequent chip manufacturing. Furthermore, during the layout design phase, the reticle layout can be modified by modifying the parameters in the configuration information.

[0084] In some embodiments of the layout method of the present invention, as Figure 6 As shown, the layout method includes:

[0085] S711, constructing a measurement link tag library, wherein the measurement link tag library includes a plurality of measurement link tags, and each measurement link tag is connected to a measurement graphic file;

[0086] S713, building a measurement layout framework library, the measurement layout framework library including multiple measurement layout frameworks, each measurement layout framework having one or more measurement link tags set therein;

[0087] S715, using automatic layout tools to lay out multiple chip frame areas and dicing lanes on the mask;

[0088] S717 , determining a plurality of measurement layout frames from a measurement layout frame library, and respectively placing them in one or more cutting lanes.

[0089] By building a measurement layout framework library and a measurement link tag library in advance and choosing to use them when laying out measurement graphics, layout efficiency can be further improved.

[0090] In this embodiment, the measurement link label library can generate measurement link labels using historical measurement patterns. New measurement patterns can also be added as needed (e.g., when upgrading a process node) and corresponding measurement link labels generated. After updating the measurement link label library, the measurement layout framework library can be updated for use during layout.

[0091] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in all every case. In addition, the method may include additional operations. Within the scope of the technical ideas provided by the method of this embodiment, additional changes can be made to the above method.

[0092] It should be understood that in some embodiments, each part can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0093] The embodiment of the present invention further provides a computer program product 10 , a computer-readable storage medium 20 , and a computer device 30 . Figure 7 is a schematic diagram of a computer program product 10 according to one embodiment of the present invention, Figure 8 is a schematic diagram of a computer-readable storage medium 20 according to one embodiment of the present invention, Figure 9is a schematic diagram of a computer device 30 according to one embodiment of the present invention. A computer program product 10 includes a computer program 11. When executed by a processor 32, the computer program 11 implements the steps of any of the aforementioned layout methods. A computer-readable storage medium 20 stores the computer program 11. When executed by the processor 32, the computer program 11 implements the steps of any of the aforementioned layout methods. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and executed by the processor 32.

[0094] The computer program 11 for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit.

[0095] In the description of this embodiment, the computer program product 10 is a related product including the computer program 11 .

[0096] For the purposes of the description of this embodiment, the computer-readable storage medium 20 is a tangible device capable of retaining and storing the computer program 11, and can be any device that can contain, store, communicate, propagate, or transmit the computer program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium 20 include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, and any suitable combination of the foregoing.

[0097] The computer device 30 can be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smartphone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. The computer device 30 can be implemented in a distributed cloud computing environment where remote processing devices linked via a communication network perform tasks. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media, including storage devices.

[0098] The computer device 30 may include a processor 32 adapted to execute stored instructions, and a memory 31 that provides temporary storage for the instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0099] The computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows data to be input and output with external devices that can be connected to the computer device. The network adapter / interface can provide communication between the computer device and a network, which is generally shown as a communication network.

[0100] At this point, those skilled in the art will recognize that, although a number of exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications consistent with the principles of the present invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A mask layout method, characterized in that: include: Dividing the mask into a plurality of chip frame areas, each of which is used to set a chip layout of a corresponding chip, and having cutting lanes between the chip frame areas; Constructing a measurement layout framework, wherein the measurement layout framework is used to set one or more measurement link tags, each of which corresponds to a measurement pattern, and the measurement pattern is used to reflect the corresponding process indicators of the mask in the chip manufacturing process; One or more measurement layout frames are respectively set in one or more cutting streets.

2. The layout method according to claim 1, wherein: The steps of constructing the measurement link tag include: Based on the process nodes of the corresponding chips in the chip frame regions of the mask, and / or the process indicators of the mask during chip manufacturing, constructing a plurality of the measurement patterns, and generating a measurement pattern file for each of the measurement patterns; For each of the measurement graphic files, a measurement link tag is constructed respectively.

3. The layout method according to claim 1, wherein: The steps of constructing the measurement layout framework include: Acquiring layout-related features of each of the cutting lines in the mask, wherein the layout-related features of the cutting lines include the size of the cutting lines and the light transmittance category of the cutting lines on each layer; Determining layout-related features of each of the measurement link tags preset on the mask, wherein the layout-related features of the measurement link tags include the type and quantity of the measurement link tags; A plurality of measurement layout frameworks are constructed according to the layout-related features of the scribe lines and the layout-related features of the measurement link tags.

4. The layout method according to claim 3, wherein: The method of constructing a plurality of measurement layout frameworks according to the layout-related features of the dicing lanes and the layout-related features of the measurement link tags includes: Determining layout-related features of each of the measurement layout frames according to the layout-related features of the dicing lanes and the layout-related features of the measurement link tags, wherein the layout-related features of the measurement layout frames include a size of the measurement layout frame and a process node to which it belongs; sequentially arranging a preset number of label placement areas in each measurement layout frame, and determining the spacing between adjacent label placement areas; and The measurement link labels of corresponding types are respectively arranged in one or more label arrangement areas in each of the measurement layout frames.

5. The layout method according to claim 1, wherein: Before the step of respectively setting one or more measurement layout frames in one or more cutting lanes, the method further includes: A plurality of the measurement layout frames are displayed in a visual interface, and each of the measurement layout frames is arranged in a corresponding cutting lane by obtaining a drag operation on the measurement layout frame display area.

6. The layout method according to claim 1, wherein: After the step of respectively setting one or more measurement layout frames in one or more cutting lanes, the method further includes: Generating configuration information for recording the layout of each chip frame area, each dicing street, each measurement layout frame, and each measurement link label in the mask; and The configuration information is changed to change the layout of the mask.

7. The layout method according to claim 6, characterized in that: The configuration information includes: Size and coordinate information of each chip frame area; size and coordinate information of each cutting path; size and coordinate information of each of the measurement layout frames; and Type and position information of each measurement link tag in each measurement layout frame.

8. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the computer program is executed by a processor, the steps of the mask layout method according to any one of claims 1 to 7 are implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the mask layout method according to any one of claims 1 to 7 are implemented.

10. A computer device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the mask layout method according to any one of claims 1 to 7.

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