Data processing method, storage device and electronic device

Abstract

The invention provides a data processing method, storage equipment and electronic equipment, and relates to the technical field of storage, the storage equipment further comprises a controller and a nonvolatile memory connected with the controller, the nonvolatile memory comprises an SLC storage unit group and a QLC storage unit group, and the data processing method can be applied to the controller. Comprising the steps of receiving to-be-written data transmitted for storage equipment; caching the data to be written into the SLC storage unit group; and writing the to-be-written data cached in the SLC storage unit group into the QLC storage unit group. According to the embodiment of the invention, the limitation caused by the DRAM capacity, bandwidth, power failure protection and the like of the storage device can be eliminated, the writing performance of the QLC SSD is improved, the performance gap between the QLC SSD and the TLC SSD is reduced, and the QLC SSD is enabled to be applied to a wider application scene to reduce the cost on a large scale.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data processing method, a storage device, and an electronic device. Background Art

[0002] With the continued rapid growth of massive data, reducing storage costs has become crucial for cloud services. One effective way to reduce storage costs is to increase storage density. Quad-Level Cell (QLC) NAND Flash, a four-layer storage structure based on a three-dimensional (3D) stacking process, is currently the highest density flash memory available for commercialization. In recent years, improvements in production processes have significantly enhanced the data retention and durability of 3D QLC NAND. Therefore, improving the performance of 3D QLC NAND and enabling its wider application is crucial. Summary of the Invention

[0003] The embodiments of the present application provide a data processing method, a storage device, and an electronic device to alleviate or solve the technical problems existing in the prior art.

[0004] In a first aspect, an embodiment of the present application provides a data processing method applied to a controller of a storage device, wherein the storage device also includes a non-volatile memory connected to the controller, and the non-volatile memory includes an SLC storage cell group and a QLC storage cell group. The method includes: receiving data to be written transmitted to the storage device; caching the data to be written to the SLC storage cell group; and writing the data to be written cached in the SLC storage cell group into the QLC storage cell group.

[0005] In a second aspect, an embodiment of the present application provides a storage device, comprising a controller and a non-volatile memory connected to the controller, wherein the non-volatile memory comprises an SLC storage unit group and a QLC storage unit group, and the controller is used to implement the data processing method of the embodiment of the present application.

[0006] In a third aspect, an embodiment of the present application provides an electronic device, including the storage device of an embodiment of the present application.

[0007] In the embodiment of the present application, the SLC storage unit configured inside the non-volatile memory (QLC NAND medium) is used as a write cache, which breaks through the capacity limitations of volatile memory caches such as DRAM, exploits the high concurrency and throughput advantages of NAND, and overcomes the bandwidth bottleneck of the DRAM controller; at the same time, the non-volatile characteristics of SLC also omit the power-off protection required for the corresponding volatile memory capacity, that is, it can eliminate the limitations brought by the DRAM capacity, bandwidth, power-off protection, etc. of the storage device, thereby improving the write performance of the QLC solid-state drive and enabling the QLC solid-state drive to be used in a wider range of application scenarios to reduce costs on a large scale.

[0008] The above description is only an overview of the technical solution of this application. In order to more clearly understand the technical means of this application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of this application more obvious and easy to understand, the specific implementation methods of this application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present application and should not be regarded as limiting the scope of the present application.

[0010] Figure 1 is a schematic diagram of an exemplary storage device architecture;

[0011] Figure 2 A schematic diagram of the architecture of a storage device provided in an embodiment of the present application;

[0012] Figure 3 A schematic diagram of the architecture of a storage device provided in an embodiment of the present application;

[0013] Figure 4 A flowchart of a data processing method provided in an embodiment of the present application;

[0014] Figure 5 Schematic diagram of an asynchronous data migration process from an SLC storage cell group to a QLC storage cell group in an embodiment of the present application;

[0015] Figure 6A Schematic diagram of write and read operations for a QLC storage cell in a conventional technical solution;

[0016] Figure 6B Schematic diagram of the non-balanced write and read operations for a QLC storage cell in an embodiment of the present application;

[0017] Figure 7ASchematic diagram of the medium state at the moment when the non-volatile memory 203 is full in an embodiment of the present application;

[0018] Figure 7B Schematic diagram of the medium state of the read cache process of the non-volatile memory 203 in the embodiment of the present application;

[0019] Figure 8 This is a schematic diagram of data transfer in an embodiment of the present application;

[0020] Figure 9 A flowchart of a data processing method provided in an embodiment of the present application;

[0021] Figure 10 This is an example diagram of the application of the data processing method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0022] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0023] To facilitate understanding of the technical solutions of the embodiments of the present application, the following describes the related technologies of the embodiments of the present application. The following related technologies can be combined with the technical solutions of the embodiments of the present application as optional solutions, and all of them fall within the scope of protection of the embodiments of the present application.

[0024] Application Scenario

[0025] Non-volatile memory (NVM) is a type of computer memory, as opposed to volatile memory. It's called "non-volatile" because it retains stored data even when power is off—it exhibits data retention. Unlike volatile memory, non-volatile memory can retain data for extended periods without requiring a power supply. Common non-volatile memory types include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory. Flash memory primarily includes NAND flash memory (NAND) and NOR flash memory (NOR). NAND is commonly used as the storage medium for solid-state drives (SSDs).

[0026] NAND can be divided into at least four types according to the particle type: Single-Level Cell (SLC) NAND, Double-Level Cell (MLC) NAND, Trinary-Level Cell (TLC) NAND and Quad-Level Cell (QLC) NAND. Among them, Cell is the smallest storage unit / smallest particle of NAND, which performs the task of data storage. Each Cell in SLC NAND stores 1 bit of data; each Cell in MLC NAND stores 2 bits of data, each Cell in TLC NAND stores 3 bits of data, and each Cell in QLC NAND stores 4 bits of data. As the amount of data stored in each Cell increases, the storage density and storage capacity of SLC NAND, MLC NAND, TLC NAND and QLC NAND also increase, but data retention capability (related to the number of erasable times and service life), storage speed and cost are usually negatively correlated with storage density.

[0027] Among them, QLC NAND is a high-storage-density flash memory that can currently be used for productization. With the improvement of production technology, the data retention capability and durability of QLC NAND have been significantly improved, and its lifespan has approached that of TLC NAND. In many scenarios, SSDs using QLC NAND as the storage medium (referred to as QLC SSDs) can already meet the service life requirements, which has accelerated the productization of low-cost 3D QLC SSDs, thereby effectively reducing costs. However, each cell of QLC NAND stores 4 bits of data, corresponding to 16 voltage levels, while each cell of TLC NAND stores 3 bits of data, corresponding to 8 voltage levels. Therefore, in a limited threshold voltage distribution range, QLC NAND requires a smaller write voltage pulse to write gradually than TLC NAND, which requires a longer write time. Similarly, when reading, it takes a longer read time because it is necessary to identify which of the 16 voltage levels it is. Therefore, the read and write delay of QLC NAND is greater than that of TLC NAND. In other words, QLC SSD access performance (such as latency and throughput) is still significantly lower than that of TLC SSDs, and therefore cannot meet user needs in some scenarios. These shortcomings limit the wider application of 3D QLC SSDs and also limit larger-scale cost savings. Therefore, exploring 3D QLC SSD performance improvements can promote the commercialization of low-cost storage media in a wider range of scenarios, thereby achieving significant benefits in ultra-large-scale infrastructure deployments.

[0028] Figure 1FIG. 1 is a schematic diagram of an exemplary storage device architecture. Figure 1 As shown, the storage device 100 is a QLC SSD, including an SSD controller 101, a volatile memory 102, a non-volatile memory 103, a capacitor group 104, and a host interface 105. Among them, the volatile memory 102 can be a static random access memory (SRAM) or a dynamic random access memory (DRAM), and the volatile memory 102 can be an on-chip memory, such as an on-chip DRAM, or an off-chip memory, such as an off-chip DRAM. The non-volatile memory 103 is a QLC NAND, that is, it includes multiple QLC NAND units, each QLC NAND unit includes multiple cells, and each cell can store 4 bits of data.

[0029] like Figure 1 As shown, the storage device 100 uses a large-capacity volatile memory 102 (such as DRAM) as a write cache. The working principle is as follows: when a user writes data to the storage device 100, under the control of the SSD controller 101, the data is first cached in the DRAM, and then a write success is returned to the host. After that, the data is asynchronously moved from the DRAM write cache to the QLC NAND unit of the non-volatile memory 103 for persistence. Because the data entering the DRAM write cache needs to pass through the power-off protection circuit in the storage device 100 to provide the power required to persist a large amount of data in the event of a failure, current engineering implementations all use supercapacitors provided by the capacitor bank 104. The reliability of this function is limited by the capacity of the capacitor bank 104.

[0030] This solution has the following disadvantages: (1) The power that the supercapacitors of capacitor bank 104 can provide is still relatively limited, so the power required to persist a large amount of data when a fault occurs is limited; (2) The amount of data written in a single QLC NAND is significantly larger than that of TLC NAND, and the write latency is significantly greater than that of TLC NAND. Therefore, under the premise of maintaining the same write throughput, the capacity requirement of on-chip DRAM increases significantly. Therefore, high-cost low-power double data rate dynamic random access memory (LPDDR DRAM) is required as on-chip DRAM, so this solution will bring about a significant increase in cost; (3) There is a bandwidth limitation between DRAM and the memory controller of the SSD controller, resulting in memory throughput bottlenecks and link bottlenecks, which in turn causes memory overflow; (4) When the on-chip DRAM capacity increases, the implementation of the power-off protection function of the storage device 100 will become unstable due to device limitations. Under fluctuation conditions, the probability of data loss increases, which directly affects the data reliability and availability of the storage device 100.

[0031] In view of the various disadvantages of using a large-capacity DRAM as a write cache in the storage device 100, an embodiment of the present application provides a technical solution for improving the write performance and read performance in a QLC SSD.

[0032] Figure 2 This is a schematic diagram of the architecture of a storage device provided in an embodiment of the present application. Figure 2 As shown, the storage device 200 is a QLC SSD, including a controller 201 and a non-volatile memory 203. The controller 201 and the non-volatile memory 203 are connected, so that an electrical connection and a communication connection can be formed between the controller 201 and the non-volatile memory 203. Among them, the non-volatile memory 203 includes an SLC storage cell group and a QLC storage cell group. Specifically, the SLC storage cell group includes a plurality of SLC storage cells (i.e., a plurality of SLC NAND cells), and the QLC storage cell group includes a plurality of QLC storage cells (i.e., a plurality of QLC NAND cells). Each SLC storage cell includes a plurality of cells, each cell stores 1 bit of data. Exemplarily, the SLC storage cell can be a pseudo single-level cell (pseudo Single-Level Cell, pSLC) NAND cell; each QLC storage cell includes a plurality of cells, each cell stores 4 bits of data.

[0033] The controller 201 can control and implement functions such as communication and data transmission, receiving and parsing input / output (I / O) requests, and maintaining one or more request queues. In an embodiment of the present application, the controller 201 can be used to control data write operations, including: receiving data to be written transmitted to the storage device 200; caching the data to be written to the SLC storage cell group; and writing the data to be written cached in the SLC storage cell group to the QLC storage cell group.

[0034] That is to say, in an embodiment of the present application, the SLC storage cell group is used as a write cache, and the data written into the SLC storage cell group is temporarily stored in the SLC storage cell group. The back-end asynchronously starts a write operation from the SLC storage cell group to the QLC storage cell group, thereby persisting the data to be written to the QLC storage cell group.

[0035] Figure 3 This is a schematic diagram of the architecture of a storage device provided in an embodiment of the present application. Figure 3 As shown, the storage device 300 is a QLC SSD, including a controller 201, a volatile memory 302, and a non-volatile memory 203. The controller 201 and the volatile memory 302 are connected, and the volatile memory 302 and the non-volatile memory 203 are connected, so that an electrical connection and a communication connection can be formed between the controller 201 and the volatile memory 302, and an electrical connection and a communication connection can be formed between the volatile memory 302 and the non-volatile memory 203. The volatile memory 302 can be SRAM or DRAM. The volatile memory 302 can be on-chip memory, such as on-chip DRAM, or can be off-chip memory, such as off-chip DRAM. This embodiment of the present application is not limited to this.

[0036] That is, in the storage device 300, the volatile memory 302 and the SLC storage unit group can be used as parallel write caches. Specifically, under the control of the controller 201, the data to be written is preferentially cached in the volatile memory 202 ( Figure 3 Path A), and then asynchronously write to the QLC storage unit group for persistence ( Figure 3 When the volatile memory 202 has a capacity bottleneck or a throughput bottleneck, causing the volatile memory 202 to enter a cache saturation state, the data to be written is cached in the SLC storage unit group ( Figure 3 In path B), the data written to the SLC storage cell group is temporarily stored in the SLC storage cell group until one SLC storage cell group is full. The backend then asynchronously starts a write operation from the SLC storage cell group to the QLC storage cell group, thereby persisting the data to be written to the QLC storage cell group.

[0037] In the embodiment of the present application, the large-capacity SLC storage unit configured inside the non-volatile memory 203 (QLC NAND medium) is used as a write cache, which breaks through the capacity limitation of volatile memory caches such as DRAM, exploits the high concurrency and throughput advantages of NAND, and overcomes the bandwidth bottleneck of the DRAM controller; at the same time, the non-volatile characteristics of SLC also omit the power-off protection required for the corresponding volatile memory capacity, that is, it can eliminate the limitations brought by the DRAM capacity, bandwidth, power-off protection, etc. of the storage device, improve the write performance of QLC SSD, narrow the performance gap between QLC SSD and TLC SSD, and enable QLC SSD to be used in a wider range of application scenarios to reduce costs on a large scale.

[0038] It should be noted that the above-mentioned application scenarios or application examples provided in the embodiments of the present application are for ease of understanding, and the embodiments of the present application do not specifically limit this. In addition, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to select or edit authorization or rejection.

[0039] The following specific embodiments are used to describe in detail the technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems. The several specific embodiments listed can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0040] Example 1

[0041] The embodiments of the present application can be applied to Figure 2 In the storage device 200 shown. Figure 4 The flowchart of the data processing method provided in the embodiment of the present application can be applied to the controller 201 of the storage device 200, that is, the data processing method can be implemented by the controller 201 of the storage device 200. Figure 2 and Figure 4 As shown, the data processing method may include:

[0042] Step S401: receiving data to be written that is transmitted to the storage device 200.

[0043] Among them, the storage device 200 can be provided with a host interface for receiving the data to be written input by the host user. The data to be written is the data that needs to be written to the storage device for persistence. When the storage device 200 is assembled on a certain electronic device (host side), the host interface can serve as an interactive interface between the storage device and the electronic device to implement interactive operations such as reading and writing data on the storage device 200. The host interface can be internally connected to the controller 201, and during the corresponding data writing process, the host interface transmits the data to be written provided by the storage engine on the electronic device to the controller 201.

[0044] For example, when any application or electronic device transmits data to be written to the storage device 200 , the controller 201 will receive the data to be written and implement the following write operation for the data to be written.

[0045] Step S402: Cache the data to be written into the SLC storage unit group.

[0046] For example, when the controller 201 receives the above-mentioned data to be written, the controller 201 can write the data to be written into the SLC storage unit group of the non-volatile memory 203 for caching, and feedback to the host side that the data to be written is written successfully, so as not to affect the host side's perception of write delay.

[0047] Step S403: writing the data to be written cached in the SLC storage unit group into the QLC storage unit group.

[0048] Under the control of controller 201, data to be written, cached in the SLC storage cell group, can be asynchronously written to the QLC storage cell group of non-volatile memory 203 for persistence. For example, when the storage space of a group of SLC storage cell groups is full, an asynchronous write operation from the SLC storage cell group to the QLC storage cell group can be initiated. For example, backend bandwidth can initiate a sequential large-block read operation from the SLC storage cell group to a sequential large-block write operation in the QLC storage cell group.

[0049] In an embodiment of the present application, the SLC storage cell group is used as a write cache, and the data written into the SLC storage cell group is temporarily stored in the SLC storage cell group. The back-end asynchronously starts the write operation from the SLC storage cell group to the QLC storage cell group, thereby eliminating the limitations of the storage device's DRAM capacity, bandwidth, power-off protection, etc., and improving the write performance of the QLC SSD.

[0050] It should be noted that controller 201 can be a multi-channel controller, with each channel corresponding to a cache channel formed by M1 SLC storage cell groups and a storage channel formed by M2 QLC storage cell groups. During write operations, the channels are activated in parallel to increase throughput. M1 and M2 are positive integers and are not limited to 1. The ratio of M1 to M2 can be adjusted based on the balance between storage capacity and throughput, which is not limited in this embodiment of the present application.

[0051] In one embodiment, in step S403, writing the data to be written cached in the SLC storage cell group into the QLC storage cell group may include: reading N data pages from the SLC storage cell group; and writing the read N data pages into N / 4 QLC storage cells, where N is a positive integer and is greater than or equal to 1.

[0052] As mentioned above, each SLC storage cell group includes multiple SLC storage cells. Each time a read is performed, a data page (also called a flash memory page) can be read from one SLC storage cell. Assuming that each SLC storage cell group includes N SLC storage cells, then each time a read is performed, N data pages can be read from one SLC storage cell group.

[0053] For example, Figure 5 As shown, during the asynchronous data migration process from the SLC storage cell group to the QLC storage cell group, N data pages are read from an SLC storage cell group each time, the batch of data is folded and merged, written to the page buffer of N / 4 QLC storage cells, and then writing to these N / 4 QLC storage cells is started. Taking the SLC storage cell group as one group and the QLC storage cell group as four groups as an example, the N data pages read from the SLC storage cell group for the first time are written to the page cache of the N / 4 QLC storage cells in the first group; the N pages read from the SLC storage cell group for the second time are written to the page cache of the N / 4 QLC storage cells in the second group; the N pages read from the SLC storage cell group for the third time are written to the page cache of the N / 4 QLC storage cells in the third group; the N pages read from the SLC storage cell group for the fourth time are written to the page cache of the N / 4 QLC storage cells in the fourth group; after the above four groups of QLC storage cells are successfully written, the above operation is repeated until the valid data in the SLC storage cell group storing the data is completely moved. Among them, placing the N data pages read from the SLC storage cell group into different groups of storage cell groups each time can ensure the uniformity of the data reading process, but the embodiments of the present application are not limited to this and can be configured according to the grouping of the storage cell groups and the load requirements.

[0054] It can be seen that in the technical solution of the embodiment of the present application, the data migration from the SLC storage cell group to the QLC storage cell group is asynchronous noisy data migration. Specifically, the original data read from the SLC storage cell group is directly written to the QLC storage cell group. That is, in the data migration process from the SLC storage cell to the QLC storage cell, there is no need for the controller to encode and decode the data to eliminate noise, thereby shortening the write time (or migration time) of writing the cached data to be written in the SLC storage cell group to the QLC storage cell group, and reducing the resource overhead of the controller to avoid resource occupation of concurrent host-side read and write operations.

[0055] In one embodiment, the above-mentioned writing of the read N data pages into N / 4 QLC storage units may include: in response to the presence of failed data blocks in the read N data pages, updating the mapping relationship between the logical block addresses and physical block addresses of the valid data blocks in the read N data pages, and sequentially writing the valid data blocks into the N / 4 QLC storage units.

[0056] Among them, the data page may include multiple data blocks, such as a logical block address (LBA) data block. In data storage, LBA is a common data addressing method, and each LBA corresponds to a specific data block. In the process of moving data from the SLC storage unit group to the QLC storage unit group, there may be invalid data blocks in the data page read from the SLC storage unit group. In this case, it is only necessary to fully copy the valid data blocks therein, update the mapping relationship of the valid data blocks from the logical block address (LBA) to the physical block address (PBA), and write them to the QLC storage unit group in sequence.

[0057] For example, the six LBA data blocks ABCDEF are read out from the SLC storage unit group. During the copying process, the controller 201 detects that the data block C and the data block E have become invalid (such as the data block C and the data block E are updated or deleted by the host side). In this case, there is no need to copy the data block C and the data block E, and only the valid data blocks ABDF need to be copied. The specific implementation can be to sequentially move the valid data blocks ABDF in units of LBA data block size, and update the LBA to PBA mapping to fill the "holes" in the six data blocks.

[0058] Based on this, on the one hand, correct access to data can be ensured, and on the other hand, the utilization of storage space can be maximized to avoid space waste caused by "holes".

[0059] In one embodiment, the method of the embodiment of the present application may further include: in response to the data to be written cached in the SLC storage cell group being written to the QLC storage cell group, erasing the data to be written cached in the SLC storage cell group.

[0060] Among them, when the data in an SLC storage cell group is successfully moved to the QLC storage cell group, the data in the SLC storage cell group is erased, so that the SLC storage cell group can be placed in the write cache resource pool to release resources for subsequent cache allocation.

[0061] In one embodiment, the method of the embodiment of the present application may further include: in response to the data to be written in the SLC storage cell group being written into the QLC storage cell group, updating the data refresh time of the QLC storage cell group.

[0062] Among them, the SLC storage unit and the QLC storage unit have different data retention capabilities. Each Cell in the SLC storage unit only stores one bit of data, and its data retention capability is strong, while each Cell in the QLC storage unit stores four bits of data, and its data retention capability is relatively weak. In the embodiment of the present application, in order to improve the writing efficiency, direct copying of data with noise is adopted, that is, the data movement from the SLC storage cell group to the QLC storage cell group is asynchronous noisy data movement. Therefore, after the data is stored in the SLC storage cell group for a period of time, some erroneous data bits will be generated, that is, noise is superimposed. However, these data are not decoded by the Error Correction Code (ECC) to correct the noise, but are directly written to the QLC storage cell group.

[0063] Therefore, a predicted data refresh time (deadline) is calculated based on the data retention capabilities of SLC and QLC storage cells, and the data stored in the QLC storage cells is actively or passively refreshed before this data refresh time arrives. This ensures that the data is refreshed before it naturally degrades to the point where it cannot be read correctly, thus preventing data from being read correctly and maintaining data integrity and readability.

[0064] In one embodiment, an SLC storage cell group includes a plurality of SLC storage cells, a QLC storage cell group includes a plurality of QLC storage cells, two bits of to-be-written data are written into the upper two bits of the QLC storage cells, and two bits of preset padding data are written into the lower two bits of the QLC storage cells. The method of this embodiment of the present application may further include: reading data in the upper two bits of the data from the QLC storage cells each time.

[0065] Based on this, an embodiment of the present application provides a solution for asymmetrically writing data to and reading data from a QLC storage unit.

[0066] That is, when writing data to a QLC storage cell, the writing method is based on storing four bits of data per cell. Specifically, for each cell of the QLC storage unit, the upper two bits are written with two bits of data to be written, while the lower two bits are written with two bits of preset fill data, that is, filling two bits of data according to a virtual mode. The preset fill data can be a pre-set value or a value generated according to a certain algorithm or rule, and this embodiment of the application is not limited to this.

[0067] Furthermore, when reading data from the QLC storage unit, a two-bit data reading method is used for each cell (similar to the MLC reading method). Specifically, for each cell of the QLC storage unit, the upper two bits of data are read.

[0068] Figure 6A Schematic diagram of write and read operations for a QLC storage cell in a conventional technical solution; Figure 6B Schematic diagram of the non-balanced operation of writing and reading QLC storage cells in the embodiment of the present application. Figure 6A As shown in the figure, if when writing data to a QLC storage cell, four bits of original data to be written are stored in each cell, corresponding to 16 voltage levels, then when reading data from the QLC storage cell, since it is necessary to identify which of the 16 voltage levels it is, it takes at most 15 reads, so the required reading time is longer. Figure 6B As shown in the figure, since the lower two bits are filled with preset data during writing, only the upper two bits need to be read during reading, so only three reads are required at most. It can be seen that the unbalanced writing and reading scheme of the embodiment of the present application can significantly shorten the read latency of the QLC storage unit, thereby improving the cache hit rate and read performance.

[0069] In one implementation, based on the above-mentioned write and read imbalance solution, the embodiment of the present application further provides a solution of a convertible MLC read cache and a non-convertible SLC read cache based on redundant capacity.

[0070] Specifically, the storage data in the non-volatile memory 203 is divided into first storage data (hot data HS), second storage data (warm data HM), and third storage data (cold data C) according to access frequency from high to low. The QLC storage cell group includes a first QLC storage cell used as a usable capacity and a second QLC storage cell used as a redundant capacity. The SLC storage cell group is used to store the first storage data, and the first QLC storage cell is used to store the second storage data and the third storage data. The method of the embodiment of the present application may also include: reading four bits of data from the first QLC storage cell where the second storage data is located; converting the read data into two data groups, wherein the upper two bits of data of each data group come from the read data, and the lower two bits of data of each data group come from preset padding data; and writing one data group into one first QLC storage cell.

[0071] For example, the first stored data (hot data HS), the second stored data (warm data HM), and the third stored data (cold data C) are categorized based on data access frequency and importance. For example, hot data is frequently accessed and modified, such as real-time transaction data and user session data. Warm data is accessed less frequently than hot data. Cold data is accessed less frequently than warm data and may not be accessed for long periods of time, but needs to be retained for various reasons (such as compliance and backup).

[0072] Figure 7A and Figure 7B The schematic diagram of the internal medium conversion of the non-volatile memory 203 after the nominal capacity is filled is shown. Figure 7A and Figure 7B This section details the solutions for convertible MLC read cache and non-convertible SLC read cache based on redundant capacity.

[0073] in, Figure 7A The media status at the moment when the non-volatile memory 203 is full. Figure 7A In the example, the first stored data (such as hot data HS) and the second stored data (such as warm data HM) are not distinguished and are both represented as "H". The third stored data is cold data and is represented as "C". Figure 7A As shown, the SLC storage cell group is used as a write cache, and the cached data has been moved to the QLC storage cell group and erased; each QLC storage cell group is divided into two parts, one part is composed of the first QLC storage cell and used as the usable capacity, and the other part is composed of the second QLC storage cell and used as the redundant capacity.

[0074] Figure 7B It is the medium status of the read cache process of the non-volatile memory 203. Figure 7BIn the example, the first stored data is hot data, which is represented by "HS", the second stored data is warm data, which is represented by "HM", and the third stored data is cold data, which is represented by "C".

[0075] On the one hand, if Figure 7B As shown in , SLC storage units are used to store hot data for fast reading. Figure 7B As shown, a small amount of redundant flash memory cells are reserved in the redundant capacity as the first redundant capacity for bad block replacement; the rest of the storage capacity in the redundant capacity is used as the second redundant capacity, and data is written according to the aforementioned non-balanced writing and reading method, that is, the upper two bits are written with two bits of data to be written, and the lower two bits are written with two bits of preset padding data; at the same time, a portion of the capacity equal to the second redundant capacity is used to store warm data, and data is written according to the aforementioned non-balanced writing and reading method, that is, the QLC storage cells where the warm data is located are read one by one, and a group of 4-bit data read is divided into two groups of 2-bit data, and 2 bits of preset padding data are appended to the 2-bit data of each group to form a group of 4-bit data, which is written to the Cell of a QLC storage cell, so that when a QLC storage cell group (for example, group A) is full of data, its data is adjusted and written to the other two QLC storage cell groups.

[0076] Furthermore, after writing each data group to a first QLC storage unit, the process may also include erasing the data in the first QLC storage unit where the second data is stored. For example, after the data in group A is moved, the data thereon is erased and group A is reclaimed to free up space. The remaining capacity is then used to store cold data, maintaining the read latency of the QLC storage unit.

[0077] For example, Figure 8 As shown, with a large page of data (super page) as a reading unit, a reading unit contains two QLC pages, such as QLC page A and QLC page B. For each Cell of QLC page A, the upper two bits of data are read, and the lower two bits of preset filling data are filled to form four bits of data and transferred to one reading unit; similarly, for each Cell of QLC page B, the upper two bits of data are read, and the lower two bits of preset filling data are filled to form four bits of data and transferred to another reading unit. It can be seen that based on the unbalanced writing and reading scheme of the embodiment of the present application, the data of a QLC page can still be obtained each time it is read, which ensures the atomic reading and concurrent reading performance of the original data placement.

[0078] Example 2

[0079] The embodiments of the present application can be applied to Figure 3 In the storage device 300 shown. Figure 9 The flowchart of the data processing method provided in the embodiment of the present application can be applied to the controller 201 of the storage device 300, that is, the data processing method can be implemented by the controller 201 of the storage device 200. Figure 3 and Figure 9 As shown, the data processing method may include:

[0080] Step S901: receiving data to be written that is transmitted to the storage device 300.

[0081] Among them, the storage device 300 can be provided with a host interface for receiving the data to be written input by the host-side user. The data to be written is the data that needs to be written into the storage device for persistence. When the storage device 300 is assembled on a certain electronic device (host side), the host interface can serve as an interactive interface between the storage device and the electronic device to implement interactive operations such as data reading and writing for the storage device 300. The host interface can be connected to the controller 201 internally, and then in the corresponding data writing process, the host interface transmits the data to be written provided by the storage engine on the electronic device to the controller 201. Exemplarily, when any application or electronic device transmits the data to be written to the storage device 300, the controller 201 will receive the data to be written and implement the write operation for the data to be written below.

[0082] Step S902 : Buffering data to be written into the volatile memory 302 .

[0083] For example, after the controller 201 receives the data to be written, the controller 201 may write the data to be written into the volatile memory 302 for caching, and feedback to the host that the data to be written is written successfully, thereby not affecting the host's perception of write delay.

[0084] Step S903 : when the cache of the volatile storage 302 is saturated and there is uncached data to be written, the uncached data to be written is cached in the SLC storage unit group of the non-volatile memory 203 .

[0085] That is, the SLC storage unit group of the volatile memory 302 and the non-volatile memory 203 can be used as a parallel write cache. The data to be written is first cached in the volatile memory 202 ( Figure 3 In path A), when the volatile memory 202 has a capacity bottleneck or a throughput bottleneck causing the volatile memory 202 to enter a cache saturation state, the data to be written is cached in the SLC storage unit group ( Figure 3 Middle path B).

[0086] The step of caching the data to be written into the SLC storage unit group of the non-volatile memory 203 may refer to step S402 in the first embodiment, and will not be described in detail here.

[0087] Step S904 : writing the data to be written cached in the volatile memory 302 into the QLC storage unit group of the non-volatile memory 203 .

[0088] Under the control of the controller 201, the data to be written is first cached in the volatile memory 202 ( Figure 3 Path A), and then asynchronously write to the QLC storage unit group for persistence ( Figure 3 Middle path C).

[0089] Step S905: writing the data to be written cached in the SLC storage unit group into the QLC storage unit group.

[0090] When the volatile memory 202 has a capacity bottleneck or a throughput bottleneck, causing the volatile memory 202 to enter a cache saturation state, the data to be written is cached in the SLC storage unit group ( Figure 3 In path B), the data written to the SLC storage cell group is temporarily stored in the SLC storage cell group until one SLC storage cell group is full. The backend then asynchronously starts a write operation from the SLC storage cell group to the QLC storage cell group, thereby persisting the data to be written to the QLC storage cell group.

[0091] Among them, step S905 can adopt the same or similar implementation as step S403 in embodiment 1, which will not be repeated here. It should be noted that step S904 and step S905 can be executed concurrently, and their order is not limited in this embodiment of the application.

[0092] Based on the solution of the embodiment of the present application, when the volatile memory 302 in the storage device 300 has a capacity bottleneck or a throughput bottleneck, in order to match the front-end write performance, in addition to the volatile memory 302 as a write cache, the SLC storage unit of the non-volatile memory 203 is added as a parallel write cache, which can eliminate the limitations brought by the DRAM capacity, bandwidth, power-off protection, etc. of the storage device and improve the write performance of the QLC SSD. Furthermore, the embodiment of the present application utilizes the characteristics of the QLC NAND medium, and the area configured as the SLC storage unit can be continuously used as the SLC write cache, which can avoid the loss of service life caused by mode switching. On the other hand, as far as the non-volatile memory 203 as a whole is concerned, the data write mode has not changed, and therefore has no effect on the service life of the QLC NAND medium. The area of ​​the subsequent SLC storage unit can still be used as a QLC area to read and write storage data.

[0093] For example, Figure 10As shown, after the host-side write traffic data starts to enter the storage device 200, the storage device 300 receives the user write data (i.e., data to be written), and preferentially places it into the volatile memory 302 (such as a DRAM write cache), and returns a write success to the host side. The back-end integrates the format of the data in the DRAM write cache and asynchronously writes it to the QLC storage cell group. When a capacity bottleneck or a throughput bottleneck occurs, causing the volatile memory 202 to enter a cache saturation state, it switches to a parallel mode in which the DRAM and SLC storage cells are parallel write caches. The data outside the DRAM is cached from the controller 201 to the SLC storage cell group, and a write success is returned to the host side. The data written to the SLC storage cell group is temporarily stored in the area of ​​the SLC storage cell group until a group of SLC storage cell groups is full, and then a noisy copy is performed from the SLC storage cell group to the QLC storage cell group. After the data in a group of SLC storage cell groups is copied, the SLC storage cell group that has copied all the data is erased and released (returned) to the SLC resource pool.

[0094] It can be understood that, optionally, the method of the embodiment of the present application may further include: in response to the data to be written cached in the SLC storage cell group being written to the QLC storage cell group, erasing the data to be written cached in the SLC storage cell group. For specific implementation methods, please refer to the relevant description of Example 1. Optionally, the method of the embodiment of the present application may further include: in response to the data to be written in the SLC storage cell group being written to the QLC storage cell group, updating the data refresh time of the QLC storage cell group. For specific implementation methods, please refer to the relevant description of Example 1. In addition, in the technical solution of the embodiment of the present application, a scheme of unbalanced writing of data to the QLC storage cell and reading of data from the QLC storage cell, a scheme of convertible MLC read cache based on redundant capacity, and a scheme of non-convertible SLC read cache can also be adopted. For specific implementation methods, please refer to the relevant description of Example 1.

[0095] In the embodiment of the present application, the SLC configured inside the non-volatile memory 203 (QLC NAND medium) is used as a write cache, breaking through the capacity limitations of volatile memory caches such as DRAM, and exploiting the high concurrent throughput advantages of NAND to overcome the bandwidth bottleneck of the DRAM controller. At the same time, the non-volatile characteristics of SLC also omit the power-off protection required for the corresponding volatile memory capacity, that is, it can eliminate the limitations brought by the DRAM capacity, bandwidth, power-off protection, etc. of the storage device, improve the write performance of the QLC SSD, narrow the performance gap between QLC SSD and TLC SSD, and enable QLC SSD to be used in a wider range of application scenarios to reduce costs on a large scale. Furthermore, the technical solution of the embodiment of the present application connects the data retention management of SLC and QLC, and can realize asynchronous noisy data migration from the SLC storage cell group to the QLC storage cell group without going through the controller, achieving high-throughput and user-imperceptible asynchronous data migration and background refresh. Furthermore, the asymmetric design of writing and reading data to and from QLC storage cells allows for the reuse of a small amount of redundant capacity beyond the reserved space for bad block management. This significantly improves cache hit rates through low-latency, high-capacity, two-bit read caching without impacting the media's lifespan. This improvement in QLC SSD read and write performance is achieved through firmware and algorithm design within existing hardware.

[0096] Example 3

[0097] Corresponding to the application scenario and method of the method provided in the embodiment of the present application, the embodiment of the present application also provides a data processing device, which can be applied to the controller 201 of the storage device, and the storage device also includes a non-volatile memory connected to the controller, and the non-volatile memory includes an SLC storage cell group and a QLC storage cell group. The data processing device includes: a receiving module for receiving the data to be written transmitted to the storage device; a cache control module for caching the data to be written to the SLC storage cell group; and a write control module for writing the data to be written cached in the SLC storage cell group into the QLC storage cell group.

[0098] In one embodiment, the QLC storage cell group includes multiple QLC storage cells, and the cache control module is specifically used to: read N data pages from the SLC storage cell group; write the read N data pages into N / 4 QLC storage cells; where N is a positive integer and is greater than or equal to 1.

[0099] In one embodiment, the cache control module is further used to update the mapping relationship between the logical block addresses and physical block addresses of the valid data blocks in the N data pages read in response to the presence of invalid data blocks in the N data pages read, and sequentially write the valid data blocks into the N / 4 QLC storage units.

[0100] In one embodiment, the device further includes an erasing module for erasing the data to be written cached in the SLC storage cell group in response to the data to be written cached in the SLC storage cell group being written into the QLC storage cell group.

[0101] In one embodiment, the apparatus further includes an updating module configured to update a data refresh time of the QLC storage cell group in response to the data to be written in the SLC storage cell group being written into the QLC storage cell group.

[0102] In one embodiment, the QLC storage cell group includes multiple QLC storage cells, the upper two bits of the QLC storage cells are written with two bits of data to be written, and the lower two bits of the QLC storage cells are written with two bits of preset filling data.

[0103] In one embodiment, the device further includes a read control module configured to read data in two upper-order data bits from the QLC storage unit each time.

[0104] In one embodiment, the storage data of the non-volatile memory is divided into first storage data, second storage data, and third storage data according to access frequency from high to low, the QLC storage cell group includes a first QLC storage cell used as a usable capacity and a second QLC storage cell used as a redundant capacity, the SLC storage cell group is used to store the first storage data, and the first QLC storage cell is used to store the second storage data and the third storage data.

[0105] In one embodiment, the device further includes a copy control module configured to: read four bits of data from the first QLC storage unit where the second stored data is located; convert the read data into two data groups, wherein the upper two bits of data of each data group come from the read data, and the lower two bits of data of each data group come from preset padding data; and write one data group into one first QLC storage unit.

[0106] In one embodiment, the copy control module is further configured to erase data in the first QLC storage unit where the second storage data is located.

[0107] In one embodiment, the storage device also includes a volatile memory connected to the controller, and the cache control module is further used to cache the data to be written cached in the SLC storage cell group to the QLC storage unit before writing the data to be written to the volatile memory; when the volatile memory cache is saturated and there is uncached data to be written, the uncached data to be written is cached to the SLC storage cell group; the write control module is further used to write the data to be written cached in the volatile memory to the QLC storage cell group.

[0108] The functions of each module in each device in the embodiment of the present application can be referred to the corresponding description in the above method, and have corresponding beneficial effects, which will not be repeated here.

[0109] The present application also provides an electronic device including a storage device according to any of the above embodiments, such as storage device 200 or storage device 300. The storage device may be one or more, and the multiple storage devices may have the same operating principle or different operating principles, which is not limited in the present application.

[0110] When electronic devices are used in different systems or fields, other components of the electronic devices may be different. Other components of the electronic devices in the above embodiments may adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0111] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0112] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0113] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0114] Any process or method described in the flowchart or otherwise described herein can be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process. The scope of the preferred embodiments of the present application includes other implementations in which the functions may be performed in a different order than shown or discussed, including performing the functions substantially simultaneously or in reverse order depending on the functions involved.

[0115] The logic and / or steps described in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, apparatus or device and execute instructions), or used in combination with such instruction execution systems, apparatuses or devices.

[0116] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above embodiment method can be completed by instructing the relevant hardware through a program, which can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0117] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing module, or each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the aforementioned integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic disk, or an optical disk, etc.

[0118] The above is merely an exemplary embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope described in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, applied to a controller of a storage device, wherein the storage device further includes a non-volatile memory connected to the controller, the non-volatile memory including an SLC storage cell group and a QLC storage cell group, the method comprising: receiving data to be written transmitted to the storage device; caching the data to be written into the SLC storage unit group; The data to be written cached in the SLC storage unit group is written into the QLC storage unit group.

2. The method according to claim 1, wherein The QLC storage cell group includes a plurality of QLC storage cells, and writing the to-be-written data cached in the SLC storage cell group into the QLC storage cell group includes: Reading N data pages from the SLC storage unit group; Write the read N data pages into N / 4 QLC storage units; Wherein, N is a positive integer and is greater than or equal to 1.

3. The method according to claim 2, wherein: Write the read N data pages into N / 4 QLC storage units, including: In response to the presence of failed data blocks in the N data pages read, a mapping relationship between logical block addresses and physical block addresses of valid data blocks in the N data pages read is updated, and the valid data blocks are sequentially written into the N / 4 QLC storage units.

4. The method according to claim 1, further comprising: In response to the to-be-written data cached in the SLC storage unit group being written into the QLC storage unit group, the to-be-written data cached in the SLC storage unit group is erased.

5. The method according to claim 1, further comprising: In response to the data to be written in the SLC storage cell group being written into the QLC storage cell group, a data refresh time for the QLC storage cell group is updated.

6. The method according to claim 1, wherein The QLC storage cell group includes a plurality of QLC storage cells, wherein two bits of data to be written are written into the upper two bits of the QLC storage cells, and two bits of preset filling data are written into the lower two bits of the QLC storage cells.

7. The method according to claim 6, further comprising: The data in the upper two bits are read from the QLC storage unit each time.

8. The method according to claim 1, wherein the storage data of the non-volatile memory is divided into first storage data, second storage data, and third storage data according to access frequency from high to low, the QLC storage cell group includes a first QLC storage cell used as a usable capacity and a second QLC storage cell used as a redundant capacity, the SLC storage cell group is used to store the first storage data, and the first QLC storage cell is used to store the second storage data and the third storage data.

9. The method according to claim 8, further comprising: Reading four bits of data from the first QLC storage unit where the second stored data is located; Convert the read data into two four-bit data groups, wherein the upper two bits of each data group come from the read data, and the lower two bits of each data group come from the preset padding data; A data group is written into a first QLC storage unit.

10. The method according to claim 9, further comprising: Erasing data in the first QLC storage unit where the second storage data is located.

11. The method according to any one of claims 1 to 10, wherein The storage device further includes a volatile memory connected to the controller. Before writing the to-be-written data cached in the SLC storage unit group into the QLC storage unit, the method further includes: caching the data to be written into the volatile memory; When the volatile memory cache is saturated and there is uncached data to be written, the uncached data to be written is cached in the SLC storage unit group.

12. The method according to claim 11, further comprising: Writing the data to be written cached in the volatile memory into the QLC storage unit group.

13. A storage device comprising a controller and a non-volatile memory connected to the controller, the non-volatile memory comprising an SLC storage cell group and a QLC storage cell group, the controller being configured to implement the method according to any one of claims 1 to 10. 14 . The storage device according to claim 13 , further comprising a volatile memory connected to the controller, wherein the controller is further configured to implement the method according to claim 11 or 12 .

15. An electronic device comprising the storage device according to claim 13 or 14.

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