Write amplification suppression method and device and storage equipment

Abstract

The invention discloses a write amplification suppression method and device and storage equipment. The method comprises the following steps: selecting a memory which frequently eliminates memory data of the memory to a storage chip of the memory from a plurality of memories as a target memory; and sending a read IO request to the target memory, thereby inhibiting the target memory from performing data elimination. Due to the fact that the multiple storages have the corresponding idle triggering time, under the condition that the time when the storages do not receive the IO requests continuously reaches the idle triggering time, the storages eliminate the memory data of the storages into the storage chips of the storages. According to the process, the target memory can receive the IO request all the time by sending the read IO request to the target memory without touching the idle trigger time, so that the frequency of eliminating data in the memory data of the target memory to a memory chip of the target memory can be reduced, the erasing frequency of the target memory is further reduced, and the user experience is improved. A write amplification problem of a target memory is suppressed.

Description

Technical Field

[0001] The present application relates to the field of storage, and in particular to a write amplification suppression method, apparatus, and storage device. Background Art

[0002] Solid-state drives (SSDs) are widely used because they offer faster read and write speeds and faster system boot times than traditional mechanical hard drives, improving overall system performance. They are often used by disk manufacturers as system disks to store operating systems and system software. SSDs read and write in pages, but erase in blocks. A page contains 4K of data, while a block contains 64 pages. Therefore, when data to be written needs to be written to the SSD and there is insufficient disk space, garbage collection of a block is required to free up space for the data to be written. Because the block may contain valid data, the valid data in the block cannot be directly erased. Instead, the valid data in the block must be relocated, and then the block must be erased before the data to be written can be written.

[0003] The above process is garbage collection. This process causes the actual amount of data written to be many times greater than the data to be written, resulting in write amplification (WA) on the disk, which in turn affects the lifespan of the SSD. When the SSD's lifespan is affected, upper-tier storage application vendors are forced to replace the disk, which increases costs. Currently, SSD WA is typically reduced by increasing the SSD's over-provisioning (OP) or executing the TRIM instruction. To reduce the amount of data relocation during garbage collection, the number of reserved blocks in the SSD can be increased, allowing for more flexible block management and allocation. This reduces the probability of writing to blocks with valid data, thereby reducing the number of garbage collection triggers and, consequently, the amount of data relocation during garbage collection. The TRIM instruction enables the SSD to identify and mark garbage data within a block area, thus avoiding its relocation during garbage collection. These two methods can reduce WA to a certain extent, but they cannot fundamentally resolve the issue. Furthermore, increasing the SSD's OP WA reduces the actual available disk space. The TRIM instruction also requires support from the corresponding SSD firmware and may not be applicable to all SSDs. Summary of the Invention

[0004] The present application discloses a write amplification suppression method, apparatus, and storage device. By sending a read IO request to an idle area of ​​a target memory, the target memory is determined to be in a non-idle state at all times, thereby reducing the triggering operation of writing data in the memory memory to the storage medium of the memory, reducing the number of erase and write times of the memory, thereby suppressing the write amplification problem of the memory, extending the service life of the memory, reducing replacement, and reducing costs.

[0005] In a first aspect, the present application provides a write amplification suppression method, which includes: selecting a target memory from a plurality of memories, wherein the target memory is a memory that frequently eliminates data from the memory 220 to the flash memory chip 230 of the memory; and suppressing data elimination from the target memory by sending a read IO request to the target memory.

[0006] The first aspect is that by actively initiating IO requests, the memory is prevented from eliminating data in its own memory into the storage chip, thereby reducing the number of garbage collections, reducing the write amplification factor of the memory, and improving the service life of the memory.

[0007] In one possible implementation of the first aspect, this IO request is not an IO request required by the current business (not a user currently needs to read the corresponding data). For example, it may be an invalid IO request generated specifically to suppress data elimination (invalid means that the data generated by this IO request is not used to satisfy the user's data access); or it may be an IO request to pre-read data in advance to satisfy a future user's data read request (not the current user request).

[0008] Exemplarily, the memory is a solid state drive (SSD), or a memory having a write amplification problem caused by writing data.

[0009] Exemplarily, the method also includes: the target memory is a memory with a smaller idle trigger time among multiple memories, wherein the idle trigger time is a time period during which no input / output IO request is continuously received corresponding to the operation of triggering the memory to eliminate data from the memory 220 to the flash memory chip 230.

[0010] The above process shows that memories with shorter idle trigger times are more likely to trigger their idle trigger times, resulting in a higher frequency of data being removed from memory 220 and transferred to flash memory chip 230. This results in more valid data relocations and block erases within the memory, exacerbating the write amplification problem. Selecting memories with shorter idle trigger times as target memories identifies memories with more severe write amplification problems. Suppressing write amplification for these memories can improve efficiency and precisely address the write amplification problem.

[0011] Exemplarily, the specific process of sending a read IO request to the target memory is: sending a read IO request to a free area of ​​the target storage device.

[0012] Exemplarily, the specific process of sending a read IO request to the target memory is as follows: sending a read IO request to the target memory at a first time interval, wherein the first time interval is fixed and is less than the idle trigger time corresponding to the target memory; or sending a read IO request to the target memory at a second time interval, wherein the second time interval varies and is less than the idle trigger time corresponding to the target storage device.

[0013] The above process sends read IO requests to the target memory at time intervals determined according to the idle trigger time, so that the target memory can continuously receive read IO requests, so that the duration during which the target memory does not receive IO requests cannot reach the idle trigger time, thereby enabling the main controller of the target memory to determine that the target memory is not in an idle state, reducing the number of times the memory data of the target memory is eliminated to the storage medium of the memory, reducing the number of data migrations, and suppressing the write amplification problem of the target memory.

[0014] Illustratively, before obtaining the device information of the memory, the write amplification suppression method provided in the present application further includes: determining that the memory is proprietary hardware, the proprietary hardware including a memory with a capacitor, or a memory whose device has a battery backup unit.

[0015] A method for determining whether a memory is proprietary hardware specifically includes: obtaining capacitance parameters of the memory, or battery backup unit parameters of a device to which the memory belongs, where the capacitance parameters are used to indicate that the memory has a power-off protection function, and the battery backup unit parameters are used to indicate that the device to which the memory belongs has a battery backup unit; when the capacitance parameters of the memory or the battery backup unit parameters of the device to which the memory belongs are obtained, determining that the memory is proprietary hardware.

[0016] Because the write amplification suppression method provided in this application is implemented by reducing the frequency with which data in the memory is written to the memory's storage medium, there are situations in which the data in the memory cannot be written to the memory's storage medium in a timely manner for permanent storage. Determining whether the memory is proprietary hardware can determine whether the memory has a power-off protection function. If the memory is proprietary hardware, the memory can be enabled to protect data in the memory that is not written to the memory's storage medium in a timely manner during the application of the write amplification suppression method provided in this application.

[0017] After determining that the memory is proprietary hardware, the write amplification suppression method provided in the present application also includes: obtaining operating system parameters corresponding to the memory and performing parameter configuration, the operating system parameters including the mount directory of the memory and the write cache strategy of the memory.

[0018] Exemplarily, the operating system parameters corresponding to the memory are obtained and configured, specifically including: obtaining the memory mount directory and the memory write cache policy, then configuring the memory mount directory as an asynchronous (nobarrier) parameter, and configuring the memory write cache policy as a write-through policy.

[0019] The above process configures the mount directory as an asynchronous parameter, so that the synchronization mechanism is not used when writing, and the data in the memory is quickly written to the storage medium of the storage device. The write cache policy is configured as a write-through policy. Compared with other write cache policies, the data can be written to the storage medium of the storage device before being stored. This can reduce the amount of data written to the storage medium of the storage device, reduce the number of times the data in the memory of the storage device is written to the storage medium of the storage device, reduce the number of block erases and rewrites in the storage medium, and achieve the write amplification suppression effect of the storage device.

[0020] Exemplarily, after obtaining the free area of ​​the target memory, the above-mentioned write amplification suppression method further includes: determining whether the target memory exists based on the result of obtaining the free area of ​​the target memory; in the case of failure to obtain the free area of ​​the target memory, determining that the target memory does not exist and ending all operations.

[0021] In the case that the free area of ​​the target memory is successfully acquired, it is determined that the target memory exists, and the above operation of sending a read IO request to the free area of ​​the target memory is performed.

[0022] Determining whether the target memory exists can ensure that subsequent steps are effectively performed when the target memory exists. If the target memory does not exist, all operations are terminated, thereby reducing invalid operations.

[0023] Illustratively, since the target memory may also be in a replacement state during the process of sending a read IO request to the free area of ​​the target memory, after sending the read IO request to the free area of ​​the target memory, the above-mentioned write amplification suppression method further includes: determining whether the target memory exists based on the result of the read IO request; if the read IO request is successful, determining that the target memory exists, and sending the read IO request at a time interval; or, if the read IO request fails, determining that the target memory does not exist, and stopping sending the read IO request.

[0024] In summary, the write amplification suppression method provided by this application, on the one hand, reduces the amount of data written to the storage medium of the memory by configuring the mount directory as an asynchronous parameter and configuring the write cache policy as a write-through policy, thereby reducing the number of times the data in the memory of the memory is written to the storage medium of the memory, thereby suppressing the write amplification problem of the memory. On the other hand, by sending read IO to the target memory, the target memory is always in a non-idle state, reducing the number of operations to eliminate the memory data of the memory to the storage medium of the memory, reducing the number of data relocations in the target memory, and achieving the effect of suppressing write amplification.

[0025] In a second aspect, the present application provides a write amplification suppression device for use in a storage device including a memory. The device includes an acquisition unit and a processing unit. The acquisition unit is configured to select a target memory from a plurality of memories, wherein the target memory is a memory that frequently eliminates data from a memory 220 to a flash memory chip 230 of the memory; and the processing unit is configured to suppress data elimination from the target memory by sending a read IO request to the target memory.

[0026] In a third aspect, the present application provides a storage device, which includes a processor and multiple memories, wherein the multiple memories are used to persistently store data; the processor is used to execute the method in the first aspect or any possible implementation of the first aspect.

[0027] In a fourth aspect, the present application provides a computer program product, which, when executed by a storage device, implements the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0028] In a fifth aspect, the present application provides a computer-readable storage medium comprising computer instructions, which, when executed by a storage device, implement the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0029] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments.

[0031] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0032] Figure 2 This is a schematic diagram of the structure of an SSD provided in an embodiment of the present application;

[0033] Figure 3 This is a schematic structural diagram of a flash memory chip provided in an embodiment of the present application;

[0034] Figure 4 This is a flow chart of a write amplification suppression method provided by an embodiment of the present application;

[0035] Figure 5 Schematic diagram of the structure of a write amplification suppression device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will describe the technical solutions in the embodiments of this application in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] Manufacturers of solid state drives (SSDs) usually specify the idle duration of the SSD during design. When the SSD does not receive an IO request sent by an application for a period of time that reaches the idle duration, the SSD will write the data in the memory of the memory to the storage medium of the SSD for permanent storage. When the idle duration of the SSD is short, the frequency of the SSD writing the data in the memory of the SSD to the storage medium of the SSD is high, causing a high frequency of data relocation in the storage medium of the SSD, resulting in the actual amount of data written to the SSD being multiple times the amount of data to be written. In order to suppress the write amplification problem of the actual amount of written data doubling, the present application periodically sends a read IO request to the SSD so that the SSD determines that there is an IO request to be processed and that the SSD itself is not in an idle state. This will not trigger the writing of the data in the memory of the memory to the storage medium of the memory, thereby reducing the frequency of the operation of writing the data in the memory of the memory to the storage medium of the SSD, thereby achieving the write amplification suppression effect.

[0038] In addition to being applicable to SSDs, the embodiments of the present application are also applicable to other memories that cause write amplification when writing data. For such memories, when storing data in a memory chip, it is not possible to directly overwrite the old data in the memory chip. Instead, the storage space occupied by the old data in the memory chip must be erased first. These operations of erasing the memory chip (specifically, a portion of the storage space in the memory chip) include garbage collection (GC), which involves the migration of a portion of the old data, thereby causing the so-called "write amplification."

[0039] First, the application scenarios involved in this application are described. Figure 1 , Figure 1The storage device 100 includes at least a processor 110, a memory 120, and a storage 130. In one embodiment, the storage device may further include a battery backup unit 140 to protect data integrity in the event of a power outage.

[0040] The processor 110 is a central processing unit (CPU) for processing data access requests from outside the storage device 100 or requests generated within the storage device 100. In one possible implementation, Figure 1 Only one CPU is shown. In actual applications, there are often multiple CPUs, each of which has one or more CPU cores. This embodiment does not specifically limit the number of CPUs or CPU cores. In one possible embodiment, a device manager may run in processor 110. The device manager is a management tool in the operating system that is used to manage and monitor hardware devices in the computer. Through the device manager, users can view and manage various hardware devices in the computer, including the display, keyboard, mouse, battery, etc.

[0041] Memory 120 is used to store software programs. Processor 110 manages memory by running the software programs in memory 120. Memory 120 is also used to exchange data with the processor, storing data to be written to memory 130 or reading data from memory 130 to be sent. Memory 120 includes at least two types of memory. For example, memory can be either random access memory (RAM) or read-only memory (ROM). For example, RAM is dynamic random access memory (DRAM) or storage class memory (SCM). DRAM and SCM are merely exemplary in this embodiment. Memory can also include other types of random access memory, such as static random access memory (SRAM). For example, read-only memory can be programmable read-only memory (PROM) or erasable programmable read-only memory (EPROM). This embodiment does not specifically limit the number or type of memory.

[0042] The memory 130 can be a disk or other type of storage medium, such as an SSD or other type of hard disk, used to provide storage resources for storing data. This embodiment does not specifically limit the number and type of memory. In addition, the memory can be used as a system disk or a data disk. The memory in this application is generally a system disk, and this application does not specifically limit this. For convenience, the embodiments of this application are described using an SSD as an example.

[0043] The battery backup unit 140 is used to provide power to the storage device in the event of a sudden power outage, allowing the memory to completely write data to the memory's storage medium for permanent storage, thereby implementing data protection in the event of a power outage. In one possible embodiment, the battery backup unit can also be integrated into the memory, which is not specifically limited in this application.

[0044] like Figure 2 As shown, Figure 2 2 is a schematic diagram of the structure of an SSD provided by an embodiment of the present application. SSD 200 is a memory that mainly uses NAND Flash as a permanent memory, and includes a main controller 210, a memory 220, and multiple flash memory chips 230.

[0045] The main controller 210 is an embedded microchip that performs complex tasks such as managing data storage and maintaining SSD performance and lifespan. It includes a host interface 211, a processor 212, and multiple channel controllers 213. In one embodiment, to protect data integrity in the event of a power outage, the main controller may also include a capacitor 214.

[0046] The host interface 211 is used to communicate with a host, which may be any device such as a server, a personal computer, or an array controller.

[0047] The processor 212 is used to perform functions such as reading / writing data, garbage collection, and wear leveling.

[0048] The channel controller 213 provides multiple channels for the processor 212, which enables the processor to operate multiple flash memory chips in parallel through the multiple channels, thereby improving the underlying bandwidth.

[0049] Capacitor 214 is used to maintain normal power supply to the SSD for a short period of time in the event of a sudden power outage, allowing the SSD to completely write data from memory 220 to flash memory chip 230, thereby protecting data integrity in the event of a power outage. Capacitors may include supercapacitors, electrolytic capacitors, etc., and this application does not specifically limit the type of capacitor.

[0050] Memory 220 is used to store data to be written to the flash memory chip, store data to be sent after being read from the flash memory chip, or store mapping tables, block management information, and the like. Memory 220 can be a random access memory, such as DRAM or SCM. DRAM and SCM are merely exemplary in this embodiment. Memory can also include other random access memories, such as static random access memory, and this application does not specifically limit this.

[0051] The flash memory chip 230 includes multiple areas. Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a flash memory chip provided in an embodiment of the present application. Each plane 310 includes multiple blocks 320, and a block 320 is composed of multiple pages 330 (pages). A page is the smallest unit for writing data. The main controller writes data to a block 320 at a page granularity. However, when erasing data, the main controller can only erase an entire block 320 at a time. Block 320 is the smallest unit for data erasure. In one possible embodiment, the size of a page 330, the capacity of a block 320, the capacity of the flash memory chip, and the number of regions each flash memory chip has all have different specifications, and this application does not specifically limit this.

[0052] In the specific implementation, Figure 1 This is only one possible example of a storage device. A storage device may include more types and quantities of components, and this application does not specifically limit this. Storage device 100 may be used in the storage layer of a distributed storage system, a centralized storage system, or a personal PC. It may also be used in other systems or devices that provide storage services, and this application does not specifically limit this.

[0053] According to the above Figure 2 The SSD shown, and Figure 3 As can be seen from the flash memory chip structure shown, when writing data in the memory 220 into the flash memory chip of the SSD for permanent storage, it is necessary to check the block to determine whether there is enough space in the block to write the data to be written. If there is not enough space to write the data to be written, the valid data in the block is relocated and then the entire block is erased so that there is space to write the data to be written. Therefore, the above process causes the write amplification problem of the SSD.

[0054] Because writing data from memory 220 to the SSD's flash memory chips can cause write amplification, reducing the number of times data from memory 220 is written to the SSD's flash memory chips can alleviate this write amplification problem. However, to reduce the number of times data from memory 220 is written to the SSD's flash memory chips, it is necessary to first determine the cause of the data from memory 220 being written to the SSD's flash memory chips. Research has determined that the causes of data from SSD memory 220 being written to SSD's flash memory chips 230 include at least the following two:

[0055] The first method: When the application sends a write IO request, in order to ensure the persistence of the data and prevent data loss caused by sudden power failure during the data writing process, the operating system needs to first write the metadata stored in the memory 220 into the flash memory chip of the SSD for permanent storage, and then write the data in the memory 220 into the flash memory chip of the SSD.

[0056] The metadata includes the start and end markers of the write IO request transaction, the addresses of the blocks involved in the write IO request, and the data modification operations caused by the write IO request, such as modifying file content, creating or deleting files, etc. The metadata can also include more types and quantities of data, which are not specifically limited in this application.

[0057] The above-mentioned process of first writing the metadata to the flash memory chip of the SSD and then writing the data to be written corresponding to the actual write IO request to the flash memory chip of the SSD is the process of executing the synchronization (barrier) mechanism. The synchronization mechanism specifically includes: when the application sends the first write IO request, the file system first records the first metadata to the log stored in the flash memory chip, and after determining that the first metadata is successfully recorded in the log, the actual first data to be written is written to the flash memory chip of the SSD. While waiting for the confirmation message that the first metadata is successfully recorded in the log, the application continues to send write IO requests, and more data to be written to the flash memory chip accumulates in the memory of the memory. When receiving the confirmation message that the first metadata is successfully recorded in the log, the memory writes the data stored in the memory to the flash memory chip of the SSD.

[0058] At this point, the data being written to the SSD's flash memory chip includes not only the first data to be written but also a lot of data that has been subsequently written. This data is not the first data to be written by the current write IO request. Furthermore, after the metadata corresponding to the later accumulated write IO requests is recorded in the log, the later accumulated data will be written to the SSD's flash memory chip, causing the later accumulated data to be written to the SSD's flash memory chip to be written repeatedly.

[0059] The subsequent accumulation of pending data and the repeated writing of the pending data into the SSD's flash memory chips increase the amount of data written from the memory to the SSD's flash memory chips, requiring more blocks to store data. This in turn increases the number of block erases and rewrites, exacerbating the SSD's write amplification problem. The second approach: If the SSD does not receive an I / O request from an application within a certain period of time, the SSD controller determines that the SSD is currently idle and writes the data stored in memory 220 to the SSD's flash memory chips for permanent storage.

[0060] The above-mentioned process in which the SSD controller determines that the SSD is currently in an idle state and writes the data stored in the memory 220 to the flash memory chip of the SSD for permanent storage when the SSD does not receive an IO request sent by the application within a certain period of time is executed by the SSD self-flush mechanism. The self-flush mechanism specifically includes: when the SSD continuously does not receive an IO request sent by the application for a period reaching the idle trigger time, the SSD is determined to be in an idle state and the data stored in the memory 220 is written to the flash memory chip of the SSD for permanent storage. The idle trigger time is designed and determined by the SSD manufacturer and varies according to the model and purpose of the SSD. It can be a few milliseconds or a few seconds, and this application does not specifically limit this.

[0061] Whenever the SSD does not receive any IO requests from the application for a period of time that reaches the idle trigger time, the data stored in the memory 220 is written into the flash memory chip of the SSD. The shorter the idle trigger time is, the easier it is for the SSD to reach the idle trigger time for a period of time that does not receive any IO requests from the application. This causes an increase in the frequency of writing the data stored in the memory 220 into the flash memory chip of the SSD, resulting in an increase in the number of writes, block erases, and rewrites, which intensifies the write amplification problem of the SSD.

[0062] The above two methods are only specific examples. In actual applications, there may be other implementation methods, which are not specifically limited here. Since the write amplification problem of SSDs will affect the lifespan of SSDs, replacing SSDs will increase costs. Therefore, this application provides a write amplification suppression method. By configuring operating system parameters and sending read IO requests to the memory, the number of times the memory writes data temporarily stored in the memory to the flash memory chip is reduced, thereby reducing the number of garbage collection times, alleviating the write amplification problem, and improving the lifespan of the memory, saving costs for upper-layer storage application manufacturers.

[0063] After determining the reason for writing the data in the memory 220 to the flash memory chip of the SSD, solutions can be proposed for the above two reasons. Specifically, for the first method, the mount directory parameter is modified to nobarrier, so that when the application sends a write IO request, the data to be written does not need to wait for the confirmation information of the metadata being written to the storage medium of the SSD, and is written to the storage medium of the SSD faster, avoiding writing redundant data. In addition, the write cache strategy is modified to a write-through strategy, so that the data is written to the storage medium before being cached, and there is no data in the memory of the memory that has been modified but not written to the storage medium, which reduces the number of times the data in the memory of the memory is written to the storage medium of the memory. The modification of the above two parameters can achieve a write amplification suppression effect; for the second method, a read IO request is sent to the SSD to make the SSD determine that there is an IO request to be processed and that the SSD itself is not in an idle state, so that the operation of eliminating the data in the memory of the memory to the storage medium of the memory will not be triggered, thereby reducing the frequency of data elimination operations and achieving a write amplification suppression effect. The specific implementation process can be found in Figure 4 .

[0064] like Figure 4 As shown, Figure 4 This is a flowchart of a write amplification suppression method provided by an embodiment of the present application, which is applied to Figure 1 The storage device shown in FIG. 4 includes the following steps.

[0065] Step S410: Determine whether the memory is proprietary hardware. If it is determined that the memory is proprietary hardware, step S420 may be executed; otherwise, subsequent operations are not executed.

[0066] The memory can be Figure 2 The SSD, or other flash memory devices with write amplification issues, such as USB flash drives and SD cards, is described herein. This application does not specifically limit the type or quantity of memory. The proprietary hardware is a memory with a capacitor, or a memory device including a battery backup unit (BBU). When the proprietary hardware memory is proprietary, it ensures that data stored in the memory will not be lost when the system loses power and then powers back on.

[0067] The processor obtains relevant data of the memory by executing commands to determine whether the memory is proprietary hardware. The relevant data of the memory may include the manufacturer, model, and power-off protection related properties of the memory. In addition to executing commands, the processor can also obtain relevant data of the memory by checking system logs, calling third-party tools, etc. This application does not specifically limit the specific data acquisition method, the amount and content of the acquired data. The methods for determining whether the memory is proprietary hardware include at least the following two:

[0068] In the first method, whether the memory is proprietary hardware is determined by querying the product specification information table. Among them, the product specification information table stores the product specification information of each model of memory produced by each manufacturer. The product specification information includes one or more of the capacity, interface, controller, flash memory type, power loss protection (PLP) parameter, data integrity protection parameter, and capacitor-based power backup parameter. Here, the PLP parameter, data integrity parameter, and capacitor-based power backup parameter can be used to determine whether the memory is proprietary hardware. Specifically, the PLP parameter is used to indicate whether it has a power loss protection function. For example, when the product specification information includes the PLP parameter, it indicates that it has a power loss protection function. Therefore, it can be determined that the memory is proprietary hardware. When the product specification information does not include the PLP parameter, it indicates that it does not have a power loss protection function. Therefore, it can be determined that the memory is not proprietary hardware. The data integrity parameter is used to indicate whether the device has a power-failure protection function. For example, when the product specification information includes the data integrity parameter, it indicates that the device has a power-failure protection function. Therefore, it can be determined that the memory is proprietary hardware. When the product specification information does not include the data integrity parameter, it indicates that the device does not have a power-failure protection function. Therefore, it can be determined that the memory is not proprietary hardware. The capacitor power backup parameter is used to indicate whether the device has a power-failure protection function. For example, when the product specification information includes the capacitor power backup parameter, it indicates that the device has a power-failure protection function. Therefore, it can be determined that the memory is proprietary hardware. When the product specification information does not include the capacitor power backup parameter, it indicates that the device does not have a power-failure protection function. Therefore, it can be determined that the memory is not proprietary hardware. It is understood that when the product specification information includes multiple of the PLP parameter, the data integrity parameter, and the capacitor power backup parameter, it also indicates that the device has a power-failure protection function. Therefore, it can be determined that the memory is proprietary hardware. When none of the PLP parameter, the data integrity parameter, and the capacitor power backup parameter are present in the product specification information, it indicates that the device does not have a power-failure protection function. Therefore, it can be determined that the memory is not proprietary hardware.

[0069] Therefore, after obtaining the manufacturer and model of the memory, it is possible to query whether the memory has a power-off protection function based on a pre-stored product specification information table or a technical document information table including multiple models of memories from multiple manufacturers. If the table query result determines that the memory has a power-off protection function, it is determined that the memory is proprietary hardware; otherwise, it is determined that the memory is not proprietary hardware.

[0070] In a specific embodiment, the product specification information table may be as shown in Table 1.

[0071] Table 1 Product Specifications

[0072]

[0073] The product specification information in Table 1 above only uses the memory capacity, interface, controller, flash memory type and PLP parameters as examples. The product specification information can also include more types and quantities of data, which is not specifically limited in this application.

[0074] When the memory is determined to be model 2 produced by manufacturer A, the product specification information corresponding to the memory, including data such as capacity / interface / controller / flash type / PLP, is determined based on the product specification information table shown in Table 1. The product specification information includes PLP parameters, so it is determined that the memory has a power-off protection function, and further determined that the memory is proprietary hardware. In addition, whether the memory has a power-off protection function can also be judged by whether the product specification information includes parameters for protecting data integrity or whether it includes data such as capacitor-type power supply backup. If these data are present, it is determined that the memory has a power-off protection function and is proprietary hardware. If none of these data are present, it is determined that the memory does not have a power-off protection function and is not proprietary hardware. This application does not specifically limit the types of parameters used for judgment.

[0075] In the second method, the device manager of the storage device to which the memory belongs is run to view the battery backup unit information. If "Microsoft ACPI-Compliant Control Method Battery" or similar information including "Battery" is present, it can be determined that the storage device to which the memory belongs has a battery backup unit with power-failure protection and that the memory is proprietary hardware. Otherwise, it is determined that the memory is not proprietary hardware. "Microsoft ACPI-Compliant Control Method Battery" is only one possible example. Other content in similar information, except "Battery," may vary depending on the storage device model, operating system, and interface, and this application does not specifically limit this.

[0076] The above contents are only two specific processes for determining whether the memory is proprietary hardware based on obtaining different data. This application does not elaborate on other specific processes for obtaining relevant data based on different data acquisition methods to determine whether the memory is proprietary hardware.

[0077] Determining that the memory is proprietary hardware is a prerequisite for executing the write amplification suppression method provided in this application. It can reduce the number of times that data in the memory of the memory is written to the storage medium of the memory, while ensuring that data stored in the memory of the memory that is not written to the storage medium of the memory in time will not be lost in the event of a power outage, thereby achieving data protection.

[0078] Step S420: When the memory is proprietary hardware, obtain operating system parameters corresponding to the memory and perform parameter configuration.

[0079] Operating system parameters include the mount directory and write cache policy. The mount directory provides users with access points to the storage, while the write cache policy manages data write operations. If the storage is proprietary hardware and the mount directory and write cache policy are known, configure the mount directory to be asynchronous and the write cache policy to be write-through. The following describes the configuration of these two different parameters in detail.

[0080] (1) Corresponding to the case where the parameter is a mount directory, the mount directory needs to be configured as asynchronous. In the case where the memory is proprietary hardware, the processor can obtain the mount directory of the file system by executing the df and mount commands. Of course, the mount directory of the memory can also be obtained by running other commands, and this application does not specifically limit this. After obtaining the mount directory of the memory, determine whether the parameters of the mount directory are asynchronous (no barrier). If the mount directory is not asynchronous, execute the mount|grep no barrie command to modify the mount directory to asynchronous. The following will provide a detailed introduction to the cases where the mount directory is synchronous and asynchronous.

[0081] When the mount directory parameter is set to synchronization, the file system will use a synchronization mechanism when writing data. Before writing the data to be written corresponding to the write IO request in the memory to the storage medium of the memory, the file system needs to record the metadata of this write operation in the log. If the metadata is successfully recorded in the log, a confirmation message is sent to enable the memory to write the data in the memory to the storage medium of the memory. At this time, the data written to the storage medium includes not only the data to be written corresponding to the write IO request, but also the data to be written corresponding to the redundant write IO request. This increases the amount of data written by the memory to the flash memory chip of the SSD, resulting in the need for more blocks to store data, which in turn increases the number of block erases and rewrites, thereby exacerbating the write amplification problem of the SSD. In addition, when the file system records the metadata of the redundant write IO request in the log and sends a new confirmation message, the memory will once again write the data to be written corresponding to the redundant write IO request to the storage medium of the memory, resulting in repeated data writing, which increases the number of block erases and rewrites, further exacerbating the write amplification problem of the SSD.

[0082] When the parameters of the mount directory are not synchronized, the file system can be made to not use the synchronization mechanism when writing data, and quickly write the data to the storage medium of the memory without waiting for the metadata of the write operation to be written to the log of the file system. This operation is completed and the data in the memory can be written to the storage medium of the memory. Because the waiting time is not stored, the data to be written corresponding to the redundant write IO requests will not be included, resulting in an increase in the amount of data written by the memory to the flash memory chip of the SSD, resulting in the need for more blocks to store data, which will lead to an increase in the number of block erases and rewrites, thereby exacerbating the write amplification problem of the SSD. Each time data is written, only the data to be written corresponding to the current write IO request is written to the storage medium of the memory, which will not cause repeated writing of data, increase the number of block erases and rewrites, and thus will not aggravate the write amplification problem of the SSD.

[0083] (2) For the case where the parameter is a write cache policy, the write cache policy needs to be configured as a write-through policy. If the memory is proprietary hardware, the processor checks the memory's write cache policy by executing the "cat / sys / block / sda / queue / write_cache" command to determine whether the write cache policy is a write-through policy. If the memory's write cache policy is not a write-through policy, the write cache policy is modified to a write-through policy. The following will describe in detail the cases where the write cache policy is a write-through policy and the case where the write cache policy is not a write-through policy.

[0084] In the case where the write cache policy is a non-write-through policy, the write operation first writes the data to be written into the memory of the memory, and the data to be written in the memory is written into the confirmation information in the log when the memory receives the metadata of the write operation, or is written into the storage medium of the memory when the idle trigger time is reached. Among them, the non-write-through policy includes the write-back policy, etc., which is not specifically limited in this application. The non-write-through policy writes the modified data into the memory of the memory first. At this time, the modified data in the memory is different from the data before the modification stored in the storage medium. The modified data in the memory becomes dirty data. If it is modified again in a short time, the non-write-through policy will also write the modified data into the memory of the memory, and the modified data is also dirty data. When the memory receives the confirmation information in the log of the metadata of the write operation, or when the idle trigger time is reached, the non-write-through policy can merge the write operations corresponding to multiple modifications, and then write the dirty data in the cache into the storage medium of the memory. This process results in multiple writes to the same block, increasing the number of block erases and rewrites, further exacerbating the write amplification problem of the SSD.

[0085] When the write cache policy is a write-through policy, the write operation immediately writes the data to the storage medium of the memory. The data has been written to the storage medium before being cached. There is no data in the memory that has been modified but not written to the storage medium. This reduces the number of times the data in the memory of the memory is written to the storage medium of the memory. There is no need to merge write operations, which reduces the number of writes to the same block and does not increase the number of block erases and rewrites, thereby not aggravating the write amplification problem of the SSD.

[0086] In one possible implementation, since the application's requirements for write latency and data consistency may change, and the requirements for memory write performance may also change, the determination of the mount directory parameters and write cache policy is affected by the application's requirements for write latency, data consistency, and memory write performance. Therefore, the mount directory parameters and write cache policy may change. After the mount directory is configured as asynchronous and the write cache policy is configured as a write-through policy, the mount directory may still change from asynchronous to synchronous, and the write cache policy may change from a write-through policy to a non-write-through policy. Therefore, it is necessary to periodically obtain the mount directory parameters and write cache policy corresponding to the memory. If the mount directory is not configured as asynchronous or the write cache policy is not configured as a write-through policy, reconfigure the parameters to ensure that the mount directory is asynchronous and the write cache policy is a write-through policy.

[0087] In the above process, by configuring the memory mount directory parameters and the write cache policy, the write amplification problem caused by the first method of writing the data in memory 220 to the flash memory chip of the SSD can be solved. By causing the operating system to not first write the metadata stored in memory 220 to the flash memory chip of the SSD when the application sends a write IO request, but instead directly write the data in memory 220 to the flash memory chip of the SSD, the amount of data written to the storage medium of the memory can be reduced, the number of block erases and rewrites can be reduced, and the write amplification effect of the memory can be suppressed. In addition, by immediately writing the data to the storage medium of the memory during each write operation, the number of times the memory data of the memory is eliminated from the storage medium of the memory can be reduced, the number of block erases and rewrites can be reduced, and the write amplification effect of the memory can be suppressed.

[0088] Step S430: Select a target memory from a plurality of memories, where the target memory is a memory that frequently eliminates data from the memory 220 to the flash memory chip 230 of the memory.

[0089] Device information of multiple memories is obtained, and a memory with a short idle trigger time is selected from the memories according to the device information as a target memory.

[0090] The device information includes the memory's manufacturer, model, capacity, and idle trigger time. The idle trigger time is the period of time during which no input / output (IO) requests are received, which triggers the memory to eliminate data from the memory 220 to the flash memory chip 230. The shorter the idle trigger time, the more frequently the memory eliminates data.

[0091] Obtaining the device information of the memory can specifically be: since the device information of the memory is pre-stored in the memory, the processor can obtain the device information of the memory, such as the idle trigger time, by running disk management software or using disk management tools. This application does not specifically limit the type and quantity of the device information obtained. The processor can also obtain the above information by executing other commands or using third-party tools. This application does not specifically limit the specific method of obtaining device information.

[0092] Exemplarily, based on the device information of each memory, a memory having an idle trigger time less than a time threshold is selected from the memory as the target memory. The time threshold can be determined based on a memory whitelist, which includes memories with a long idle trigger time, a low frequency of eliminating data from the memory's internal memory to the memory's flash memory chip, and a less obvious write amplification problem. For example, a memory with an idle trigger time of 2 seconds or 3 seconds, etc. In this case, the determined time threshold can be 1 second, 100 milliseconds, 10 milliseconds, etc. The specific value of the time threshold is not specifically limited in this application. In addition, the time threshold can be set based on empirical data, which is not specifically limited in this application.

[0093] In a specific embodiment, after determining the device information of the memory, a memory not on the memory whitelist is selected from the memory as the target memory in combination with a predetermined memory whitelist, and the idle trigger time of the target memory is less than a time threshold. Based on the device information of the target memory, the idle trigger time of the target memory is determined to be 1 millisecond. In other words, as long as the target memory does not receive an I / O request within 1 millisecond, the main controller of the target memory will consider the target memory to be idle and write the data in the memory to the flash memory chip of the target memory. The target memory frequently performs data elimination operations, and the write amplification problem is serious.

[0094] The above process obtains the device information of the memory and determines the idle trigger time corresponding to each memory. In order to maintain processing performance and make rational use of time, the memory triggers the operation of eliminating data from the memory's internal memory to the memory's flash memory chip when it determines that the time for which the memory has not continuously received input / output IO requests reaches the idle trigger time, and writes the data in the memory's internal memory to the memory's flash memory chip for permanent storage. The target memory determined according to the above method has a shorter idle trigger time and a higher data elimination frequency than other memories in the memory. Therefore, the number of valid data relocations and block erases in the blocks in the target memory is greater, and the write amplification problem is more serious. By screening out the target memory through the method provided in the present application, the write amplification suppression operation provided in the present application can be performed only on the target memory in the subsequent process, thereby improving efficiency and accurately solving the write amplification problem.

[0095] Step S440: Obtain a free area of ​​the target memory.

[0096] The free area includes an area of ​​the target memory that is not allocated and does not store data, or may also include some additional areas provided for maintaining and improving the performance of the target memory, such as blocks that have not been written with valid data, garbage collection buffers, bad block spare blocks that are not allocated to users, and single-level cell cache (SLC), etc. This application does not make specific limitations on this.

[0097] The processor can directly obtain the size of the target memory's free area by running the fsutil command or the df -h command, or obtain the target memory's total capacity and the amount of data space already used for data storage, and then determine the size of the remaining free area for unstored data based on the difference between the target memory's total capacity and the amount of data space already used for data storage. For example, if running either of these commands reveals that the target memory's capacity is 20GB and the amount of data space already used for data storage is 10GB, then the remaining free area is 10GB.

[0098] Step S450: Determine whether the target memory exists.

[0099] During the process of replacing the target memory, the target memory may not exist. Therefore, after reading the free area of ​​the alternative memory, it is necessary to determine whether the target memory exists based on the result of obtaining the free area of ​​the target memory. If the target memory exists, perform subsequent operations.

[0100] In the case that the free area of ​​the target memory cannot be normally obtained through step S440, it is determined that the target memory does not exist. For example, after executing the command, the total capacity of the target memory and the data space that has been used for data storage are not obtained, then it is determined that the target memory does not exist. After determining that the target memory does not exist, step S470 is executed to end all steps.

[0101] If the memory is reconnected, step S430 is re-executed to reselect the target memory. If the target memory is found, the free area of ​​the target memory is read, and the existence of the target memory is determined based on the read result of the free area. Alternatively, if the memory is re-connected, step S410 is re-executed to determine whether the memory is proprietary hardware, which is not specifically limited in this application.

[0102] When the free area of ​​the target memory can be obtained normally, it is determined that the target memory exists. For example, after executing the fsutil command or the df -h command, the size of the free area of ​​the target memory is directly obtained, and it can be determined that the target memory exists, and step S460 is executed.

[0103] Determining whether the target memory exists can ensure that subsequent steps are effectively performed when the target memory exists. If the target memory does not exist, all operations are terminated, thereby reducing invalid operations.

[0104] Step S460: Send a read IO request to the free area of ​​the target memory.

[0105] Exemplarily, a read IO request may be a business pre-read IO request, for example, an IO request for pre-reading data in advance to satisfy a user's future data read request (rather than a current user request) or a non-business IO request; or, a non-business IO request (not a current user needs to read the corresponding data), for example, an invalid IO request generated specifically to suppress data elimination (invalid means that the data generated by this IO request is not used to satisfy the user's data access).

[0106] Exemplarily, a read IO request includes at least a file descriptor, an offset, and a read size, wherein the file descriptor and the offset are used to determine the location from which the data is read in the file, and the read size is the number of bytes read. In an embodiment of the present application, the read size is generally 4K bytes, or 512 bytes. In a possible implementation, the read request may also include more types and quantities of data, such as a buffer address, a read mode, etc., which is not specifically limited in the present application.

[0107] Since the target memory has a read disturb characteristic, when a read IO request is sent to a non-idle area of ​​the target memory to read a storage unit included in a block in the non-idle area, since the storage unit and the adjacent storage units have a certain amount of charge, the charge state of the adjacent storage units is also affected. The change in charge state may cause data loss or damage. Therefore, in order to protect the data, when the target memory determines that the number of reads of a block in the non-idle area reaches a certain threshold, it is necessary to relocate the data in the block, erase the remaining data in the block, and write back the relocated data.

[0108] When a read IO request is sent to a free area of ​​the target memory to read a certain storage unit included in a block in the free area, since the charge in the storage unit is usually close to zero, the charge is less affected by the read operation, and there is no data that needs to be protected. Therefore, if the target memory determines that the number of reads of a block in the free area has reached a certain threshold, there is no need to relocate the data in the block. Since there is no valid data that needs to be relocated, there is no need to write back the relocated data. Therefore, sending a read IO request to a non-free area of ​​the target memory to suppress data eviction is less effective than sending a read IO request to a free area of ​​the target memory to suppress data eviction.

[0109] Through step S440, the processor has determined the size of the free area of ​​the target memory, and then mapped the physical blocks corresponding to the free area of ​​the memory to logical blocks. Since each logical block is assigned a corresponding logical address, the set of logical addresses corresponding to all logical blocks is the logical address corresponding to the free area, and the mapping relationship between the physical blocks corresponding to the free area and the logical blocks is saved in the memory for subsequent search. Through the above method, the processor can determine the logical address of the free area of ​​the target memory. When the logical address of the free area is determined, a read IO request including a file descriptor, an offset and a read size can be sent to the free area of ​​the target memory. The main controller in the target memory determines the corresponding physical address according to the mapping relationship between the storage physical blocks and the logical blocks and the logical address sent by the file system to read the data.

[0110] After the reading operation is completed, the process returns to step S450 .

[0111] The processor determines whether the target memory exists according to whether the read IO request is successful.

[0112] The processor can determine whether the read IO request is successful based on the value indicating the number of bytes read returned by the memory. For example, if the read is successful in a free area of ​​the target memory, the value may be 0, indicating that 0 bytes were successfully read. Alternatively, the processor can determine whether the read is successful by checking whether the read data content is empty. In one possible implementation, there are other ways to determine whether the read IO request is successful, such as checking the system log, using a timeout mechanism, etc., which are not specifically limited in this application.

[0113] When it is determined that the read IO request fails to read through any of the above methods, it is determined that the target memory does not exist. For example, in the case of read timeout or read content error, it is determined that the read IO request fails to read, then it is determined that the target memory does not exist. After determining that the target memory does not exist, step S470 is executed to end all steps.

[0114] If the memory is re-accessed, step S430 is re-executed to reselect the target memory. If the target memory is found, the free area of ​​the target memory is obtained. If the free area of ​​the target memory is obtained and the target memory is determined to exist, step S460 is continued to be executed, and the existence of the target memory is determined based on whether the read IO request is successful. Alternatively, if the memory is re-accessed, step S410 is re-executed to determine whether the memory is proprietary hardware, which is not specifically limited in this application.

[0115] When the read IO request is determined to be successful by any of the above methods, it is determined that the target memory exists. For example, when the value indicating the number of bytes read returned by the target memory is 0, the read is determined to be successful. It can be determined that the target memory exists, and step S460 can be continued.

[0116] While the target memory is always available, read IO requests are continuously sent to the idle area of ​​the target memory. The time interval between each of the multiple read IO requests is determined based on the idle trigger time corresponding to the target memory. To ensure that the target memory is always in a non-idle state and does not write data from the memory to the storage medium of the memory, the time interval between each of the two read IO requests is determined to be less than the idle trigger time. Based on the time interval that meets the requirements, sending read IO requests to the idle area of ​​the target memory includes at least the following two methods:

[0117] The first method: If the target memory is always available, read IO requests can be periodically sent to the idle area of ​​the target memory. In this case, the time interval between each read IO request remains unchanged, and the time interval between sending read IO requests is less than or equal to the idle trigger time. This application does not specifically limit the time interval for sending read IO requests.

[0118] The second method: If the target memory is always available, read IO requests can be sent to the idle area of ​​the target memory non-periodically. In this case, the time interval between each read IO request varies, but always remains less than or equal to the idle trigger time. This application does not specifically limit the length of the variable time interval for sending read IO requests.

[0119] In any of the above processes, the shorter the time interval for sending read IO requests to the free area of ​​the target memory and the more frequently the read IO requests are sent, the better the effect of suppressing the number of times the target memory writes data in the internal memory to the storage medium of the target memory. However, frequently sending read IO requests will also affect the normal processing of the target memory's business IO and increase the latency of the business IO. Therefore, the determination of the time interval for sending read IO requests to the free area of ​​the target memory also needs to consider the impact on the normal business IO of the target memory.

[0120] Since the target memory may have high-frequency service IO and low-frequency service IO, the following describes the operation of sending a read IO request to the idle area of ​​the target memory in service IO scenarios with different frequencies.

[0121] In the first case, when the target memory receives high-frequency business IO, the IO scheduling algorithm of the target memory is configured so that the target memory prioritizes business IO. After processing the business IO, the read IO request is sent to the idle area. In this case, the time interval between read IO requests sent to the idle area of ​​the target memory is determined to be longer. The time interval can be determined by the idle trigger time of the target memory and the frequency corresponding to the business IO. This application does not specifically limit this. In the above case, due to the high business IO frequency, the controller of the target memory can determine that the probability of the target memory being idle is low. In this case, sending read IO requests at a longer time interval can effectively suppress the number of times the target memory writes data from the memory to the storage medium of the target memory and reduce the impact on high-frequency business IO. In the second case, when the target memory receives low-frequency business IO, the target memory triggers the idle trigger time, and the probability of writing data from the memory to the storage medium of the target memory is high. In this case, the time interval between read IO requests sent to the idle area of ​​the target memory is determined to be shorter. The time interval can be determined by the idle trigger time of the target memory and the frequency corresponding to the business IO. This application does not specifically limit this. In the above case, since the business IO frequency is low, the controller of the target memory is more likely to determine that the target memory is in an idle state. At this time, sending read IO requests according to shorter time intervals can achieve a better suppression effect on the number of times the target memory writes data in the memory to the storage medium of the target memory, and has less impact on non-high-frequency business IO.

[0122] In a specific embodiment, when the target storage device has an idle trigger time of 1 millisecond and receives non-high-frequency business IO, the interval for sending read IO requests, determined based on the idle trigger time, can be 1 millisecond. In this case, the target storage device can achieve a disk read / write rate of up to 1000 IOPS (input / output per second). However, in this case, the excessive frequency of read IO requests can affect the processing of business IO of the target storage device. After multiple tests, the interval for periodically sending read IO requests to the idle areas of the target storage device can be set to 1.05 milliseconds. In this case, the read IO requests sent can effectively suppress the number of times the target storage device writes data from the memory to the storage medium of the target storage device while reducing the impact on business IO.

[0123] It can be understood that as the service IO frequency increases, the time interval for sending read IO requests can be set to a larger reasonable value, such as 1.1 milliseconds, 1.2 milliseconds, etc., and according to the determined reasonable time interval, the read IO request is sent periodically or non-periodically, and this application does not make specific restrictions on this. At this time, the corresponding IOPS can reach more than 800r / s. In the case where the service IO received by the target memory changes to a high frequency, the time interval for sending read IO requests can be further set to a larger reasonable value, such as 2 milliseconds, 2.1 milliseconds, etc. Similarly, according to the determined reasonable time interval, the read IO request is sent periodically or non-periodically, and this application does not make specific restrictions on this. At this time, the corresponding IOP can be lower than 500r / s.

[0124] The above process sends read IO requests to the idle area of ​​the target memory at a higher frequency, so that the target memory still receives read IO requests even if it does not receive any business IO, and the duration for which the target memory does not receive any IO request cannot reach the idle trigger time, so that the main controller of the target memory determines that the target memory is not in an idle state, which can reduce the number of times the data in the memory is written to the storage medium of the target memory, reduce the number of data relocations, and suppress the write amplification problem of the target memory.

[0125] Step S470: End.

[0126] In summary, the present application provides a write amplification suppression method. On the one hand, by configuring the mount directory as an asynchronous parameter and configuring the write cache policy as a write-through policy, the amount of data written to the storage medium of the storage device can be reduced, and the number of times the data in the memory of the storage device is written to the storage medium of the storage device can be reduced, thereby suppressing the write amplification problem of the storage device. On the other hand, by sending a read IO to the idle area of ​​the target storage device, the target storage device can be kept in a non-idle state, reducing the number of times the target storage device writes the data in the memory to the storage medium of the target storage device, reducing the number of times the data in the target storage device is relocated, and achieving the write amplification suppression effect. Since the number of times the target storage device writes the data in the memory to the storage medium of the target storage device is reduced, the data in the memory cannot be written to the storage medium of the target storage device in a timely manner. Therefore, it is necessary to ensure that the target storage device to which the write amplification suppression method provided by the present application is applied, or the storage device to which the target storage device belongs, has a power-off protection function, so that the data can be protected even when it cannot be written to the storage medium in a timely manner. In addition, the write amplification suppression method provided by this application can be executed by storage application manufacturers. Compared with the current write amplification suppression methods that can only be implemented in disk firmware by most storage manufacturers, the write amplification suppression method provided by this application is more flexible and has better write amplification suppression effect, which can reduce the number of disk replacements and reduce costs.

[0127] like Figure 5 As shown, Figure 5 This is a schematic diagram of a write amplification suppression device provided by an embodiment of the present application. The device is applied to Figure 1 In the storage device shown, the write amplification suppression device 500 includes an acquisition unit 510 and a processing unit 520. The acquisition unit 510 is used to select a target memory from a plurality of memories, wherein the target memory is a memory that frequently eliminates data from the memory 220 to the flash memory chip 230 of the memory; the processing unit 520 is used to suppress the target memory from performing data elimination by sending a read IO request to the target memory. Specifically, the acquisition unit 510 can be used to perform Figure 4 The processing unit can be used to perform the data acquisition part of steps S410 to S430 and step S440 shown in FIG. Figure 4 In the steps S410 to S430 shown, regarding the judgment and parameter configuration, and steps S450 to S470, in a possible implementation, the acquisition unit and the processing unit may also perform more steps in addition to the above-mentioned contents, which is not specifically limited in this application.

[0128] In one possible implementation, Figure 5 This is only a possible example provided in the embodiment of the present application. The device may also include more types and quantities of units, which is not specifically limited in the present application.

[0129] The present application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions that can be run on a storage device or stored in any available medium. When the computer program product is run on at least one storage device, the at least one storage device executes Figure 4 The write amplification suppression method shown.

[0130] The present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a storage device or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that instruct the storage device to execute Figure 4 A write amplification suppression method is shown.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A write amplification suppression method, characterized in that: The method comprises: Selecting a target memory from a plurality of memories, wherein the target memory is a memory that frequently eliminates data from a memory 220 of the memory to a flash memory chip 230 of the memory; The target memory is inhibited from performing data elimination by sending a read IO request to the target memory.

2. The method according to claim 1, wherein: The memory is a solid state drive SSD.

3. The method according to claim 1, wherein: The read IO request is a business pre-read IO request or a non-business IO request.

4. The method according to claim 1, wherein The method further comprises: The target memory is a memory with a short idle trigger time among the multiple memories, wherein the idle trigger time is: the time period during which the memory triggers the operation of eliminating data from the memory 220 to the flash memory chip 230 and does not continuously receive an input / output IO request.

5. The method according to any one of claims 1 to 4, characterized in that The sending of a read IO request to the target memory specifically includes: A read IO request is sent to a free area of ​​the target memory.

6. The method according to claim 1, wherein Sending a read IO request to the target memory specifically includes: Sending a read IO request to the target memory at a first time interval, wherein the first time interval is fixed and is less than an idle trigger time corresponding to the target memory; or A read IO request is sent to the target memory at a second time interval, wherein the second time interval varies and is less than an idle trigger time corresponding to the target memory.

7. The method according to any one of claims 1 to 3, characterized in that Before selecting the target memory from the plurality of memories, the method further includes: It is determined that the memory is proprietary hardware, where the proprietary hardware includes a memory having a capacitor, or a memory of which the device has a battery backup unit.

8. A write amplification suppression device, characterized in that: Applied to a storage device including a memory to be selected, the apparatus comprises: An acquiring unit selects a target memory from a plurality of memories, wherein the target memory is a memory that frequently eliminates data from a memory 220 of the memory to a flash memory chip 230 of the memory; The processing unit suppresses the target memory from performing data elimination by sending a read IO request to the target memory.

9. A storage device, characterized in that: The storage device includes: Multiple memories for persistent storage of data; A processor, configured to execute the method according to any one of claims 1 to 7.

10. A computer program product comprising instructions, characterized in that When the instructions are executed by the storage device, the storage device is caused to perform the method according to claims 1 to 7.

11. A computer-readable storage medium, characterized in that The device comprises computer program instructions which, when executed by a storage device, cause the storage device to perform the method according to claims 1 to 7.

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