Storage system, processor system, access method and chip system
By marking the quality of service (QoS) priority for the processor cores and scheduling access requests, the bandwidth bottleneck problem in the symmetric multi-processor system is solved and the system performance is improved.
Patent Information
- Application Number
- CN202410295457.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-14
- Publication Date
- 2025-09-16
AI Technical Summary
In a symmetric multi-processor system, when low-traffic memory access flows and high-traffic memory access flows run simultaneously, it may cause a bandwidth bottleneck in the critical path, resulting in a decrease in program performance.
The memory controller marks the quality of service (QoS) priority for each processor core, schedules access requests, and prioritizes access requests with high QoS priority, reducing latency and improving chip system performance.
It effectively reduces the latency of the chip system in processing multiple access requests and improves system performance.
Smart Images
Figure CN120653182A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a storage system, a processor system, an access method, and a chip system. Background Art
[0002] In a symmetrical multi-processing (SMP) system, more processor cores can be provided for parallel program processing. Specifically, different services can be deployed on different processor cores. Because different services have different memory access patterns, such as data dependencies and reuse, the amount of traffic sent to the system on chip (SoC) by each service varies.
[0003] In some scenarios, such as those with severe data dependencies, out-of-order instructions, and inability to parallelize memory access instructions, low-volume memory access flows may be the critical path for program performance. In these cases, if both low-volume and high-volume memory access flows run simultaneously on an SMP system, they may both need to queue at bandwidth bottlenecks, causing service delays and, in turn, degrading the program's instruction per clock (IPC) performance. Summary of the Invention
[0004] The embodiments of the present application provide a storage system, a processor system, an access method, and a chip system, which reduce the latency of the chip system in processing multiple access requests and improve the performance of the chip system.
[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.
[0006] In a first aspect, an embodiment of the present application provides a storage system comprising a memory controller and at least one memory. The memory controller is configured to receive multiple first access requests from multiple processor cores, and to mark the first access requests sent by each processor core with a quality of service (QoS) priority based on the number of first access requests sent by each processor core, thereby obtaining multiple second access requests, each of which carries a QoS priority. The memory controller is further configured to schedule the multiple second access requests to access the at least one memory based on the QoS priority.
[0007] Therefore, the storage system provided by the embodiment of the present application can be applied to a chip system, and the chip system can also include multiple processor cores. The memory controller can mark the QoS priority of the first access request sent by each processor core respectively, and obtain multiple second access requests, that is, each second access request carries a corresponding QoS priority. Among them, the number of first access requests sent by each processor core can be understood as the required bandwidth of the processor core. The required bandwidth of each processor core is related to the QoS priority. For example, a high QoS priority corresponds to a small required bandwidth, and a low QoS priority corresponds to a large required bandwidth. Therefore, the memory controller can schedule multiple second access requests based on the required bandwidth of each processor core, which can improve the scheduling efficiency of the chip system, reduce the delay of the chip system in processing multiple access requests, and improve the performance of the chip system.
[0008] In one possible design, the memory controller includes a counter and at least one set of comparators. The counter is configured to receive multiple third access requests within a first time period and count the number of at least one third access request from the same processor core, thereby obtaining multiple first count results. The at least one set of comparators is configured to determine whether the multiple first count results are greater than a first threshold in each of the at least one set of comparators, thereby obtaining multiple first comparison results, each of which corresponds to the identifiers of the multiple processor cores. The at least one set of comparators is further configured to, within a second time period following the first time period, tag a first access request sent by each processor core with a QoS priority based on the multiple first comparison results, thereby obtaining multiple second access requests, each of which carries the identifier of the corresponding processor core. Thus, the QoS priority of the third access request from a processor core determined in the first time period can be used to tag the QoS priority of the first access request sent by each processor core in the second time period. This improves the scheduling efficiency of the chip system, reduces the latency of the chip system in processing multiple access requests, and improves the performance of the entire chip system.
[0009] In one possible design, at least two second access requests among the multiple second access requests have different QoS priorities, and the multiple QoS priorities correspond one-to-one to the multiple queues. The memory controller is specifically used to: schedule the second access requests stored in the first queue among the multiple queues to access at least one memory, and the first queue corresponds to the first QoS priority among the multiple QoS priorities. When the first queue is empty, schedule the second access requests stored in the second queue among the multiple queues to access at least one memory, and the second queue corresponds to the second QoS priority among the multiple QoS priorities, and the first QoS priority is higher than the second QoS priority. Thus, the storage system can schedule the second access requests with high QoS priority first, and then schedule the second access requests with low QoS priority. Since the QoS priority is related to the number of access requests, that is, multiple access requests with a smaller number of access requests from the same processor core can be scheduled first, reducing the latency of this part of the access requests. In addition, the impact on multiple access requests with a larger number of access requests from the same processor core is smaller.
[0010] In one possible design, the memory controller includes a counter, at least one group of comparators, and multiple queues. The counter is used to receive multiple first access requests and count the number of first access requests sent by each processor core in the multiple queues to obtain multiple second counting results. The at least one group of comparators is used to respectively determine whether the multiple second counting results are greater than the second threshold value in each group of comparators in the at least one group of comparators to obtain multiple second comparison results, and mark the QoS priority of the first access request sent by each processor core based on the multiple second comparison results to obtain multiple second access requests. Therefore, by counting the number of requests in all queues and marking the QoS priority, the latency of the storage system in scheduling a small number of access requests from the same processor core can be reduced, thereby improving the performance of the chip system.
[0011] In one possible design, at least two second access requests among the multiple second access requests have different QoS priorities, and the multiple QoS priorities correspond one-to-one to the multiple queues. The memory controller is specifically used to: schedule a first preset number of second access requests stored in a third queue among the multiple queues to access at least one memory, and the third queue corresponds to a third QoS priority among the multiple QoS priorities. Schedule a second preset number of second access requests stored in a fourth queue among the multiple queues to access at least one memory, and the fourth queue corresponds to a fourth QoS priority among the multiple QoS priorities, and the third QoS priority is higher than the fourth QoS priority. Among them, the first preset number and the second preset number can be understood as scheduling weights, and the scheduling weights can be considered to avoid the situation where access requests with low QoS priorities are never scheduled, thereby improving the performance of the chip system.
[0012] In one possible design, the QoS priority level is negatively correlated with the number of first access requests from each processor core. That is, the more first access requests from the same processor core, the lower the QoS priority; and the fewer first access requests from the same processor core, the higher the QoS priority.
[0013] In a second aspect, an embodiment of the present application provides a processor system comprising multiple processor cores and multiple counters, wherein the multiple processor cores correspond to the multiple counters in a one-to-one manner. Each processor core is configured to output at least one first access request to the corresponding counter. Each counter is configured to count the number of the at least one first access request, obtain a count result, and mark a quality of service (QoS) priority for the at least one first access request based on the count result, thereby obtaining at least one second access request, wherein the at least one second access request carries a QoS priority.
[0014] Therefore, the processor system provided in the embodiment of the present application can complete QoS priority marking on the processor side, and the QoS priority carried by the second access request can be applied to the subsequent scheduling of access requests by the storage system, thereby reducing the latency of the processor system and the storage system as a whole in processing multiple access requests, and improving the overall performance of the processor system and the storage system.
[0015] In one possible design, the number of at least one first access request and the QoS priority are negatively correlated, that is, the fewer the number of first access requests, the higher the QoS priority, and the more the number of first access requests, the lower the QoS priority.
[0016] In a third aspect, an embodiment of the present application provides an access method, which is applied to a storage system, the storage system including a memory controller and at least one memory, the method comprising: controlling the memory controller to receive multiple first access requests from multiple processor cores, marking the first access request sent by each processor core with a quality of service (QoS) priority based on the number of first access requests sent by each processor core, and obtaining multiple second access requests, the multiple second access requests carrying QoS priorities. Controlling the memory controller to schedule the multiple second access requests to access the at least one memory based on the QoS priority.
[0017] In one possible design, a memory controller includes a counter and at least one set of comparators, and controls the memory controller to receive multiple first access requests from multiple processor cores, and to mark the first access requests sent by each processor core with a QoS priority based on the number of first access requests sent by each processor core, thereby obtaining multiple second access requests. The design includes: controlling the counter to receive multiple third access requests from the multiple processor cores within a first time period, and to count the number of third access requests sent by each processor core, thereby obtaining multiple first counting results; controlling the at least one set of comparators to determine whether the multiple first counting results are greater than a first threshold in each of the at least one set of comparators, thereby obtaining multiple first comparison results, wherein the multiple first comparison results correspond to identifiers of the multiple processor cores; and controlling the at least one set of comparators to mark the first access requests sent by each processor core with a QoS priority based on the multiple first comparison results within a second time period following the first time period, thereby obtaining multiple second access requests, wherein the first access requests carry the identifiers of the corresponding processor cores.
[0018] In one possible design, at least two of the multiple second access requests have different QoS priorities, the multiple QoS priorities correspond to the multiple queues one-to-one, and the memory controller is controlled to schedule the multiple second access requests to access at least one memory based on the QoS priorities, including: controlling the memory controller to schedule second access requests stored in a first queue among the multiple queues to access the at least one memory, the first queue corresponding to a first QoS priority among the multiple QoS priorities. When the first queue is empty, controlling the memory controller to schedule second access requests stored in a second queue among the multiple queues to access the at least one memory, the second queue corresponding to a second QoS priority among the multiple QoS priorities, the first QoS priority being higher than the second QoS priority.
[0019] In one possible design, a memory controller includes a counter, at least one set of comparators, and multiple queues. The memory controller is controlled to receive multiple first access requests from multiple processor cores, and based on the number of first access requests sent by each processor core, the memory controller is marked with a QoS priority for the first access request sent by each processor core to obtain multiple second access requests. The design includes: controlling the counter to receive the multiple first access requests and counting the number of first access requests sent by each processor core in the multiple queues to obtain multiple second counting results; controlling the at least one set of comparators to determine whether the multiple second counting results are greater than a second threshold in each set of comparators in the at least one set of comparators to obtain multiple second comparison results; and marking the first access request sent by each processor core with a QoS priority based on the multiple second comparison results to obtain multiple second access requests.
[0020] In one possible design, at least two of the multiple second access requests have different QoS priorities, the multiple QoS priorities correspond to the multiple queues one-to-one, and controlling the memory controller to schedule the multiple second access requests to access at least one memory based on the QoS priorities includes: controlling the memory controller to schedule a first preset number of second access requests stored in a third queue among the multiple queues to access the at least one memory, the third queue corresponding to a third QoS priority among the multiple QoS priorities. Controlling the memory controller to schedule a second preset number of second access requests stored in a fourth queue among the multiple queues to access the at least one memory, the fourth queue corresponding to a fourth QoS priority among the multiple QoS priorities, the third QoS priority being higher than the fourth QoS priority.
[0021] In a possible design, the QoS priority level is negatively correlated with the number of first access requests of each processor core.
[0022] The beneficial effects of the third aspect can be found in the description of the first aspect.
[0023] In a fourth aspect, embodiments of the present application provide an access method, which is applied to a processor system, the processor system including multiple processor cores and multiple counters, wherein the multiple processor cores and the multiple counters have a one-to-one correspondence. The method includes: controlling each processor core to output at least one first access request to the corresponding counter. Controlling each counter to count the number of the at least one first access request to obtain a count result, and marking the at least one first access request with a quality of service (QoS) priority based on the count result to obtain at least one second access request, wherein the at least one second access request carries a QoS priority.
[0024] In one possible design, the number of at least one first access request and the QoS priority are negatively correlated.
[0025] The beneficial effects of the fourth aspect can be found in the description of the second aspect.
[0026] In a fifth aspect, an embodiment of the present application provides a chip system, which includes multiple processor cores and the storage system of the first aspect, and the multiple processor cores and the storage system are coupled via a bus.
[0027] In a sixth aspect, an embodiment of the present application provides a chip system, which includes a memory and the processor system of the second aspect, and the processor system and the memory are coupled via a bus.
[0028] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the access method in the possible implementation of the third aspect or the fourth aspect mentioned above.
[0029] In an eighth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer or a processor, enables the computer or the processor to execute the access method in a possible implementation of the third aspect or the fourth aspect.
[0030] It can be understood that any of the storage systems, processor systems, chip systems, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.
[0031] These and other aspects of the present application will become more readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A schematic diagram of the structure of a chip system provided in an embodiment of the present application;
[0033] Figure 2 A schematic diagram of the structure of a storage system provided in an embodiment of the present application;
[0034] Figure 3 A schematic diagram of the structure of another storage system provided in an embodiment of the present application;
[0035] Figure 4 A schematic diagram of the structure of another storage system provided in an embodiment of the present application;
[0036] Figure 5 A schematic diagram of the structure of a processor system provided in an embodiment of the present application;
[0037] Figure 6 A flowchart of an access method provided in an embodiment of the present application;
[0038] Figure 7 A flowchart of another access method provided in an embodiment of the present application. DETAILED DESCRIPTION
[0039] For ease of understanding, some examples of concepts related to the embodiments of this application are provided for reference as follows:
[0040] 1. First-in-first-out (FIFO): the first incoming message is scheduled first, and the later incoming message is scheduled later.
[0041] 2. Round robin (RR) scheduling: fair scheduling based on packets. After each queue dispatches a packet, it is transferred to the next queue.
[0042] 3. Weighted round robin (WRR): After each queue has dispatched a certain number of packets, it is transferred to the next queue. The number is the scheduling weight. For example, if queue 0 has a scheduling weight of 2 and queue 1 has a scheduling weight of 3, then after 2 packets are dispatched from queue 0, they are transferred to queue 1. After 3 packets are dispatched from queue 1, they are transferred to the next queue.
[0043] 4. Weighted Deficit Round Robin (WDRR) is a weighted scheduling algorithm based on message bytes. This scheduling algorithm is based on two variables: quota (quantum) and credit counter. The quota represents the weight, measured in bytes, and is a configurable parameter. The credit counter is used to indicate the accumulation and consumption of the quota and is a state parameter that is not configurable. Initially, each queue's credit counter equals its quota. Each time a queue sends a message, the credit counter's credit counter is reduced by the number of bytes in the message. When the credit counter falls below 0, scheduling for that queue is stopped. When scheduling stops for all queues, the credit counters are replenished for all queues.
[0044] It can be understood that the above scheduling method is exemplified by messages. In the embodiment of the present application, access requests may be stored in the queue.
[0045] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.
[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.
[0047] Currently, in an SMP system, each processor core can issue multiple access requests, i.e., multiple memory access flows. Multiple memory access flows may include high-traffic access flows and low-traffic memory access flows. High-traffic access flows refer to flows with a larger number of access requests from the processor core, while low-traffic memory access flows refer to flows with a smaller number of access requests from the processor core. High-traffic memory access flows may affect the access of low-traffic memory access flows to the memory. For example, if the SMP system uses a first-in, first-out method to schedule access requests, low-traffic memory access flows will have to queue. After the high-traffic memory access flows are scheduled, the low-traffic memory access flows will be scheduled, causing delays in the services corresponding to the low-traffic memory access flows and creating a bandwidth bottleneck.
[0048] To reduce bandwidth bottlenecks, low-volume memory access flows can be marked with a higher Quality of Service (QoS) priority. This allows for higher-QoS priority memory access flows to be prioritized during queue scheduling, thus ensuring lower latency in the SMP system. Furthermore, since high-volume memory access flows, which already have to queue up in long queues, present bandwidth bottlenecks, high-volume memory access flows are less sensitive to latency. Therefore, prioritizing higher-QoS priority memory access flows has less impact on high-volume memory access flows.
[0049] In one possible implementation, a technique for implementing queue scheduling is proposed. This technique provides an SMP system with a hardware control interface and software that implements the query, calculation, and configuration process to ensure the priority of different programs. However, this technique places high demands on the software, requiring specialized development and deployment. Furthermore, the software's use of the query interface incurs significant latency, such as the time overhead of switching between user mode and kernel mode. This can cause hardware traffic to change by the time the software obtains data, significantly delaying subsequent calculations and configurations for the hardware. Consequently, software control can potentially disrupt the SMP system. In one possible example, assume that program A has low traffic at time t0, while program B has high traffic at time t0. The software detects that program A is significantly impacted by program B and therefore increases the priority of program A. At time t1, the software completes the query, calculation, and configuration process. By this time, tens or even hundreds of milliseconds have passed since time t0. At this time, program A may already be requiring a large amount of traffic, and this high-priority, high-traffic traffic could severely impact other programs. In addition, the dedicated interface instruction stream is also a considerable overhead for the central processing unit (CPU), so this technology cannot be applied to large-scale business systems with complex behaviors.
[0050] Therefore, an embodiment of the present application provides a storage system, which is applied to a chip system. The chip system may further include multiple processor cores. The memory controller may respectively mark the QoS priority of the first access request sent by each processor core to obtain multiple second access requests, that is, each second access request carries a corresponding QoS priority. Among them, the number of first access requests sent by each processor core can be understood as the required bandwidth of the processor core. The required bandwidth of each processor core is related to the QoS priority. For example, a high QoS priority corresponds to a small required bandwidth, and a low QoS priority corresponds to a large required bandwidth. Therefore, the memory controller can schedule multiple second access requests based on the required bandwidth of each processor core, which can improve the scheduling efficiency of the chip system, reduce the delay of the chip system in processing multiple access requests, and improve the performance of the chip system.
[0051] In some scenarios, the device to which the storage system or processor system provided in the embodiments of the present application is applied may be an execution device, which may be a terminal such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle terminal, etc., or a server cluster, etc. The storage system or processor system provided in the embodiments of the present application may be applied in fields involving memory-based data communication in execution devices.
[0052] In some embodiments, the chip system provided in the embodiments of the present application may be a system on chip (SoC), a terminal chip or a server chip. Figure 1 As shown, Figure 1 A schematic structural diagram of a chip system provided in an embodiment of the present application. Figure 1 , multiple processor cores are shown, namely processor core_0, processor core_1, processor core_2 and processor core_3, and the multiple processor cores are equivalent to a master disk. Figure 1 The figure also shows a memory controller and a memory, where the memory is equivalent to a slave disk and the memory controller is equivalent to a slave controller. Specifically, the memory controller may have a queue, which can be used to store multiple requests from the processor cores. For example, the request from processor core_0 is recorded as "m0", the request from processor core_1 is recorded as "m1", the request from processor core_2 is recorded as "m2", and the request from processor core_3 is recorded as "m3".
[0053] Among them, the internal behaviors of multiple processor cores vary greatly, and the access patterns to the memory are also different. Specifically, the number of access requests from multiple processor cores entering the queue of the memory controller at the same time varies greatly. Without adding additional scheduling methods, the queue can schedule the access requests according to the first-in-first-out mode or the round-robin scheduling mode. In a possible example, continue to refer to Figure 1 Processor core 1 has the highest traffic volume and the largest number of access requests in the queue. Its access requests introduce significant queuing delays for all other access requests in the queue. Processor core 1 is more bandwidth-constrained than latency-constrained, while processor cores 0, 2, and 3 are more latency-constrained, with the delays being more severe for these cores.
[0054] Applied to the above scenario, a storage system provided in an embodiment of the present application is further introduced below.
[0055] like Figure 2 As shown, Figure 2 The present invention provides a schematic diagram of a storage system structure, wherein the storage system 20 may include a memory controller 21 and at least one memory 22. Figure 2 , m memories are shown, namely memory 22_1, memory 22_2, ..., memory 22_m, where m is an integer greater than or equal to 1.
[0056] Among them, the memory controller 21 is used to receive multiple first access requests from multiple processor cores, and mark the service quality QoS priority of the first access request sent by each processor core according to the number of first access requests sent by each processor core, to obtain multiple second access requests, and the multiple second access requests carry QoS priorities.
[0057] For example, the multiple processor cores and the memory controller 21 may be coupled via a bus, and the memory controller 21 may obtain multiple first access requests via the bus. The first access requests may include reading data from the memory 22 and writing data to the memory 22.
[0058] Exemplarily, each processor core can issue at least one first access request, and the memory controller 21 can obtain the number of first access requests from each processor core, and mark the QoS priority based on the number of first access requests from each processor core, to obtain multiple second access requests. Specifically, when marking the QoS priority, the memory controller 21 can mark the delay-sensitive access requests of small traffic with a high QoS priority, and can mark the non-delay-sensitive access requests of large traffic with a low QoS priority. Among them, the delay-sensitive access requests of small traffic can be understood as the number of access requests from the same processor core is small, and the non-delay-sensitive access requests of large traffic can be understood as the number of access requests from the same processor core is large. When scheduling, the storage system 20 can first schedule the delay-sensitive access requests of small traffic with a high QoS priority, and then schedule the non-delay-sensitive access requests of large traffic with a low QoS priority. As a result, the queuing delay of the delay-sensitive access requests of small traffic is reduced, and the throughput rate of the storage system in processing the delay-sensitive access requests of small traffic is improved.
[0059] In a specific example, assuming that the number of first access requests from processor core_1 is higher than that from processor core_2, if the first access requests from processor core_1 are scheduled first, a longer delay will be caused for the first access requests from processor core_2. Therefore, the memory controller 21 can mark the first access requests from processor core_2 with a higher QoS priority and mark the first access requests from processor core_1 with a lower QoS priority. This ensures that the first access requests from processor core_2 are scheduled before the first access requests from processor core_1, thereby reducing the delay of the first access requests from processor core_2.
[0060] The memory controller 21 is further configured to schedule multiple second access requests to access the at least one memory 22 based on QoS priorities.
[0061] Exemplarily, the memory 22 may be a synchronous dynamic random access memory (DRAM) or a double data rate synchronous dynamic random access memory (DDR SDRAM), which may be referred to as DDR. The embodiments of the present application do not specifically limit this. The memory 22 may be used to store data and instructions.
[0062] Exemplarily, the memory controller 21 may schedule multiple second access requests by first scheduling second access requests with a high QoS priority and then scheduling second access requests with a low QoS priority. Specifically, when scheduling second access requests with a high QoS priority or scheduling second access requests with a low QoS priority, a first-in-first-out method, a round-robin method, a weighted round-robin method, or a weighted difference round-robin method may be used.
[0063] Therefore, the memory controller 21 can schedule the second access request based on the QoS priority, which can reduce the latency of the chip system in processing multiple first access requests and improve the performance of the chip system.
[0064] Optional, such as Figure 3 As shown, Figure 3 A schematic diagram of another storage system provided in an embodiment of the present application. The memory controller 21 may include a counter 211 and at least one group of comparators 212, and the output of the counter 211 is coupled to the input of the comparator 212. It is understandable that Figure 3 Only one set of comparators 212 is shown in FIG. Figure 3 2 also shows multiple processor cores, namely processor core_0, processor core_1, processor core_2 and processor core_3. The multiple processor cores can be coupled to the counter 211 via a bus.
[0065] The counter 211 is configured to receive a plurality of third access requests within a first time period, and to count the number of third access requests sent by each processor core to obtain a plurality of first counting results.
[0066] Exemplarily, the first time period can also be understood as a time window. In a possible example, the first time period can be a 16-bit time window, that is, 2 16 It is understandable that the first time period can be configured according to the application scenario, process and frequency, etc., and the second time period described below is also the same. The embodiment of the present application does not limit the length of the first time period and the second time period.
[0067] Exemplarily, counter 211 can count the number of third access requests issued by multiple processor cores, wherein the third access request can carry the identifier of the corresponding processor core. Specifically, assume that the counters represent the number of third access requests from processor core_0, processor core_1, processor core_2, and processor core_3 with A, B, C, and D, respectively. The initial values of A, B, C, and D can be 0. For example, within a first time period, if counter 211 receives a third access request from processor core_0, the value of A is incremented by 1. If counter 211 receives a third access request from processor core_2, the value of C is incremented by 1. Thus, counter 211 can obtain multiple first counting results, and the first counting results can correspond to the identifier of each processor core.
[0068] Among them, at least one group of comparators 212 is used to respectively determine whether multiple first counting results are greater than the first threshold in each group of comparators 212 in at least one group of comparators 212, and obtain multiple first comparison results, and the multiple first comparison results correspond to the identifiers of multiple processor cores one by one.
[0069] Exemplarily, the number of comparators 212 may be related to the number of QoS priorities. In one possible example, assume that there are 8 QoS priorities (e.g., QoS0 to QoS7), and these 8 QoS priorities are represented by 3-bit data, for example, "000" corresponds to QoS0, "001" corresponds to QoS1, "010" corresponds to QoS2, "011" corresponds to QoS3, "100" corresponds to QoS4, "101" corresponds to QoS5, "110" corresponds to QoS6, and "111" corresponds to QoS7. It can be understood that the number of QoS priorities can be configured according to the application scenario, process, frequency, etc., and the embodiment of the present application does not limit the number of QoS priorities. At this time, there are 8 groups of comparators 212, and the 8 groups of comparators 212 can save 8 groups of first thresholds, each of which can include multiple bits.
[0070] For example, Table 1 is a schematic diagram of the first threshold value of 8 groups of comparators. The first threshold value stored by each group of comparators in the eight groups of comparators shown in Table 1 can include 16 bits. It will be understood that Table 1 is only intended to help those skilled in the art better understand the technical solutions of the embodiments of the present application, rather than limiting the technical solutions provided by the embodiments of the present application. In practical applications, the number of bits of the first threshold value may also be less than or greater than 16 bits, and the embodiments of the present application do not limit the number of bits of the first threshold value. Similarly, the number of comparators 212 may also be less than or greater than 8, and the embodiments of the present application do not limit the number of comparators 212.
[0071] Table 1
[0072] Comparator First threshold QoS priority The first set of comparators 0000 0000 0000 0000 QoS7 The second set of comparators 0000 0000 0000 0100 QoS6 The third comparator 0000 0000 0001 0000 QoS5 The fourth comparator 0000 0000 0100 0000 QoS4 The fifth comparator 0000 0001 0000 0000 QoS3 The sixth comparator 0000 0100 0000 0000 QoS2 The seventh group of comparators 0001 0000 0000 0000 QoS1 The eighth comparator 0100 0000 0000 0000 QoS0
[0073] It will be appreciated that the first counting result can be compared with the first thresholds of the plurality of comparators 212 respectively. If the first counting result is less than the first threshold of a particular comparator 212, a first comparison result can be obtained, and the QoS priority corresponding to the comparator is the priority of the first comparison result. Specifically, if the first counting result of the third access request from processor core_1 is greater than "0000 0000 0000 0100" and less than "0000 00000001 0000", the QoS priority corresponding to processor core_1 is QoS 6.
[0074] Among them, at least one group of comparators is also used to: mark the QoS priority of the first access request sent to each processor core based on multiple first comparison results in a second time period after the first time period, and obtain multiple second access requests, and the first access request carries the identification of the corresponding processor core.
[0075] Exemplarily, the second time period may be the next time window, and the length of the second time period may be the same as the length of the first time period. When the lengths of the first time period and the second time period are sufficiently short, the storage system 20 may schedule the first access request from each processor core in real time based on the QoS priority.
[0076] Continuing with the example of the QoS priority of QoS 6 assigned to processor core_1 during the first time period, the first access request from processor core_1 during the second time period can be marked with a QoS priority of QoS 6. That is, the QoS priority determined during the first time period applies to access requests during the second time period, and the QoS priority determined during the second time period applies to access requests during the third time period, which is the time period after the second time period.
[0077] It will be appreciated that, during the second time period, the counter 211 is further configured to receive multiple first access requests and count the number of first access requests sent by each processor core, respectively, to obtain multiple third counting results. During the third time period, the at least one set of comparators 212 is further configured to tag the first access requests sent by each processor core with a QoS priority based on the multiple third comparison results, thereby obtaining new access requests.
[0078] The QoS priority level is negatively correlated with the number of first access requests from each processor core. That is, the greater the number of first access requests from the same processor core, the lower the QoS priority, and the fewer the number of first access requests from the same processor core, the higher the QoS priority.
[0079] Optionally, at least two of the multiple second access requests have different QoS priorities, and the multiple QoS priorities correspond one-to-one to the multiple queues. The memory controller 21 is specifically configured to: schedule second access requests stored in a first queue among the multiple queues to access at least one memory, where the first queue corresponds to a first QoS priority among the multiple QoS priorities. And, when the first queue is empty, schedule second access requests stored in a second queue among the multiple queues to access at least one memory, where the second queue corresponds to a second QoS priority among the multiple QoS priorities, where the first QoS priority is higher than the second QoS priority.
[0080] For example, see Figure 3 , Figure 3 Only the first queue and the second queue are shown, wherein the first queue corresponds to the first QoS priority, the second queue corresponds to the second QoS priority, and the first queue stores the second access request from the processor core _1, that is, Figure 3 As shown in “m1”, the second queue stores the second access request from processor core _2, i.e. Figure 3 The “m2” shown in .
[0081] Exemplarily, the memory controller 21 can schedule multiple second access requests stored in the first queue and the second queue in a round-robin scheduling manner. Specifically, since the first QoS priority is higher than the second QoS priority, the memory controller 21 can first schedule the second access requests in the first queue, and then schedule the second access requests in the second queue when the first queue is empty. Thus, when there are still access requests in the queue with high QoS priority, the access requests in the queue with low QoS priority will not be scheduled, thereby ensuring the latency of the access requests with high QoS priority. In addition, since the number of access requests is taken into account in the process of marking the QoS priority, the proportion of access requests with low QoS priority in the time period is relatively small, and there will be no situation where access requests with low QoS priority are not scheduled all the time.
[0082] In addition, the memory controller 21 may also schedule multiple second access requests stored in the first queue and the second queue using a weighted round-robin scheduling method. The scheduling weight in the first queue may be higher than the scheduling weight in the second queue, i.e., the access requests in the first queue are scheduled preferentially. Furthermore, the memory controller 21 may also schedule the access requests in the queues using other methods. The embodiments of the present application do not limit the scheduling method of the memory controller 21.
[0083] Optional, such as Figure 4 As shown, Figure 4A schematic diagram of the structure of another storage system provided in an embodiment of the present application. A memory controller 21 includes a queue, a counter 211, and at least one set of comparators 212. Counter 211 is configured to receive multiple first access requests and count the number of first access requests sent by each processor core in the multiple queues to obtain multiple second counting results.
[0084] For example, at a certain moment, the counter 211 can count the number of first access requests from each processor core currently stored in all queues to obtain multiple second counting results. Figure 4 In the queue shown in , the second count result of “m0” from processor core_0 is 3, the second count result of “m1” from processor core_1 is 16, the second count result of “m2” from processor core_2 is 2, and the second count result of “m3” from processor core_3 is 1.
[0085] Among them, at least one group of comparators 212 is used to respectively determine whether multiple second counting results are greater than the second threshold value in each group of comparators 212 in at least one group of comparators, obtain multiple second comparison results, and mark the QoS priority of the first access request sent to each processor core based on the multiple second comparison results to obtain multiple second access requests.
[0086] Exemplarily, the second threshold in each group of comparators 212 may be the value of the second counting result, i.e., the memory controller 21 may determine the QoS priority of each first access request based on the relative number of first access requests from the multiple processor cores. For example, since m1>m0>m2>m3, the memory controller 21 may mark the highest QoS priority for the first access request from processor core_3, mark the second highest QoS priority for the two first access requests from processor core_2, mark the second lowest QoS priority for the three first access requests from processor core_0, and mark the lowest QoS priority for the 16 first access requests from processor core_1.
[0087] Optionally, at least two second access requests among the multiple second access requests have different QoS priorities, and the multiple QoS priorities correspond to the multiple queues one-to-one.
[0088] The memory controller 21 is specifically configured to: schedule a first preset number of second access requests stored in a third queue among the multiple queues to access at least one memory, where the third queue corresponds to a third QoS priority among the multiple QoS priorities; and schedule a second preset number of second access requests stored in a fourth queue among the multiple queues to access at least one memory, where the fourth queue corresponds to a fourth QoS priority among the multiple QoS priorities, where the third QoS priority is higher than the fourth QoS priority.
[0089] For example, in a certain scenario, assuming that the second access request from processor core_2 has a high QoS priority, after the memory controller 21 schedules the second access request from processor core_2, the counter 211 may receive a first access request from processor core_2. Since the counter 211 counts the number of first access requests in all queues in real time, the second access request with a low QoS priority may not be scheduled for a long time. Therefore, the memory controller 21 can schedule multiple second access requests based on a weighted scheduling algorithm.
[0090] For example, the memory controller 21 can schedule multiple second access requests stored in the third queue and the fourth queue in a weighted round-robin manner, wherein the first preset number is the scheduling weight of the third queue, and the second preset number is the scheduling weight of the fourth queue. Specifically, referring to the above example, assuming that the queue storing "m2" is the third queue, and the queue storing "m0" is the fourth queue, the first preset number is 2, and the second preset number is 1, since the third QoS priority is higher than the fourth QoS priority, the memory controller 21 can first schedule the two second access requests in the third queue, and then schedule the one second access request in the fourth queue. Thus, while ensuring that the second access request with a high QoS priority is scheduled first, the second access request with a low QoS priority can also be scheduled, thereby reducing the latency of the chip system in processing access requests and improving the performance of the chip system.
[0091] The embodiment of the present application further provides a chip system, which includes multiple processor cores and the above-mentioned storage system, wherein the multiple processor cores and the storage system are coupled via a bus. In other words, the chip system can be a system with multiple processor cores and multiple memories.
[0092] Optional, such as Figure 5 As shown, Figure 5 A schematic diagram of the structure of a processor system provided in an embodiment of the present application. The processor system 50 includes multiple processor cores 51 and multiple counters 52. The multiple processor cores 51 and the multiple counters 52 have a one-to-one correspondence, and the output of each processor core 51 is coupled to the input of the corresponding counter 52. Figure 5 Figure 5 shows n processor cores 51 and n counters 52, where n is a positive integer. The n processor cores 51 are processor core 51_1, processor core 51_2, ..., and processor core 51_n, and the n counters 52 are counter 52_1, counter 52_2, ..., and counter 52_n. Processor core 51_1 corresponds to counter 52_1, processor core 51_2 corresponds to counter 52_2, ..., and processor core 51_n corresponds to counter 52_n.
[0093] Each processor core 51 is configured to output at least one first access request to a corresponding counter 52. Each counter 52 is configured to count the number of the at least one first access request, obtain a count result, and, based on the count result, mark the at least one first access request with a QoS priority, thereby obtaining at least one second access request. The at least one second access request carries a QoS priority. The number of the at least one first access request and the QoS priority are negatively correlated. That is, a greater number of first access requests indicates a lower QoS priority, while a smaller number of first access requests indicates a higher QoS priority.
[0094] For example, assuming that the bandwidth capability of each processor core 51 is consistent, the counter 52 can mark the QoS priority based on the number of first access requests issued by the corresponding processor core 51, and obtain at least one second access request. In one possible example, assuming that the count result of the first access request from processor core 51_1 is 10, the count result of the first access request from processor core 51_2 is 8, and the count result of the first access request from processor core 51_n is 4, then the first access request from processor core 51_n can be marked with the highest QoS priority, the first access request from processor core 51_2 can be marked with the second highest QoS priority, and the first access request from processor core 51_1 can be marked with the lowest QoS priority. In this way, QoS priority marking can be completed on the processor system 50 side, which can reduce the delay of the subsequent storage system processing access requests and improve the performance of the entire chip system.
[0095] The embodiment of the present application also provides another chip system, which includes a memory and the above-mentioned processor system, and the processor system and the memory are coupled via a bus. In other words, the chip system can be a system with multiple processor cores and a single memory.
[0096] Applied to the above-mentioned storage system or processor system, the access method provided by the embodiment of the present application is introduced below.
[0097] like Figure 6 As shown, Figure 6 This is a flowchart of an access method provided in an embodiment of the present application. The method may include S601 and S602.
[0098] S601. The storage system controls the memory controller to receive multiple first access requests from multiple processor cores, and marks the quality of service (QoS) priority of the first access request sent by each processor core according to the number of first access requests sent by each processor core, to obtain multiple second access requests.
[0099] The multiple second access requests carry QoS priorities.
[0100] For example, each processor core can issue at least one first access request, and the memory controller can obtain the number of first access requests from each processor core and mark the QoS priority based on the number of first access requests from each processor core to obtain multiple second access requests. When marking the QoS priority, the memory controller can mark low-traffic delay-sensitive access requests with a high QoS priority, and can mark high-traffic non-delay-sensitive access requests with a low QoS priority. This reduces the queuing delay of low-traffic delay-sensitive access requests and improves the storage system's throughput in processing low-traffic delay-sensitive access requests.
[0101] S602: The storage system controls the memory controller to schedule multiple second access requests to access at least one memory based on QoS priorities.
[0102] Exemplarily, the memory controller may schedule multiple second access requests by first scheduling the second access request with high QoS priority and then scheduling the second access request with low QoS priority, wherein the specific scheduling method may be a first-in-first-out method, a round-robin scheduling method, a weighted round-robin scheduling method, or a weighted difference round-robin scheduling method.
[0103] It can be understood that the specific implementation of S601 and S602 can be found in the above description of the storage system, which will not be repeated here.
[0104] like Figure 7 As shown, Figure 7 This is a flowchart of another access method provided in an embodiment of the present application. The method may include S701 and S702.
[0105] S701: The processor system controls each processor core to output at least one first access request to a corresponding counter.
[0106] S702: The processor system controls each counter to count the number of at least one first access request to obtain a counting result, and marks a quality of service (QoS) priority for the at least one first access request based on the counting result to obtain at least one second access request.
[0107] At least one second access request carries a QoS priority.
[0108] For example, assuming that the bandwidth capability of each processor core is consistent, the counter can mark the QoS priority based on the number of first access requests issued by the corresponding processor core, and obtain at least one second access request, that is, the processor system can complete the QoS priority marking on the processor core side, which can reduce the delay of subsequent storage system processing access requests and improve the performance of the entire chip system.
[0109] An embodiment of the present application also provides a computer storage medium, which stores computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the access method in the above-mentioned embodiment.
[0110] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the access method executed by the electronic device in the above-mentioned embodiment.
[0111] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory to enable the chip to execute the access method executed by the electronic device in the above-mentioned method embodiments.
[0112] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.
[0113] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.
[0114] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0115] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0116] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.
[0117] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0118] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A storage system, characterized in that: include: a memory controller and at least one memory; The memory controller is configured to: receive a plurality of first access requests from a plurality of processor cores, and mark a quality of service (QoS) priority for the first access request sent by each processor core according to the number of the first access requests sent by each processor core, to obtain a plurality of second access requests, wherein the plurality of second access requests carry the QoS priority; The memory controller is further configured to: respectively schedule the multiple second access requests to access the at least one memory based on the QoS priority.
2. The storage system according to claim 1, wherein: The memory controller includes a counter and at least one set of comparators; The counter is configured to: receive a plurality of third access requests within a first time period, and respectively count the number of at least one third access request from each processor core to obtain a plurality of first counting results; The at least one group of comparators is configured to: determine whether the plurality of first counting results are greater than a first threshold in each group of comparators in the at least one group of comparators, respectively, to obtain a plurality of first comparison results, wherein the plurality of first comparison results correspond to the identifiers of the plurality of processor cores in a one-to-one manner; The at least one group of comparators is also used to: mark the QoS priority of the first access request sent to each processor core based on the multiple first comparison results in a second time period after the first time period, and obtain multiple second access requests, where the first access request carries the identifier of the corresponding processor core.
3. The storage system according to claim 1 or 2, characterized in that: At least two of the multiple second access requests have different QoS priorities, and the multiple QoS priorities correspond to the multiple queues one-to-one; The memory controller is specifically used for: Scheduling a second access request stored in a first queue of the plurality of queues to access the at least one memory, the first queue corresponding to a first QoS priority of the plurality of QoS priorities; When the first queue is empty, the second access request stored in the second queue among the multiple queues is scheduled to access the at least one memory, the second queue corresponds to the second QoS priority among the multiple QoS priorities, and the first QoS priority is higher than the second QoS priority.
4. The storage system according to claim 1, wherein: The memory controller includes a counter, at least one set of comparators and a plurality of queues; The counter is configured to: receive the plurality of first access requests, and count the number of first access requests sent by each processor core in the plurality of queues to obtain a plurality of second counting results; The at least one group of comparators is used to: respectively determine whether the multiple second counting results are greater than the second threshold value in each group of comparators in the at least one group of comparators, to obtain multiple second comparison results, and mark the QoS priority of the first access request sent by each processor core based on the multiple second comparison results, to obtain the multiple second access requests.
5. The storage system according to claim 4, wherein: At least two of the multiple second access requests have different QoS priorities, and the multiple QoS priorities correspond to the multiple queues one-to-one; The memory controller is specifically used for: Scheduling a first preset number of second access requests stored in a third queue among the multiple queues to access the at least one memory, the third queue corresponding to a third QoS priority among the multiple QoS priorities; Schedule a second preset number of second access requests stored in a fourth queue among the multiple queues to access the at least one memory, the fourth queue corresponds to a fourth QoS priority among the multiple QoS priorities, and the third QoS priority is higher than the fourth QoS priority.
6. The storage system according to any one of claims 1 to 5, characterized in that: The level of the QoS priority and the number of the first access requests of each processor core are negatively correlated.
7. A processor system, characterized in that: comprising a plurality of processor cores and a plurality of counters, wherein the plurality of processor cores and the plurality of counters correspond to each other in a one-to-one manner; Each processor core is configured to: output at least one first access request to the corresponding counter; Each of the counters is used to: count the number of the at least one first access request to obtain a counting result, and mark the quality of service QoS priority of the at least one first access request based on the counting result to obtain at least one second access request, wherein the at least one second access request carries the QoS priority.
8. The processor system according to claim 7, wherein: The number of the at least one first access request and the QoS priority are negatively correlated.
9. An access method, characterized in that: The method is applied to a storage system, the storage system including a memory controller and at least one memory, and the method includes: Controlling the memory controller to receive multiple first access requests, and marking the first access request sent by each processor core with a quality of service (QoS) priority according to the number of first access requests sent by each processor core, to obtain multiple second access requests, wherein the multiple second access requests carry the QoS priority; The memory controller is controlled to respectively schedule the plurality of second access requests to access the at least one memory based on the QoS priority.
10. The method according to claim 9, characterized in that The memory controller includes a counter and at least one group of comparators. The control of the memory controller to receive multiple first access requests from multiple processor cores and to mark a QoS priority for the first access request sent by each processor core according to the number of the first access requests sent by each processor core to obtain multiple second access requests includes: Controlling the counter to receive a plurality of third access requests from a plurality of processor cores within a first time period, and respectively counting the number of the third access requests sent by each processor core to obtain a plurality of first counting results; controlling the at least one group of comparators to respectively determine whether the plurality of first counting results are greater than a first threshold in each group of comparators in the at least one group of comparators, to obtain a plurality of first comparison results, wherein the plurality of first comparison results correspond one-to-one to the identifiers of the plurality of processor cores; Control at least one group of comparators to mark the QoS priority of the first access request sent to each processor core based on the multiple first comparison results within a second time period after the first time period, and obtain multiple second access requests, where the first access request carries the identifier of the corresponding processor core.
11. The method according to claim 9 or 10, characterized in that At least two of the multiple second access requests have different QoS priorities, the multiple QoS priorities correspond to the multiple queues one-to-one, and controlling the memory controller to schedule the multiple second access requests to access the at least one memory based on the QoS priorities includes: Controlling the memory controller to schedule a second access request stored in a first queue of the plurality of queues to access the at least one memory, the first queue corresponding to a first QoS priority among the plurality of QoS priorities; When the first queue is empty, the memory controller is controlled to schedule a second access request stored in a second queue among the multiple queues to access the at least one memory, the second queue corresponds to a second QoS priority among the multiple QoS priorities, and the first QoS priority is higher than the second QoS priority.
12. The method according to claim 9, characterized in that The memory controller includes a counter, at least one group of comparators, and multiple queues. The control of the memory controller to receive multiple first access requests from multiple processor cores, marking the QoS priority of the first access request sent by each processor core according to the number of first access requests sent by each processor core, and obtaining multiple second access requests includes: controlling the counter to receive the plurality of first access requests and to count the number of first access requests sent by each processor core in the plurality of queues to obtain a plurality of second counting results; Control the at least one group of comparators to respectively determine whether the multiple second counting results are greater than the second threshold value in each group of comparators in the at least one group of comparators to obtain multiple second comparison results, and mark the QoS priority of the first access request sent by each processor core based on the multiple second comparison results to obtain the multiple second access requests.
13. The method according to claim 12, characterized in that At least two of the multiple second access requests have different QoS priorities, the multiple QoS priorities correspond to the multiple queues one-to-one, and controlling the memory controller to schedule the multiple second access requests to access the at least one memory based on the QoS priorities includes: Controlling the memory controller to schedule a first preset number of second access requests stored in a third queue among the multiple queues to access the at least one memory, wherein the third queue corresponds to a third QoS priority among the multiple QoS priorities; Control the memory controller to schedule a second preset number of second access requests stored in a fourth queue among the multiple queues to access the at least one memory, the fourth queue corresponds to a fourth QoS priority among the multiple QoS priorities, and the third QoS priority is higher than the fourth QoS priority.
14. The method according to any one of claims 9 to 13, characterized in that: The level of the QoS priority and the number of the first access requests of each processor core are negatively correlated.
15. An access method, characterized in that: The method is applied to a processor system, the processor system including multiple processor cores and multiple counters, the multiple processor cores and the multiple counters corresponding one to one, and the method includes: Controlling each of the processor cores to output at least one first access request to the corresponding counter; Control each of the counters to count the number of the at least one first access request to obtain a counting result, and mark the at least one first access request with a quality of service QoS priority based on the counting result to obtain at least one second access request, wherein the at least one second access request carries the QoS priority.
16. The method according to claim 15, characterized in that The number of the at least one first access request and the QoS priority are negatively correlated.
17. A chip system, characterized in that: include: A plurality of processor cores and the memory system according to claims 1-6, wherein the plurality of processor cores and the memory system are coupled via a bus.
18. A chip system, characterized in that: include: A memory and a processor system as claimed in claims 7-8, wherein the processor system and the memory are coupled via a bus.
19. A computer-readable storage medium, characterized in that The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 9 to 14 or claims 15 to 16.