Performance enhancement method and device based on artificial intelligence engine, storage medium and computer program product
By using an AI engine-based approach and predictive models generated by training servers to optimize NAND flash memory processing settings, the problem of improving NAND flash memory performance was solved, achieving higher data writing and reading speeds and more stable storage performance.
Patent Information
- Application Number
- CN202411234001.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-14
- Filing Date
- 2024-09-04
- Publication Date
- 2025-09-16
Smart Images
Figure CN120653186A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a storage device, and more particularly to a performance improvement method, device, computer-readable storage medium, and computer program product based on an artificial intelligence engine. Background Art
[0002] Flash memory is generally categorized as NOR flash and NAND flash. NOR flash is a random-access device. The central processing unit (CPU) can provide any address to access NOR flash on the address pins and promptly retrieve the data stored at that address from the NOR flash's data pins. In contrast, NAND flash is not random-access, but serial-access. Unlike NOR flash, NAND flash cannot access any random address. Instead, the CPU must write serial byte values to the NAND flash to define the type of command requested (e.g., read, write, erase, etc.) and the address used for that command. The address can point to a page (the smallest data block in flash memory for write operations) or a block (the smallest data block in flash memory for erase operations). Improving NAND flash access performance, such as host data write speed, host data read speed, stored data stability, and storage space utilization, has always been a key issue for flash memory controllers. Summary of the Invention
[0003] In view of this, how to alleviate or eliminate the defects in the above-mentioned related fields is indeed a problem to be solved.
[0004] The present invention relates to a performance improvement method based on an artificial intelligence engine, which is executed by a processing unit and includes: generating the value of a first type of parameter based on commands and parameters exchanged between a host end and a flash memory controller; generating the value of a second type of parameter based on the software and firmware status of the flash memory controller; generating the value of a third type of parameter based on the status of the flash memory module, so that a prediction model running in the artificial intelligence engine can generate multiple types of prediction results based on the values of the first type of parameter, the second type of parameter, and the third type of parameter, wherein a training server uses a machine learning algorithm to generate the prediction model based on training data; and adjusting the settings of the processing running in the flash memory controller based on the multiple types of prediction results.
[0005] The present invention also relates to a computer-readable storage medium for storing program code that can be loaded and executed by a processing unit, and when the program code is executed by the processing unit, the performance improvement method based on the artificial intelligence engine as described above is implemented.
[0006] The present invention also relates to a performance enhancement device comprising: an artificial intelligence engine; and a processing unit. The processing unit is configured to: generate values of first-category parameters based on commands and arguments exchanged between a host and a flash memory controller; generate values of second-category parameters based on the software and firmware status of the flash memory controller; and generate values of third-category parameters based on the status of the flash memory module, so that a prediction model running in the artificial intelligence engine can generate multiple types of prediction results based on the values of the first, second, and third types of parameters, wherein a training server generates the prediction model based on training data using a machine learning algorithm; and adjust settings of a process running in the flash memory controller based on the multiple types of prediction results.
[0007] The present invention further relates to a computer program product, comprising a computer program, wherein when the computer program is executed by a processing unit, the performance improvement method as described above is implemented.
[0008] One of the advantages of the above embodiment is that the frequency of modifying the program code of the firmware translation layer can be reduced by using the prediction model generated by the training server as described above.
[0009] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.
[0011] Figure 1 FIG. 4 is a system architecture diagram of an electronic device according to an embodiment of the present invention.
[0012] Figure 2 FIG. 1 is a schematic diagram of a flash memory module according to an embodiment of the present invention.
[0013] Figure 3 FIG. 4 is a partial hardware architecture diagram of a NAND flash memory unit according to an embodiment of the present invention.
[0014] Figure 4 Schematic diagram of a machine learning and deployment system according to an embodiment of the present invention.
[0015] Figure 5 FIG. 4 is a timing diagram of executing a host read command between a host and a device according to an embodiment of the present invention.
[0016] Figure 6 FIG. 4 is a schematic diagram of the operation of an artificial intelligence engine according to an embodiment of the present invention.
[0017] Figure 7Flowchart of a performance improvement method based on an artificial intelligence engine according to an embodiment of the present invention.
[0018] Figure 8 FIG. 1 is a schematic diagram of setting adjustment for garbage collection processing according to an embodiment of the present invention.
[0019] Description of reference numerals:
[0020] 10: Electronic devices
[0021] 110: Host side
[0022] 130: Flash memory controller
[0023] 131: Host interface
[0024] 132: Bus Architecture
[0025] 134: Processing unit
[0026] 135: Artificial Intelligence Engine
[0027] 136: Random Access Memory
[0028] 139: Flash memory interface
[0029] 150: Flash memory module
[0030] 151: Interface
[0031] 153#0 to 153#15: NAND flash memory cells
[0032] CH#0~CH#3:channel
[0033] CE#0~CE#3: Start signal
[0034] 300: Storage block
[0035] 310: Floating-gate transistor
[0036] BL1~BL3: bit lines
[0037] WL0~WL5: word lines
[0038] 40: Machine Learning and Deployment Systems
[0039] 400: Network
[0040] 410: Training Server
[0041] 450: Tablet computer
[0042] 470: Mobile Phone
[0043] 610: Firmware Translation Layer
[0044] 630: Register
[0045] 635: Multi-class prediction results
[0046] 650: Commands and parameters for interaction between the host and the flash memory controller
[0047] 655: First category parameters
[0048] 670: Flash controller status
[0049] 675: Second type of parameters
[0050] 690: NAND status
[0051] 695: Third type parameters
[0052] S710, S730, S750: Method steps
[0053] 810: Prediction result of host application identification
[0054] 830: Prediction results of host performance indicator
[0055] 851: Prediction results of foreground garbage collections at garbage collection types and time points
[0056] 855: Prediction results of background garbage collection at garbage collection type and time point
[0057] 881, 882, 883, 884, 885: Use Cases DETAILED DESCRIPTION
[0058] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.
[0059] The following provides various aspects and embodiments of the present invention. Some embodiments can be implemented independently, while others can be combined and implemented as readily apparent to one skilled in the art. The following description is for illustrative purposes only, with specific details provided to provide a complete understanding of the various aspects of the present invention. However, it will be apparent that these embodiments do not necessarily require such exhaustive implementation. The drawings and description are not intended to limit the present invention.
[0060] The following descriptions are merely examples of various aspects and are not intended to limit the scope, applicability, or configuration of this specification. Instead, the various examples are intended to provide a description that one of ordinary skill in the art can implement. It should be understood that the functions and arrangements of the components herein may be modified without violating the scope and spirit of the claims.
[0061] reference Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as the device side (Device Side). The electronic device 10 can be implemented in electronic products such as peripheral storage devices, personal computers, laptop computers (Laptop PCs), tablet computers, mobile phones, digital cameras, digital video cameras, smart TVs, smart refrigerators, and automotive electronic systems (Automotive Electronics System). The host side 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash memory controller 130's flash interface 139 and the flash memory module 150 can communicate with each other using a double data rate (DDR) communication protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR Toggle), or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (e.g., a single processor, a microcontroller unit, a multi-processor with parallel processing capabilities, a graphics processor, or other processor with computing capabilities), and provides the functions described below when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as write commands and read commands, through the host interface 131, and schedules and executes these commands.The flash controller 130 also includes a random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM 136 is used to configure space as a data buffer for storing user data (also referred to as host data) read from the host 110 and to be written to the flash memory module 150, as well as user data read from the flash memory module 150 and to be output to the host 110. The RAM 136 can also store data required during execution, such as variables, data tables, data structures, host-to-flash (H2F) tables, and flash-to-host (F2H) tables. The flash memory interface 139 includes a NAND Flash Controller (NFC) that provides functions required for accessing the flash memory module 150 , such as a command serializer (CSerializer) and a low-density parity check (LDPC).
[0062] Flash memory controller 130 may be configured with a bus architecture 132 for coupling components to each other for transmitting data, addresses, and control signals. These components include, but are not limited to, host interface 131, processing unit 134, RAM 136, and flash memory interface 139. Direct memory access (DMA) circuits within these components can transfer data between components via bus architecture 132 based on instructions or control signals. For example, a DMA circuit within host interface 131 or flash memory interface 139 can move data from a specific data buffer therein to a specific address within RAM 136, or vice versa.
[0063] Flash memory module 150 provides a large amount of storage space, typically hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. Flash memory module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. Processing unit 134 writes user data to a specified address (destination address) in flash memory module 150 and reads user data from a specified address (source address) in flash memory module 150 via flash memory interface 139. Flash memory interface 139 coordinates the transfer of data and commands between flash memory controller 130 and flash memory module 150 using multiple electronic signals, including data lines, clock signals, and control signals. The data lines can be used to transmit commands, addresses, read and write data; the control signal lines can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), and write enable (WE).
[0064] refer to Figure 2 The interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which connects to four NAND flash memory cells. For example, channel CH#0 connects to NAND flash memory cells 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as an independent chip (die). The flash memory interface 139 may activate NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals CE#0 to CE#3 via the interface 151, and then read user data from or write user data to the activated NAND flash memory cells in parallel.
[0065] refer to Figure 3The local hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may include a memory block 300, which includes multiple memory cells, such as floating gate transistors 310 or other charge trap devices. The structure of the memory block 300 includes multiple bit lines and multiple word lines. For simplicity, Figure 3 Only bit lines BL1 to BL3 and word lines WL0 to WL5 are labeled. For example, the floating gate transistors on each of word lines WL0 to WL5 can be used to store one or more pages of data.
[0066] Each NAND flash memory cell may contain multiple data planes, and each data plane may contain multiple physical blocks. To improve data writing and reading efficiency, the physical pages in the multiple data planes of multiple NAND flash memory cells may be organized into a super page (SP), and each super block may contain multiple physical pages. Super blocks and physical pages may be identified using super-block numbers and page numbers, respectively. The combination of these numbers may be referred to as the physical address of the flash memory module 150.
[0067] Each superblock can be classified as a data block or a current block based on its function. Processing unit 134 can select an empty superblock as the current block to prepare for writing user data received from host 110 or management information from flash memory module 150. Management information can include a flash identifier (ID), a bad block table (BBT), a bad column table (BBT), a host-to-flash (H2F) table, and the like. To improve data writing efficiency, user data provided by host 110 or management information from flash memory module 150 can be written in parallel to specific physical pages in a superblock spanning multiple NAND flash memory cells. Processing unit 134 can maintain an F2H table for each current block in RAM 136. The table contains multiple records, storing information, in page number order, indicating which logical address the user data at each physical address in the current block is associated with (or mapped to). Logical addresses can be represented by logical block addresses (LBAs), main page numbers, or other methods and are managed by the host 110. For example, each logical block address or main page is associated with 4KB of user data or management information. In some embodiments, after all physical pages in a current block are filled with user data, or after the remaining pages in a current block are filled with dummy values, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 to the data portion of a specified physical page (e.g., the last physical page) of the current block. Once all records in the corresponding F2H table have been written to the flash memory module 150, the current block is converted to a data block, and the user data stored in the data block remains unchanged. In other embodiments, after all physical pages in a current block are filled with management information, or after the remaining pages other than the management information pages are filled with management information, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 to the data portion of a specified physical page (e.g., the last physical page) of the current block. After the corresponding F2H table has been written into the flash memory module 150, the current block is changed to a system block, and the management information stored in the system block will not be changed. The data block and the system block can also be called closed blocks.
[0068] In order to improve the performance of the device side, the processing unit 134 of the flash memory controller 130 loads and executes the program code of the Firmware Translation Layer (FTL), which is used to make various decisions and switch between different working modes when predefined conditions are met. These modes include but are not limited to optimal quality of service (QoS), optimal write amplification factor (WAF), optimal performance, etc. In some embodiments, the manufacturer of the flash memory controller 130 can add situational awareness (Situation Awareness) or host pattern recognition (Host Pattern Recognition) program code to the FTL, and achieve the above-mentioned decisions and mode conversions through a large number of conditional judgments and rules. However, in order to adapt to more types of flash memory modules 150 or application environments, the program code of the FTL often needs to be modified, making version maintenance difficult.
[0069] In order to solve or alleviate the technical problems arising from the above-mentioned embodiments, an embodiment of the present invention proposes a performance improvement mechanism based on an artificial intelligence engine. This mechanism uses an artificial intelligence engine 135 to perform complex decisions based on real-time operating conditions, and sets and executes corresponding processing based on the results of the decision to improve device-side performance. In some embodiments, the artificial intelligence engine 135 is an application-specific integrated circuit (ASIC) that includes a large number of logic gates for storing input parameters generated by the processing unit 134, executing a prediction model to generate prediction results based on these input parameters, and storing the prediction results for reading by the processing unit 134. In other embodiments, the artificial intelligence engine 135 is a program code that can be loaded and executed by the processing unit 134 to execute one or more specific prediction models to generate prediction results based on real-time operating conditions.
[0070] To generate the artificial intelligence engine 135, the manufacturer of the flash memory controller 130 may set up a laboratory and install a training server there. In other embodiments, the manufacturer of the flash memory controller 130 may rent a training server on an artificial intelligence cloud. The training server executes a machine learning algorithm to generate a predictive model based on training data. The training data includes a large number of samples, each of which includes actual historical input parameter values or simulated input parameter values associated with the execution of one or more host commands, or associated with a period of time (independent of host commands), as well as output results corresponding to facts, simulated scenarios, and / or engineer experience. After the predictive model is trained, the training server generates program code that incorporates the predictive model, which serves as the artificial intelligence engine 135. In some embodiments, manufacturing engineers store this program code in non-volatile storage space on the device. The non-volatile storage space can be a designated address in the read-only memory or static random access memory of the flash memory controller 130, or a designated system block in the flash memory module 150. When the device is running, the processing unit 134 loads and executes this program code to use the trained predictive model to generate prediction results based on real-time input parameter values. In other embodiments, circuit design engineers can design an ASIC for the artificial intelligence engine 135 based on the trained prediction model and integrate this ASIC into the flash memory controller 130. When the device is running, the processing unit 134 feeds real-time input parameters to the artificial intelligence engine 135 and obtains prediction results from the artificial intelligence engine 135. It should be noted that since a single device does not have enough samples, the processing unit 134 of the flash memory controller 130 cannot execute the machine learning algorithm to generate a prediction model.
[0071] In some embodiments, to update the artificial intelligence engine 135, refer to Figure 4The machine learning and deployment system 40 includes a training server 410, a tablet computer 450, and a mobile phone 470. The manufacturer of the flash memory controller 130 can establish a laboratory and place the training server 410 therein to execute a machine learning algorithm to generate a prediction model based on a large amount of training data. After the latest prediction model training is completed, the training server 410 generates program code containing the latest prediction model. The training server 410 transmits artificial intelligence engine update information and the latest program code to the tablet computer 450 and the mobile phone 470 via the network 400, allowing the central processing unit (CPU) in the tablet computer 450 and the mobile phone 470 (i.e., the host 110) to update the program code of the artificial intelligence engine 135 according to the instructions, thereby updating the original prediction model to the latest prediction model. The network 400 can be the Internet, a wired local area network (LAN), a wireless local area network, or any combination thereof. The host 110 can send a customized AI engine update command and updated program code to the flash memory controller 130 via the host interface 131, so that the processing unit 134 can overwrite the updated program code to a specified address of the static random access memory or write it to a specified system block in the flash memory module 150. Figure 4 The embodiment only describes a tablet computer 450 and a mobile phone 470, but the training server 410 can also update the program code of the intelligent engine 135 in other electronic devices, such as an external storage device, a personal computer, a notebook computer, a digital camera, a digital video camera, a smart TV, a smart refrigerator, a car electronic system, etc.
[0072] The training data samples may include the following multiclass output results: Host Type Identification; Host Performance Identification; Host Application Identification; Garbage Collection (GC Type and Timing); Auto Write Boost; Wear Leveling Strategy; Read Refresh / Reclaim Strategy; Power Saving Mode Entrance Period; Power Throttling; Standby Period for Command Continuity; LDPC Throughput. Each class of output results for each sample is assigned a value. If the output result for any class in any sample is set to "0" or a null value, it means that there is no output result for that class for that sample.
[0073] The value of the host type identifier can be set to an integer greater than 0, representing a specific host type, for example, "1" represents a mobile phone, "2" represents a personal computer, "3" represents a server, "4" represents a game console, etc.
[0074] The value of the host performance indicator can be set to an integer greater than 0, representing the busyness level of the host driver, for example, "1" represents low, "2" represents medium, and "3" represents high. Figure 5 FIG2 shows a timing diagram of a host-device communication sequence for executing a host read command between the host and the device. The host sends a read command to the device to retrieve user data at a specific logical address from the device. Block “C” represents a read command, block “R” represents a reply, and block “D” represents user data. Figure 5 The upper part (A) in FIG1 shows the execution of three read commands, wherein the host latency (Host Latency) between the execution of two commands is short, which indicates that the host performance is high. Figure 5 The lower half (B) in FIG. 3 shows the execution of two read commands, wherein the host latency between the execution of the two commands is long, which may indicate a low host performance situation.
[0075] The value of the host application identifier can be set to an integer greater than 0, representing the specific application being executed on the host. For example, "1" represents office software, "2" represents games, "3" represents Computer Aided Design (CAD), "4" represents 3D drawing, "5" represents stress testing, "6" represents audio / video player, "7" represents web browser, etc.
[0076] The values of garbage collection type and time point can be set to integers greater than 0, representing the execution mode of GC processing. For example, "1" represents only foreground GC, "2" represents only background GC, "3" represents both foreground and background GC, "4" represents pause GC, "5" represents emergency GC, etc.
[0077] The value of automatic write acceleration can be set to an integer greater than 0, which represents the space reserved for SLC cache in the flash controller's RAM, in bytes.
[0078] The Wear Leveling Strategy value can be set to an integer greater than 0, representing the Program / Erase (P / E Count) threshold at which wear leveling is initiated. The Read Refresh / Reclaim Strategy value can be set to a positive integer greater than 0, representing the Read Disturbance Count threshold at which read reclaim / refresh is initiated.
[0079] The power saving mode entry duration value can be set to a floating point number greater than 0, representing the duration of the power saving mode entry, for example, any number of seconds from 500 microseconds (μs) to 5 milliseconds (ms). The power throttle value can be set to a floating point number greater than 0, representing the flash memory controller clock adjustment factor, for example, any value from 0.3 to 1.1. For example, if it is set to 0.3, the flash memory controller will operate at a frequency that is 0.3 times the default frequency. If it is set to 1.1, the flash memory controller will operate at a frequency that is 1.1 times the default frequency.
[0080] The command continuity wait time can be set to an integer greater than 0, representing a period for determining command continuity, such as any number of seconds from 1 to 5 milliseconds. For example, the flash memory controller can detect the logical address ranges of all host commands within the command continuity wait time to determine the continuity of these host commands.
[0081] The value of the low-density parity check throughput can be set to an integer greater than 0, representing the length of the LDPC in bits.
[0082] In samples associated with the execution of host commands, the machine learning algorithm needs to collect as many input parameters as possible that will affect the output results of the above multiple categories. The input parameters required by the machine learning algorithm may include the following three categories: input and output communication between the host and device ends; the software and firmware status of the flash memory controller; and the flash memory module status. The first type of input parameters is used to collect basic data of one or more host commands. The second type of input parameters is used to indicate the hardware and firmware status of the flash memory controller when this or these host commands are executed. The third type of input parameters is used to indicate the status of the flash memory module when this or these host commands are executed. When any input parameter value in any sample is set to "0" or an empty value, it means that this sample lacks this input parameter value.
[0083] Regarding input and output communications between the host and device, input parameters may include, but are not limited to, command type, additional command arguments, chunk size, address distribution, host interface settings, host latency, host idle time, exceptions, and the like. The command type value may be an integer greater than 0, for example, "1" for a read command, "2" for a write command, "3" for a discard command, "4" for a task management command (TaskMgt), and "5" for a write boost command (WriteBoost). Additional command argument values may include, but are not limited to, values carried in host commands, such as host-initiated defragmentation (HID), priority, and file-based optimization (FBO). The chunk size value may be an integer greater than 0, expressed in bytes, for example, representing a size from 4K to 1M. The address distribution may represent a range of logical block addresses. The value of the host interface setting may include but is not limited to information such as the gear (Gear), channel condition (LaneCondition), and mode when the host interface is running. The value of the host-side delay time may be an integer greater than 0, indicating the time from the device side executing one or more host commands to the next host command. The value of the host idle time may be an integer greater than 0, indicating the time when the host side does not send any host commands to the device side. The value of the exception event may be an integer greater than 0, for example, "1" represents entering the write protection state, "2" represents executing the sudden power off recovery (SPOR) process, etc.
[0084] Regarding the software and firmware status of the flash memory controller, the input parameters may include, but are not limited to, the operating mode, clock setting, spare block count (Spare Count), available SLC cache capacity, etc. of the flash memory controller. The value of the operating mode of the flash memory controller may be an integer greater than 0, for example, "1" represents normal mode, "2" represents power saving mode, etc. The clock setting of the flash memory controller may be a floating point number greater than 0, with MHz as the basic unit. The value of the spare block count may be an integer greater than 0, representing the number of spare blocks currently available in the flash memory module. The value of the available SLC cache capacity of the flash memory controller may be an integer greater than 0, representing the space currently reserved as SLC cache in the RAM of the flash memory controller, in bytes.
[0085] Regarding the flash memory module status, input parameters may include, but are not limited to, the program / erase count and read disturb count of the flash memory module. The program / erase count of the flash memory module may be an integer greater than 0, representing the average number of times a physical block in the flash memory module is currently programmed or erased. The read disturb count of the flash memory module may be an integer greater than 0, representing the average number of times a physical block in the flash memory module is currently read.
[0086] The machine learning algorithm can first analyze the correlations between the multiple input parameters based on a large number of training samples, combine any two or more highly correlated input parameters into a single summed parameter, and generate a calculation formula for combining these input parameters. For each output result category, the machine learning algorithm can calculate the correlation direction (e.g., positive or negative correlation) and contribution (i.e., coefficient) of each input parameter to that category's output result based on a large number of training samples, and generate one or more calculation formulas that incorporate the correlation direction and contribution of all input parameters. The machine learning algorithm collects the calculation formulas used to generate output results for all categories to form a candidate prediction model. The machine learning algorithm can repeatedly generate candidate prediction models until the error estimate of the candidate prediction model is lower than the expected level. The error estimate can be, for example, mean squared error (MSE), mean absolute error (MAE), mean squared logarithmic error (MSLE), etc. The candidate prediction model with an error estimate lower than the expected level is output as the final prediction model.
[0087] The prediction model generated by the training server can be multi-class logistic regression, multi-class artificial neural network, clustering, multi-class decision forest, or other similar but different models. Because this prediction model is generated by a machine learning algorithm based on a large number of training samples and is not limited to the specific characteristics of the device, it can be universally applied to different types of devices.
[0088] refer to Figure 6 Schematic diagram of the operation of the artificial intelligence engine. An artificial intelligence engine 135 is provided within the flash memory controller 130. The artificial intelligence engine 135 can be implemented as an ASIC or program code that can be loaded and executed by the processing unit 134 and includes a prediction model generated by the training server. The flash memory controller 130 also includes registers 630 that store the values of first-category parameters 655, second-category parameters 675, and third-category parameters 695, providing access for the artificial intelligence engine 135. In other embodiments, RAM 136 can be configured with space to store the values of first-category parameters 655, second-category parameters 675, and third-category parameters 695, allowing the artificial intelligence engine 135 to read these parameter values from specific addresses within RAM 136. For details on the first-category parameters 655, refer to the input parameters for input / output communication between the host and device described above. For details on the second-category parameters 675, refer to the input parameters for the software and firmware status of the flash memory controller described above. For details on the third-category parameters 695, refer to the input parameters for the flash memory module status described above.
[0089] When executing the FTL 610, the processing unit 134 continuously monitors the commands and arguments 650 exchanged between the host 110 and the flash controller 130 via the host interface 131, generates values for first-category parameters 655, and stores the values of the first-category parameters 655 in registers 630 or designated addresses in the RAM 136. While executing host commands and / or background operations, the FTL 610 continuously updates the flash controller state 670 stored in the RAM 136, generates values for second-category parameters 675, and stores the values of the second-category parameters 675 in registers 630 or designated addresses in the RAM 136. Furthermore, while executing host commands and / or background operations, the FTL 610 continuously updates the NAND state 690 stored in the RAM 136, generates values for third-category parameters 695, and stores the values of the third-category parameters 695 in registers 630 or designated addresses in the RAM 136. Background operations may include garbage collection (GC) processing, wear leveling processing, read regeneration / refresh processing, and the like.
[0090] The artificial intelligence engine 135 reads the values of the first parameter 655, the second parameter 675, and the third parameter 695, which are updated in real time by the FTL 610, from the register 630 or the specified address in the RAM 136. Using a default prediction model, the engine calculates multiple-class prediction results 635 based on the values of the parameters 655, 675, and 695. The specific contents correspond to the multiple-class output results used by the training server as described above. In some embodiments, the artificial intelligence engine 135 may write the multiple-class prediction results 635 to the register 630. In other embodiments, the artificial intelligence engine 135 may write the multiple-class prediction results 635 to the specified address in the RAM 136. The FTL 610 may retrieve the multiple-class prediction results 635 from the register 630 or the specified address in the RAM 136 and adjust the settings of the flash memory controller 130 accordingly to improve device-side performance.
[0091] refer to Figure 7 The flowchart of the performance enhancement method based on the artificial intelligence engine is shown. This method is implemented by the processing unit 134 when loading and executing the FTL program code. This method is repeatedly executed in a loop to continuously adjust the settings of specific processing based on the real-time multi-class prediction results generated by the artificial intelligence engine 135. The details are as follows:
[0092] Step S710: Obtain multi-class prediction results from the artificial intelligence engine 135. In some embodiments, the artificial intelligence engine 135 continuously updates the multi-class prediction results 635 in the register 630 or at a specified address in the RAM 136, and the FTL reads the multi-class prediction results 635 from the register 630 or the specified address in the RAM 136. In other embodiments, the FTL queries the artificial intelligence engine 135, causing the artificial intelligence engine 135 to respond with the multi-class prediction results 635 to the FTL.
[0093] Step S730: Adjust the settings of specific processes based on the multiple prediction results 635. These processes include but are not limited to GC, wear leveling, automatic write acceleration, read regeneration / refresh, power saving mode, and power throttling.
[0094] In some embodiments, reference is made to Figure 8 The artificial intelligence engine 135 generates prediction results of the host application identifier 810 , host performance identifier 830 , GC recovery type, and foreground GC 851 and background GC 855 at a certain time point based on the values of the input parameters 655 , 675 , and 695 .
[0095] In use case 881, the prediction results indicate that the currently executing host application is office software, and the busyness level between the host and device is low, so it is recommended to enable both foreground and background GC. In addition to enabling foreground and background GC based on the prediction results, FTL can also set the execution time of each foreground and background GC batch to a shorter time based on the currently executing host application and the busyness level between the host and device.
[0096] Foreground GC processing involves interleaving multiple batches of GC operations during the execution of host commands to free up more available space in the flash memory module 150. Background GC processing involves executing one or more batches of GC operations while the flash memory controller 130 is in power saving mode to free up more available space in the flash memory module 150.
[0097] In use case 882, the prediction indicates that the currently executing host application is a game, and the busyness between the host and device is high, so both foreground and background GC are recommended to be enabled. FTL not only enables foreground and background GC based on the prediction, but also sets a longer execution time for each foreground and background GC batch.
[0098] In use case 883, the prediction results indicate that the host application currently being executed is a stress test, and the traffic level between the host and device is high. Therefore, it is recommended to disable foreground GC and enable background GC. FTL not only disables foreground GC and enables background GC based on the prediction results, but also sets a shorter execution time for each background GC batch.
[0099] In use case 884, the prediction results indicate that the currently executing host application is an audio / video player, and the busyness level between the host and device is low, so both foreground and background GC are recommended to be enabled. FTL not only enables foreground and background GC based on the prediction results, but also sets the execution time of each foreground and background GC batch to a shorter time.
[0100] In use case 885, the prediction results indicate that the currently executing host application is a web browser, and the busyness level between the host and device is medium. Therefore, it is recommended to enable both foreground and background GC. FTL not only enables foreground and background GC according to the prediction results, but also sets the execution time of each foreground GC batch to a shorter time and the execution time of each background GC batch to a medium time.
[0101] In other embodiments, the FTL resets the space reserved for the SLC cache in the RAM 136 with reference to the prediction result of the automatic write acceleration. The flash memory controller 130 can start the automatic write acceleration process to accelerate the execution efficiency of the host write command. In the automatic acceleration process, the processing unit 134 allocates space for the SLC cache in the RAM 136 for storing the user data to be written. Once the user data to be written by the host write command has been successfully stored in the SLC cache in the RAM 136, the processing unit 134 replies to the host end 110 through the host interface 131 that the host write command has been successfully executed. Until the default condition is detected, the processing unit 134 drives the flash memory interface 139 to write the user data in the SLC cache in the RAM 136 to the specified physical address of the flash memory module 150.
[0102] In other embodiments, the FTL resets the thresholds of the program / erase count and the read disturb count respectively based on the prediction results of the wear leveling strategy and the read regeneration / refresh strategy.
[0103] Flash memory controller 130 can initiate wear leveling to even out the wear of super blocks in flash memory module 150, thereby extending the lifespan of flash memory module 150. Flash memory controller 130 continuously calculates the program / erase count for each super block. Once processing unit 134 detects that the program / erase count for any data block or system block exceeds a threshold, it initiates wear leveling to migrate user data or management information from that data block or system block to the current block.
[0104] Flash memory controller 130 can initiate a read regeneration / refresh process to even out the read load of super-blocks in flash memory module 150, thereby extending the lifespan of flash memory module 150. Flash memory controller 130 continuously calculates a read disturb count for each super-block. Once processing unit 134 detects that the read disturb count for any data block or system block exceeds a threshold, it initiates a read regeneration / refresh process to migrate user data or management information from that data block or system block to the current block.
[0105] In some other embodiments, the FTL refers to the prediction result during the power saving mode entry and allows the flash memory controller 130 to enter the power saving mode for a recommended period of time.
[0106] In some other embodiments, the FTL adjusts the operating clock of the flash memory controller 130 to a specified level based on the power throttling prediction result.
[0107] In other embodiments, the FTL adjusts the length of the data buffer in the RAM 136 based on the prediction result of the waiting time of the command continuity, so that the data buffer can store host commands of more than a specified number of seconds.
[0108] In some other embodiments, the FTL refers to the prediction result of the low-density parity check throughput and drives the flash memory interface 139 to change the length of the LDPC generated according to the user data.
[0109] Step S750: Detecting that a specific condition is met. In some embodiments, after the adjustment in step S730 is completed, the FTL may start a timer to count a period of time, such as n seconds, where n is a floating point number greater than 0. Once the timer has counted the period of time, it sends a signal to the FTL indicating that the condition is met.
[0110] Although the present invention is illustrated and described herein with reference to specific embodiments, the present invention is not intended to be limited to the details shown. On the contrary, various modifications may be made to the details within the scope and equivalents of the claims without departing from the present invention. It should be understood that the above description is an illustration of the present invention and should not be construed as limiting the present invention. Various modifications, applications, and / or combinations of the embodiments may be envisioned by those of ordinary skill in the art without departing from the scope of the present invention as defined by the claims.
[0111] Those skilled in the art will readily appreciate that the present invention discussed above may be implemented using different configurations of hardware components than those disclosed. Thus, while the present invention has been described based on these preferred embodiments, certain modifications, variations, and alternative configurations will be apparent to those skilled in the art and are within the scope of the present invention.
[0112] It must be understood that the words "comprise", "include", etc. used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, parts and / or components, but do not exclude the addition of more technical features, values, method steps, operation processes, components, parts, or any combination of the above.
[0113] The terms "first", "second", "third", etc. used in the present invention are used to modify the components in the claims and are not used to indicate a priority order or a precedence relationship between them, or that one component precedes another, or the temporal order of executing method steps. They are only used to distinguish components with the same name.
[0114] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and intervening components may be present. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner, for example, "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.
[0115] The word "device" or "module" is not limited to one or a specific number of physical objects (e.g., a smart mobile phone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some of the functions of the present invention in this disclosure. Although the description and examples use the word "device" or "module" to describe various aspects of the present disclosure, the word "device" or "module" is not limited to a specific configuration, type, or number of objects. In addition, the word "system" or "module" is not limited to multiple components or a specific direction. For example, a system can be implemented on one or more printed circuit boards or other substrates and can have movable or static components. Although the description and examples use the word "system" to describe various aspects of the present invention in this disclosure, the word "system" is not limited to a specific configuration, type, or number of objects.
[0116] Specific details are provided in the above description to assist in a thorough understanding of various inventive aspects. However, it will be understood by those skilled in the art that these aspects may be practiced in the absence of these specific details. To enable clarity of explanation, in some instances, the present technology may be presented as comprising separate functional blocks comprising devices, device components, steps or subroutines embodied in methods of software, or a combination of hardware and software. Other additional components other than those shown in the figures and / or described herein may also be used. For example, circuits, systems, networks, processes, and other components may be displayed as components in block diagram form to avoid obscuring these aspects with unnecessary details. In other instances, to avoid obscuring these aspects with unnecessary details, known circuits, processes, algorithms, structures, and techniques may be displayed without unnecessary details.
[0117] Some aspects may be described herein as processes or methods, which may be shown as flow charts, data flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as sequential processes, multiple operations may be performed in parallel or simultaneously. Furthermore, the order of the operations may be rearranged. A process terminates when the operations are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.
[0118] All or part of the steps in the method described in the present invention can be implemented by a computer program, such as a firmware translation layer (FTL) in the device end, a driver for specific hardware, etc. In addition, it can also be implemented in other types of programs as shown above. Those skilled in the art can write the method of the embodiment of the present invention into program code, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable storage medium, or it can be placed on a network server that can be accessed through a network (e.g., the Internet, or other appropriate media).
[0119] Computer-readable storage media include volatile and non-volatile, removable and non-removable media that implement the storage of information, such as computer-readable instructions, data structures, program modules, or other data, by any method or technology. Computer-readable storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage media, magnetic cards, magnetic tape, hard disk or other magnetic storage media, or other carriers that can be used to store information required and accessed by the instruction execution system. It should be noted that the computer-readable storage medium can be paper or other suitable media for printing program code so that the program code can be obtained electronically, such as by optically scanning the paper or other media, and then, if necessary, compiled, interpreted or processed in other suitable ways, and then stored in the memory of the electronic device.
[0120] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits, field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor may be configured to perform any of the techniques described in the disclosure. A general-purpose processor may be a microprocessor; however, in an alternative embodiment, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors with a DSP core, or any other similar configuration. Accordingly, the term "processor" as used herein may represent any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counting described herein.
[0121] The various illustrative logic blocks, modules, engines, circuits, and algorithmic steps described in conjunction with the inventive aspects disclosed herein may be implemented as electronic hardware, computer software, firmware, or any combination thereof. In order to clearly represent the interchangeability of hardware and software, various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above in terms of their functions. Whether these functions are to be implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the entire system. Those of ordinary skill in the art may implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be interpreted as departing from the scope of this application.
[0122] Although Figures 1 to 3 、 Figure 6 The components described above are included in the invention, but it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention. Figure 7 The flowchart is executed in the specified order. However, those skilled in the art may modify the order of these steps without violating the spirit of the invention, provided that the same effect is achieved. Therefore, the present invention is not limited to the above-described order. In addition, those skilled in the art may also combine several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereby.
[0123] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Those skilled in the art may make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the content defined in the claims of this application.
Claims
1. A performance improvement method, implemented by a processing unit when loading and executing program code of a firmware translation layer, wherein: The flash memory controller includes the processing unit and the artificial intelligence engine, and the flash memory controller is coupled to the host and the flash memory module. The performance improvement method includes: generating a value of a first type of parameter according to commands and arguments exchanged between the host and the flash memory controller; generating a value of a second parameter according to software and firmware status of the flash memory controller; generating a value of a third parameter based on the state of the flash memory module, so that the prediction model running in the artificial intelligence engine can generate multiple types of prediction results based on the values of the first parameter, the second parameter, and the third parameter, wherein the training server generates the prediction model based on training data using a machine learning algorithm; and The settings of the processes running in the flash memory controller are adjusted based on the prediction results of the multiple categories.
2. The performance improvement method according to claim 1, wherein: The artificial intelligence engine is a dedicated integrated circuit.
3. The performance improvement method according to claim 1, wherein: The artificial intelligence engine is a program code that can be loaded and executed by the processing unit.
4. The performance improvement method according to claim 3, wherein: Also includes: receiving an artificial intelligence engine update command and an updated program code from the host; as well as The program code of the artificial intelligence engine is replaced with the updated program code, wherein the updated program code includes the latest prediction model.
5. The performance improvement method according to claim 1, wherein: The prediction model is multi-class logistic regression, multi-class neural network, clustering or multi-class decision forest.
6. The performance improvement method according to claim 1, wherein: The multiple categories of prediction results include host application identification, host performance identification, foreground garbage collection and background garbage collection. The performance improvement method includes: Setting the execution time of each batch of foreground garbage collection according to the host application identifier, the host performance identifier, and the predicted result of foreground garbage collection; and The execution time of each batch of background garbage collection is set according to the host application identifier, the host performance identifier, and the predicted result of the background garbage collection.
7. The performance improvement method according to claim 1, wherein: The multiple types of prediction results include automatic write acceleration, and the performance improvement method includes: Based on the prediction result of the automatic write acceleration, the space reserved for cache in the random access memory is reset for the host write command.
8. The performance improvement method according to claim 1, wherein: The multiple types of prediction results include a wear averaging strategy, and the performance improvement method includes: The threshold of the program / erase count is reset according to the prediction result of the wear leveling strategy.
9. The performance improvement method according to claim 1, wherein: The multiple types of prediction results include read regeneration / refresh strategies, and the performance improvement method includes: The threshold of the read disturb count is reset according to the prediction result of the read regeneration / refresh strategy.
10. The performance improvement method according to claim 1, wherein: The plurality of prediction results include a power saving mode entry period, and the performance improvement method includes: According to the prediction result of the power saving mode entry period, the flash memory controller is allowed to enter the power saving mode for a specified period of time.
11. The performance improvement method according to claim 1, wherein: The multiple types of prediction results include power throttling, and the performance improvement method includes: The operating clock of the flash memory controller is adjusted according to the prediction result of the power throttling.
12. A computer-readable storage medium for storing program code that can be executed by a processing unit, characterized in that: When the program code is executed by the processing unit, the performance improvement method according to any one of claims 1 to 11 is implemented.
13. A performance enhancement device, provided in a flash memory controller, wherein: The flash memory controller is coupled to the host and the flash memory module, and the performance enhancement device includes: Artificial Intelligence Engine; and A processing unit is coupled to the artificial intelligence engine and is configured to: generate values of first-category parameters based on commands and arguments exchanged between the host and the flash memory controller; generate values of second-category parameters based on the software and firmware status of the flash memory controller; and generate values of third-category parameters based on the status of the flash memory module, so that the prediction model running in the artificial intelligence engine can generate multiple types of prediction results based on the values of the first-category parameters, the second-category parameters, and the third-category parameters, wherein a training server uses a machine learning algorithm to generate the prediction model based on training data; and adjust the settings of the processing running in the flash memory controller based on the multiple types of prediction results.
14. The performance enhancement device according to claim 13, wherein: The artificial intelligence engine is a dedicated integrated circuit.
15. The performance enhancement device according to claim 13, wherein: The artificial intelligence engine is a program code that can be loaded and executed by the processing unit.
16. The performance enhancement device according to claim 15, wherein: The processing unit is configured to: receive an artificial intelligence engine update command and an updated program code from the host side; and replace the program code of the artificial intelligence engine with the updated program code, wherein the updated program code includes the latest prediction model.
17. The performance enhancement device according to claim 13, wherein: The prediction model is multi-class logistic regression, multi-class neural network, clustering or multi-class decision forest.
18. The performance enhancement device according to claim 13, wherein: The plurality of prediction results include a host application identifier, a host performance identifier, a foreground garbage collection, and a background garbage collection, and the processing unit is configured to: set an execution time of each batch of foreground garbage collection according to the host application identifier, the host performance identifier, and the prediction result of the foreground garbage collection; And the execution time of each batch of background garbage collection is set according to the host application identifier, the host performance identifier, and the prediction result of the background garbage collection.
19. The performance enhancement device according to claim 13, wherein: The multiple types of prediction results include automatic write acceleration, and the processing unit is configured to reallocate space reserved for cache in a random access memory for a host write command based on the prediction result of the automatic write acceleration.
20. The performance enhancement device according to claim 13, wherein: The plurality of prediction results include a wear leveling strategy, and the processing unit is configured to reset a threshold of a program / erase count according to the prediction result of the wear leveling strategy.
21. The performance enhancement device according to claim 13, wherein: The plurality of prediction results include read regeneration / refresh strategies, and the processing unit is configured to reset a threshold of a read disturbance count according to the prediction results of the read regeneration / refresh strategies.
22. The performance enhancement device according to claim 13, wherein: The plurality of prediction results include power saving mode entry periods, and the processing unit is configured to enable the flash memory controller to enter the power saving mode for a specified period of time according to the prediction result of the power saving mode entry period.
23. The performance enhancement device according to claim 13, wherein: The multiple types of prediction results include power throttling, and the processing unit is configured to adjust the operating clock of the flash memory controller according to the prediction result of the power throttling.
24. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processing unit, the performance improvement method according to any one of claims 1 to 11 is implemented.