A method for reading and writing NAND flash data, a computer device and a storage medium

Abstract

The embodiment of the application provides a NAND Flash data reading and writing method, a computer device and a storage medium, the method comprises the following steps: firstly receiving a write request of original data; obtaining ECC check information according to the original data, performing randomization processing on the ECC check information to obtain target data; writing the target data into a NAND Flash page; reading data of the NAND Flash page to an ECC decoding unit; inputting a randomization seed corresponding to the ECC check information into the ECC decoding unit to obtain the original data. Through the randomization processing on the ECC check information, the randomization degree of the NAND Flash data is improved, the reliability of the read and write data is improved, and the stability of the NAND Flash storage system is significantly improved.

Description

Technical Field

[0001] This application relates to the field of NAND Flash data reading and writing technology, and in particular to a method for reading and writing NAND Flash data, a computer device, and a storage medium. Background Technology

[0002] In related technologies, with the iterative upgrades of NAND Flash products, especially the latest QLC products, there are higher requirements for error correction capabilities. At the same time, the page size is gradually increasing, such as the known spare area QLC NAND Flash with a size of nearly 2800 bytes (the purpose of which is to allow the spare area to accommodate more ECC check information to bring higher error correction capabilities). The impact of this is that, according to current application methods, the proportion of non-randomized data in the data written to NAND Flash has increased significantly, and it is more difficult to meet the randomization indicators required by the product. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for reading and writing NAND Flash data, a computer device, and a storage medium, aiming to improve the reliability of data reading and writing and enhance the stability of the NAND Flash storage system.

[0004] In a first aspect, embodiments of this application provide a method for reading and writing NAND Flash data, including:

[0005] Receive write requests for raw data;

[0006] Based on the original data, ECC verification information is obtained, and the ECC verification information is randomized to obtain target data;

[0007] Write the target data into the NAND Flash page;

[0008] The data of the NAND Flash Page is read into the ECC decoding unit;

[0009] The randomization seed corresponding to the ECC verification information is input into the ECC decoding unit to obtain the original data.

[0010] According to some embodiments of this application, the step of obtaining ECC verification information from the original data and randomizing the ECC verification information to obtain target data includes:

[0011] The original data is randomized to obtain the first data;

[0012] The first data is ECC encoded to obtain ECC verification information;

[0013] The ECC verification information is randomized to obtain the second data;

[0014] The target data is obtained based on the first data and the second data.

[0015] According to some embodiments of this application, the step of obtaining ECC verification information from the original data and randomizing the ECC verification information to obtain target data further includes:

[0016] The original data is ECC encoded to obtain ECC verification information;

[0017] The target data is obtained by randomizing the ECC verification information and the original data.

[0018] According to some embodiments of this application, the step of inputting the randomization seed corresponding to the ECC verification information into the ECC decoding unit to obtain the original data includes:

[0019] The randomized seed corresponding to the ECC verification information is input into the ECC decoding unit;

[0020] The original data is obtained by determining the LLR sign bit of the bit information of the ECC decoding unit.

[0021] According to some embodiments of this application, the step of inputting the randomization seed corresponding to the ECC verification information into the ECC decoding unit to obtain the original data includes:

[0022] The randomized seed corresponding to the ECC verification information is input into the ECC decoding unit;

[0023] The third data is obtained by determining the randomization seed and the LLR sign bit corresponding to the ECC check information;

[0024] The third data is derandomized to obtain the original data.

[0025] According to some embodiments of this application, writing the target data into a NAND Flash page includes:

[0026] Get the list of free pages in NAND Flash;

[0027] Select a target page from the list of free pages according to a preset write strategy;

[0028] Before writing the target data to the target page, the target page is erased.

[0029] If the erasure is successful, the target data is written to the NAND Flash page according to the target page.

[0030] According to some embodiments of this application, reading the data of the NAND Flash Page into the ECC decoding unit includes:

[0031] Obtain the read request for the original data;

[0032] The corresponding NAND Flash page is obtained based on the storage address of the original data;

[0033] The data of the target page in the NAND Flash page is read into the ECC decoding unit;

[0034] The read data is obtained by ECC decoding through the ECC decoding unit;

[0035] The read data is verified using a CRC check algorithm. If the verification fails, the data of the NAND Flash Page is read again.

[0036] According to some embodiments of this application, the step of determining the third data by using the randomization seed and the LLR sign bit corresponding to the ECC check information includes:

[0037] The LLR symbol with the first randomized bit is flipped according to the randomization seed to obtain the third data.

[0038] Secondly, embodiments of this application provide a computer device, including:

[0039] At least one memory;

[0040] At least one processor;

[0041] At least one computer program;

[0042] The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the NAND Flash data read / write method described in the first aspect above.

[0043] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program for causing a computer to execute the NAND Flash data reading and writing method described in the first aspect.

[0044] The technical solution according to the embodiments of this application has at least the following beneficial effects: First, a write request for the original data is received;

[0045] ECC verification information is obtained from the original data. This ECC verification information is then randomized to obtain target data. The target data is written to a NAND Flash page. The data from the NAND Flash page is read into the ECC decoding unit. The randomization seed corresponding to the ECC verification information is input into the ECC decoding unit to obtain the original data. This embodiment improves the randomization degree of NAND Flash data reading and writing by randomizing the ECC verification information, thereby improving the reliability of data reading and writing and significantly enhancing the stability of the NAND Flash storage system.

[0046] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0047] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0048] Figure 1 This is a flowchart illustrating a method for reading and writing NAND Flash data according to an embodiment of this application;

[0049] Figure 2 This is a schematic diagram of the process for obtaining target data provided in one embodiment of this application;

[0050] Figure 3 This is a schematic diagram of the process for obtaining target data provided in another embodiment of this application;

[0051] Figure 4 This is a schematic diagram of the process for obtaining raw data provided in one embodiment of this application;

[0052] Figure 5 This is a schematic diagram of the process for obtaining raw data provided in another embodiment of this application;

[0053] Figure 6 This is a schematic diagram of the process of writing target data into a NAND Flash page according to an embodiment of this application;

[0054] Figure 7 This is a schematic diagram of a process for reading data from a NAND Flash Page according to an embodiment of this application;

[0055] Figure 8 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. Detailed Implementation

[0056] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0057] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0059] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0060] First, let's analyze some of the terms used in this application:

[0061] ECC (Error Correction Code) decoding: refers to using redundant information to detect and correct errors that occur during data transmission or storage. Redundant coding: adding check bits (such as Hamming code, Reed-Solomon code, etc.) to the original data to form error-correctable codewords; Error detection and location: calculating the syndrome through the check relation to locate the error position; Error correction: reversing or correcting the error bits according to the error position and type.

[0062] LLR sign bit (Log-Likelihood Ratio Sign Bit): A binary flag used in communication systems to indicate whether the value of the log-likelihood ratio (LLR) is positive or negative.

[0063] NAND Flash (Non-Volatile Memory, NVM): Based on the floating-gate MOSFET structure, it achieves long-term data storage through charge storage, requiring no continuous power supply. Its name comes from its circuit structure, which is a NAND gate logic array, and it is widely used in solid-state drives (SSDs), USB flash drives, mobile phone storage, and other fields.

[0064] The method for reading and writing NAND Flash data provided in this application is specifically illustrated through the following embodiments.

[0065] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0066] Foundational technologies for artificial intelligence generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies mainly encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0067] The NAND Flash data reading and writing method provided in this application relates to the field of data monitoring and extraction technology. This method can be applied to a terminal, a server, or software running on either the terminal or the server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can implement the NAND Flash data reading and writing method, but is not limited to the above forms.

[0068] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0069] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent will be obtained first. Furthermore, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user will be obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent will the necessary user-related data for the normal operation of the embodiments of this application be obtained.

[0070] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for reading and writing NAND Flash data according to an embodiment of this application. The method for reading and writing NAND Flash data according to an embodiment of this application includes, but is not limited to, steps S110 to S150, which will be described in turn below.

[0071] Step S110: Receive the write request for the original data;

[0072] Step S120: Obtain ECC verification information based on the original data, and randomize the ECC verification information to obtain the target data;

[0073] Step S130: Write the target data into the NAND Flash page;

[0074] Step S140: Read the data from the NAND Flash Page into the ECC decoding unit;

[0075] Step S150: Input the randomization seed corresponding to the ECC verification information into the ECC decoding unit to obtain the original data.

[0076] In one embodiment, a write request for raw data can be sent from the host to the storage controller via an interface such as PCIe, SATA, or USB. The request includes the raw data to be stored (user file data, system logs, etc.) and data storage address information. Upon receiving the request, the storage controller verifies its validity, including checking whether the data format conforms to the protocol specification and whether the storage address is not occupied. If the verification is successful, the data processing flow begins.

[0077] In one embodiment, the storage controller integrates an ECC encoding unit. First, the original data undergoes ECC encoding. The ECC check information is generated using internationally recognized BCH or LDPC encoding algorithms. During encoding, the check bit length is determined based on the length of the original data to automatically correct single-bit errors and detect multi-bit errors. After generating the ECC check information, the storage controller calls a randomization module to encrypt it. The storage controller has a built-in pseudo-random number generator that generates a unique randomization seed based on the storage address of the original data, the current timestamp, or a hardware feature code. The ECC check information and the randomization seed are XORed bitwise to obtain the randomized check information. The target data is composed of the original data and the randomized check information concatenated in the format "original data + randomized check information," where the starting address of the randomized check information is at the end of the original data for easy separation during subsequent reading.

[0078] In one embodiment, the NAND Flash memory cell uses pages as the basic writing unit. Each page contains a data area and a free area. In this embodiment, the target data is written to the data area. The memory controller sends a write command to the NAND Flash through a NAND interface (such as an ONFI protocol interface). The command contains the target page address and the target data. During the write process, the memory controller performs level conversion on the target data (converting the digital signal into a voltage signal recognizable by the NAND Flash) and stores the data in the floating gate transistor through charge injection. Simultaneously, the randomization seed is stored in the OOB area of ​​the NAND Flash or in the non-volatile register of the memory controller. An association mapping is established between the seed and the page address of the target data to ensure that the corresponding seed can be accurately called during subsequent reads. When the host sends a data read request, the memory controller locates the target NAND Flash page according to the address information in the request. The target data (including the original data and randomization verification information) stored in the page is read into the memory controller's cache unit through a read command. During the read process, the memory controller performs analog-to-digital conversion on the voltage signal output by the NAND Flash to restore it to the target data in digital signal form. The caching unit separates the target data into raw data segments and randomized verification information according to a preset format. The raw data segments are temporarily stored, while the randomized verification information is transmitted to the ECC decoding unit for processing.

[0079] In one embodiment, the storage controller retrieves the corresponding randomization seed from the OOB area or register based on the target page address. The seed is then input into the ECC decoding unit. The decoding unit first performs inverse randomization processing on the randomization verification information, using an XOR operation to restore the original ECC verification information from the randomization verification information and the seed (the inverse operation formula is "original verification information = randomization verification information ⊕ seed"). Subsequently, the ECC decoding unit uses the original ECC verification information to perform error correction operations on the original data segments: by comparing the redundancy relationship between the data segments and the verification information, errors generated during data transmission or storage are detected and corrected. After error correction is completed, the decoding unit outputs the complete original data, which the storage controller feeds back to the host via an interface, completing the data reading process.

[0080] It is worth noting that this embodiment improves the randomization of data written to NAND Flash by randomizing the ECC verification information, thereby improving the uniformity of charge distribution in each cell of NAND Flash and reducing inter-cell crosstalk, thus improving the reliability of written data and significantly improving the stability of NAND Flash storage system.

[0081] Please see Figure 2 , Figure 2This is a schematic diagram of the process for obtaining target data provided in one embodiment of this application; regarding the above step S120, obtaining ECC verification information based on the original data, and randomizing the ECC verification information to obtain target data, including but not limited to steps S210 to S240, each step will be described in turn below.

[0082] Step S210: Randomize the original data to obtain the first data;

[0083] Step S220: Encode the first data using ECC to obtain ECC verification information;

[0084] Step S230: Randomize the ECC verification information to obtain the second data;

[0085] Step S240: Obtain the target data based on the first data and the second data.

[0086] In one embodiment, randomization involves shuffling and transforming the original data using a preset random algorithm, resulting in data with a random distribution. The random algorithm can be a linear feedback shift register (LFSR) algorithm. First, the length and feedback coefficient of the LFSR are determined, and the LFSR state is initialized based on the length of the original data. Then, each bit of the original data is XORed with a bit output by the LFSR to obtain the first randomized data. For example, if the original data is "101010" and the initial LFSR state is "110011", after the XOR operation, the first data is "011001". This randomization process disrupts the regularity of the original data, reduces the possibility of illegal parsing, and lays the foundation for subsequent encoding processing.

[0087] In one embodiment, the ECC encoding algorithm can be a Hamming code encoding algorithm. Hamming code is a linear block code that can detect two-bit errors and correct one-bit errors. For the first data, the corresponding check bits are calculated according to the Hamming code encoding rules. The check bits are added to the first data to form encoded data containing data bits and check bits, where the check bits are the ECC check information. For example, if the first data is 8 bits "01100101", according to the Hamming code encoding rules, a 4-bit check bit "1011" is calculated, and the ECC check information is "1011". The length of the ECC check information is determined according to the length of the first data and the type of ECC encoding algorithm used to ensure that errors occurring in the first data during transmission and storage can be effectively detected and corrected.

[0088] In one embodiment, step S230 uses the same LFSR algorithm as step S210, requiring the LFSR state to be reinitialized to avoid any correlation with the randomization process in step S210. The ECC verification information is "1011", and the reinitialized LFSR state is "001101". After XOR operation, the second data is "1000". By randomizing the ECC verification information, it is possible to prevent the ECC verification information from being stolen and used independently, thereby improving the security of the entire data processing process.

[0089] It should be noted that after obtaining the first and second data, they are combined according to a preset combination rule to obtain the target data. The combination rule can be to concatenate the first and second data sequentially, or to use a preset mapping relationship to mix and arrange them. If the first data is "01100101" and the second data is "1000", then the target data is "011001011000". The target data integrates the randomized original data and the randomized ECC check information, preserving the information of the original data while possessing error detection and correction capabilities. Furthermore, due to the two randomization processes, the confidentiality and anti-interference capabilities of the data are significantly improved.

[0090] Please see Figure 3 , Figure 3 This is a schematic diagram of the process for obtaining target data provided in another embodiment of this application; regarding the above step S120, obtaining ECC verification information based on the original data, and randomizing the ECC verification information to obtain target data, including but not limited to steps S310 to S320, each step will be described in turn below.

[0091] Step S310: Perform ECC encoding on the original data to obtain ECC verification information;

[0092] Step S320: Randomize the ECC verification information and the original data to obtain the target data.

[0093] In one embodiment, during the encoding process, the original data is divided into data blocks of a preset length. Each data block is 255 bytes long, of which 223 bytes are valid data and 32 bytes are ECC check information. The original data block is "00101101...11001010" (223 bytes), which, after Reed-Solomon encoding, generates 32 bytes of ECC check information "10010011...01101100". The ECC check information has a mathematical relationship with the original data block, and data integrity can be verified through a check formula.

[0094] In one embodiment, the 1024 bytes of original data are divided into four data blocks (each 256 bytes, of which 224 bytes are valid data). Using the Reed-Solomon (255, 223) encoding scheme, each data block generates 32 bytes of ECC checksum information, resulting in a total of 128 bytes of ECC checksum information. The four original data blocks are then concatenated with their corresponding ECC checksum information to form a combined data set of 1024 + 128 = 1152 bytes. The AES encryption module is initialized using a preset key to generate a random initialization vector. The combined data is then encrypted using CBC mode to obtain the 1152 bytes of target data.

[0095] Please see Figure 4 , Figure 4 This is a schematic diagram of the process for obtaining raw data provided in one embodiment of this application; regarding the above step S150 of inputting the randomization seed corresponding to the ECC verification information into the ECC decoding unit to obtain raw data, including but not limited to steps S410 to S420, each step will be described in turn below.

[0096] Step S410: Input the randomization seed corresponding to the ECC verification information into the ECC decoding unit;

[0097] Step S420: Determine the original data by using the LLR sign bit of the bit information of the ECC decoding unit.

[0098] In one embodiment, after the target data is transmitted to the receiving end or read from the storage medium, the randomization seed corresponding to the ECC verification information needs to be extracted from the target data first. The extraction process can be achieved by parsing the header information of the target data. The header of the target data has a reserved field for storing the randomization seed. The extracted randomization seed is input into the ECC decoding unit. The ECC decoding unit will perform derandomization processing on the received randomized ECC verification information according to the randomization seed to recover the original ECC verification information, providing an accurate verification basis for subsequent ECC decoding.

[0099] In one embodiment, after receiving the derandomized ECC check information and the corresponding data to be decoded, the ECC decoding unit performs soft-decision decoding on the data. The LLR sign bit is used to indicate the probability of each bit being "0" or "1", and the sign bit directly reflects the decision direction of the bit information. The ECC decoding unit calculates the LLR value of each bit information. The formula for calculating the LLR value is LLR = ln(P(bit = 1|r) / P(bit = 0|r)), where r is the received bit information. When the LLR sign bit is positive, it indicates that the bit information is "0"; when the LLR sign bit is negative, it indicates that the bit information is "1". During the decoding process, the ECC decoding unit combines the ECC check information to make a comprehensive judgment on the LLR sign bit. For bit information with errors, error correction is performed through the redundant check bits of the ECC check information, and finally the accurate original data is recovered.

[0100] Please see Figure 5 , Figure 5 This is a schematic diagram of the process for obtaining raw data provided in another embodiment of this application; regarding the above step S150 of inputting the randomization seed corresponding to the ECC verification information into the ECC decoding unit to obtain raw data, including but not limited to steps S510 to S520, each step will be described in turn below.

[0101] Step S510: Input the randomization seed corresponding to the ECC verification information into the ECC decoding unit;

[0102] Step S520: Determine the third data by using the randomization seed and the LLR sign bit corresponding to the ECC check information;

[0103] Step S530: Perform derandomization on the third data to obtain the original data.

[0104] In one embodiment, the LLR symbol with the first randomized bit is flipped according to the randomization seed to obtain the third data. The LLR symbol with the XOR bit (randomization bit) set to 1 is flipped, i.e., positive becomes negative and negative becomes positive. Before LDPC decoding, the ECC check information is preprocessed with "de-randomization". However, within the LDPC unit, this is manifested as using randomization information to perform the logical action of LLR symbol bit determination and flipping. After completing the above LLR symbol bit processing, conventional LDPC decoding (including hardware decoding and software decoding processes) is performed to obtain the third data. Then, the third data is de-randomized to finally obtain the original data.

[0105] In one embodiment, within the LDPC decoding unit, a determination module based on randomization information is constructed. This module traverses the LLR data of the ECC check information, checking the XOR bit (randomization bit) value bit by bit. When an XOR bit of 1 is detected, a sign-flipping logic is triggered, changing the LLR sign of that bit from positive to negative or vice versa; if the XOR bit is 0, the LLR sign remains unchanged. In conjunction with the LDPC decoding process: after processing the LLR sign bit, the processed data enters the LDPC hard and soft decoding processes. The hard decoding stage performs preliminary error correction based on the processed LLR information, while the soft decoding stage performs more refined probability iteration updates based on this, gradually approaching the correct data, and finally outputting the decoded third data. After obtaining the third data, an anti-randomization operation is performed on the third data using the randomization information according to a predefined anti-randomization algorithm in the storage system. If randomization is achieved through a specific XOR operation during writing, derandomization is restored through an inverse XOR operation, ultimately obtaining the original main area data for use by upper-layer applications or storage systems, completing the entire process of reading data from NAND Flash, correcting errors, and restoring the original data.

[0106] In one embodiment, when anomalies such as randomization information reading failure or sign bit flipping logic error occur, a default processing strategy can be set for randomization information reading failure. For sign bit flipping logic error, a self-detection module built into the decoding unit verifies the logical consistency of the data before and after sign bit processing in real time. If an anomaly is found, a retry or error reporting mechanism is triggered. To ensure the effectiveness of the processing flow, a verification module is built into the storage system. By writing known test data, a bit flipping scenario can be simulated to verify the accuracy of data recovery after logical processing by the LDPC decoding unit. The data recovery results in actual storage services are sampled and verified periodically, and the consistency between the original written data and the recovered data is compared to continuously optimize the processing logic, thereby ensuring the long-term stable and reliable operation of the system.

[0107] It should be noted that the ECC verification information was also randomized, which improved the randomness of the data written to NAND Flash, thereby improving the reliability of the written data.

[0108] Table 1 shows the bit flipping events that occur after data is read from NAND Flash:

[0109]

[0110] Table 1

[0111] The derandomized data after reading data from NAND Flash without bit flipping is shown in Table 2:

[0112]

[0113] Table 2

[0114] Please see Figure 6 , Figure 6 This is a schematic diagram of the process of writing target data into a NAND Flash page according to an embodiment of this application; the above step S130 of writing target data into a NAND Flash page includes, but is not limited to, steps S610 to S640, which will be described in turn below.

[0115] Step S610: Obtain the list of free pages in the NAND Flash;

[0116] Step S620: Select the target page from the list of free pages according to the preset write strategy;

[0117] Step S630: Before writing the target data to the target page, perform an erase operation on the target page;

[0118] Step S640: If erasure is successful, write the target data into the NAND Flashpage according to the target page.

[0119] In one embodiment, the page management module of the NAND Flash controller monitors the status of each page in real time and generates a list of free pages. The list includes information on multiple free pages, such as block10-page20 (85 erase / write cycles), block15-page10 (70 erase / write cycles), and block20-page5 (100 erase / write cycles). Using a wear leveling strategy, the average number of erase / write cycles for each block is calculated. Block15 has the lowest average number of erase / write cycles at 70. Therefore, page10 is selected as the target page from the free pages of block15. An erase command is sent to block15 to erase the block containing page10. After the erase process lasts 500 microseconds, the status register indicates that the erase is complete and error-free, indicating successful erasure. The processed target data is then transferred to the page buffer register, and a programming command and the address of page10 are sent to write the data to page10. After writing, the controller reads the data from page10 for ECC verification. If the verification result is correct, the data writing is complete. During subsequent data writing processes, the free page list is dynamically updated, and the writing strategy is automatically adjusted according to the device's operating status.

[0120] It is worth noting that by selecting the target page through the wear leveling strategy, the number of erases and writes of each storage block is more evenly distributed, avoiding premature damage of some blocks due to excessive erasure and writing, and significantly extending the lifespan of NAND Flash. The target page is erased before data is written, and data is only written after the erasure is successful, ensuring that the target page is in a clean initial state and reducing data write errors caused by incomplete erasure.

[0121] Please see Figure 7 , Figure 7 This is a schematic diagram of the process of reading data from a NAND Flash Page according to an embodiment of this application; regarding the above step S140 of reading data from the NAND Flash Page into the ECC decoding unit, including but not limited to steps S710 to S750, each step will be described in turn below.

[0122] Step S710: Obtain the read request for the raw data;

[0123] Step S720: Obtain the corresponding NAND Flash page based on the storage address of the original data;

[0124] Step S730: Read the data of the target page in the NAND Flash page into the ECC decoding unit;

[0125] Step S740: Obtain the read data by performing ECC decoding through the ECC decoding unit;

[0126] Step S750: Use the CRC check algorithm to check the read data. If the check fails, reread the data of the NAND Flash Page.

[0127] In one embodiment, when it is necessary to obtain raw data stored in NAND Flash, a raw data read request is sent to the data read control module. This read request includes relevant identification information of the raw data to be read, such as the data name and number, so that the data read control module can accurately identify the data to be read. After receiving the raw data read request, the data read control module finds the storage address of the raw data in the NAND Flash according to the pre-stored correspondence between raw data and storage addresses. Since NAND Flash data is stored in pages as the basic storage unit, the corresponding NAND Flash page can be determined based on the found storage address; this page is the storage unit containing the target raw data. After determining the corresponding NAND Flash page, the data read control module controls the NAND Flash read circuit to read the data of the target page from that NAND Flash page. The read data is transmitted to the ECC decoding unit, which performs subsequent error detection and correction preparation work on the data. After receiving the read data, the ECC decoding unit first verifies the data using a verification algorithm. The verification algorithm generates a checksum by performing polynomial operations on the data. This checksum is then compared to the original checksum generated during data storage. If they match, it indicates that no errors occurred during the data reading process, the verification is successful, and the data can be output normally for subsequent use. If they do not match, it indicates that an error occurred during the data reading process, and the verification fails. In this case, the data reading control module will control the reading circuit to reread the data of that NAND Flash Page and transmit it to the ECC decoding unit for verification again. If the verification still fails after multiple rereads and verifications, an error message will be issued.

[0128] This application also provides a computer device, which includes: at least one memory, at least one processor, and at least one computer program. The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the NAND Flash data read / write method of any of the above embodiments. This computer device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0129] See Figure 8 , Figure 8 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. The computer device includes:

[0130] The processor 810 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0131] The memory 820 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 820 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 820 and is called and executed by the processor 810 to execute the NAND Flash data read / write method of the embodiments of this application.

[0132] The input / output interface 830 is used to implement information input and output;

[0133] The communication interface 840 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0134] Bus 850 transmits information between various components of the device (e.g., processor 810, memory 820, input / output interface 830, and communication interface 840);

[0135] The processor 810, memory 820, input / output interface 830 and communication interface 840 are connected to each other within the device via bus 850.

[0136] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for reading and writing NAND Flash data.

[0137] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0138] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0139] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0140] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0142] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0143] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0144] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0145] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0146] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0147] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for reading and writing NAND Flash data, characterized in that, include: Receive write requests for raw data; Based on the original data, ECC verification information is obtained, and the ECC verification information is randomized to obtain target data; Write the target data into the NAND Flash page; The data of the NAND Flash page is read into the ECC decoding unit; The randomization seed corresponding to the ECC verification information is input into the ECC decoding unit to obtain the original data; The step of inputting the randomization seed corresponding to the ECC verification information into the ECC decoding unit to obtain the original data includes: The randomized seed corresponding to the ECC verification information is input into the ECC decoding unit; The LLR symbol with the first value bit of the randomization bit is flipped according to the randomization seed to obtain the processed data; The processed data is then subjected to LDPC decoding to obtain the third data; The third data is derandomized to obtain the original data.

2. The method according to claim 1, characterized in that, The step of obtaining ECC verification information based on the original data, and then randomizing the ECC verification information to obtain target data includes: The original data is randomized to obtain the first data; The first data is ECC encoded to obtain ECC verification information; The ECC verification information is randomized to obtain the second data; The target data is obtained based on the first data and the second data.

3. The method according to claim 1, characterized in that, The step of obtaining ECC verification information based on the original data, and randomizing the ECC verification information to obtain target data, further includes: The original data is ECC encoded to obtain ECC verification information; The target data is obtained by randomizing the ECC verification information and the original data.

4. The method according to claim 1, characterized in that, The step of writing the target data into the NAND Flashpage includes: Get the list of free pages in NAND Flash; Select a target page from the list of free pages according to a preset write strategy; Before writing the target data to the target page, the target page is erased. If the erasure is successful, the target data is written to the NAND Flash page according to the target page.

5. The method according to claim 1, characterized in that, The step of reading the data from the NAND Flash page into the ECC decoding unit includes: Obtain the read request for the original data; The corresponding NAND Flash page is obtained based on the storage address of the original data; The data of the target page in the NAND Flash page is read into the ECC decoding unit; The read data is obtained by ECC decoding through the ECC decoding unit; The read data is verified using a CRC check algorithm. If the verification fails, the data of the NAND Flash page is read again.

6. The method according to claim 1, characterized in that, The step of inputting the randomized seed corresponding to the ECC verification information into the ECC decoding unit to obtain the original data further includes: The randomized seed corresponding to the ECC verification information is input into the ECC decoding unit; The original data is obtained by determining the LLR sign bit of the bit information of the ECC decoding unit.

7. A computer device, characterized in that, include: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for causing a computer to perform the method as described in any one of claims 1 to 6.

Images