Method and system for optimizing computing performance of neural network based on on-chip storage

Abstract

The invention discloses a method for optimizing the computing performance of a neural network based on on-chip storage, which comprises the following steps: firstly, carrying out SPM space division according to the access characteristics of pulse input data, internal weight and external weight so as to improve the data utilization efficiency, then, carrying out batch processing on the computing process in the time step dimension so as to enable the task scheduling to be more balanced, and then, carrying out optimization on the computing performance of the neural network. According to the method, repeated transmission is reduced through one-time loading of internal weights, storage pressure is avoided through blocking loading of external weights according to needs, and finally, a continuous and stable neural network calculation process is constructed in combination with membrane potential updating and pulse output management. The method can be widely applied to scenes sensitive to computing resources and storage bandwidth, such as embedded AI chips and edge computing equipment. According to the method, the technical problems of unreasonable SPM space division and serious access conflict existing in an existing neural network calculation performance optimization method based on a hardware accelerator can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of neural network accelerated computing and edge artificial intelligence processing, and more specifically, relates to a method and system for optimizing neural network computing performance based on on-chip storage. Background Art

[0002] With the continuous development of artificial intelligence (AI) technology, neural network models have been widely used in a variety of fields, including image recognition, speech processing, and natural language understanding. In recent years, with the rapid adoption of edge computing and IoT devices, an increasing number of intelligent tasks have been delegated to end-user devices for processing. This computing approach can reduce data transmission costs, improve response speeds, and alleviate reliance on central computing resources. However, compared to traditional servers, edge devices are often limited by computing power, memory capacity, and power consumption. Especially in embedded systems, the limited on-chip resources make efficient and sustainable execution of neural network inference tasks extremely challenging. Therefore, optimizing neural network computing performance within resource-constrained conditions is of great practical significance.

[0003] In response to the above needs, researchers have proposed a variety of neural network computing performance optimization methods for resource-constrained platforms: the first is a neural network computing performance optimization method based on a block computing mechanism, which divides tasks in the neuron or time step dimensions to improve data parallelism and reuse rate; the second is a neural network computing performance optimization method based on a hardware accelerator, which improves the execution speed of the neural network through customized processing units and efficient storage access structures; the third is a neural network computing performance optimization method based on model optimization technology, which reduces storage occupancy and computing overhead through model optimization technologies such as neural network structure pruning and quantization compression, thereby adapting to the computing power level of edge devices; the above three methods have alleviated the resource pressure in edge computing to a certain extent and promoted the actual implementation of deep learning on the terminal side.

[0004] However, the above three neural network computing performance optimization methods all have some non-negligible defects:

[0005] First, although neural network performance optimization methods based on block computing mechanisms introduce task partitioning based on the neuron or time step dimensions, some methods still fail to implement effective block parallelization strategies during execution, ignoring the scheduling requirements for different computing dimensions (such as time steps and neurons), which limits the pipelining and concurrency of tasks.

[0006] Second, while neural network computing performance optimization methods based on hardware accelerators can improve execution speed, they generally lack refined management and dynamic scheduling of the on-chip system (Scratchpad Memory, or SPM) space. This makes it impossible to flexibly allocate storage resources based on the actual computing process, which can easily lead to space waste or access conflicts, affecting overall system efficiency.

[0007] Third, neural network computing performance optimization methods based on model optimization technology mainly focus on network structure compression and parameter simplification, but lack a unified optimization mechanism when loading pulse input data and weight data. Internal and external weights often use the same loading strategy, without fully considering their access frequency and data size differences, resulting in low loading efficiency.

[0008] Fourth, the three existing methods mentioned above do not fully consider the data update and storage switching mechanism during the calculation process, which leads to problems such as data interruption and repeated loading between multiple calculation batches, reducing the reasoning stability and real-time performance of neural networks on edge devices. Summary of the Invention

[0009] In response to the above defects or improvement needs of the prior art, the present invention provides a method and system for optimizing the computing performance of a neural network based on on-chip storage. Its purpose is to solve the problem that although the existing neural network computing performance optimization method based on the block computing mechanism introduces the task division in the dimension of neurons or time steps, some methods still fail to implement an effective block parallel strategy during execution, ignore the scheduling requirements for different computing dimensions (such as time steps, neurons, etc.), and limit the technical problems of task streamlining and concurrency, and the existing neural network computing performance optimization method based on hardware accelerators can improve the execution speed, but generally lacks the refined management and dynamic scheduling of the on-chip system space, and cannot flexibly allocate storage resources according to the actual computing process, which easily causes space waste or access conflicts, affecting the entire system. The technical problem of overall efficiency is that the existing neural network computing performance optimization method based on model optimization technology mainly focuses on network structure compression and parameter simplification, but lacks a unified optimization mechanism when loading pulse input data and weight data. Internal weights and external weights often adopt the same loading strategy, and their access frequency and data scale differences are not fully considered, resulting in low loading efficiency. The three existing optimization methods do not fully consider the data update and storage switching mechanism during the calculation process, resulting in data interruption and repeated loading between multiple calculation batches, which reduces the inference stability and real-time performance of neural networks on edge devices.

[0010] To achieve the above objectives, according to one aspect of the present invention, a method for optimizing neural network computing performance based on on-chip storage is provided, comprising the following steps:

[0011] (1) Obtaining the input scale parameters of the neural network model, including the amount of pulse input data, the internal weight dimension, the external weight dimension, the total number of neurons, the total number of time steps time_steps, and the input scale input_num of each time step, obtaining the data base address of the neural network model in the external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data, and setting a storage area for storing the pulse input data, the internal weight data, and the external weight data in the on-chip storage area of ​​the computing platform;

[0012] (2) respectively allocating the pulse input data storage area, the internal weight storage area, and the external weight storage area with a storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area, the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area, and the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area to the pulse input data storage area, the internal weight storage area, and the external weight storage area obtained in step (1);

[0013] (3) According to the total number of time steps time_steps and the input size input_num of each time step obtained in step (1), the time step division parameters for iterative control are obtained, including the time step size of each batch t_batch_size, the number of time step batches t_batch_num, and the tail time step size t_tail_size;

[0014] (4) Obtain the weight block parameters for scheduling based on the total number of neurons neuron_num obtained in step (1), including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size; the external weight block parameters include the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size;

[0015] (5) Obtaining the internal weight data from the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained in step (1), and writing the obtained internal weight data once into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2);

[0016] (6) Set counter cnt = 1;

[0017] (7) Determine whether the counter cnt is greater than the time step batch number t_batch_num obtained in step (3). If so, the process ends; otherwise, proceed to step (8).

[0018] (8) Obtain the offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data of the cnt-th time step in the external storage according to the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained in step (1) and the size t_batch_size of each batch of time steps obtained in step (3), read the pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the offset address, obtain the write address SPIKE_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area obtained in step (2) and the size t_batch_size of each batch of time steps obtained in step (3), and write the read pulse input data block SPIKE_WRITE_BLOCK to the write address;

[0019] (9) Obtain the offset address IN_WEIGHT_OFFSET_ADDR of the internal weight storage area at the cnt-th time step according to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2) and the internal weight block size in_n_batch_size obtained in step (4), obtain the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size from the offset address, perform weight calculation on the pulse input data block SPIKE_WRITE_BLOCK and the internal weight data block IN_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_1, perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step;

[0020] (10) According to the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data in the external storage obtained in step (1) and the external weight block size ex_n_batch_size obtained in step (4), the offset address EX_WEIGHT_OFFSET_ADDR of the external weight data of the cnt-th time step in the external storage is obtained, and the external weight data block EX_WEIGHT_BLOCK of the size ex_n_batch_size is read from the offset address. According to the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area obtained in step (2) and the external weight block size ex_n_batch_size obtained in step (4), the write address EX_WEIGHT_WRITE_ADDR of the cnt-th time step is obtained, and the external weight data block EX_WEIGHT _BLOCK is written to the write address, and the pulse input data block SPIKE_WRITE_BLOCK written to the offset address in step (8) and the external weight data block EX_WEIGHT_BLOCK are weighted to obtain the weight calculation result WEIGHT_RESULT_2, and the weight calculation result WEIGHT_RESULT_1 is subjected to neuronal current accumulation processing to obtain the second round current increment CURRENT_DELTA_2 of the cnt-th time step, and the second round current increment CURRENT_DELTA_2 is accumulated with the first round current increment CURRENT_DELTA_1 obtained in step (9) to obtain the current current accumulation result CURRENT, and the membrane potential update operation is performed on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK of the cnt-th time step;

[0021] (11) obtaining the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data of the cnt-th time step according to the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained in step (1) and the time step size t_batch_size of each batch obtained in step (3), and writing the pulse output data SPIKE_OUTPUT_BLOCK obtained in step (10) to the write address;

[0022] (12) Set cnt=cnt+1 and return to step (7).

[0023] Preferably, step (1) includes the following sub-steps:

[0024] (1-1) Obtain the input scale parameters of the neural network model, including the pulse input data size spike_data_size, the internal weight dimension in_weight_dim, the external weight dimension ex_weight_dim, and the total number of neurons neuron_num, obtain the total number of time steps time_steps required for neural network model inference and the input scale input_num of each time step, and obtain the data base address of the neural network model in external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data;

[0025] (1-2) Obtain the target size SPM_SPIKE_SIZE of the pulse input data storage area based on the pulse input data size spike_data_size obtained in step (1-1):

[0026] SPM_SPIKE_SIZE=ceil(spike_data_size·BIT_PER_SPIKE / 8),

[0027] Where BIT_PER_SPIKE represents the number of storage bits required for each unit pulse input data, and its value is 1. ceil() represents the rounding up function, which ensures integer alignment after converting the number of bits to bytes.

[0028] (1-3) Obtain the target size SPM_IN_WEIGHT_SIZE of the internal weight storage area based on the internal weight dimension in_weight_dim obtained in step (1-1):

[0029] SPM_IN_WEIGHT_SIZE=in_weight_dim·BYTE_PER_WEIGHT

[0030] BYTE_PER_WEIGHT represents the number of bytes required to store each unit of weight data, and its value is 1.

[0031] (1-4) Obtain the target size SPM_EX_WEIGHT_SIZE of the external weight storage area according to the external weight dimension ex_weight_dim obtained in step (1-1): SPM_EX_WEIGHT_SIZE = ex_weight_dim·BYTE_PER_WEIGHT.

[0032] Preferably, step (2) includes the following sub-steps:

[0033] (2-1) Initialize the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area to 0, which is used as the base address of the pulse input data storage area for storing pulse input data;

[0034] (2-2) According to the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area after initialization in step (2-1) and the size SPM_SPIKE_SIZE of the pulse input data storage area obtained in step (1-2), calculate the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area: SPM_IN_WEIGHT_BASE_ADDR = SPM_SPIKE_BASE_ADDR + SPM_SPIK E_SIZE.

[0035] (2-3) According to the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area calculated in step (2-2) and the internal weight storage area size SPM_IN_WEIGHT_SIZE calculated in step (1-3), calculate the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area: SPM_EX_WEIGHT_BASE_ADDR = SPM_IN_WEIGHT_BASE_ADDR + SPM_IN_WEIGHT_SIZE.

[0036] Preferably, step (3) includes the following sub-steps:

[0037] (3-1) Perform an alignment operation on the input size input_num of each time step obtained in step (1-1) to obtain the number of pulse input bytes ALIGN_SPIKE_SIZE for each time step after alignment:

[0038] ALIGN_SPIKE_SIZE=align512(input_num)

[0039] align512(input_num) indicates that the input size input_num is aligned to 512 bits.

[0040] (3-2) According to the size of the pulse input data storage area SPM_SPIKE_SIZE obtained in step (1-2) and the number of aligned pulse input bytes ALIGN_SPIKE_SIZE obtained in step (3-1), calculate the size of each batch time step t_batch_size:

[0041] t_batch_size=SPM_SPIKE_SIZE / ALIGN_SPIKE_SIZE

[0042] (3-3) Calculate the number of time step batches t_batch_num based on the total number of time steps time_steps obtained in step (1-1) and the size of each batch of time steps t_batch_size obtained in step (3-2):

[0043] t_batch_num=time_steps / t_batch_size

[0044] (3-4) Calculate the time step tail size t_tail_size based on the total number of time steps time_steps obtained in step (1-1) and the size of each batch of time steps t_batch_size obtained in step (3-2):

[0045] t_tail_size=time_steps%t_batch_size.

[0046] Preferably, step (4) includes the following sub-steps:

[0047] (4-1) According to the total number of neurons neuron_num and the input scale of each time step input_num obtained in step (1-1), and the internal weight storage area size SPM_IN_WEIGHT_SIZE obtained in step (1-3), calculate the internal weight block parameters, including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size:

[0048] in_n_batch_size=neuron_num·BYTE_PER_WEIGHT

[0049] in_n_tail_size=SPM_IN_WEIGHT_SIZE% in_n_batch_size

[0050] (4-2) According to the total number of neurons neuron_num and the input scale of each time step input_num obtained in step (1-1), and the external weight storage area size SPM_EX_WEIGHT_SIZE obtained in step (1-4), calculate the external weight block parameters, including the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size:

[0051] ex_n_batch_size=input_num·BYTE_PER_WEIGHT

[0052] ex_n_tail_size=SPM_EX_WEIGHT_SIZE%ex_n_batch_size

[0053] Step (5) specifically involves performing a one-time transfer process on the internal weight data pointed to by the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained in step (1-1), and writing it into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2-2).

[0054] Preferably, step (8) includes the following sub-steps:

[0055] (8-1) Based on the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained in step (1-1) and the size t_batch_size of each batch of time steps obtained in step (3-2), calculate the read offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data at the cnt-th time step:

[0056] SPIKE_DATA_OFFSET_ADDR=SPIKE_DATA_BASE_ADDR+cnt·t_batch_size

[0057] (8-2) Reading a pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the external storage according to the pulse input data offset address SPIKE_DATA_OFFSET_ADDR obtained in step (8-1);

[0058] (8-3) Based on the pulse input data storage area base address SPM_SPIKE_BASE_ADDR obtained in step (2-1), calculate the write address SPIKE_WRITE_ADDR of the pulse input data at the cnt-th time step:

[0059] SPIKE_WRITE_ADDR=SPM_SPIKE_BASE_ADDR+cnt·t_batch_size (8-4) The pulse input data block SPIKE_WRITE_BLOCK obtained in step (8-2) is written to the write address of the pulse input data obtained in step (8-3).

[0060] Preferably, step (9) includes the following sub-steps:

[0061] (9-1) Based on the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2-2) and the internal weight block size in_n_batch_size obtained in step (4-1), calculate the internal weight offset address IN_WEIGHT_OFFSET_ADDR corresponding to the cnt-th time step:

[0062] IN_WEIGHT_OFFSET_ADDR=SPM_IN_WEIGHT_BASE_ADDR+cnt·in_n_batch_size.

[0063] (9-2) Extract the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size according to the internal weight offset address IN_WEIGHT_OFFSET_ADDR obtained in step (9-1).

[0064] (9-3) Perform channel-by-channel dot multiplication on the pulse input data block SPIKE_WRITE_BLOCK corresponding to the cnt-th time step obtained in step (8-3) and the internal weight data block IN_WEIGHT_BLOCK obtained in step (9-2) to obtain the weight calculation result WEIGHT_RESULT_1:

[0065] WEIGHT_RESULT_1=SPIKE_WRITE_BLOCK·IN_WEIGHT_BLOCK

[0066] (9-4) Perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 obtained in step (9-3) to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step:

[0067] CURRENT_DELTA_1=accumulate(WEIGHT_RESULT_1)

[0068] Where accumulate() means adding the weight calculation results to the corresponding current channel according to the neuron channel.

[0069] Preferably, step (10) includes the following sub-steps:

[0070] (10-1) Based on the external weight data base address EX_WEIGHT_DATA_BASE_ADDR obtained in step (1-1) and the external weight block size ex_n_batch_size obtained in step (4-2), calculate the weight offset address EX_WEIGHT_OFFSET_ADDR in the external storage at the cnt-th time step:

[0071] EX_WEIGHT_OFFSET_ADDR=EX_WEIGHT_DATA_BASE_ADDR+cnt·ex_n_batch_size

[0072] (10-2) According to the weight offset address EX_WEIGHT_OFFSET_ADDR in the external storage of the cnt-th time step obtained in step (10-1), read the external weight data block EX_WEIGHT_BLOCK of size ex_n_batch_size from the external storage.

[0073] (10-3) According to the external weight storage area base address SPM_EX_WEIGHT_BASE_ADDR obtained in step (2-3) and the ex_n_batch_size obtained in step (4-2), calculate the write address EX_WEIGHT_WRITE_ADDR of the external weight data at the cnt-th time step:

[0074] EX_WEIGHT_WRITE_ADDR=SPM_EX_WEIGHT_BASE_ADDR+cnt·ex_n_batch_size

[0075] (10-4) writing the external weight data block EX_WEIGHT_BLOCK obtained in step (10-2) to the write address EX_WEIGHT_WRITE_ADDR of the external weight data obtained in step (10-3);

[0076] (10-5) Perform channel-by-channel dot multiplication on the pulse input data block SPIKE_WRITE_BLOCK written in step (8-4) and the external weight data block EX_WEIGHT_BLOCK written in step (10-4) to obtain the weight calculation result WEIGHT_RESULT_2:

[0077] WEIGHT_RESULT_2 = SPIKE_WRITE_BLOCK · EX_WEIGHT_BLOCK (10-6) The weight calculation result WEIGHT_RESULT_2 obtained in step (10-5) is subjected to neuronal current accumulation processing to obtain the second round current increment CURRENT_DELTA_2 at the cnt-th time step. This second round current increment CURRENT_DELTA_2 is accumulated with the first round current increment CURRENT_DELTA_1 obtained in step (9-4) to obtain the current current accumulation result CURRENT. The spiking neuron model LIF (Leaky Integrate-and-Fire) is used to perform a membrane potential update operation on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK at the cnt-th time step:

[0078] URRENT_DELTA_2=accumulate(WEIGHT_RESULT_2), where accumulate() means accumulating the weighted result into the corresponding current channel according to the neuron channel.

[0079] CURRENT=URRENT_DELTA_1+URRENT_DELTA_2,

[0080] SPIKE_OUTPUT_BLOCK=LIF(CURRENT)

[0081] Where LIF(CURRENT) indicates that the pulse neuron model LIF is used to update the membrane potential of the current input.

[0082] Preferably, step (11) comprises the following sub-steps:

[0083] (11-1) Based on the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained in step (1-1) and the batch time step size t_batch_size obtained in step (3-3), calculate the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data SPIKE_OUTPUT_BLOCK at the cnt-th time step:

[0084] SPIKE_OUTPUT_WRITE_ADDR=SPIKE_OUTPUT_BASE_ADDR+cnt·t_batch_size

[0085] (11-2) Write the pulse output data SPIKE_OUTPUT_BLOCK obtained in step (10-6) to the write address obtained in step (11-1).

[0086] According to another aspect of the present invention, a system for optimizing neural network computing performance based on on-chip storage is provided, comprising:

[0087] The first module is used to obtain the input scale parameters of the neural network model, including the amount of pulse input data, the internal weight dimension, the external weight dimension, the total number of neurons, the total number of time steps time_steps and the input scale input_num of each time step, obtain the data base address of the neural network model in the external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data, and set a storage area for storing the pulse input data, the internal weight data and the external weight data in the on-chip storage area of ​​the computing platform;

[0088] The second module is used to allocate the pulse input data storage area, the internal weight storage area and the external weight storage area obtained by the first module respectively to the pulse input data storage area SPM_SPIKE_BASE_ADDR, the internal weight storage area SPM_IN_WEIGHT_BASE_ADDR and the external weight storage area SPM_EX_WEIGHT_BASE_ADDR;

[0089] The third module is used to obtain the time step division parameters for iterative control according to the total number of time steps time_steps and the input scale input_num of each time step obtained in the first module, including the time step size of each batch t_batch_size, the number of time step batches t_batch_num, and the tail time step size t_tail_size;

[0090] The fourth module is used to obtain the weight block parameters for scheduling according to the total number of neurons neuron_num obtained in the first module, including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size. The external weight block parameters include the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size.

[0091] The fifth module is used to obtain the internal weight data from the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained by the first module, and write the obtained internal weight data into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained by the second module at one time;

[0092] The sixth module is used to set the counter cnt=1;

[0093] The seventh module is used to determine whether the counter cnt is greater than the time step batch number t_batch_num obtained in the third module. If so, the process ends, otherwise it enters the eighth module.

[0094] An eighth module is configured to obtain an offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data of the cnt-th time step in the external storage according to the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained by the first module and the size t_batch_size of each batch of time steps obtained by the third module, read a pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the offset address, obtain a write address SPIKE_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area obtained by the second module and the size t_batch_size of each batch of time steps obtained by the third module, and write the read pulse input data block SPIKE_WRITE_BLOCK to the write address;

[0095] The ninth module is used to obtain the offset address IN_WEIGHT_OFFSET_ADDR of the internal weight storage area at the cnt-th time step according to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained by the second module and the internal weight block size in_n_batch_size obtained by the fourth module, obtain the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size from the offset address, perform weight calculation on the pulse input data block SPIKE_WRITE_BLOCK and the internal weight data block IN_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_1, and perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step;

[0096] The tenth module is used to obtain the offset address EX_WEIGHT_OFFSET_ADDR of the external weight data in the external storage of the cnt-th time step according to the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data in the external storage obtained by the first module and the external weight block size ex_n_batch_size obtained by the fourth module, read the external weight data block EX_WEIGHT_BLOCK of size ex_n_batch_size from the offset address, obtain the write address EX_WEIGHT_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area obtained by the second module and the external weight block size ex_n_batch_size obtained by the fourth module, and write the external weight data block EX_WEIGHT _BLOCK is written to the write address, and weight calculation is performed on the pulse input data block SPIKE_WRITE_BLOCK at the offset address written by the eighth module and the external weight data block EX_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_2, and the weight calculation result WEIGHT_RESULT_1 is subjected to neuronal current accumulation processing to obtain the second round of current increment CURRENT_DELTA_2 at the cnt-th time step, and the second round of current increment CURRENT_DELTA_2 is accumulated with the first round of current increment CURRENT_DELTA_1 obtained in the ninth module to obtain the current current accumulation result CURRENT, and the membrane potential update operation is performed on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK of the cnt-th time step;

[0097] The eleventh module is used to obtain the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data of the cnt-th time step according to the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained by the first module and the time step size t_batch_size of each batch obtained by the third module, and write the pulse output data SPIKE_OUTPUT_BLOCK obtained by the tenth module to the write address;

[0098] The twelfth module is used to set cnt=cnt+1 and return to the seventh module.

[0099] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0100] (1) The present invention adopts steps (1) to (2), presetting storage areas for pulse input data, internal weight data, and external weight data in the on-chip storage area, and sequentially allocating corresponding base addresses according to the data size, thereby achieving fine division of the SPM space and non-overlapping scheduling, thereby solving the technical problems of unreasonable SPM space division and serious access conflicts in existing hardware accelerator-based neural network computing performance optimization methods;

[0101] (2) The present invention adopts steps (3) to (5), which introduces block parameters of two dimensions, time step and neuron, and combines the one-time loading of internal weights with the on-demand batch loading mechanism of external weights and pulse inputs to form a unified data scheduling process. Therefore, it can solve the technical problems of the single loading mechanism and low access efficiency in the existing neural network computing performance optimization method based on model optimization technology;

[0102] (3) The present invention adopts steps (6) to (10), which sequentially execute pulse loading, weight extraction, two rounds of current calculation and membrane potential update in each time step, and cooperate with the time step counter for batch scheduling. Therefore, it can solve the technical problems of the existing neural network computing performance optimization method based on the block computing mechanism in that the block scheduling is not fine-grained and the computational parallelism is insufficient;

[0103] (4) The present invention adopts steps (7) to (11), designs a complete time-step batch control logic, and uses a unified offset address calculation method in various data loading and writing, ensuring uninterrupted data access in continuous batch calculations. Therefore, it can solve the technical problems of incoherent reasoning execution and imperfect data update mechanism existing in the three existing optimization methods;

[0104] (5) The implementation of the present invention is simple, and all calculation and scheduling processes are based on a unified data structure and address offset logic, which facilitates software implementation and hardware mapping;

[0105] (6) The present invention has good applicability and scalability, supports deployment on a variety of edge computing platforms, system-on-chips, and embedded AI chips, and is particularly suitable for applications with high requirements for inference efficiency and stability in resource-constrained scenarios;

[0106] (7) The data loading and calculation logic of the present invention has predictable timing, which is conducive to optimizing the resource usage of high-speed channels such as DMA. The loading process of the present invention is carried out in a phased and fixed-step manner in steps (5), (8), and (10), and the data access in each stage is distributed periodically, thereby improving bus efficiency and reducing loading waiting delay;

[0107] (8) The "one-time loading and multiple reuse of internal weight data" mechanism introduced in the present invention improves the reuse rate of SPM space. In step (5), the internal weight data is written to the SPM through a one-time loading and is accessed multiple times by offset in step (9), reflecting a cache mechanism of one-time loading and multiple rounds of use, which significantly improves the efficiency of SPM use and reduces data handling overhead;

[0108] (9) The present invention can adapt to different SPM capacities and system resource constraints, and has hardware-aware adaptability. By utilizing block parameters derived from input parameters such as SPM space capacity and input_num, the present invention has flexible adjustment capabilities, allowing the present invention to automatically scale inference based on the target platform configuration, improving platform adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] Figure 1 It is a flow chart of the method of optimizing neural network computing performance based on on-chip storage of the present invention. DETAILED DESCRIPTION

[0110] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0111] The basic idea of ​​the present invention is to propose an efficient computing method that integrates fine division of storage space, time step batch scheduling, weight layered loading and block parallel computing mechanism to address the problems of limited resources of the system on chip (Scratchpad Memory, abbreviated as SPM) and low execution efficiency of traditional neural networks. First, the SPM space is divided according to the access characteristics of pulse input data, internal weights and external weights to improve data utilization efficiency. Thereafter, the calculation process is batched in the time step dimension to make task scheduling more balanced. Then, the internal weights are loaded at one time to reduce repeated transmission, and the external weights are loaded in blocks on demand to avoid storage pressure. Finally, the membrane potential update and pulse output management are combined to construct a continuous and stable neural network calculation process. The present invention can be widely used in scenarios that are sensitive to computing resources and storage bandwidth, such as embedded AI chips and edge computing devices.

[0112] like Figure 1 As shown, the present invention provides a method for optimizing neural network computing performance based on on-chip storage, comprising the following steps:

[0113] (1) Obtaining the input scale parameters of the neural network model, including the amount of pulse input data, the internal weight dimension, the external weight dimension, the total number of neurons, the total number of time steps time_steps, and the input scale input_num of each time step, obtaining the data base address of the neural network model in the external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data, and setting a storage area for storing the pulse input data, the internal weight data, and the external weight data in the on-chip storage area of ​​the computing platform;

[0114] (2) respectively allocating the pulse input data storage area, the internal weight storage area, and the external weight storage area with a storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area, the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area, and the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area to the pulse input data storage area, the internal weight storage area, and the external weight storage area obtained in step (1);

[0115] (3) According to the total number of time steps time_steps and the input size input_num of each time step obtained in step (1), the time step division parameters for iterative control are obtained, including the time step size of each batch t_batch_size, the number of time step batches t_batch_num, and the tail time step size t_tail_size;

[0116] (4) Obtain the weight block parameters for scheduling based on the total number of neurons neuron_num obtained in step (1), including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size; the external weight block parameters include the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size;

[0117] The advantage of the above steps (1) to (5) is that they can complete the parameter initialization and storage space division required for neural network inference, establish a unified data layout and loading structure, and thus provide structured support for subsequent data scheduling and block calculation.

[0118] (5) Obtaining the internal weight data from the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained in step (1), and writing the obtained internal weight data once into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2);

[0119] The advantage of this step is that the internal weight data can be loaded at one time, thereby improving the continuity of data loading and reducing the overhead of repeated transmission.

[0120] (6) Set counter cnt=1 (which is used as the current time step number to establish a control index for subsequent batch calculations).

[0121] (7) Determine whether the counter cnt is greater than the time step batch number t_batch_num obtained in step (3). If so, the process ends; otherwise, proceed to step (8);

[0122] (8) Obtain the offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data of the cnt-th time step in the external storage according to the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained in step (1) and the size t_batch_size of each batch of time steps obtained in step (3), read the pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the offset address, obtain the write address SPIKE_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area obtained in step (2) and the size t_batch_size of each batch of time steps obtained in step (3), and write the read pulse input data block SPIKE_WRITE_BLOCK to the write address;

[0123] (9) Obtain the offset address IN_WEIGHT_OFFSET_ADDR of the internal weight storage area at the cnt-th time step according to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2) and the internal weight block size in_n_batch_size obtained in step (4), obtain the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size from the offset address, perform weight calculation on the pulse input data block SPIKE_WRITE_BLOCK written at the offset address in step (8) and the internal weight data block IN_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_1, perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step;

[0124] (10) According to the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data in the external storage obtained in step (1) and the external weight block size ex_n_batch_size obtained in step (4), obtain the offset address EX_WEIGHT_OFFSET_ADDR of the external weight data of the cnt-th time step in the external storage, read the external weight data block EX_WEIGHT_BLOCK of size ex_n_batch_size from the offset address, according to the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area obtained in step (2) and the external weight block size ex_n_batch_size obtained in step (4), obtain the write address EX_WEIGHT_WRITE_ADDR of the cnt-th time step, and write the external weight data block EX_WEIGHT_BLOCK to the external storage area. T_BLOCK is written to the address, and the pulse input data block SPIKE_WRITE_BLOCK written to the offset address in step (8) and the external weight data block EX_WEIGHT_BLOCK are weighted to obtain the weight calculation result WEIGHT_RESULT_2. The weight calculation result WEIGHT_RESULT_1 is subjected to neuronal current accumulation processing to obtain the second round current increment CURRENT_DELTA_2 of the cnt-th time step. The second round current increment CURRENT_DELTA_2 is accumulated with the first round current increment CURRENT_DELTA_1 obtained in step (9) to obtain the current current accumulation result CURRENT, and the membrane potential update operation is performed on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK of the cnt-th time step;

[0125] The advantage of the above steps (6) to (10) is that a unified time step scheduling and block calculation process is constructed, which makes the neural network reasoning process have higher continuity and execution efficiency.

[0126] (11) obtaining the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data of the cnt-th time step according to the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained in step (1) and the time step size t_batch_size of each batch obtained in step (3), and writing the pulse output data SPIKE_OUTPUT_BLOCK obtained in step (10) to the write address;

[0127] (12) Set cnt=cnt+1 and return to step (7);

[0128] Step (1) includes the following sub-steps:

[0129] (1-1) Obtain the input scale parameters of the neural network model, including the pulse input data size spike_data_size, the internal weight dimension in_weight_dim, the external weight dimension ex_weight_dim, and the total number of neurons neuron_num, obtain the total number of time steps time_steps required for neural network model inference and the input scale input_num of each time step, and obtain the data base address of the neural network model in external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data;

[0130] (1-2) Obtain the target size SPM_SPIKE_SIZE of the pulse input data storage area according to the pulse input data amount spike_data_size obtained in step (1-1);

[0131] Specifically, this step uses the following formula:

[0132] SPM_SPIKE_SIZE=ceil(spike_data_size·BIT_PER_SPIKE / 8),

[0133] BIT_PER_SPIKE represents the number of storage bits required for each unit pulse input data, and its value is 1. ceil() represents the round-up function, which converts the number of bits into bytes to ensure integer alignment.

[0134] (1-3) Obtain the target size SPM_IN_WEIGHT_SIZE of the internal weight storage area according to the internal weight dimension in_weight_dim obtained in step (1-1);

[0135] Specifically, this step uses the following formula:

[0136] SPM_IN_WEIGHT_SIZE=in_weight_dim·BYTE_PER_WEIGHT

[0137] BYTE_PER_WEIGHT represents the number of bytes required to store each unit of weight data, and its value is 1.

[0138] (1-4) Obtain the target size SPM_EX_WEIGHT_SIZE of the external weight storage area according to the external weight dimension ex_weight_dim obtained in step (1-1);

[0139] Specifically, this step uses the following formula:

[0140] SPM_EX_WEIGHT_SIZE=ex_weight_dim·BYTE_PER_WEIGHT;

[0141] Step (2) includes the following sub-steps:

[0142] (2-1) Initialize the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area to 0, which is used as the base address of the pulse input data storage area for storing pulse input data;

[0143] (2-2) Calculating the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area based on the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area initialized in step (2-1) and the size SPM_SPIKE_SIZE of the pulse input data storage area obtained in step (1-2);

[0144] Specifically, this step uses the following formula:

[0145] SPM_IN_WEIGHT_BASE_ADDR=SPM_SPIKE_BASE_ADDR+SPM_SPIKE_SIZE.

[0146] (2-3) Calculate the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area according to the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area calculated in step (2-2) and the size SPM_IN_WEIGHT_SIZE of the internal weight storage area calculated in step (1-3);

[0147] Specifically, this step uses the following formula:

[0148] SPM_EX_WEIGHT_BASE_ADDR=SPM_IN_WEIGHT_BASE_ADDR+SPM_IN_WEIGHT_SIZE

[0149] Step (3) includes the following sub-steps:

[0150] (3-1) Perform an alignment operation on the input size input_num of each time step obtained in step (1-1) to obtain the number of pulse input bytes ALIGN_SPIKE_SIZE for each time step after alignment;

[0151] Specifically, this step uses the following formula:

[0152] ALIGN_SPIKE_SIZE=align512(input_num)

[0153] align512(input_num) indicates that the input size input_num is aligned to 512 bits.

[0154] (3-2) Calculate the size of each batch of time steps t_batch_size based on the size of the pulse input data storage area SPM_SPIKE_SIZE obtained in step (1-2) and the number of aligned pulse input bytes ALIGN_SPIKE_SIZE obtained in step (3-1);

[0155] Specifically, this step uses the following formula:

[0156] t_batch_size=SPM_SPIKE_SIZE / ALIGN_SPIKE_SIZE

[0157] (3-3) Calculate the number of time step batches t_batch_num based on the total number of time steps time_steps obtained in step (1-1) and the size of each batch of time steps t_batch_size obtained in step (3-2);

[0158] Specifically, this step uses the following formula:

[0159] t_batch_num=time_steps / t_batch_size

[0160] (3-4) Calculate the time step tail size t_tail_size based on the total number of time steps time_steps obtained in step (1-1) and the size of each batch of time steps t_batch_size obtained in step (3-2);

[0161] Specifically, this step uses the following formula:

[0162] t_tail_size=time_steps%t_batch_size

[0163] Step (4) includes the following sub-steps:

[0164] (4-1) According to the total number of neurons neuron_num and the input scale of each time step input_num obtained in step (1-1), and the internal weight storage area size SPM_IN_WEIGHT_SIZE obtained in step (1-3), calculate the internal weight block parameters, including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size;

[0165] Specifically, this step uses the following formula:

[0166] in_n_batch_size=neuron_num·BYTE_PER_WEIGHT

[0167] in_n_tail_size=SPM_IN_WEIGHT_SIZE% in_n_batch_size

[0168] (4-2) According to the total number of neurons neuron_num and the input scale of each time step input_num obtained in step (1-1), and the external weight storage area size SPM_EX_WEIGHT_SIZE obtained in step (1-4), calculate the external weight block parameters, including the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size;

[0169] Specifically, this step uses the following formula:

[0170] ex_n_batch_size=input_num·BYTE_PER_WEIGHT

[0171] ex_n_tail_size=SPM_EX_WEIGHT_SIZE%ex_n_batch_size

[0172] Step (5) specifically involves performing a one-time transfer process on the internal weight data pointed to by the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained in step (1-1), and writing it into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2-2).

[0173] Step (8) includes the following sub-steps:

[0174] (8-1) Calculate the read offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data at the cnt-th time step based on the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained in step (1-1) and the size t_batch_size of each batch of time steps obtained in step (3-2);

[0175] Specifically, this step uses the following formula:

[0176] SPIKE_DATA_OFFSET_ADDR=SPIKE_DATA_BASE_ADDR+cnt·t_batch_size

[0177] (8-2) Reading a pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the external storage according to the pulse input data offset address SPIKE_DATA_OFFSET_ADDR obtained in step (8-1);

[0178] (8-3) Calculate the write address SPIKE_WRITE_ADDR of the pulse input data at the cnt-th time step according to the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area obtained in step (2-1);

[0179] Specifically, this step uses the following formula:

[0180] SPIKE_WRITE_ADDR=SPM_SPIKE_BASE_ADDR+cnt·t_batch_size (8-4) The pulse input data block SPIKE_WRITE_BLOCK obtained in step (8-2) is written to the write address of the pulse input data obtained in step (8-3).

[0181] Step (9) includes the following sub-steps:

[0182] (9-1) Based on the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2-2) and the internal weight block size in_n_batch_size obtained in step (4-1), calculate the internal weight offset address IN_WEIGHT_OFFSET_ADDR corresponding to the cnt-th time step;

[0183] Specifically, this step uses the following formula:

[0184] IN_WEIGHT_OFFSET_ADDR=SPM_IN_WEIGHT_BASE_ADDR+cnt·in_n_batch_size.

[0185] (9-2) Extract the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size according to the internal weight offset address IN_WEIGHT_OFFSET_ADDR obtained in step (9-1).

[0186] (9-3) Perform channel-by-channel dot multiplication on the pulse input data block SPIKE_WRITE_BLOCK corresponding to the cnt-th time step obtained in step (8-3) and the internal weight data block IN_WEIGHT_BLOCK obtained in step (9-2) to obtain the weight calculation result WEIGHT_RESULT_1.

[0187] Specifically, this step uses the following formula:

[0188] WEIGHT_RESULT_1=SPIKE_WRITE_BLOCK·IN_WEIGHT_BLOCK

[0189] (9-4) Perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 obtained in step (9-3) to obtain the first round of current increment CURRENT_DELTA_1 in the cnt-th time step.

[0190] Specifically, this step uses the following formula:

[0191] CURRENT_DELTA_1=accumulate(WEIGHT_RESULT_1)

[0192] Where accumulate() means adding the weight calculation results to the corresponding current channel according to the neuron channel.

[0193] Step (10) includes the following sub-steps:

[0194] (10-1) Calculate the weight offset address EX_WEIGHT_OFFSET_ADDR in the external storage at the cnt-th time step based on the external weight data base address EX_WEIGHT_DATA_BASE_ADDR obtained in step (1-1) and the external weight block size ex_n_batch_size obtained in step (4-2);

[0195] Specifically, this step uses the following formula:

[0196] EX_WEIGHT_OFFSET_ADDR=EX_WEIGHT_DATA_BASE_ADDR+cnt·ex_n_batch_size

[0197] (10-2) According to the weight offset address EX_WEIGHT_OFFSET_ADDR in the external storage of the cnt-th time step obtained in step (10-1), read the external weight data block EX_WEIGHT_BLOCK of size ex_n_batch_size from the external storage.

[0198] (10-3) Calculate the write address EX_WEIGHT_WRITE_ADDR of the external weight data at the cnt-th time step based on the external weight storage area base address SPM_EX_WEIGHT_BASE_ADDR obtained in step (2-3) and the ex_n_batch_size obtained in step (4-2);

[0199] Specifically, this step uses the following formula:

[0200] EX_WEIGHT_WRITE_ADDR=SPM_EX_WEIGHT_BASE_ADDR+cnt·ex_n_batch_size

[0201] (10-4) writing the external weight data block EX_WEIGHT_BLOCK obtained in step (10-2) to the write address EX_WEIGHT_WRITE_ADDR of the external weight data obtained in step (10-3);

[0202] (10-5) performing a channel-by-channel dot multiplication operation on the pulse input data block SPIKE_WRITE_BLOCK written in step (8-4) and the external weight data block EX_WEIGHT_BLOCK written in step (10-4) to obtain a weight calculation result WEIGHT_RESULT_2;

[0203] Specifically, this step uses the following formula:

[0204] WEIGHT_RESULT_2=SPIKE_WRITE_BLOCK·EX_WEIGHT_BLOCK

[0205] (10-6) The weight calculation result WEIGHT_RESULT_2 obtained in step (10-5) is processed by neuronal current accumulation to obtain the second round current increment CURRENT_DELTA_2 of the cnt-th time step, and the second round current increment CURRENT_DELTA_2 is accumulated with the first round current increment CURRENT_DELTA_1 obtained in step (9-4) to obtain the current current accumulation result CURRENT, and the pulse neuron model LIF (Leaky Integrate-and-Fire) is used to perform a membrane potential update operation on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK of the cnt-th time step.

[0206] Specifically, this step uses the following formula:

[0207] URRENT_DELTA_2=accumulate(WEIGHT_RESULT_2), where accumulate() means accumulating the weighted result into the corresponding current channel according to the neuron channel.

[0208] CURRENT=URRENT_DELTA_1+URRENT_DELTA_2,

[0209] SPIKE_OUTPUT_BLOCK=LIF(CURRENT)

[0210] Where LIF(CURRENT) indicates that the pulse neuron model LIF is used to perform a membrane potential update operation (i.e., membrane potential integration and threshold release operation) on the current input, and outputs the pulse output data of the cnt-th time step.

[0211] Step (11) includes the following sub-steps:

[0212] (11-1) Calculate the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data SPIKE_OUTPUT_BLOCK at the cnt-th time step based on the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained in step (1-1) and the batch time step size t_batch_size obtained in step (3-3);

[0213] Specifically, this step uses the following formula:

[0214] SPIKE_OUTPUT_WRITE_ADDR=SPIKE_OUTPUT_BASE_ADDR+cnt·t_batch_size

[0215] (11-2) writing the pulse output data SPIKE_OUTPUT_BLOCK obtained in step (10-6) into the write address obtained in step (11-1);

[0216] In summary, the present invention improves the efficiency and stability of neural network reasoning by constructing a unified execution framework that integrates storage partitioning, data scheduling and block calculation in a resource-constrained system-on-chip (Scratchpad Memory, SPM) environment. Specifically, this method first finely divides the on-chip storage space based on the access characteristics of pulse input data, internal weights and external weights, and assigns independent storage base addresses to various types of data. It introduces block parameters in the two dimensions of time step and neuron, and constructs a unified loading and calculation scheduling process. It adopts a separate loading strategy to load the internal weight data at one time and load the external weight data in blocks according to the time step. In each time step, pulse input loading, two rounds of weight calculation, membrane potential update and result writeback are completed to ensure the continuity of the calculation process and resource reuse rate. The method has a clear overall structure and efficient scheduling, and is suitable for computing platforms with limited storage and bandwidth such as edge computing and embedded AI chips.

[0217] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for optimizing neural network computing performance based on on-chip storage, characterized in that: The following steps are involved: (1) Obtaining the input scale parameters of the neural network model, including the amount of pulse input data, the internal weight dimension, the external weight dimension, the total number of neurons, the total number of time steps time_steps, and the input scale input_num of each time step, obtaining the data base address of the neural network model in the external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data, and setting a storage area for storing the pulse input data, the internal weight data, and the external weight data in the on-chip storage area of ​​the computing platform; (2) respectively allocating the pulse input data storage area, the internal weight storage area, and the external weight storage area with a storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area, the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area, and the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area to the pulse input data storage area, the internal weight storage area, and the external weight storage area obtained in step (1); (3) According to the total number of time steps time_steps and the input size input_num of each time step obtained in step (1), the time step division parameters for iterative control are obtained, including the time step size of each batch t_batch_size, the number of time step batches t_batch_num, and the tail time step size t_tail_size; (4) Obtain the weight block parameters for scheduling based on the total number of neurons neuron_num obtained in step (1), including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size; the external weight block parameters include the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size; (5) Obtaining the internal weight data from the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained in step (1), and writing the obtained internal weight data once into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2); (6) Set counter cnt = 1; (7) Determine whether the counter cnt is greater than the time step batch number t_batch_num obtained in step (3). If so, the process ends; otherwise, proceed to step (8). (8) Obtain the offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data of the cnt-th time step in the external storage according to the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained in step (1) and the size t_batch_size of each batch of time steps obtained in step (3), read the pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the offset address, obtain the write address SPIKE_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area obtained in step (2) and the size t_batch_size of each batch of time steps obtained in step (3), and write the read pulse input data block SPIKE_WRITE_BLOCK to the write address; (9) Obtain the offset address IN_WEIGHT_OFFSET_ADDR of the internal weight storage area at the cnt-th time step according to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2) and the internal weight block size in_n_batch_size obtained in step (4), obtain the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size from the offset address, perform weight calculation on the pulse input data block SPIKE_WRITE_BLOCK and the internal weight data block IN_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_1, perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step; (10) According to the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data in the external storage obtained in step (1) and the external weight block size ex_n_batch_size obtained in step (4), the offset address EX_WEIGHT_OFFSET_ADDR of the external weight data of the cnt-th time step in the external storage is obtained, and the external weight data block EX_WEIGHT_BLOCK of the size ex_n_batch_size is read from the offset address. According to the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area obtained in step (2) and the external weight block size ex_n_batch_size obtained in step (4), the write address EX_WEIGHT_WRITE_ADDR of the cnt-th time step is obtained, and the external weight data block EX_WEIGHT _BLOCK is written to the write address, and the pulse input data block SPIKE_WRITE_BLOCK written to the offset address in step (8) and the external weight data block EX_WEIGHT_BLOCK are weighted to obtain the weight calculation result WEIGHT_RESULT_2, and the weight calculation result WEIGHT_RESULT_1 is subjected to neuronal current accumulation processing to obtain the second round current increment CURRENT_DELTA_2 of the cnt-th time step, and the second round current increment CURRENT_DELTA_2 is accumulated with the first round current increment CURRENT_DELTA_1 obtained in step (9) to obtain the current current accumulation result CURRENT, and the membrane potential update operation is performed on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK of the cnt-th time step; (11) obtaining the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data of the cnt-th time step according to the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained in step (1) and the time step size t_batch_size of each batch obtained in step (3), and writing the pulse output data SPIKE_OUTPUT_BLOCK obtained in step (10) to the write address; (12) Set cnt=cnt+1 and return to step (7).

2. The method for optimizing neural network computing performance based on on-chip storage according to claim 1, characterized in that: Step (1) includes the following sub-steps: (1-1) Obtain the input scale parameters of the neural network model, including the pulse input data size spike_data_size, the internal weight dimension in_weight_dim, the external weight dimension ex_weight_dim, and the total number of neurons neuron_num, obtain the total number of time steps time_steps required for neural network model inference and the input scale input_num of each time step, and obtain the data base address of the neural network model in external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data; (1-2) Obtain the target size SPM_SPIKE_SIZE of the pulse input data storage area based on the pulse input data size spike_data_size obtained in step (1-1): SPM_SPIKE_SIZE=ceil(spike_data_size·BIT_PER_SPIKE / 8), Where BIT_PER_SPIKE represents the number of storage bits required for each unit pulse input data, and its value is 1. ceil() represents the rounding up function, which ensures integer alignment after converting the number of bits to bytes. (1-3) Obtain the target size SPM_IN_WEIGHT_SIZE of the internal weight storage area based on the internal weight dimension in_weight_dim obtained in step (1-1): SPM_IN_WEIGHT_SIZE=in_weight_dim·BYTE_PER_WEIGHT BYTE_PER_WEIGHT represents the number of bytes required to store each unit of weight data, and its value is 1. (1-4) Obtain the target size SPM_EX_WEIGHT_SIZE of the external weight storage area according to the external weight dimension ex_weight_dim obtained in step (1-1): SPM_EX_WEIGHT_SIZE = ex_weight_dim·BYTE_PER_WEIGHT.

3. The method for optimizing neural network computing performance based on on-chip storage according to claim 1 or 2, characterized in that: Step (2) includes the following sub-steps: (2-1) Initialize the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area to 0, which is used as the base address of the pulse input data storage area for storing pulse input data; (2-2) According to the base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area after initialization in step (2-1) and the size SPM_SPIKE_SIZE of the pulse input data storage area obtained in step (1-2), calculate the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area: SPM_IN_WEIGHT_BASE_ADDR = SPM_SPIKE_BASE_ADDR + SPM_SPIKE_SIZE. (2-3) According to the storage base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area calculated in step (2-2) and the internal weight storage area size SPM_IN_WEIGHT_SIZE calculated in step (1-3), calculate the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area: SPM_EX_WEIGHT_BASE_ADDR = SPM_IN_WEIGHT_BASE_ADDR + SPM_IN_WEIGHT_SIZE.

4. The method for optimizing neural network computing performance based on on-chip storage according to any one of claims 1 to 3, characterized in that: Step (3) includes the following sub-steps: (3-1) Perform an alignment operation on the input size input_num of each time step obtained in step (1-1) to obtain the number of pulse input bytes ALIGN_SPIKE_SIZE for each time step after alignment: ALIGN_SPIKE_SIZE=align512(input_num) align512(input_num) indicates that the input size input_num is aligned to 512 bits. (3-2) According to the size of the pulse input data storage area SPM_SPIKE_SIZE obtained in step (1-2) and the number of aligned pulse input bytes ALIGN_SPIKE_SIZE obtained in step (3-1), calculate the size of each batch time step t_batch_size: t_batch_size=SPM_SPIKE_SIZE / ALIGN_SPIKE_SIZE (3-3) Calculate the number of time step batches t_batch_num based on the total number of time steps time_steps obtained in step (1-1) and the size of each batch of time steps t_batch_size obtained in step (3-2): t_batch_num=time_steps / t_batch_size (3-4) Calculate the time step tail size t_tail_size based on the total number of time steps time_steps obtained in step (1-1) and the size of each batch of time steps t_batch_size obtained in step (3-2): t_tail_size=time_steps%t_batch_size.

5. The method for optimizing neural network computing performance based on on-chip storage according to claim 4, characterized in that: Step (4) includes the following sub-steps: (4-1) According to the total number of neurons neuron_num and the input scale of each time step input_num obtained in step (1-1), and the internal weight storage area size SPM_IN_WEIGHT_SIZE obtained in step (1-3), calculate the internal weight block parameters, including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size: in_n_batch_size=neuron_num·BYTE_PER_WEIGHT in_n_tail_size=SPM_IN_WEIGHT_SIZE% in_n_batch_size (4-2) According to the total number of neurons neuron_num and the input scale of each time step input_num obtained in step (1-1), and the external weight storage area size SPM_EX_WEIGHT_SIZE obtained in step (1-4), calculate the external weight block parameters, including the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size: ex_n_batch_size=input_num·BYTE_PER_WEIGHT ex_n_tail_size=SPM_EX_WEIGHT_SIZE%ex_n_batch_size Step (5) specifically involves performing a one-time transfer process on the internal weight data pointed to by the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained in step (1-1), and writing it into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2-2).

6. The method for optimizing neural network computing performance based on on-chip storage according to claim 5, characterized in that: Step (8) includes the following sub-steps: (8-1) Based on the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained in step (1-1) and the size t_batch_size of each batch of time steps obtained in step (3-2), calculate the read offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data at the cnt-th time step: SPIKE_DATA_OFFSET_ADDR=SPIKE_DATA_BASE_ADDR+cnt·t_batch_size (8-2) Reading a pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the external storage according to the pulse input data offset address SPIKE_DATA_OFFSET_ADDR obtained in step (8-1); (8-3) Based on the pulse input data storage area base address SPM_SPIKE_BASE_ADDR obtained in step (2-1), calculate the write address SPIKE_WRITE_ADDR of the pulse input data at the cnt-th time step: SPIKE_WRITE_ADDR=SPM_SPIKE_BASE_ADDR+cnt·t_batch_size (8-4) The pulse input data block SPIKE_WRITE_BLOCK obtained in step (8-2) is written to the write address of the pulse input data obtained in step (8-3).

7. The method for optimizing neural network computing performance based on on-chip storage according to claim 6, characterized in that: Step (9) includes the following sub-steps: (9-1) Based on the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained in step (2-2) and the internal weight block size in_n_batch_size obtained in step (4-1), calculate the internal weight offset address IN_WEIGHT_OFFSET_ADDR corresponding to the cnt-th time step: IN_WEIGHT_OFFSET_ADDR=SPM_IN_WEIGHT_BASE_ADDR+cnt·in_n_batch_size. (9-2) Extract the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size according to the internal weight offset address IN_WEIGHT_OFFSET_ADDR obtained in step (9-1). (9-3) Perform channel-by-channel dot multiplication on the pulse input data block SPIKE_WRITE_BLOCK corresponding to the cnt-th time step obtained in step (8-3) and the internal weight data block IN_WEIGHT_BLOCK obtained in step (9-2) to obtain the weight calculation result WEIGHT_RESULT_1: WEIGHT_RESULT_1=SPIKE_WRITE_BLOCK·IN_WEIGHT_BLOCK (9-4) Perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 obtained in step (9-3) to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step: CURRENT_DELTA_1=accumulate(WEIGHT_RESULT_1) Where accumulate() means adding the weight calculation results to the corresponding current channel according to the neuron channel.

8. The method for optimizing neural network computing performance based on on-chip storage according to claim 7, characterized in that: Step (10) includes the following sub-steps: (10-1) Based on the external weight data base address EX_WEIGHT_DATA_BASE_ADDR obtained in step (1-1) and the external weight block size ex_n_batch_size obtained in step (4-2), calculate the weight offset address EX_WEIGHT_OFFSET_ADDR in the external storage at the cnt-th time step: EX_WEIGHT_OFFSET_ADDR=EX_WEIGHT_DATA_BASE_ADDR+cnt·ex_n_batch_size (10-2) According to the weight offset address EX_WEIGHT_OFFSET_ADDR in the external storage of the cnt-th time step obtained in step (10-1), read the external weight data block EX_WEIGHT_BLOCK of size ex_n_batch_size from the external storage. (10-3) According to the external weight storage area base address SPM_EX_WEIGHT_BASE_ADDR obtained in step (2-3) and the ex_n_batch_size obtained in step (4-2), calculate the write address EX_WEIGHT_WRITE_ADDR of the external weight data at the cnt-th time step: EX_WEIGHT_WRITE_ADDR=SPM_EX_WEIGHT_BASE_ADDR+cnt·ex_n_batch_size (10-4) writing the external weight data block EX_WEIGHT_BLOCK obtained in step (10-2) to the write address EX_WEIGHT_WRITE_ADDR of the external weight data obtained in step (10-3); (10-5) Perform channel-by-channel dot multiplication on the pulse input data block SPIKE_WRITE_BLOCK written in step (8-4) and the external weight data block EX_WEIGHT_BLOCK written in step (10-4) to obtain the weight calculation result WEIGHT_RESULT_2: WEIGHT_RESULT_2 = SPIKE_WRITE_BLOCK · EX_WEIGHT_BLOCK (10-6) The weight calculation result WEIGHT_RESULT_2 obtained in step (10-5) is subjected to neuronal current accumulation processing to obtain the second round current increment CURRENT_DELTA_2 at the cnt-th time step. This second round current increment CURRENT_DELTA_2 is accumulated with the first round current increment CURRENT_DELTA_1 obtained in step (9-4) to obtain the current current accumulation result CURRENT. The spiking neuron model LIF (Leaky Integrate-and-Fire) is used to perform a membrane potential update operation on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK at the cnt-th time step: URRENT_DELTA_2=accumulate(WEIGHT_RESULT_2), where accumulate() means accumulating the weighted result into the corresponding current channel according to the neuron channel. CURRENT=URRENT_DELTA_1+URRENT_DELTA_2, SPIKE_OUTPUT_BLOCK=LIF(CURRENT) Where LIF(CURRENT) indicates that the pulse neuron model LIF is used to update the membrane potential of the current input.

9. The method for optimizing neural network computing performance based on on-chip storage according to claim 8, characterized in that: Step (11) includes the following sub-steps: (11-1) Based on the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained in step (1-1) and the batch time step size t_batch_size obtained in step (3-3), calculate the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data SPIKE_OUTPUT_BLOCK at the cnt-th time step: SPIKE_OUTPUT_WRITE_ADDR=SPIKE_OUTPUT_BASE_ADDR+cnt·t_batch_size (11-2) Write the pulse output data SPIKE_OUTPUT_BLOCK obtained in step (10-6) to the write address obtained in step (11-1).

10. A system for optimizing neural network computing performance based on on-chip storage, characterized in that: include: The first module is used to obtain the input scale parameters of the neural network model, including the amount of pulse input data, the internal weight dimension, the external weight dimension, the total number of neurons, the total number of time steps time_steps and the input scale input_num of each time step, obtain the data base address of the neural network model in the external storage, including the base address SPIKE_DATA_BASE_ADDR of the pulse input data, the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data, the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data, and the base address SPIKE_OUTPUT_BASE_ADDR of the pulse output data, and set a storage area for storing the pulse input data, the internal weight data and the external weight data in the on-chip storage area of ​​the computing platform; The second module is used to allocate the pulse input data storage area, the internal weight storage area and the external weight storage area obtained by the first module respectively to the pulse input data storage area SPM_SPIKE_BASE_ADDR, the internal weight storage area SPM_IN_WEIGHT_BASE_ADDR and the external weight storage area SPM_EX_WEIGHT_BASE_ADDR; The third module is used to obtain the time step division parameters for iterative control according to the total number of time steps time_steps and the input scale input_num of each time step obtained in the first module, including the time step size of each batch t_batch_size, the number of time step batches t_batch_num, and the tail time step size t_tail_size; The fourth module is used to obtain the weight block parameters for scheduling according to the total number of neurons neuron_num obtained in the first module, including the internal weight block size in_n_batch_size and the internal weight tail block size in_n_tail_size. The external weight block parameters include the external weight block size ex_n_batch_size and the external weight tail block size ex_n_tail_size. The fifth module is used to obtain the internal weight data from the base address IN_WEIGHT_DATA_BASE_ADDR of the internal weight data obtained by the first module, and write the obtained internal weight data into the internal weight storage area corresponding to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained by the second module at one time; The sixth module is used to set the counter cnt=1; The seventh module is used to determine whether the counter cnt is greater than the time step batch number t_batch_num obtained in the third module. If so, the process ends, otherwise it enters the eighth module. An eighth module is configured to obtain an offset address SPIKE_DATA_OFFSET_ADDR of the pulse input data of the cnt-th time step in the external storage according to the base address SPIKE_DATA_BASE_ADDR of the pulse input data obtained by the first module and the size t_batch_size of each batch of time steps obtained by the third module, read a pulse input data block SPIKE_WRITE_BLOCK of size t_batch_size from the offset address, obtain a write address SPIKE_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_SPIKE_BASE_ADDR of the pulse input data storage area obtained by the second module and the size t_batch_size of each batch of time steps obtained by the third module, and write the read pulse input data block SPIKE_WRITE_BLOCK to the write address; The ninth module is used to obtain the offset address IN_WEIGHT_OFFSET_ADDR of the internal weight storage area at the cnt-th time step according to the base address SPM_IN_WEIGHT_BASE_ADDR of the internal weight storage area obtained by the second module and the internal weight block size in_n_batch_size obtained by the fourth module, obtain the internal weight data block IN_WEIGHT_BLOCK of size in_n_batch_size from the offset address, perform weight calculation on the pulse input data block SPIKE_WRITE_BLOCK and the internal weight data block IN_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_1, and perform neuronal current accumulation processing on the weight calculation result WEIGHT_RESULT_1 to obtain the first round of current increment CURRENT_DELTA_1 at the cnt-th time step; The tenth module is used to obtain the offset address EX_WEIGHT_OFFSET_ADDR of the external weight data in the external storage of the cnt-th time step according to the base address EX_WEIGHT_DATA_BASE_ADDR of the external weight data in the external storage obtained by the first module and the external weight block size ex_n_batch_size obtained by the fourth module, read the external weight data block EX_WEIGHT_BLOCK of size ex_n_batch_size from the offset address, obtain the write address EX_WEIGHT_WRITE_ADDR of the cnt-th time step according to the storage base address SPM_EX_WEIGHT_BASE_ADDR of the external weight storage area obtained by the second module and the external weight block size ex_n_batch_size obtained by the fourth module, and write the external weight data block EX_WEIGHT _BLOCK is written to the write address, and weight calculation is performed on the pulse input data block SPIKE_WRITE_BLOCK at the offset address written by the eighth module and the external weight data block EX_WEIGHT_BLOCK to obtain the weight calculation result WEIGHT_RESULT_2, and the weight calculation result WEIGHT_RESULT_1 is subjected to neuronal current accumulation processing to obtain the second round of current increment CURRENT_DELTA_2 at the cnt-th time step, and the second round of current increment CURRENT_DELTA_2 is accumulated with the first round of current increment CURRENT_DELTA_1 obtained in the ninth module to obtain the current current accumulation result CURRENT, and the membrane potential update operation is performed on the accumulation result CURRENT to obtain the pulse output data SPIKE_OUTPUT_BLOCK of the cnt-th time step; The eleventh module is used to obtain the write address SPIKE_OUTPUT_WRITE_ADDR of the pulse output data of the cnt-th time step according to the pulse output data base address SPIKE_OUTPUT_BASE_ADDR obtained by the first module and the time step size t_batch_size of each batch obtained by the third module, and write the pulse output data SPIKE_OUTPUT_BLOCK obtained by the tenth module to the write address; The twelfth module is used to set cnt=cnt+1 and return to the seventh module.

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