Memory CE storm suppression method, device and equipment and readable storage medium

Abstract

The invention provides a memory CE storm suppression method and device, equipment and a readable storage medium. The method comprises the steps that the number of memory CEs in a target time period is counted according to a preset algorithm; in response to a statistical result of which the statistical result is greater than a preset real threshold value, triggering a memory CE overrun alarm; and in response to an event that the memory CE over-limit alarm triggering times within the preset unit time length reach the preset target times, after the preset waiting time length, resetting the accumulated SMI interruption times of the BIOS triggered by the accumulated memory CE. According to the technical scheme, real-time CE statistics is triggered based on SMI interruption, accidental interference is filtered in combination with a preset real threshold value, invalid alarm generation is reduced, a delay reset and interruption counting zero clearing mechanism is introduced, interruption storm caused by instantaneous CE sharp increase can be blocked, and it is ensured that an SMI interruption mechanism cannot fail while the problems of CPU downtime and the like are avoided.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a memory CE storm suppression method, device, equipment, and readable storage medium. Background Art

[0002] In the field of server technology, memory is a key component for server operation, and its stability and reliability are crucial. Memory failure rate ranks second only to hard drives. While numerous memory RAS (Reliability, Availability, and Serviceability) technologies exist, RAS capabilities vary significantly across processor platforms.

[0003] In one platform scenario, significant flaws exist in the hardware design of memory CE reporting. First, the CE threshold can be set within a narrow range, such as 0-4095. Second, the memory controller's ability to trigger an SMI interrupt is limited, with only four SMI interrupt modes available: 1, a fixed number of times (e.g., 40), no SMI interrupt reporting, and unlimited triggering.

[0004] In actual operation, when a memory CE storm occurs—that is, when SMI interrupts are frequently triggered for memory CE—the excessive frequency of SMI interrupts can cause CPU crashes. This is because the BIOS continues to manage server hardware resources after the OS boots. When an SMI interrupt is triggered, the OS hands over processing to the BIOS, which then completes the process before continuing. Frequent SMI interrupts inevitably have a significant impact on OS-side business operations, including performance and functionality. CPU crashes are an unacceptable and serious consequence.

[0005] Directly disabling SMI interrupt triggering avoids host downtime caused by CE storms, but it also eliminates the CE threshold-exceeding alarm capability. CE threshold-exceeding alarms are supposed to be a warning before uncorrectable errors (UCEs) occur, alerting users to memory module status, enabling them to promptly migrate services and replace potentially risky memory modules.

[0006] If the second solution exists, its disadvantage is also closely related to the technical problem that the present invention aims to solve, that is, it cannot effectively balance the relationship between avoiding CPU downtime caused by CE storm and normally reporting CE over-threshold alarms. Summary of the Invention

[0007] In view of this, the present disclosure provides a memory CE storm suppression method, device, electronic device, and readable storage medium to improve the above-mentioned problem of balancing memory CE storm when the memory CE overlimit warning is enabled.

[0008] The specific technical solutions are as follows:

[0009] This specification provides a memory CE storm suppression method, which is applied to a server. The method includes: in response to an SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, counting the number of memory CEs within a target time period according to a preset algorithm; in response to a statistical result that is greater than a preset real threshold, triggering a memory CE over-limit alarm; in response to an event in which the number of memory CE over-limit alarm triggers reaches a preset target number within a preset unit time length, marking the occurrence of a memory CE storm event; in response to the memory CE storm event, after a preset waiting time, resetting the accumulated number of SMI interrupts of the BIOS triggered by the accumulated memory CE, and removing the mark of the memory CE storm event.

[0010] As a technical solution, the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to a preset algorithm, including: the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to the SMI interrupt calculation times and the target time period; the target time period is the time period from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs; the first SMI interrupt is the first SMI interrupt that occurs after resetting the cumulative number of SMI interrupts triggered by the BIOS for the accumulated memory CE, or the first SMI interrupt that occurs after the most recent memory CE over-limit alarm is triggered; the SMI interrupt calculation times are the cumulative number of SMI interrupts that occur from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs.

[0011] As a technical solution, the number of memory CEs within the target time period is calculated based on the number of SMI interrupt calculations and the target time period, including: multiplying the number of SMI interrupt calculations by a preset threshold, subtracting a funnel mechanism parameter, to obtain the number of memory CEs within the target time period; the funnel mechanism parameter is positively correlated with the length of the target time period.

[0012] As a technical solution, in response to a memory CE storm event, after a preset waiting time, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset, and the mark of the occurrence of the memory CE storm event is eliminated, including: recording the number of eliminations of the memory CE storm event; the preset waiting time is a preset variable time length that is positively correlated with the number of eliminations.

[0013] As a technical solution, the elimination mark of the memory CE storm event includes: starting a recovery timer, and if the memory CE overrun alarm does not occur again after a preset recovery time, resetting the elimination count.

[0014] As a technical solution, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset periodically, wherein the period interval is greater than the preset waiting time.

[0015] This specification also provides a memory CE storm suppression device, which is applied to a server. The device includes: a first module, which is used to respond to the SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, count the number of memory CEs within the target time period according to a preset algorithm, and trigger a memory CE over-limit alarm in response to the statistical result being greater than the preset real threshold; a second module, which is used to respond to the event that the number of memory CE over-limit alarm triggers reaches a preset target number within a preset unit time length, and mark the occurrence of a memory CE storm event; a third module, which is used to respond to the memory CE storm event, reset the accumulated number of SMI interrupts of the BIOS triggered by the accumulated memory CE after a preset waiting time, and clear the mark of the memory CE storm event.

[0016] As a technical solution, the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to a preset algorithm, including: the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to the SMI interrupt calculation times and the target time period; the target time period is the time period from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs; the first SMI interrupt is the first SMI interrupt that occurs after resetting the cumulative number of SMI interrupts triggered by the BIOS for the accumulated memory CE, or the first SMI interrupt that occurs after the most recent memory CE over-limit alarm is triggered; the SMI interrupt calculation times are the cumulative number of SMI interrupts that occur from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs.

[0017] As a technical solution, the number of memory CEs within the target time period is calculated based on the number of SMI interrupt calculations and the target time period, including: multiplying the number of SMI interrupt calculations by a preset threshold, subtracting a funnel mechanism parameter, to obtain the number of memory CEs within the target time period; the funnel mechanism parameter is positively correlated with the length of the target time period.

[0018] As a technical solution, in response to a memory CE storm event, after a preset waiting time, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset, and the mark of the occurrence of the memory CE storm event is eliminated, including: recording the number of eliminations of the memory CE storm event; the preset waiting time is a preset variable time length that is positively correlated with the number of eliminations.

[0019] As a technical solution, the elimination mark of the memory CE storm event includes: starting a recovery timer, and if the memory CE overrun alarm does not occur again after a preset recovery time, resetting the elimination count.

[0020] As a technical solution, the third module is further used to periodically reset the accumulated number of SMI interruptions of the BIOS triggered by the memory CE, wherein the period interval is greater than the preset waiting time.

[0021] This specification also provides an electronic device, including a processor and a readable storage medium, wherein the readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the aforementioned memory CE storm suppression method.

[0022] This specification also provides a readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the aforementioned memory CE storm suppression method.

[0023] The above technical solutions provided in this specification bring at least the following beneficial effects:

[0024] Real-time CE statistics are triggered based on SMI interrupts, combined with preset real thresholds to filter occasional interference, reduce the generation of invalid alarms, and introduce delayed reset and interrupt count clearing mechanisms. While blocking interrupt storms caused by instantaneous CE surges and avoiding CPU crashes, it ensures that the SMI interrupt mechanism will not fail. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the implementation methods of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the implementation methods of this specification or the description of the prior art. Obviously, the drawings described below are only some implementation methods recorded in this specification. For ordinary technicians in this field, other drawings can also be obtained based on these drawings of the implementation methods of this specification.

[0026] Figure 1 This is a flow chart of a memory CE storm suppression method in one embodiment of this specification;

[0027] Figure 2 It is a structural diagram of a memory CE storm suppression device in one embodiment of this specification;

[0028] Figure 3 This is a hardware structure diagram of an electronic device in one embodiment of this specification.

[0029] Reference numerals: first module 21 , second module 22 , third module 23 . DETAILED DESCRIPTION

[0030] The terms used in the embodiments of this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The singular forms "a," "the," and "the" used in this specification and claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to any or all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when...", "when...", or "in response to determining."

[0032] This specification provides a memory CE storm suppression method, device, electronic device, and readable storage medium to at least improve one of the above technical problems.

[0033] The specific technical solution is described below.

[0034] In one embodiment, the present specification provides a memory CE storm suppression method, which is applied to a server, and the method includes: in response to an SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, counting the number of memory CEs within a target time period according to a preset algorithm; in response to a statistical result that is greater than a preset real threshold, triggering a memory CE overlimit alarm; in response to an event in which the number of memory CE overlimit alarm triggerings reaches a preset target number within a preset unit time length, marking the occurrence of a memory CE storm event; in response to the memory CE storm event, after a preset waiting time, resetting the accumulated number of SMI interruptions of the BIOS triggered by the memory CE, and removing the mark of the memory CE storm event; when the accumulated number of SMI interruptions of the BIOS triggered by the memory CE reaches the SMI interruption threshold, stopping the triggering of the SMI interruption threshold.

[0035] Specifically, if Figure 1 , including the following steps:

[0036] Step S11 , in response to the SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, the number of memory CEs within a target time period is counted according to a preset algorithm.

[0037] A preset threshold is set. When the number of correctable errors (CE) in memory reaches this threshold, a System Management Interrupt (SMI) is triggered to the BIOS. This step is based on hardware design. Taking the Hygon platform as an example, due to platform hardware limitations, there are certain limitations in setting the CE threshold. In practice, the hardware register is set to the maximum value of 4095. After receiving the SMI interrupt, the BIOS software performs further processing based on the funnel and the actual threshold.

[0038] Once an SMI interrupt is triggered, the number of memory CE errors within the target time period is counted. A funnel mechanism algorithm can be used here, although other algorithms that meet the needs of the scenario are also feasible. Using a software-level funnel mechanism to simulate the hardware funnel function helps filter out occasional CE errors that do not affect system stability, focusing on clusters of CE errors that may indicate more serious problems.

[0039] Step S12: In response to the statistical result being greater than a preset real threshold, a memory CE over-limit alarm is triggered.

[0040] When the statistics show that the number of CEs exceeds the preset threshold, the system triggers a memory CE limit alarm. This alarm not only serves as a warning of the current memory status, but also serves as an important basis for subsequent actions.

[0041] Step S13: In response to the event that the number of memory CE over-limit alarm triggering times reaches a preset target number within a preset unit time, a memory CE storm event is marked as occurring.

[0042] If the memory CE limit alarm is triggered multiple times in a short period of time during server operation, it may mean that the system is experiencing a CE storm.

[0043] At this point, the system needs to further determine whether the target number of memory CE limit alarm triggering times within the preset unit time has been reached. If a CE storm event is confirmed, the system will mark this situation and initiate appropriate countermeasures.

[0044] Step S14, in response to the memory CE storm event, after a preset waiting time, reset the accumulated number of SMI interrupts of the BIOS triggered by the memory CE, and clear the mark of the memory CE storm event.

[0045] For events marked as CE storms, after a preset waiting period, the accumulated number of SMI interrupts triggered by the BIOS by the memory CE is reset, and the previously marked CE storm events are eliminated. The preset waiting period can be a fixed value, such as 5 minutes, 6 minutes, etc. In one embodiment, the preset waiting period may not be fixed, but dynamically adjusted according to actual conditions. For example, after the CE storm mark is triggered for the first time, the system may wait for 5 minutes to reactivate the SMI interrupt function; if the CE storm has not subsided during this period, the next waiting period will be doubled to 10 minutes, and so on. The purpose of this design is to give the system enough time to calm down, while preventing excessive burden from attempting to reset the SMI interrupt too frequently.

[0046] When the cumulative number of SMI interrupts triggered by the BIOS by the accumulated memory CE reaches the preset SMI interrupt threshold (such as 40 times), the system will stop triggering new SMI interrupts and reset the number, that is, reactivate the SMI interrupt function, which can prevent the SMI interrupt function associated with the memory CE from failing. Therefore, the SMI interrupt function associated with the memory CE can be kept enabled under a lower SMI interrupt threshold, and at the same time, the CPU can be protected from excessive interrupt requests, avoiding performance degradation or even downtime due to frequent entry into SMI mode.

[0047] In one embodiment, the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to a preset algorithm, including: the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to the SMI interrupt calculation times and the target time period; the target time period is the time period from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs; the first SMI interrupt is the first SMI interrupt that occurs after resetting the cumulative number of SMI interrupts triggered by the BIOS for the accumulated memory CE, or the first SMI interrupt that occurs after the most recent memory CE over-limit alarm is triggered; the SMI interrupt calculation times are the cumulative number of SMI interrupts that occur from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs.

[0048] In one embodiment, the number of memory CEs within the target time period is calculated based on the number of SMI interrupt calculations and the target time period, including: multiplying the number of SMI interrupt calculations by a preset threshold, subtracting a funnel mechanism parameter, to obtain the number of memory CEs within the target time period; the funnel mechanism parameter is positively correlated with the length of the target time period.

[0049] See the following formula:

[0050] Time目标时间段 =t 当前SMI中断 -t 第一SMI中断

[0051] Reduce 漏斗机制参数 =Time 目标时间段 / (F 漏斗频率 ×Count 单位时间漏CE个数 )

[0052] Total CE个数 =∑C SMI中断次数 ×4096

[0053] (Total CE个数 -Reduce 漏CE总数 )>Threshold CE阈值

[0054] Threshold CE阈值 is the actual threshold value, which can be set arbitrarily according to the needs of the scene; 4096 is the pre-configured threshold value taking the Haiguang platform as an example, and this value should be adjusted according to the actual configuration; F 漏斗频率 The frequency can be pre-configured, such as once every 1 second, once every 15 seconds, once every minute, etc. 单位时间漏CE个数 The number of CEs that should be missed each time the funnel mechanism is triggered, such as 1, 2, etc.

[0055] In one embodiment, in response to a memory CE storm event, after a preset waiting time, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset, and the mark of the occurrence of the memory CE storm event is eliminated, including: recording the number of eliminations of the memory CE storm event; the preset waiting time is a preset variable time length that is positively correlated with the number of eliminations.

[0056] If at least five memory CE limit exceeding alarms are received within one minute, a memory CE storm is marked as occurring. The timer starts counting each time a memory CE limit exceeding event is received. If no next memory CE limit exceeding warning is received within the preset waiting time, such as 5 minutes or 10 minutes, a GPIO-style SMI interrupt is triggered, which the BMC transmits to the BIOS. The SMI interrupt count is reset. This may be because the SMI interrupt count set on the BIOS side has reached the upper limit, or the memory CE storm has stopped.

[0057] The above preset waiting time is positively correlated with the number of eliminations that have occurred, such as 5 minutes for the first time and 10 minutes for the second time, or 10 minutes for the first time and 30 minutes for the second time, to avoid frequent resetting of the SMI interruption number.

[0058] In one embodiment, the elimination marking of a memory CE storm event includes: starting a recovery timer, and if the memory CE limit overrun alarm does not occur again after a preset recovery time, resetting the elimination count.

[0059] If the memory CE limit alarm is not triggered again for a long time, the memory CE storm is considered to be over and the elimination count is reset to restore the initial state.

[0060] In one embodiment, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset periodically, wherein the period interval is greater than the preset waiting time.

[0061] Regularly, such as daily or weekly, proactively trigger the reset to avoid mechanism failure.

[0062] In one embodiment, Figure 2 , this specification also provides a memory CE storm suppression device, which is applied to a server, and the device includes: a first module, which is used to respond to the SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, count the number of memory CEs in the target time period according to a preset algorithm, and trigger a memory CE over-limit alarm in response to the statistical result being greater than the preset real threshold; a second module, which is used to respond to the event that the number of memory CE over-limit alarm triggers reaches a preset target number within a preset unit time length, mark the occurrence of a memory CE storm event; a third module, which is used to respond to the memory CE storm event, reset the accumulated number of SMI interrupts of the BIOS triggered by the accumulated memory CE after a preset waiting time, and clear the mark of the memory CE storm event.

[0063] In one embodiment, the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to a preset algorithm, including: the SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold counts the number of memory CEs within the target time period according to the SMI interrupt calculation times and the target time period; the target time period is the time period from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs; the first SMI interrupt is the first SMI interrupt that occurs after resetting the cumulative number of SMI interrupts triggered by the BIOS for the accumulated memory CE, or the first SMI interrupt that occurs after the most recent memory CE over-limit alarm is triggered; the SMI interrupt calculation times are the cumulative number of SMI interrupts that occur from the time the first SMI interrupt occurs to the time the current SMI interrupt occurs.

[0064] In one embodiment, the number of memory CEs within the target time period is calculated based on the number of SMI interrupt calculations and the target time period, including: multiplying the number of SMI interrupt calculations by a preset threshold, subtracting a funnel mechanism parameter, to obtain the number of memory CEs within the target time period; the funnel mechanism parameter is positively correlated with the length of the target time period.

[0065] In one embodiment, in response to a memory CE storm event, after a preset waiting time, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset, and the mark of the occurrence of the memory CE storm event is eliminated, including: recording the number of eliminations of the memory CE storm event; the preset waiting time is a preset variable time length that is positively correlated with the number of eliminations.

[0066] In one embodiment, the elimination marking of a memory CE storm event includes: starting a recovery timer, and if the memory CE limit overrun alarm does not occur again after a preset recovery time, resetting the elimination count.

[0067] In one embodiment, the third module is further configured to periodically reset the accumulated number of SMI interruptions of the BIOS triggered by the memory CE, wherein the periodic interval is greater than the preset waiting time.

[0068] The device implementation is the same as or similar to the corresponding method implementation, and will not be repeated here.

[0069] In one embodiment, this specification provides an electronic device, including a processor and a readable storage medium, wherein the readable storage medium stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the aforementioned memory CE storm suppression method. From the hardware level, the hardware architecture diagram can be seen in Figure 3 shown.

[0070] In one embodiment, this specification provides a readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the aforementioned memory CE storm suppression method.

[0071] Here, the readable storage medium can be any electronic, magnetic, optical or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, the readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as optical disk, DVD, etc.), or similar storage media, or a combination thereof.

[0072] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email transceiver, game console, tablet computer, wearable device, or any combination of these devices.

[0073] For the convenience of description, the above devices are described as being divided into various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0074] Those skilled in the art will appreciate that embodiments of this specification may be provided as methods, systems, or computer program products. Thus, this specification may take the form of a fully hardware implementation, a fully software implementation, or an implementation combining software and hardware. Furthermore, embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0076] Furthermore, these computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0077] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0078] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Thus, this specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0079] The foregoing is merely an embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be included within the scope of the claims of the present invention.

Claims

1. A memory CE storm suppression method, characterized in that: Applied to a server, the method includes: In response to an SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, the number of memory CEs within a target time period is counted according to a preset algorithm; In response to a statistical result that is greater than a preset real threshold, a memory CE over-limit alarm is triggered; In response to the event that the number of memory CE over-limit alarm triggering times reaches a preset target number within a preset unit time length, a memory CE storm event is marked; In response to a memory CE storm event, after a preset waiting time, the accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset, and the mark of the memory CE storm event is cleared.

2. The method according to claim 1, characterized in that The SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold, and counting the number of memory CEs within a target time period according to a preset algorithm, includes: In response to an SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, the number of memory CEs within the target time period is calculated based on the number of SMI interrupts and the target time period; The target time period is the time period from the time when the first SMI interrupt occurs to the time when the current SMI interrupt occurs; The first SMI interrupt is the first SMI interrupt that occurs after resetting the cumulative number of SMI interrupts of the BIOS triggered by the accumulated memory CE, or the first SMI interrupt that occurs after the most recent memory CE over-limit alarm is triggered; The calculated number of SMI interruptions is the cumulative number of SMI interruptions that have occurred since the first SMI interruption occurred until the current SMI interruption occurs.

3. The method according to claim 2, characterized in that Calculating the number of memory CEs within the target time period based on the number of SMI interrupt calculations and the target time period includes: The number of memory CEs within the target time period is obtained by multiplying the number of SMI interrupt calculations by the preset threshold and subtracting the funnel mechanism parameter; The funnel mechanism parameters are positively correlated with the duration of the target time period.

4. The method according to claim 1, wherein The method of responding to the memory CE storm event, resetting the accumulated number of SMI interrupts of the BIOS triggered by the memory CE after a preset waiting time, and removing the mark of the memory CE storm event, includes: Record the number of times the memory CE storm event is cleared; The preset waiting time is a preset variable time that is positively correlated with the number of eliminations.

5. The method according to claim 4, characterized in that The elimination of the memory CE storm event includes: The recovery timer is started. If the memory CE limit exceeding alarm does not occur again after the preset recovery time, the number of elimination times is reset.

6. The method according to claim 1, characterized in that The accumulated number of SMI interruptions of the BIOS triggered by the memory CE is reset periodically, wherein the period interval is greater than the preset waiting time.

7. A memory CE storm suppression device, characterized in that: Applied to a server, the device includes: The first module is configured to respond to an SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, count the number of memory CEs within a target time period according to a preset algorithm, and trigger a memory CE over-limit alarm in response to a statistical result that is greater than a preset real threshold; The second module is used to mark the occurrence of a memory CE storm event in response to an event in which the number of memory CE over-limit alarm triggering times reaches a preset target number within a preset unit time length; The third module is used to respond to the memory CE storm event, reset the accumulated number of SMI interrupts of the BIOS triggered by the memory CE after a preset waiting time, and clear the mark of the memory CE storm event.

8. The device according to claim 7, characterized in that The SMI interrupt triggered to the BIOS in response to the memory CE reaching a preset threshold, and counting the number of memory CEs within a target time period according to a preset algorithm, includes: In response to an SMI interrupt triggered to the BIOS when the memory CE reaches a preset threshold, the number of memory CEs within the target time period is calculated based on the number of SMI interrupts and the target time period; The target time period is the time period from the time when the first SMI interrupt occurs to the time when the current SMI interrupt occurs; The first SMI interrupt is the first SMI interrupt that occurs after resetting the cumulative number of SMI interrupts of the BIOS triggered by the accumulated memory CE, or the first SMI interrupt that occurs after the most recent memory CE over-limit alarm is triggered; The calculated number of SMI interruptions is the cumulative number of SMI interruptions that have occurred since the first SMI interruption occurred until the current SMI interruption occurs.

9. The device according to claim 8, characterized in that Calculating the number of memory CEs within the target time period based on the number of SMI interrupt calculations and the target time period includes: The number of memory CEs within the target time period is obtained by multiplying the number of SMI interrupt calculations by the preset threshold and subtracting the funnel mechanism parameter; The funnel mechanism parameters are positively correlated with the duration of the target time period.

10. The device according to claim 7, characterized in that The method of responding to the memory CE storm event, resetting the accumulated number of SMI interrupts of the BIOS triggered by the memory CE after a preset waiting time, and removing the mark of the memory CE storm event, includes: Record the number of times the memory CE storm event is cleared; The preset waiting time is a preset variable time that is positively correlated with the number of eliminations.

11. The device according to claim 10, characterized in that The elimination of the memory CE storm event includes: The recovery timer is started. If the memory CE limit exceeding alarm does not occur again after the preset recovery time, the number of elimination times is reset.

12. The device according to claim 7, characterized in that The third module is further configured to periodically reset the accumulated number of SMI interruptions of the BIOS triggered by the memory CE, wherein the period interval is greater than the preset waiting time.

13. An electronic device, characterized in that: include: A processor and a readable storage medium, wherein the readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the method according to any one of claims 1 to 6.

14. A readable storage medium, characterized in that The readable storage medium stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the method according to any one of claims 1 to 6.

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