Data processing method, processor core and electronic equipment

Abstract

The invention provides a data processing method, which comprises the following steps that: a data request node sends a data reading request to a main memory based on a first communication path, and the data reading request is used for requesting to read first data; the data request node sends a data prefetching request to the main memory according to a data prefetching strategy based on a second communication path, and the data prefetching request is used for requesting to read the first data; storing the first data in a data cache; and the data request node reads the first data.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data processing method, a processor core, and an electronic device. Background Art

[0002] Processor cores often request data from other cores. Alternatively, when a processor core is connected to an external device such as memory, the processor core may request data from the external device. Because a processor core can access data from another processor core or an external device through multiple communication channels, how to quickly obtain data with minimal latency is a pressing issue. Summary of the Invention

[0003] Embodiments of the present application provide a data processing method, a processor core, and an electronic device, so that the processor core can quickly acquire data with a small time delay.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a data processing method, the method comprising:

[0006] The data requesting node sends a data read request to the main memory based on the first communication path, wherein the data read request is used to request to read the first data;

[0007] The data requesting node sends a data prefetch request to the main memory based on the second communication path according to the data prefetch strategy, where the data prefetch request is used to request to read the first data;

[0008] storing the first data in a data cache;

[0009] The data requesting node reads the first data.

[0010] In some optional embodiments, the data requesting node sending the data prefetch request to the main memory based on the second communication path according to the data prefetch strategy includes:

[0011] The data requesting node sends a data prefetching request to the first node located on the second communication path according to the data prefetching strategy, so that the first node reads the first data from the main memory based on the data prefetching request.

[0012] In some optional embodiments, the method further comprises:

[0013] Setting a first counter for the data prefetching strategy, wherein the first counter is used to count the number of times the data requesting node reads data from the main memory based on the first communication path;

[0014] If the value of the first counter reaches a first threshold, the data pre-fetching strategy is adjusted from the first strategy to a second strategy, so as to obtain data from the main memory based on the second communication path.

[0015] In some optional embodiments, the method further comprises:

[0016] Setting a second counter for the data prefetching strategy, the second counter being used to count the number of requests by the data requesting node to read data from the main memory based on the first communication path without prefetching data from the main memory based on the second communication path;

[0017] If the value of the second counter reaches a second threshold, the data prefetching strategy is adjusted from the second strategy to a third strategy to increase the frequency of obtaining data from the main memory based on the second communication path.

[0018] In some optional embodiments, the method further comprises:

[0019] Setting a third counter for the data prefetch strategy, the third counter being used to count the number of times the data requesting node sends a data prefetch request and the data received by the data requesting node does not carry a prefetch identifier, and being used to count the number of times the data requesting node generates a data prefetch request and the data prefetch request is not sent to the main memory;

[0020] If the value of the third counter reaches a third threshold, the data prefetching strategy is adjusted from the third strategy to the second strategy to reduce the frequency of obtaining data from the main memory based on the second communication path.

[0021] In some optional embodiments, the method further comprises:

[0022] If the data prefetching strategy is adjusted, the value of the counter corresponding to the data prefetching strategy before the adjustment is cleared.

[0023] In some optional embodiments, the data requesting node reading the first data includes:

[0024] The node corresponding to the main memory receives the data read request;

[0025] The node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request;

[0026] If the first data is stored in the data cache, the node corresponding to the main memory reads the first data from the data cache;

[0027] The data requesting node receives the first data sent by the node corresponding to the main memory.

[0028] In some optional embodiments, the data requesting node reading the first data includes:

[0029] The node corresponding to the main memory receives the data read request;

[0030] The node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request;

[0031] If the first data is not stored in the data cache, the node corresponding to the main memory reads the first data from the main memory;

[0032] The data requesting node receives the first data sent by the node corresponding to the main memory.

[0033] In some optional embodiments, the method further includes: configuring the data prefetching strategy in a register.

[0034] In a second aspect, an embodiment of the present application provides a processor core, the processor core being located at a data requesting node, the processor core comprising:

[0035] A first sending unit, configured to send a data read request to the main memory based on the first communication path, wherein the data read request is used to request to read first data;

[0036] a second sending unit, configured to send a data prefetch request to the main memory based on a second communication path and in accordance with a data prefetch strategy, wherein the data prefetch request is used to request reading of the first data;

[0037] A storage unit, configured to store the first data in a data cache;

[0038] A reading unit, configured to read the first data:

[0039] In a third aspect, an embodiment of the present application provides an electronic device, comprising: at least one processor; and

[0040] a memory communicatively connected to the at least one processor; wherein,

[0041] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned data processing method.

[0042] The data processing method provided in an embodiment of the present application includes: a data requesting node sends a data read request to the main memory based on a first communication path, wherein the data read request is used to request to read the first data; the data requesting node sends a data prefetch request to the main memory based on a second communication path in accordance with a data prefetch strategy, wherein the data prefetch request is used to request to read the first data; the first data is stored in a data cache; and the data requesting node reads the first data. In an embodiment of the present application, the first data is obtained by the data requesting node based on the second communication path in accordance with the data prefetch strategy, and the first data is stored in the data cache, so that when the data requesting node or other data requesting nodes request to obtain the first data again, they can directly read the data from the data cache, thereby reducing the delay in reading the data and increasing the speed of reading the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a processing flow diagram of the data processing method provided in an embodiment of the present application;

[0044] Figure 2 This is a detailed processing flow diagram of the data processing method provided in the embodiment of the present application;

[0045] Figure 3 This is a schematic diagram of the structure of a multi-level cache provided in an embodiment of the present application;

[0046] Figure 4 This is a schematic diagram of a secondary cache reading data from a main memory in the related art;

[0047] Figure 5 This is a schematic diagram of a secondary cache reading data from a main memory provided by an embodiment of the present application;

[0048] Figure 6 This is a schematic diagram of the structure of the Mesh network provided in the embodiment of the present application;

[0049] Figure 7 Schematic diagram of the structure of the processor core provided in the embodiment of the present application;

[0050] Figure 8 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limiting this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0052] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0053] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0055] It should be understood that in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0056] Before further explaining the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0057] 1) Processor core: It is the most core part of the processor and can also be called the processor core.

[0058] 2) Cache, also known as high-speed cache memory, is used to better exploit the principle of locality and reduce the number of times the central processing unit (CPU) accesses main memory. Simply put, the instructions and data currently being accessed by the CPU may be accessed multiple times later, or the memory area near these instructions and data may also be accessed multiple times. Therefore, when accessing this area for the first time, it is copied to the cache. Subsequent accesses to instructions or data in this area do not require retrieving them from main memory.

[0059] 3) Mesh networks, which connect multiple devices or nodes and exchange data directly, achieve self-organization, self-healing, and efficient communication. Each node in a mesh network can not only send and receive data but also act as a relay node, helping other nodes forward information.

[0060] 4) Main memory, also known as main memory, is an important component of computer hardware. Its function is to store instructions and data and can be directly accessed randomly by the CPU.

[0061] For example, in a multi-level cache processor, if a data read request is lost in the cache, the data must be retrieved from the next level of cache or main memory. The latency associated with retrieving data from the next level of cache or main memory is a significant component of processor latency. Long latency can severely impact cache performance and slow down the processor's data retrieval process.

[0062] The data processing method provided in the embodiments of the present application can at least solve the above problems.

[0063] A processing flow diagram of the data processing method provided in the embodiment of the present application is as follows: Figure 1 As shown, at least the following steps are included:

[0064] In step S101 , a data requesting node sends a data read request to a main memory based on a first communication path, where the data read request is used to request to read first data.

[0065] In some embodiments, the data requesting node is a node for requesting to obtain the first data, and the data requesting node may also be referred to as a request node (RN). The data requesting node may be a processor core located in a processor.

[0066] In some embodiments, the first communication path may include one or more nodes, which may also be referred to as Home Nodes. The Home Node may be located in the internal interconnect of the processor, receive a request from the RN, perform a consistency operation corresponding to the request, and respond to the request.

[0067] Step S102: The data requesting node sends a data prefetch request to the main memory based on the second communication path and in accordance with a data prefetch strategy, where the data prefetch request is used to request to read the first data.

[0068] In some embodiments, the first communication path is different from the second communication path; specifically, the Home Node passed by the first communication path is not exactly the same as or is completely different from the Home Node passed by the second communication path; the starting point and end point of the first communication path and the second communication path are exactly the same.

[0069] In some embodiments, the data requesting node may simultaneously send a data prefetch request over the second communication path and a data read request over the first communication path. The time interval between the data requesting node sending the data prefetch request over the second communication path and sending the data read request over the first communication path may be less than a preset time threshold. The time threshold can be flexibly set based on actual needs.

[0070] In some embodiments, the data prefetch strategy can be configured through a system register. As an example, the data prefetch strategy may include at least a first strategy, a second strategy, a third strategy, and a fourth strategy. Two bits are configured in the system register to indicate the current data prefetch strategy. For example, if the two bits are 01, it indicates that the data prefetch strategy is the first strategy; if the two bits are 10, it indicates that the data prefetch strategy is the second strategy; if the two bits are 11, it indicates that the data prefetch strategy is the third strategy; if the two bits are 00, it indicates that the data prefetch strategy is the fourth strategy. Among them, the first strategy may be not sending any data prefetch request. The second strategy may be sending a data prefetch request when the number of times the data request node reads data from the main memory based on the first communication path reaches a first value; for example, if the first value is 10, the number of times the data request node reads data from the main memory based on the first communication path reaches 10 times, then when the data request node sends a data read request to the main memory based on the first communication path for the 11th time, the data request node sends a data prefetch request based on the second communication path at the same time or within a time threshold. A third strategy may be to send a data prefetch request when the number of times the data requesting node reads data from the main memory via the first communication path reaches a second value. For example, if the second value is 5, and the number of times the data requesting node reads data from the main memory via the first communication path reaches 5, then when the data requesting node sends a data read request to the main memory via the first communication path for the sixth time, the data requesting node simultaneously sends a data prefetch request via the second communication path or within a time threshold; wherein the first value is greater than the second value. A fourth strategy may be to send a data prefetch request via the second communication path each time the data requesting node sends a data read request to the main memory via the first communication path, or within a time threshold.

[0071] In some embodiments, the number of times a data requesting node reads data from the main memory based on the first communication path can be counted by a first counter. Specifically, a first counter for a data prefetching strategy can be set, and the first counter can be a logic circuit. If the value of the first counter reaches a first threshold, the data prefetching strategy is adjusted from the first strategy to the second strategy to obtain data from the main memory based on the second communication path. The value of the first threshold can be flexibly set according to the actual scenario. As an example, if the first threshold is set to 30, when the first counter statistics data requesting node reads data from the main memory based on the first communication path 30 times, the data prefetching strategy is adjusted from the first strategy to the second strategy.

[0072] In some embodiments, the data requesting node does not prefetch data from the main memory via the second communication path, and the number of requests by the data requesting node to read data from the main memory via the first communication path can be counted using a second counter. Specifically, a second counter for the data prefetching strategy can be set, and the second counter can be a logic circuit. If the value of the second counter reaches a second threshold, the data prefetching strategy is adjusted from the second strategy to a third strategy to increase the frequency of obtaining data from the main memory via the second communication path. The value of the second threshold can be flexibly set according to the actual scenario. As an example, if the second threshold is set to 50, when the second counter counts that the data requesting node does not prefetch data from the main memory via the second communication path, and the number of requests to read data from the main memory via the first communication path reaches 50, the data prefetching strategy is adjusted from the second strategy to the third strategy. In a specific implementation, after the second counter is reset to 0, if the data requesting node only sends data read requests to the main memory via the first communication path and does not additionally send data prefetch requests to the main memory via the second communication path, the count value of the second counter is increased by one. If the data requesting node sends a data prefetch request to the main memory based on the second communication path, but the data received by the data requesting node does not carry the prefetch flag, the count value of the second counter is cleared to zero, indicating that the data prefetch request sent by the data requesting node based on the second communication path is invalid.

[0073] By setting a first counter, the number of times the data requesting node reads data from the main memory based on the first communication path can be counted, thereby adjusting the data prefetching strategy from the first strategy to the second strategy, so that the data requesting node can read data from the main memory based on the second communication path, thereby reducing the delay in reading data. By setting a second counter, the number of requests for the data requesting node to read data from the main memory based on the first communication path without prefetching data from the main memory based on the second communication path can be counted, thereby adjusting the data prefetching strategy from the second strategy to the third strategy, so that the data requesting node can read data from the main memory based on the second communication path at a greater frequency, thereby reducing the delay in reading data.

[0074] In a specific implementation, if the data prediction strategy is adjusted from the third strategy to the second strategy, this can be achieved by setting a third counter. Specifically, the third counter is used to count the number of times the data request node sends a data prefetch request and the data received by the data request node does not carry a prefetch identifier, and is used to count the number of times the data request node generates a data prefetch request and the data prefetch request is not sent to the main memory; if the value of the third counter reaches a third threshold, the data prefetch strategy is adjusted from the third strategy to the second strategy to reduce the frequency of obtaining data from the main memory based on the second communication path.

[0075] It should be noted that in the embodiments of the present application, when the data prefetch strategy is adjusted, the counter corresponding to the data prefetch strategy before the adjustment is cleared. As an example, if the data prefetch strategy is adjusted from the first strategy to the second strategy, the first counter is cleared. If the data prefetch strategy is adjusted from the second strategy to the third strategy, the second counter is cleared. If the data prefetch strategy is adjusted from the third strategy to the second strategy, the third counter is cleared.

[0076] Step S103: store the first data in a data cache.

[0077] In some embodiments, the data cache may be a cache or the like.

[0078] Step S104: the data requesting node reads the first data.

[0079] In some embodiments, when a data requesting node sends a data read request to a node corresponding to a main memory through a Home Node, the node corresponding to the main memory determines whether the first data is stored in a data cache based on the data read request. If the first data is stored in the data cache, the node corresponding to the main memory directly reads the first data from the data cache and sends the first data to the data requesting node. The node corresponding to the main memory reading the first data from the data cache can reduce data read latency and increase data read speed.

[0080] In some embodiments, when the data requesting node Home Node sends a data read request to the node corresponding to the main memory, the node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request; if the first data is not stored in the data cache, the node corresponding to the main memory reads the first data from the main memory; the data requesting node receives the first data sent by the node corresponding to the main memory.

[0081] In some embodiments, the default data prefetching strategy can be flexibly set to one of the first strategy, the second strategy, the third strategy, and the fourth strategy according to actual scenarios; for example, the default data prefetching strategy can be set to the first strategy.

[0082] A detailed processing flow diagram of the data processing method provided in the embodiment of the present application is as follows: Figure 2 As shown, at least the following steps are included:

[0083] In step S201 , a first data requesting node sends a first data read request to a main memory based on a first communication path, where the first data read request is used to request to read first data.

[0084] Step S202: confirm that the data prefetching strategy is the default data prefetching strategy.

[0085] In some embodiments, the default data prefetching strategy is a first strategy.

[0086] In the embodiment of the present application, the data pre-fetching strategy and the first strategy are the same as the data pre-fetching strategy and the first strategy in the above step S102, and are not repeated here.

[0087] Step S203: The first counter counts the number of times each data requesting node reads data from the main memory based on the first communication path.

[0088] Step S204 : If it is determined that the number of times each data requesting node reads data from the main memory based on the first communication path counted by the first counter reaches a first threshold, the data prefetching strategy is adjusted from the first strategy to the second strategy.

[0089] In some embodiments, when the number of times each data requesting node reads data from main memory via the first communication path, as counted by the first counter, reaches a first threshold, this indicates that each data requesting node is frequently reading data from main memory via the first communication path, potentially leading to data read delays. Therefore, in this scenario, the first strategy is adjusted to the second strategy, increasing the number of data prefetch requests sent via the second communication path. This increases the number of data acquisition requests received via the second communication path and allows subsequent data requesting nodes to quickly read data from the data cache.

[0090] In an embodiment of the present application, the second strategy may be to send a data prefetch request when the number of times the data requesting node reads data from the main memory via the first communication path reaches a first value. For example, if the first value is 10, and the number of times the data requesting node reads data from the main memory via the first communication path reaches 10, then when the data requesting node sends a data read request to the main memory via the first communication path for the 11th time, the data requesting node simultaneously sends a data prefetch request via the second communication path or within a time threshold. In some embodiments, after the data prefetch strategy is adjusted from the first strategy to the second strategy, the value of the first counter is reset to zero.

[0091] Step S205 : A second counter counts the number of requests by each data requesting node to read data from the main memory based on the first communication path without pre-fetching data from the main memory based on the second communication path.

[0092] Specifically, the second counter can count the number of requests for the data requesting node to read data from the main memory based on the first communication path without the data requesting node pre-fetching data from the main memory based on the second communication path.

[0093] Step S206: If it is determined that the data requesting nodes counted by the second counter do not pre-fetch data from the main memory based on the second communication path, and the number of requests to read data from the main memory based on the first communication path reaches a second threshold, the data pre-fetching strategy is adjusted from the second strategy to the third strategy.

[0094] In some embodiments, a second counter counts the number of data requesting nodes that have not pre-fetched data from the main memory based on the second communication path. When the number of requests by data requesting nodes to read data from the main memory based on the first communication path reaches a second threshold, it indicates that more data requests are needed from each data requesting node to be transmitted based on the second communication path. In this scenario, the second strategy is adjusted to the third strategy, and the number of data pre-fetching requests sent based on the second communication path is increased to obtain more data through the second communication path, and the data is stored in the data cache, so that subsequent data requesting nodes can quickly read data from the data cache.

[0095] In some embodiments, a prefetch enhancement flag may be set. If the data prefetch strategy is adjusted from the second strategy to the third strategy, the prefetch enhancement flag is switched from "0" to "1."

[0096] In an embodiment of the present application, the third strategy may be that when the data requesting node does not prefetch data from the main memory via the second communication path, and the number of requests for the data requesting node to read data from the main memory via the first communication path reaches a second threshold, the data requesting node sends a data prefetch request; for example, if the second threshold is 5, and the number of times the data requesting node has read data from the main memory via the first communication path reaches 5, then when the data requesting node sends a data read request to the main memory via the first communication path for the sixth time, the data requesting node simultaneously sends a data prefetch request via the second communication path or within a time threshold. In some embodiments, after the data prefetch strategy is adjusted from the second strategy to the third strategy, the value of the second counter is cleared.

[0097] In step S207, the third counter counts the number of times each data requesting node sends a data prefetch request and the data received by the data requesting node does not carry a prefetch identifier, and counts the number of times each data requesting node generates a data prefetch request and the data prefetch request is not sent to the main memory.

[0098] In some embodiments, if a data requesting node sends a data prefetch request but the data received by the data requesting node does not carry a prefetch flag, the value of the third counter is incremented by 1. Alternatively, if a data requesting node generates a data prefetch request but the data prefetch request is not sent to the main memory, the value of the third counter is incremented by 1. The function of the third counter can be implemented by a logic circuit.

[0099] Step S208 : If it is determined that the value of the third counter reaches a third threshold, the data prefetching strategy is adjusted from the third strategy to the second strategy.

[0100] In some embodiments, a prefetch reduction flag may be set. If the data prefetch strategy is adjusted from the third strategy to the second strategy, the prefetch reduction flag is switched from "1" to "0."

[0101] In some embodiments, if the data prefetching strategy is adjusted from the third strategy to the second strategy, the value of the third counter is cleared to zero.

[0102] Step S209: The node corresponding to the main memory receives the second data read request sent by the second data requesting node.

[0103] In step S210 , the node corresponding to the main memory determines whether the second data corresponding to the second data read request is stored in the data cache.

[0104] In some embodiments, if the judgment result is yes, step S211 is executed. If the judgment result is no, step S212 is executed.

[0105] In step S211 , the node corresponding to the main memory reads the second data from the data cache and sends the second data to the second data requesting node.

[0106] In step S212 , the node corresponding to the main memory reads the second data from the main memory and sends the second data to the second data requesting node.

[0107] The embodiment of the present application can be applied to the scenario of multi-level cache. The structural diagram of the multi-level cache is as follows: Figure 3As shown, each processor core has a secondary cache and a primary cache, where the primary cache includes an instruction cache and a data cache, and the instruction cache and the data cache share the secondary cache; and multiple processor cores in a region can share a third-level cache, and processor cores in multiple regions share system-level storage in the external interconnection. In this application scenario, if a data request node sends a data read request to the secondary cache, but the data corresponding to the data read request is not stored in the secondary cache; then when the secondary cache sends a data read request to the main memory based on the first communication path, it can simultaneously send a data prefetch request to the main memory based on the second communication path; if the transmission time of the second communication path is less than the transmission time of the first path, the secondary cache can quickly read the corresponding data and store the data in the data cache. Afterwards, when other data request nodes request to read the data, they can read the data directly from the data cache without having to read the data from the main memory, thereby reducing data read latency.

[0108] In the related art, the schematic diagram of the secondary cache reading data from the main memory is as follows: Figure 4 As shown, the L2 cache sends a data read request to the main memory, and the main memory sends the data to the L2 cache based on the data read request. However, if the L2 caches corresponding to multiple processor cores simultaneously request data from the main memory, or request to read the same data, the multiple processor cores must queue for the main memory's response, increasing data latency.

[0109] In the embodiment of the present application, a schematic diagram of the secondary cache pre-fetching data from the main memory is shown as follows: Figure 5 As shown, the secondary cache can store the data pre-fetched from the main memory in the data cache in advance by sending a data pre-fetch request to the main memory. When the secondary cache needs to read data from the main memory later, it can directly read the data from the data cache, which improves the speed of data reading and reduces latency. In specific implementation, the secondary cache can feedback the source of data reading. If the read data mainly comes from the main memory, the frequency of pre-fetching data can be reduced (such as adjusting the data pre-fetching strategy from the third strategy to the second strategy). If the read data mainly comes from the data cache, the frequency of pre-fetching data can be increased (such as adjusting the data pre-fetching strategy from the second strategy to the third strategy).

[0110] The following describes the data processing method provided in the embodiment of the present application for the scenario of Mesh network.

[0111] Mesh network structure diagram, such as Figure 6As shown, the Mesh network includes 16 network elements. At the same time that network element 2 sends a data read request to network element 10 via the first communication path "2-3-7-11-10," network element 2 simultaneously sends a data prefetch request to network element 10 via the second communication path "2-6-10." Because the first communication path passes through three network elements, namely, network element 3, network element 7, and network element 11, and the second communication path passes through one network element, network element 6, network element 10 first receives the data prefetch request via the second communication path, and then receives the data read request via the first communication path. After receiving the data prefetch request via the second communication path, network element 10 sends the data corresponding to the data prefetch request to network element 2. This allows network element 2 to quickly read the required data via the shorter communication path, improving the data reading speed and reducing latency.

[0112] After reading the data via the second communication path, NE 2 can also store the data in the data cache. When other NEs in the Mesh network request to read the data again, they can directly read the data from the data cache, which improves the data reading speed and reduces the latency.

[0113] The embodiment of the present application further provides a processor core, which is located at a data request node. The composition structure diagram of the processor core provided by the embodiment of the present application is as follows: Figure 7 As shown, including at least:

[0114] A first sending unit 601 is configured to send a data read request to a main memory based on a first communication path, wherein the data read request is used to request to read first data;

[0115] A second sending unit 602 is configured to send a data prefetch request to the main memory based on the second communication path according to the data prefetch strategy, where the data prefetch request is used to request to read the first data;

[0116] The storage unit 603 is configured to store the first data in a data cache;

[0117] The reading unit 604 is configured to read the first data.

[0118] In some embodiments, the second sending unit 602 is used to send a data prefetch request to the first node located on the second communication path according to the data prefetch strategy, so that the first node reads the first data from the main memory based on the data prefetch request.

[0119] In some embodiments, the processor core further includes:

[0120] a setting unit (not shown in the figure), configured to set a first counter for the data prefetching strategy, the first counter being configured to count the number of times data is read from the main memory based on the first communication path;

[0121] If the value of the first counter reaches a first threshold, the data pre-fetching strategy is adjusted from the first strategy to a second strategy, so as to obtain data from the main memory based on the second communication path.

[0122] In some embodiments, the processor core further includes:

[0123] a setting unit (not shown in the figure), configured to set a second counter for the data prefetching strategy, the second counter being configured to count the number of requests by the data requesting node to read data from the main memory based on the first communication path without the data requesting node prefetching data from the main memory based on the second communication path;

[0124] If the value of the second counter reaches a second threshold, the data prefetching strategy is adjusted from the second strategy to a third strategy to increase the frequency of obtaining data from the main memory based on the second communication path.

[0125] In some embodiments, the processor core further includes:

[0126] a setting unit (not shown in the figure), configured to set a third counter for the data prefetch strategy, the third counter being configured to count the number of times a data prefetch request is sent and the data received by the data requesting node does not carry a prefetch identifier, and the number of times a data prefetch request is generated and the data prefetch request is not sent to the main memory;

[0127] If the value of the third counter reaches a third threshold, the data prefetching strategy is adjusted from the third strategy to the second strategy to reduce the frequency of obtaining data from the main memory based on the second communication path.

[0128] In some embodiments, if the data prefetching strategy is adjusted, the value of the counter corresponding to the data prefetching strategy before the adjustment is cleared.

[0129] In some embodiments, the node corresponding to the main memory receives the data read request; the node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request;

[0130] If the first data is stored in the data cache, the node corresponding to the main memory reads the first data from the data cache; the reading unit 604 is used to receive the first data sent by the node corresponding to the main memory.

[0131] In some embodiments, the node corresponding to the main memory receives the data read request; the node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request; if the first data is not stored in the data cache, the node corresponding to the main memory reads the first data from the main memory; the reading unit 604 is used to receive the first data sent by the node corresponding to the main memory.

[0132] In some embodiments, the data prefetching strategy is configured in a register.

[0133] The embodiment of the present application also provides an electronic device, Figure 8 is a structural diagram of an electronic device 400 provided in an embodiment of the present application, Figure 8 The electronic device 400 shown includes: at least one processor 410, a memory 450 and a bus 440; the various components in the electronic device 400 are coupled together via the bus 440. It is understood that the bus 440 is used to achieve connection and communication between these components. In addition to the data bus, the bus 440 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the bus 440 is not shown in FIG. Figure 8 Various buses are labeled as bus 440.

[0134] The processor 410 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0135] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof.

[0136] In some embodiments, the electronic device 400 may further include:

[0137] Operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, and driver layer, which are used to implement various basic services and process hardware-based tasks;

[0138] The network communication module 452 is used to reach other computing devices via one or more (wired or wireless) network interfaces 420 or user interfaces 430. Exemplary network interfaces 420 include Bluetooth, Wireless LAN (WiFi), and Universal Serial Bus (USB).

[0139] The above are merely examples of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and scope of the present application are included in the scope of protection of the present application.

Claims

1. A data processing method, characterized in that: The method comprises: The data requesting node sends a data read request to the main memory based on the first communication path, wherein the data read request is used to request to read the first data; The data requesting node sends a data prefetch request to the main memory based on the second communication path according to the data prefetch strategy, where the data prefetch request is used to request to read the first data; storing the first data in a data cache; The data requesting node reads the first data.

2. The method according to claim 1, characterized in that The data requesting node sending the data prefetch request to the main memory based on the second communication path according to the data prefetch strategy includes: The data requesting node sends a data prefetching request to the first node located on the second communication path according to the data prefetching strategy, so that the first node reads the first data from the main memory based on the data prefetching request.

3. The method according to claim 1, characterized in that The method further comprises: Setting a first counter for the data prefetching strategy, wherein the first counter is used to count the number of times the data requesting node reads data from the main memory based on the first communication path; If the value of the first counter reaches a first threshold, the data pre-fetching strategy is adjusted from the first strategy to a second strategy, so as to obtain data from the main memory based on the second communication path.

4. The method according to claim 2, characterized in that The method further comprises: Setting a second counter for the data prefetching strategy, the second counter being used to count the number of requests by the data requesting node to read data from the main memory based on the first communication path without prefetching data from the main memory based on the second communication path; If the value of the second counter reaches a second threshold, the data prefetching strategy is adjusted from the second strategy to a third strategy to increase the frequency of obtaining data from the main memory based on the second communication path.

5. The method according to claim 2, characterized in that The method further comprises: Setting a third counter for the data prefetch strategy, the third counter being used to count the number of times the data requesting node sends a data prefetch request and the data received by the data requesting node does not carry a prefetch identifier, and being used to count the number of times the data requesting node generates a data prefetch request and the data prefetch request is not sent to the main memory; If the value of the third counter reaches a third threshold, the data prefetching strategy is adjusted from the third strategy to the second strategy to reduce the frequency of obtaining data from the main memory based on the second communication path.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: If the data prefetching strategy is adjusted, the value of the counter corresponding to the data prefetching strategy before the adjustment is cleared.

7. The method according to any one of claims 1 to 5, characterized in that The data requesting node reading the first data includes: The node corresponding to the main memory receives the data read request; The node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request; If the first data is stored in the data cache, the node corresponding to the main memory reads the first data from the data cache; The data requesting node receives the first data sent by the node corresponding to the main memory.

8. The method according to any one of claims 1 to 5, characterized in that The data requesting node reading the first data includes: The node corresponding to the main memory receives the data read request; The node corresponding to the main memory determines whether the first data is stored in the data cache based on the data read request; If the first data is not stored in the data cache, the node corresponding to the main memory reads the first data from the main memory; The data requesting node receives the first data sent by the node corresponding to the main memory.

9. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The data prefetching strategy is configured in a register.

10. A processor core, characterized in that: The processor core is located at the data request node, and the processor core includes: A first sending unit, configured to send a data read request to the main memory based on the first communication path, wherein the data read request is used to request to read first data; a second sending unit, configured to send a data prefetch request to the main memory based on a second communication path and in accordance with a data prefetch strategy, wherein the data prefetch request is used to request reading of the first data; A storage unit, configured to store the first data in a data cache; A reading unit is configured to read the first data.

11. An electronic device, characterized in that: The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the data processing method according to any one of claims 1 to 9.

Images