High-speed serial communication system physical coding layer circuit oriented to D2D interconnection between integrated chip core particles

Abstract

The invention provides a high-speed serial communication system physical coding layer circuit oriented to D2D interconnection between integrated chip core particles. Based on the characteristics of short D2D transmission distance and reliable transmission environment, a simple link management mechanism is adopted, efficient flow control is realized through a specific training sequence, and a data reliability guarantee mechanism is arranged in other control layers. A modular design idea is adopted, and the system comprises a coding and decoding module, a multi-channel data processing module and an APB interface module. A user configures a register through the APB interface module to realize switching of two coding schemes and monitor the working state of the circuit. The coding module is responsible for data coding and training sequence sending, the decoding module completes data decoding and training sequence identification, and the multi-channel data processing module is responsible for channel training control and multi-channel data packing and unpacking. In the training process, a two-stage training strategy is adopted, based on a training result, a circuit selects a working mode according to the number of available channels, and channel self-adaptive fault tolerance is achieved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a physical coding layer circuit of a high-speed serial communication system for D2D interconnection between integrated chip cores. Background Art

[0002] As integrated circuit design evolves toward higher levels of integration and more complex functionality, chiplet-based design methodologies are gaining increasing attention. In chiplet design, multiple functional modules are divided into independent chiplets, which are interconnected via die-to-die (D2D) interconnections to achieve high-speed data exchange. While this design approach improves chip yield and reduces costs, it also places higher demands on inter-chiplet communication.

[0003] In high-speed serial communication for D2D interconnection between chiplets, the Physical Coding Sublayer (PCS) is a key component, responsible for data encoding and decoding, link training, and maintenance. Currently, widely used PCS design solutions are mostly suitable for board-level high-speed communication systems. These solutions include complex functions such as power management, bandwidth negotiation, and clock frequency compensation, which are not necessary for short-distance, reliable transmission between chiplets. Furthermore, the link management mechanisms used in existing solutions are relatively cumbersome, increasing circuit area and power consumption. Summary of the Invention

[0004] The present application provides a physical coding layer circuit for a high-speed serial communication system for D2D interconnection between chiplets on an integrated chip, which can be used to solve the complex and onerous technical problem of a high-speed serial communication link management mechanism for D2D interconnection between chiplets.

[0005] The present application provides a physical coding layer circuit for a high-speed serial communication system for D2D interconnection between integrated chip cores, wherein the physical coding sublayer circuit includes an encoding module, a decoding module and a multi-channel data processing module. Among them, the encoding module is responsible for data encoding and training sequence transmission, the decoding module completes data decoding and training sequence recognition, and the multi-channel data module is responsible for managing channel training, configuring working modes, and allocating and reorganizing multi-channel data. In terms of link management, based on the characteristics of D2D application scenarios, a simple link management mechanism is adopted, focusing on implementing the flow control mechanism, achieving efficient flow control functions through specific training sequences, and placing data reliability assurance mechanisms (such as error detection and retransmission) in the data transmission control layer. The training sequence includes a single-channel training sequence and a multi-channel training sequence, which are used to implement frame boundary search, channel link establishment, multi-channel data alignment and flow control functions.

[0006] The training process of the multi-channel data processing module first performs single-channel synchronization header frame search training, and then performs multi-channel training after the single-channel training is completed. Based on the training results, available channels are selected and the corresponding working mode is configured.

[0007] The training process of the multi-channel data processing module first performs single-channel synchronization header frame search training, and then performs multi-channel training after the single-channel training is completed. Based on the training results, available channels are selected and the corresponding working mode is configured.

[0008] Based on the characteristics of D2D interconnection between chiplets, the circuit adopts a simple link management mechanism, including a lightweight flow control mechanism, without the need for complex power management, clock frequency compensation, bandwidth change management and other mechanisms.

[0009] The encoding module supports 8b10b and 64b66b encoding schemes, and includes a control data storage unit, an encoding unit, and a data conversion unit, etc., which are used to implement data encoding and training sequence transmission.

[0010] The decoding module supports 8b10b and 64b66b encoding schemes, and includes a data cache unit, a decoding unit, and a data synchronization unit, etc., which are used to implement data decoding and training sequence recognition.

[0011] The coding scheme is selected through the control interface configuration, single-channel training is performed, and multi-channel data alignment training is performed after completion. The available channels are dynamically selected and the corresponding working mode is configured according to the D2D link status, and a lightweight flow control mechanism is used for data transmission control.

[0012] During D2D data transmission between chiplets, specific training sequences are sent to indicate the idle state of the data stream. The receiving end recognizes and processes these training sequences to achieve efficient flow control. At the same time, by optimizing function allocation, the data reliability guarantee mechanism is placed in other control layers to achieve a lightweight PCS circuit design.

[0013] Single-channel training involves sending a specific training sequence for frame search, identifying characteristic characters to determine data boundaries, and completing the establishment of a single-channel link.

[0014] Multi-channel training includes sending multi-channel training sequences to detect channel status, confirming data alignment status based on sequence reception, and completing channel configuration.

[0015] The APB interface module enables flexible control of circuit operating modes through configuration registers. This architecture supports unified management of both 8b10b and 64b66b dual encoding schemes. Based on the unique characteristics of D2D application scenarios, this invention employs an efficient flow control mechanism, enabling flow control during link idle periods by transmitting and identifying specific training sequences. Furthermore, given the short transmission distances and reliable transmission environments of D2D, the data reliability assurance mechanism is placed in other control layers, effectively optimizing circuit resources at the PCS layer.

[0016] The present invention supports both 8b10b and 64b66b encoding schemes. The encoding modules of both implement codeword conversion while also integrating mechanisms for selecting and sending training sequences. The 64b66b encoding module employs a synchronization header identification scheme and maintains DC balance of the data stream through scrambling. The 8b10b encoding module achieves data boundary alignment by inserting boundary characters. For idle data processing, the encoding circuit can dynamically send specific training sequences based on the upstream FIFO status, achieving reliable flow control.

[0017] In the decoding circuitry, the present invention implements physical layer data decoding and training sequence recognition. The 8b10b decoding module, which includes functional units such as a boundary character detector and a shift controller, ensures decoding accuracy by identifying specific character boundaries. The 64b66b decoding module achieves frame synchronization through synchronization header recognition and integrates descrambling functionality. Furthermore, the decoding circuitry can recognize and process specific training sequences relevant to flow control. When these sequences are identified, they are treated as null packets, thereby supporting efficient flow control in the system.

[0018] The present invention implements two primary functions within the multi-channel data processing circuit: data allocation and reorganization, and channel training control. In terms of data processing, multi-channel data allocation and reorganization are implemented. In terms of channel training, a hierarchical training strategy is employed, encompassing two phases: single-channel synchronization header search and multi-channel data alignment. An adaptive channel selection mechanism is also designed. The system automatically selects the appropriate operating mode (4x, 2x, or 1x) by monitoring the reception of training data.

[0019] In terms of interfaces, the present invention provides flexible configuration and monitoring functions through the APB interface. Through the configuration register, encoding mode can be selected, training status and link status can be monitored, timeout parameters and channel selection can be set.

[0020] The advantages of this invention include: First, based on the application characteristics of inter-chip D2D, it adopts a reasonable architecture design and an efficient flow control mechanism, placing the reliability assurance mechanism in a different control layer, effectively controlling implementation complexity while ensuring functional integrity; second, it supports unified management of 8b10b and 64b66b dual encoding schemes, and uses a multi-channel management mechanism to ensure that the system can maintain stable operation even in the event of local channel failures; finally, standardized interface definitions and flexible configuration mechanisms make the system highly maintainable and scalable. These features enable this invention to provide a high-performance and highly reliable physical coding sublayer solution for inter-chip D2D interconnection scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is an overall structural diagram of the physical coding layer circuit of a high-speed serial communication system for D2D interconnection between integrated chip chips provided by an embodiment of the present application;

[0022] Figure 2 This is a structural diagram of a 64b66b encoding circuit provided in an embodiment of the present application;

[0023] Figure 3 This is a structural diagram of a 64b66b decoding circuit provided in an embodiment of the present application;

[0024] Figure 4 This is a structural diagram of the 8b10b encoding circuit provided in an embodiment of the present application;

[0025] Figure 5 This is a structural diagram of an 8b10b decoding circuit provided in an embodiment of the present application;

[0026] Figure 6 This is a structural diagram of a multi-channel data processing circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0028] The following first introduces the embodiments of the present application with reference to the accompanying drawings.

[0029] 1. Total circuit:

[0030] The present invention provides a physical coding layer circuit for a high-speed serial communication system for D2D interconnection between integrated chip cores, such as Figure 1As shown, it includes a codec unit, a configuration management unit and a multi-channel data processing unit; the codec unit includes a first codec module supporting 64b66b encoding and a second codec module supporting 8b10b encoding, the configuration management unit implements system parameter configuration through the APB bus interface, and the multi-channel data processing unit is responsible for managing channel training and multi-channel data allocation and reorganization.

[0031] The second codec module and the first codec module respectively use independent data processing paths, which include from their respective data input interfaces idata_8b10b and idata_64b66b to their respective data output interfaces odata_8b10b and odata_64b66b, to ensure that the data processing paths of the two coding schemes are independent of each other and do not interfere with each other; in terms of connection with the physical layer, the data of the selected coding scheme is connected to a unified SerDes interface through a multiple link structure, realizing multiplexing of the physical layer.

[0032] The configuration mechanism design provides configuration registers through the APB interface. The configuration management unit includes: system reset register, system operation status monitoring register, training sequence timeout configuration register, and codec mode selection register. These registers together form the system configuration management framework, ensuring controllable and flexible system operation.

[0033] During the operating phase, the user first selects the current coding scheme through the configuration interface, then enters the link training phase. During this phase, the system sequentially completes single-channel synchronization and multi-channel alignment to ensure data transmission reliability. After training is complete and successful, it enters normal operation, processing the input data according to the selected coding scheme and transmitting it through the SerDes interface. The multi-channel data processing module training process begins with single-channel synchronization header frame search training. After single-channel training is complete, multi-channel training is carried out. Based on the training results, available channels are selected and the corresponding operating mode is configured.

[0034] The following describes in detail the various important components of the circuit in this application.

[0035] 2. First Encoding Circuit

[0036] The first encoding circuit 64b66b of the present invention has a structure as follows: Figure 2As shown. The encoding circuit includes a training sequence transmitter, a multiplexer, an encoder, and a gearbox. The training sequence transmitter is used to store and manage the transmission of various training sequences, including single-channel training data TD1 and TD2 and multi-channel training data MTD1 and MTD2. The multiplexer selects to output training sequences or user data based on the system status. When the encoder is working, it first adds a 2-bit synchronization header identifier to the input 64-bit data block and further scrambles the data. In addition, the first encoding circuit also includes a gearbox for converting the 66-bit encoded data into a bit width format that meets the physical interface requirements and outputs it to the SerDes interface.

[0037] The MTD and TD training sequences are described as follows:

[0038] TD1: marks the start of single-channel training. When one side starts sending TD1, it means that the side is ready to enter the training state;

[0039] TD2: Link training sequence. By continuously receiving TD2, it is determined that the link connection is stable.

[0040] TD3: Idle sequence, which is sent when the circuit is in working state and there are no data packets that need to be transmitted using SerDes. It is used to maintain link stability.

[0041] MTD1: marks the start of multi-channel training, indicating that the first codec unit is in the multi-channel training state; at the same time, it notifies the peer end that the local end is ready for multi-channel training, which is equivalent to a handshake with the peer end;

[0042] MTD2: used to confirm the clock deviation between multiple channels;

[0043] MTD3: indicates that the multi-channel data alignment training of the current channel is successful;

[0044] MTD4: indicates that the multi-channel data alignment of the current channel fails;

[0045] MTD5: indicates that the data processing unit can work;

[0046] In terms of the channel training process, the encoding circuit of the present invention adopts phased training, first performing single-channel training and then multi-channel training;

[0047] After the system is reset, the first encoding circuit automatically starts single-channel training, first sending the TD1 training sequence to establish the initial link and waiting for the feedback signal from the local decoding circuit. When the feedback signal is detected, the encoding circuit switches to the sending state of the TD2 training sequence and waits for the completion of single-channel training.

[0048] After completing single-channel training, the encoding circuit enters the multi-channel training phase. At this point, the circuit responds to the multi-channel controller's instructions and sends an MTD1 training data packet to establish multi-channel training synchronization between the local and remote ends. When the remote end is confirmed to be ready, the first encoding circuit sends an MTD2 data packet to complete multi-channel alignment. Subsequently, the channel trained through the single channel decides whether to send an MTD3 or MTD4 data packet based on whether channel alignment is possible. MTD3 indicates using the current channel, while MTD4 indicates not using the current channel. The transmitting and receiving ends will determine the channel to use based on the MTD3 and MTD4 transmission and reception conditions of both parties, and then end channel training.

[0049] After training is complete, the first encoding circuit enters normal operation. When there is no data to be encoded, the first encoding circuit maintains the link connection by continuously sending TD3 packets. This process implements a lightweight flow control mechanism. This mechanism maintains link stability while minimizing additional resource usage by sending a minimum number of link-maintaining packets. When user data flow resumes, the first encoding circuit immediately switches to normal data transmission mode, ensuring link efficiency and real-time performance.

[0050] 3. Second decoding circuit

[0051] The 64b66b decoding circuit of the present invention is the second decoding circuit structure as shown in FIG. Figure 3 As shown, it includes a gearbox, a 64b66b descrambler, a decoding controller, and a counter; wherein the gearbox is used to complete data bit width conversion and synchronization header search function; the 64b66b descrambler is used for 66-bit data descrambling processing; the decoding controller is used to identify training data and generate control signals.

[0052] The present invention integrates a synchronization head detection mechanism into the gearbox. During the process of reorganizing the physical link interface bit width to 66 bits, a framed signal is generated in real time to indicate the current data synchronization status. A dedicated counter is configured to monitor the framed signal. When the signal remains valid for a preset number of consecutive times, the synchronization head is determined to be locked, thereby achieving data frame alignment before entering the formal training phase.

[0053] In terms of data buffering, the second decoding circuit of the present invention adopts a 66-bit asynchronous FIFO as a data cache unit and retains the synchronization header information; the 64b66b descrambler only performs data descrambling operations, and the parsing of the synchronization header is performed in the FIFO read clock domain, that is, the data decoding and the judgment of the training data are completed in the clock domain of the user end, avoiding the frequent conversion of control signals between multiple clock domains.

[0054] The data processing flow of the second decoding circuit is optimized as follows: the 20-bit data from the physical layer first enters the gearbox for bit width conversion and synchronization header detection. After synchronization, the 66-bit data enters the FIFO cache after descrambling. In the FIFO read clock domain, corresponding processing operations are performed according to the type of synchronization header: if a LOGIC_ONE type synchronization header is detected, the corresponding data will be forwarded to the upstream interface; if a LOGIC_ZERO type synchronization header is detected, it is determined to be training sequence data and is identified and processed by the decoding controller. Based on the identification result, the decoding controller generates a corresponding control signal. The control signal is fed back to the encoding circuit at the local end to adjust the sending of training data, and is transmitted to the multi-channel data processing unit to support the advancement of link training.

[0055] 4. Second Encoding Circuit

[0056] The overall structure of the second encoding circuit of the present invention is shown in FIG. Figure 4 The second codec circuit includes a second encoding circuit and a second decoding circuit. The 8b10b encoding circuit of the present invention uses a similar overall architecture to the 64b66b decoding circuit. The 8b10b encoding circuit of the present invention is one of the encoding schemes supported by the system. The second encoding circuit includes a training sequence transmitter, an 8b10b encoder, and a gearbox.

[0057] In terms of clock domain conversion design, this invention uses asynchronous FIFOs at the physical layer interface to achieve cross-clock domain data transmission. For flow control, this invention employs a lightweight flow control mechanism based on specific training sequences. When there is no upstream data transmission, the transmitter continuously sends the TD3 training sequence to maintain link status. The TD3 sequence is identified as an empty packet at the receiver and automatically discarded, ensuring simple and effective flow control while maintaining link status.

[0058] The second encoding circuit of the present invention adopts the same channel training process as the first encoding circuit, and completes single-channel training and multi-channel alignment by sending a training sequence based on the control signal provided by the multi-channel data processing unit; after the training is completed, the encoding circuit enters a normal working state and encodes the user data.

[0059] 5. Second decoding circuit

[0060] The overall structure of the 8b10b decoding circuit of the present invention is shown in FIG. Figure 5 As shown. The 8b10b decoding circuit of the present invention adopts an overall architecture similar to the 64b66b decoding circuit. In specific implementation, the second decoding circuit includes an input buffer, a boundary character detector, a shift controller, a training controller and an 8b10b decoder;

[0061] The input buffer is used to cache the channel data received in the current cycle and the previous cycle, and to splice the data into a complete data unit;

[0062] The boundary character detector establishes the correct character boundary by identifying a specific comma code, namely the K code pattern, and generates a corresponding control signal to achieve data boundary alignment through the shift controller; when multiple comma signals are detected, it is determined to be a data transmission error;

[0063] The shift controller establishes the correct data boundary under the control of the boundary character detector and transmits the aligned data to the training controller and decoder simultaneously;

[0064] The training controller generates a corresponding training status indication signal by analyzing the received data types, including TD1, TD2, and MTD1. The indication signal is fed back to the local encoding circuit to adjust the transmission of training data, and is also transmitted to the multi-channel data processing circuit to support the advancement of link training.

[0065] The second decoding circuit also uses asynchronous FIFO to achieve cross-clock domain data transmission. Before the boundary-aligned data enters the gearbox for bit width conversion, it is first converted to the clock domain by the asynchronous FIFO to ensure the reliability of data processing.

[0066] The decoder is used to decode the aligned 10-bit codeword into 8-bit data, providing the correct data stream for upper-layer applications.

[0067] 6. Multi-channel data processing unit

[0068] like Figure 6 As shown, the multi-channel data processing unit of the present invention includes a multi-channel control unit and a data processing unit; the multi-channel control unit adopts a hierarchical state machine architecture, including three state machines: global state state, link training state train_state, and receiving end state rx_train_state, which are respectively responsible for overall state control, training process management, and receiving end control; the data processing unit realizes dynamic allocation and reorganization of data based on the link state signal provided by the multi-channel control unit.

[0069] The data processing unit uses a cross switch to implement a data stream structure that supports flexible multi-channel allocation. In the sending direction, the data processing unit receives streaming user data and distributes the data to available channels through the cross switch according to the link selection lane_sel signal provided by the multi-channel control unit, generating a data stream to be encoded. In the receiving direction, the decoded data of each channel is cached and aligned, and reorganized into a complete user data packet according to preset rules, so as to maintain the continuity and integrity of data transmission under any channel configuration.

[0070] The multi-channel control unit adopts a two-stage channel training method. First, single-channel synchronization training is carried out. The synchronization header is searched by sending TD1 training data packets. After the synchronization header is detected, TD2 data packets are sent. The training completion is judged by recording the number of TD2 packets received. After the single-channel training is completed, the multi-channel alignment training phase is entered. Different MTD training sequences are sent to achieve channel alignment and determine the working mode.

[0071] The multi-channel control unit supports an adaptive channel selection mechanism. Due to clock deviations between channels, the reception status of MTD2 is determined by monitoring the FIFO full or empty status. When all channels that have passed single-channel training receive MTD2, the working channel is selected according to the default configuration. When only some channels receive MTD2, it automatically enters a specific mode and supports operation in 4-link, 2-link, or 1-link modes. When only one channel receives MTD2 and the available channel is the same, it switches to single-channel mode.

[0072] After the channel selection is completed, the channel usage status is identified by the MTD3 and MTD4 data packets, and the final channel configuration is determined by combining the training results of the sending and receiving ends; 64 clock cycles (configurable) are reserved for waiting for the other end to complete training, and then the MTD5 data packet is sent to mark the end of training; after the training is completed, the data processing unit starts normal data transmission operations according to the determined channel configuration.

[0073] The above-described embodiments of the present application do not constitute a limitation on the scope of protection of the present application.

Claims

1. A physical coding layer circuit for a high-speed serial communication system for D2D interconnection between integrated chip chips, characterized in that: The circuit comprises: Codec unit, configuration management unit and multi-channel data processing unit; The codec unit includes a first codec module supporting 64b66b encoding and a second codec module supporting 8b10b encoding; the configuration management unit implements system parameter configuration through the APB bus interface; the multi-channel data processing unit is responsible for managing channel training and multi-channel data allocation and reorganization; The first codec module includes a first encoding circuit and a first decoding circuit; the second codec module includes a second encoding circuit and a second decoding circuit; During the working phase, the user first selects the current coding scheme through the configuration interface, and then enters the link training phase. During the link training phase, single-channel synchronization and multi-channel alignment are completed in sequence. After the training is completed, if the training is successful, the system enters the normal working state, processes the input data according to the selected coding scheme, and transmits it through the SerDes interface. The training process of the multi-channel data processing module first performs single-channel synchronization header frame search training, and then performs multi-channel training after the single-channel training is completed. Based on the training results, available channels are selected and the corresponding working mode is configured.

2. The circuit according to claim 1, wherein: The second codec module and the first codec module respectively use independent data processing paths, which include from their respective data input interfaces idata_8b10b and idata_64b66b to their respective data output interfaces odata_8b10b and odata_64b66b; in terms of connection with the physical layer, the data of the selected coding scheme is connected to a unified SerDes interface through multiple link structures.

3. The circuit according to claim 1, wherein: The configuration management unit includes: system reset register, system operation status monitoring register, training sequence timeout configuration register, and codec mode selection register.

4. The circuit according to claim 1, wherein: The first encoding and decoding module includes a first encoding circuit and a first decoding circuit; The first encoding circuit includes a training sequence transmitter, a multiplexer, an encoder, and a gearbox; The training sequence transmitter is used to store and manage the transmission of various training sequences, including single-channel training data TD1, TD2 and multi-channel training data MTD1, MTD2; The multiplexer selects to output the training sequence or user data according to the system status; When the encoder is working, it first adds a 2-bit synchronization header to the input 64-bit data block and further scrambles the data; The gearbox is used to convert the 66-bit encoded data into a bit width format that meets the requirements of the physical interface and output it to the SerDes interface; The MTD and TD training sequences are described as follows: TD1: marks the start of single-channel training. When one side starts sending TD1, it means that the side is ready to enter the training state; TD2: Link training sequence. By continuously receiving TD2, it is determined that the link connection is stable. TD3: Idle sequence, which is sent when the circuit is in working state and there are no data packets that need to be transmitted using SerDes. It is used to maintain link stability. MTD1: marks the start of multi-channel training, indicating that the first codec unit is in the multi-channel training state; at the same time, it notifies the peer end that the local end is ready for multi-channel training, which is equivalent to a handshake with the peer end; MTD2: used to confirm the clock deviation between multiple channels; MTD3: indicates that the multi-channel data alignment training of the current channel is successful; MTD4: indicates that the multi-channel data alignment of the current channel fails; MTD5: indicates that the data processing unit can work; The encoding circuit adopts phased training, first single-channel training and then multi-channel training; After the system is reset, the first encoding circuit automatically starts single-channel training, first sending the TD1 training sequence to establish the initial link and waiting for the feedback signal from the local decoding circuit. When the feedback signal is detected, the encoding circuit switches to the sending state of the TD2 training sequence and waits for the completion of single-channel training. After completing single-channel training, the encoding circuit enters the multi-channel training phase. At this point, the circuit responds to the multi-channel controller's instructions and sends an MTD1 training data packet to establish multi-channel training synchronization between the local and remote ends. When the remote end is confirmed to be ready, the first encoding circuit sends an MTD2 data packet to complete multi-channel alignment. Subsequently, the channel trained through the single channel decides whether to send an MTD3 or MTD4 data packet based on whether channel alignment is possible. MTD3 indicates using the current channel, while MTD4 indicates not using the current channel. The transmitting and receiving ends will determine the channel to use based on the MTD3 and MTD4 transmission and reception conditions of both parties, and then end channel training. After training is completed, the first encoding circuit enters normal working state; when there is no data to be encoded, the first encoding circuit maintains the link connection by continuously sending TD3 data packets; when the user data flow is restored, the first encoding circuit immediately switches to normal data transmission mode to ensure the efficiency and real-time performance of the link.

5. The circuit according to claim 1, wherein: The second decoding circuit includes a gearbox, a 64b66b descrambler, a decoding controller, and a counter; Among them, the gearbox is used to complete data bit width conversion and synchronization head search function; The 64b66b descrambler is used for 66-bit data descrambling. The decoding controller is used for identifying training data and generating control signals; In the gearbox, during the process of reorganizing the physical link interface bit width to 66 bits, a framed signal is generated in real time to indicate the current data synchronization status. A dedicated counter is configured to monitor the framed signal. When the signal remains valid for a preset number of consecutive times, the synchronization header is determined to be locked, thereby achieving data frame alignment before entering the formal training phase.

6. The circuit according to claim 5, characterized in that The second decoding circuit uses a 66-bit asynchronous FIFO as a data cache unit and retains the synchronization header information. The 64b66b descrambler only performs data descrambling operations, while the synchronization header is parsed in the FIFO read clock domain. That is, data decoding and training data judgment are completed in the user-side clock domain.

7. The circuit according to claim 6, characterized in that The data processing flow of the second decoding circuit is as follows: the 20-bit data from the physical layer first enters the gearbox for bit width conversion and synchronization header detection. After synchronization, the 66-bit data is descrambled and then enters the FIFO cache. In the FIFO read clock domain, corresponding processing operations are performed according to the type of synchronization header: if a LOGIC_ONE type synchronization header is detected, the corresponding data will be forwarded to the upstream interface; if a LOGIC_ZERO type synchronization header is detected, it is determined to be training sequence data and is identified and processed by the decoding controller. Based on the identification result, the decoding controller generates a corresponding control signal. The control signal is fed back to the encoding circuit at the local end to adjust the transmission of training data, and is also transmitted to the multi-channel data processing unit to support the advancement of link training.

8. The circuit according to claim 4, characterized in that The second encoding and decoding circuit includes a second encoding circuit and a second decoding circuit; the second encoding circuit includes a training sequence transmitter, an 8b10b encoder and a gearbox; Use asynchronous FIFO at the interface with the physical layer to achieve cross-clock domain data transmission; When there is no upstream data transmission, the transmitter continues to send TD3 training sequences to maintain the link status; the TD3 sequences are recognized as empty packets at the receiver and automatically discarded; The second encoding circuit adopts the same channel training process as the first encoding circuit, and completes single-channel training and multi-channel alignment by sending a training sequence based on the control signal given by the multi-channel data processing unit; After the training is completed, the encoding circuit enters the normal working state and encodes the user data.

9. The circuit according to claim 1, wherein: The second decoding circuit includes an input buffer, a boundary character detector, a shift controller, a training controller and an 8b10b decoder; The input buffer is used to cache the channel data received in the current cycle and the previous cycle, and to splice the data into a complete data unit; The boundary character detector establishes the correct character boundary by identifying a specific comma code, namely the K code pattern, and generates a corresponding control signal to achieve data boundary alignment through the shift controller; when multiple comma signals are detected, it is determined to be a data transmission error; The shift controller establishes the correct data boundary under the control of the boundary character detector and transmits the aligned data to the training controller and decoder simultaneously; The training controller analyzes the received data types, including TD1, TD2, and MTD1, and generates corresponding training status indication signals. These indication signals are fed back to the local encoding circuit to adjust the transmission of training data and are also transmitted to the multi-channel data processing circuit to support the advancement of link training. The second decoding circuit uses an asynchronous FIFO to achieve cross-clock domain data transmission; the boundary-aligned data is first converted to the clock domain by the asynchronous FIFO before entering the gearbox for bit width conversion; The decoder is used to decode the aligned 10-bit codeword into 8-bit data, providing the correct data stream for upper-layer applications.

10. The circuit according to claim 1, wherein: The multi-channel data processing unit includes a multi-channel control unit and a data processing unit. The multi-channel control unit adopts a hierarchical state machine architecture, including three state machines: global state, link training state, train_state, and receiver state, rx_train_state. These three state machines are responsible for overall state control, training process management, and receiver control, respectively. The data processing unit implements dynamic data allocation and reorganization based on the link state signals provided by the multi-channel control unit. The data processing unit uses a crossbar switch to implement a data stream structure that supports multi-channel allocation. In the transmit direction, the data processing unit receives streaming user data and distributes the data to available channels through the crossbar switch based on the link selection lane_sel signal provided by the multi-channel control unit, generating a data stream to be encoded. In the receiving direction, the decoded data of each channel is cached and aligned, and reassembled into a complete user data packet according to preset rules; The multi-channel control unit uses a two-stage channel training method. First, single-channel synchronization training is performed. The TD1 training data packet is sent to search for the synchronization header. After the synchronization header is detected, the TD2 data packet is sent. The number of TD2 packets received is recorded to determine whether the training is complete. After the single-channel training is completed, the multi-channel alignment training phase begins. Different MTD training sequences are sent to achieve channel alignment and determine the operating mode. The multi-channel control unit supports an adaptive channel selection mechanism, which determines the reception status of MTD2 by monitoring the FIFO empty or full status. When all channels that have passed single-channel training receive MTD2, the working channel is selected according to the default configuration. When only some channels receive MTD2, it automatically enters a special mode, supporting operation in 4-link, 2-link, or 1-link modes. When only one channel receives MTD2 and the available channel is the same as it, it switches to single channel mode. After channel selection is completed, the MTD3 and MTD4 packets are used to identify the channel usage status, and the final channel configuration is determined by combining the training results of the sender and receiver. 64 clock cycles are reserved for waiting for the other end to complete training, and then the MTD5 packet is sent to mark the end of training. After the training is completed, the data processing unit starts normal data transmission operations according to the determined channel configuration.

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