Remote monitoring system based on single-chip microcomputer and control method thereof

Abstract

The invention belongs to the technical field of single-chip microcomputers, and particularly relates to a remote monitoring system based on a single-chip microcomputer and a control method thereof. The system comprises a single-chip microcomputer, a sensor acquisition unit, a wireless communication unit and an execution mechanism. When a single-chip microcomputer, a sensor acquisition unit and a system are initialized, a wireless communication unit and an execution mechanism are sequentially powered on, after the single-chip microcomputer completes hardware self-inspection, a handshake instruction is sent to the wireless communication unit, a secure channel with a remote control terminal is established, and after handshake is completed, the single-chip microcomputer writes in a unique identity identification code and enters a standby state; the single-chip microcomputer polls the sensor acquisition unit according to a preset sampling period to obtain an original data frame; the remote control terminal analyzes the error correction compressed data block, generates a control instruction according to a threshold strategy and returns the control instruction; the single-chip microcomputer receives the control instruction, then drives the execution mechanism to act, and records an execution state log. The method has the advantages of being high in communication efficiency, high in link fault-tolerant capability and fast in remote control response.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of single-chip microcomputers, and particularly relates to a remote monitoring system based on a single-chip microcomputer and a control method thereof. BACKGROUND

[0002] Under the background that Internet of Things technology and edge computing architecture are increasingly mature, remote monitoring systems based on single-chip microcomputers have been widely applied in industrial automation, environmental monitoring, smart agriculture, smart building and other fields. With the increasing complexity of application scenarios, remote monitoring systems are required to not only have high-precision data acquisition capability, but also have high-reliability data transmission mechanism and strong fault-tolerant data processing architecture. However, from the implementation of the existing public technology, such systems still have many problems in structure design, data processing mode, communication reliability and remote control closed-loop capability, and it is difficult to meet the actual application requirements of high stability, high real-time and high security.

[0003] Most of the existing monitoring systems based on single-chip microcomputers generally adopt a one-way flow architecture of "collection + upload + terminal processing". Specifically, the single-chip microcomputer periodically collects data from the sensor, directly packs the collected data into a fixed format frame, and uploads it to the server or remote control terminal through a wireless communication module such as serial port, Wi-Fi, LoRa or NB-IoT, and the terminal uniformly completes data storage, processing and control decision. This traditional architecture has certain practical value in applications with fewer sensors, simple environment, high tolerance to delay, simple system structure and low implementation cost. However, once facing application scenarios with high sampling rate, large data volume and high interference, such as multi-point climate monitoring in agricultural greenhouse, real-time detection of industrial pipeline leakage or energy management of distributed devices, the system exposes the following technical problems:

[0004] First, the data redundancy is high, resulting in serious communication link bandwidth occupation. In the existing technology, the raw data is directly uploaded without local preprocessing, and this "no difference upload" method does not consider the time correlation and information entropy structure of the data. Especially in multi-sensor long-period monitoring, the adjacent sampling values change very little, and the proportion of redundant information is very high, resulting in repeated transmission of repeated content on the wireless link, wasting valuable communication resources. In some bandwidth-limited low-power wide-area networks (such as LoRa or NB-IoT), even the frequent packet loss and retransmission caused by the super-long upload data frame seriously affects the system stability.

[0005] Second, weak link error protection leads to a lack of assurance of remote data integrity. Traditional remote monitoring systems often rely solely on simple parity checks or CRCs for integrity checks on uploaded data. These mechanisms can only detect single-bit flips and are unable to correct multi-bit burst errors, requiring only retransmissions for recovery. For systems deployed in remote areas or areas with unstable communications, frequent retransmissions can lead to decreased control timeliness, increased power consumption, and even control misjudgments due to retransmission failures. Error correction codes, such as Reed-Solomon, remain poorly integrated in most systems, primarily due to their high coding complexity and the lack of a comprehensive error correction chain within the system design. Summary of the Invention

[0006] The main purpose of the present invention is to provide a remote monitoring system based on a single-chip microcomputer and its control method. By introducing multi-level data processing mechanisms such as differential linear coding, Galois field polynomial indexing, coprime interleaving and rearrangement, Reed-Solomon redundancy check, and cyclic redundancy compression on the single-chip microcomputer side, efficient redundancy reduction, strong error correction packaging, and structured upload of sensor data are achieved. At the same time, combined with a secure handshake, command feedback, and automatic rollback mechanism, a stable and reliable data uplink and control downlink closed loop is established. The invention has the beneficial effects of high communication efficiency, strong link fault tolerance, fast remote control response, and excellent system self-recovery ability. It is particularly suitable for remote monitoring application scenarios with high interference, low bandwidth, and long periods of unattended operation.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] In one aspect, a single-chip microcomputer-based remote monitoring system is provided, comprising: a single-chip microcomputer, a sensor acquisition unit, a wireless communication unit, and an actuator. When the single-chip microcomputer, the sensor acquisition unit, and the system are initialized, the wireless communication unit and the actuator are powered on in sequence. After the single-chip microcomputer completes a hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with a remote control terminal. After the handshake is completed, the single-chip microcomputer writes a unique identification code and enters a standby state. The single-chip microcomputer polls the sensor acquisition unit according to a preset sampling period to obtain raw data frames. The raw data frames are subjected to sliding window denoising and timestamp marking to generate and temporarily store data blocks to be processed. The single-chip microcomputer performs recursive processing based on differential linear coding and cyclic redundancy compression on the data blocks to maximize the error propagation distance and minimize redundancy while maintaining real-time performance, and outputs error-corrected compressed data blocks. The wireless communication unit reads the error-corrected compressed data blocks and uploads them to the remote control terminal via a secure channel. The remote control terminal parses the error-corrected compressed data blocks, generates control instructions based on a threshold strategy, and transmits them back. After receiving the control instructions, the single-chip microcomputer drives the actuator to operate and records an execution status log.

[0009] On the other hand, a control method for the above-mentioned single chip microcomputer-based remote monitoring system is provided, the method comprising:

[0010] Step 1: Power on the MCU, sensor acquisition unit, wireless communication unit, and actuator in sequence. After the MCU completes the hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is completed, the MCU writes a unique identification code and enters the standby state.

[0011] Step 2: The MCU polls the sensor acquisition unit according to the preset sampling period to obtain the raw data frame; performs sliding window denoising and timestamp marking on the raw data frame to generate the data block to be processed and temporarily stores it;

[0012] Step 3: The MCU performs recursive processing based on differential linear coding and cyclic redundancy compression on the data block to be processed, maximizing the error propagation distance and minimizing redundancy while maintaining real-time performance, and outputs a compressed data block with error correction.

[0013] Step 4: The wireless communication unit reads the error-corrected compressed data block and uploads it to the remote control terminal through a secure channel. The remote control terminal parses the error-corrected compressed data block, generates a control instruction based on the threshold strategy, and transmits it back. After receiving the control instruction, the microcontroller drives the actuator to operate and records the execution status log.

[0014] Furthermore, the method also includes: Step 5: when the number of execution failures recorded in the execution status log reaches a set value, the single chip microcomputer automatically rolls back to Step 1 to re-handshake.

[0015] Furthermore, step 3 specifically includes:

[0016] Step 3.1: Divide the data block to be processed into data segments of equal length; the MCU generates an irreducible polynomial index for each data segment on the Galois field;

[0017] Step 3.2: Perform finite field differential encoding on each data segment to generate a set of adjoint polynomial coefficients;

[0018] Step 3.3: Use the coprime interleaving depth to establish a bidirectional mapping between the time domain and the Galois field, and rearrange the differenced data segments into an interleaving matrix;

[0019] Step 3.4: Calculate the Reed-Solomon redundancy check vector for each column of the interleaving matrix, generate a check vector group, and append it to the interleaving matrix to obtain a check interleaving matrix;

[0020] Step 3.5: The MCU linearly reconcatenates the check interleaving matrix and the Reed-Solomon redundancy check vector row by row, performs binary cyclic redundancy compression, and outputs the error-corrected compressed data block to the transmit buffer.

[0021] Furthermore, step 3.1 specifically includes: the single chip microcomputer reads the system parameter table to obtain a single data segment length threshold, which is set to a fixed value in bytes; if the total number of bytes of the data block to be processed cannot be divided by the threshold, the single chip microcomputer fills zero-value bytes at the end of the data block to be processed until the divisibility condition is met; the single chip microcomputer intercepts the data block to be processed in sequence from the first byte according to the threshold, obtains several data segments in sequence, and allocates a continuous storage block for each data segment in the internal buffer, and records the first address and the last address; the single chip microcomputer calls the finite field operation library in the firmware, regards the single data segment as a sequence of Galois field elements, and maps the sequence in sequence to the Galois field polynomial Order coefficient, the highest order coefficient corresponds to the first byte of the data segment, and the lowest order coefficient corresponds to the last byte of the data segment; the single-chip microcomputer calls the fast Euclidean algorithm to calculate the greatest common factor of the polynomial and all candidate polynomials whose order is not greater than half of it in the Galois field; if the greatest common factor is a constant term, the polynomial is deemed to be an irreducible polynomial; if the test result shows that the polynomial is reducible, the single-chip microcomputer incrementally corrects the lowest order coefficient according to the preset increment and re-executes the test until it is determined to be an irreducible polynomial; the single-chip microcomputer generates a unique serial number based on the combination information of the polynomial order and coefficient; the serial number is written into the segment header identification area of ​​the corresponding data segment as the irreducible polynomial index.

[0022] Furthermore, step 3.2 specifically includes: the single chip calls in each data segment and its corresponding irreducible polynomial index in turn, and establishes a one-to-one corresponding temporary mapping table in the internal register; the single chip uses the irreducible polynomial index as the modulus polynomial to perform the Galois field subtraction operation on the current data segment in byte order: the single chip writes the first byte of the data segment directly into the first element of the differential vector; starting from the second byte, the single chip calculates the difference between the current byte and the previous byte by Galois field subtraction, and writes the calculation results into the subsequent elements of the differential vector in turn; the length of the differential vector is equal to the length of the data segment, and all elements are limited to the corresponding Galois field range; the single chip uses the differential vector elements as coefficients, and writes them in order. The Galois field polynomials of the same order are constructed in sequence, with the highest-order coefficient corresponding to the first element of the difference vector and the lowest-order coefficient corresponding to the last element of the difference vector, which together with the irreducible polynomial form a pair of adjoint polynomials; if the highest-order coefficient of the adjoint polynomial is zero in the Galois field, the single-chip microcomputer performs normalization processing according to the following rules: the single-chip microcomputer searches for the first non-zero coefficient from high order to low order, and promotes the coefficient and its corresponding power to the highest order position; for the moved intermediate coefficients, the single-chip microcomputer inserts a zero-value placeholder in the original position to ensure that the order of the polynomial remains unchanged; the single-chip microcomputer generates a group of adjoint polynomial coefficients according to the order of the coefficients of each order of the adjoint polynomial, and uses a continuous storage block to write into the data segment tail marker area.

[0023] Furthermore, step 3.3 specifically includes: counting the number of data segments in the current batch and the byte length of a single data segment; determining the number of rows of the interleaving matrix according to a fixed row number threshold set in the system parameter table; using the number of data segments directly as the number of columns of the interleaving matrix, and allocating continuous row-first storage blocks for the interleaving matrix in the internal memory; the single-chip microcomputer sequentially scans the irreducible polynomial index of each data segment and the leading coefficient of the corresponding adjoint polynomial coefficient group, and takes the modulo the algebraic sum of the two with the byte length of the single data segment, and then adds the integer value 1 to obtain a candidate interleaving depth; if the greatest common factor of the candidate interleaving depth and the number of rows of the interleaving matrix is ​​not equal to one, the single-chip microcomputer sequentially increases the candidate interleaving depth until it is equal to the interleaving matrix. The number of rows in the matrix is ​​coprime; the final interleaving depth is recorded as the coprime interleaving depth and archived in the system log; the single-chip microcontroller establishes a time pointer for time domain mapping, and sequentially traverses the differential vector elements of each data segment starting from zero; for the first write operation, the single-chip microcontroller multiplies the time pointer value by the coprime interleaving depth, and takes the remainder of the number of rows of the interleaving matrix, and the result is used as the target row address; the time pointer takes the remainder of the number of columns of the interleaving matrix to obtain the target column address; the single-chip microcontroller writes the current differential vector element into the unit corresponding to the target row address and the target column address of the interleaving matrix based on this; after the write is completed, the time pointer is incremented by one, and the cycle continues until all differential vector elements are written, and the interleaving matrix is ​​obtained.

[0024] Furthermore, in order to verify the reversibility of the time domain write mapping, the microcontroller separately calculates the read depth of the Galois field for Galois field mapping, and the read depth is set to the coprime interleaving depth plus an integer value of one; since the coprime interleaving depth is coprime to the number of rows of the interleaving matrix, the read depth of the Galois field and the number of rows of the interleaving matrix also remain coprime; the microcontroller applies the same type of multiplication and remainder mapping rule of the Galois field read depth to the row address of the interleaving matrix in an incrementing manner of the read pointer, reads out the previously written elements row by row and reorganizes them into a differential vector sequence in the register to obtain the interleaving matrix; by checking that the head and tail check codes of the differential vector are consistent with the original differential vector, it is confirmed that the bidirectional mapping is correct.

[0025] The present invention's single-chip microcomputer-based remote monitoring system and control method have the following beneficial effects: By integrating multi-level algorithms such as differential coding, Galois field polynomial indexing, coprime interleaving, Reed-Solomon redundancy checking, and cyclic redundancy compression on the single-chip microcomputer side, the present invention implements a complete chain of data processing from acquisition, encoding, fragmentation, verification, to compressed upload, significantly enhancing the robustness and information integrity of the remote monitoring system in high-noise environments. Compared with traditional monitoring systems, the present invention not only implements unique identification and reversible mapping in the data structure, but also effectively disperses and corrects sudden bit errors through interleaving and error correction mechanisms in the communication link, reducing reliance on retransmission mechanisms and thus improving overall communication efficiency and system stability. During execution, the system features automatic rollback and self-rehandshake mechanisms, enabling the proactive reestablishment of secure control channels in the event of continuous action failures, preventing long-term system loss of control or data drift. More importantly, the present invention uses a single-chip microcomputer as the edge computing core, without relying on complex hardware resources, to achieve efficient data preprocessing and structured encoding, adapting to the requirements of low-power, high-frequency, and small-size remote monitoring deployments. By leveraging this technological framework, the present invention has developed a remote monitoring solution that combines real-time performance, fault tolerance, and controllability. This solution is particularly suitable for applications such as power generation, industrial control, and smart agriculture, where link stability and decision-making accuracy are critical. While maintaining low power consumption, the system significantly improves data upload quality, closed-loop control execution, and communication anti-interference performance, offering significant value for engineering applications and promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0027] Figure 1 A schematic diagram of the system structure of a single-chip microcomputer-based remote monitoring system provided in an embodiment of the present invention;

[0028] Figure 2 A schematic diagram of the differential linear coding and interleaving matrix rearrangement principles provided by an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of the effect of generating a Reed-Solomon redundancy check vector provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The method of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments of the present invention.

[0031] In one aspect, this embodiment provides a single-chip microcomputer-based remote monitoring system, comprising: a single-chip microcomputer, a sensor acquisition unit, a wireless communication unit, and an actuator. When the single-chip microcomputer, the sensor acquisition unit, and the system are initialized, the wireless communication unit and the actuator are powered on in sequence. After the single-chip microcomputer completes a hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with a remote control terminal. After the handshake is completed, the single-chip microcomputer writes a unique identification code and enters a standby state. The single-chip microcomputer polls the sensor acquisition unit according to a preset sampling period to obtain raw data frames. The raw data frames are subjected to sliding window denoising and timestamp marking to generate and temporarily store data blocks to be processed. The single-chip microcomputer performs recursive processing based on differential linear coding and cyclic redundancy compression on the data blocks to maximize the error propagation distance and minimize redundancy while maintaining real-time performance, and outputs error-corrected compressed data blocks. The wireless communication unit reads the error-corrected compressed data blocks and uploads them to the remote control terminal via a secure channel. The remote control terminal parses the error-corrected compressed data blocks, generates control instructions based on a threshold strategy, and transmits them back. After receiving the control instructions, the single-chip microcomputer drives the actuator to operate and records an execution status log.

[0032] On the other hand, this embodiment also provides a control method for the above-mentioned single chip microcomputer-based remote monitoring system, the method comprising:

[0033] Step 1: Power on the MCU, sensor acquisition unit, wireless communication unit, and actuator in sequence. After the MCU completes the hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is completed, the MCU writes a unique identification code and enters the standby state.

[0034] Step 2: The MCU polls the sensor acquisition unit according to the preset sampling period to obtain the raw data frame; performs sliding window denoising and timestamp marking on the raw data frame to generate the data block to be processed and temporarily stores it;

[0035] Step 3: The MCU performs recursive processing based on differential linear coding and cyclic redundancy compression on the data block to be processed, maximizing the error propagation distance and minimizing redundancy while maintaining real-time performance, and outputs a compressed data block with error correction.

[0036] Step 4: The wireless communication unit reads the error-corrected compressed data block and uploads it to the remote control terminal through a secure channel. The remote control terminal parses the error-corrected compressed data block, generates a control instruction based on the threshold strategy, and transmits it back. After receiving the control instruction, the microcontroller drives the actuator to operate and records the execution status log.

[0037] Furthermore, the method also includes: Step 5: when the number of execution failures recorded in the execution status log reaches a set value, the single chip microcomputer automatically rolls back to Step 1 to re-handshake.

[0038] refer to Figure 1 : In the remote monitoring scenario, the core goal is to enable the physical quantities distributed on site to reach the remote control terminal in a timely, complete and reliable manner, and then the terminal will calculate and make decisions and send back instructions to drive the on-site actuators to complete the closed-loop action. The present invention uses a single-chip microcomputer as the computing center of the edge node, and incorporates the sensor acquisition unit, wireless communication unit and actuator into an integrated architecture. The three main lines of hardware timing constraints, data recursive processing and link security reinforcement jointly support the real-time and reliability of remote monitoring. First, the hardware timing constraints are reflected in the power-on sequence and task scheduling: the sensor acquisition unit and the wireless communication unit are powered on in a fixed order to avoid power disturbances to each other; the single-chip microcomputer, under the scheduling of the on-chip real-time operating system, manages the four types of tasks of sampling, encoding, transmission and execution with interrupt priority to ensure the cycle determinism of the critical path.

[0039] Secondly, the data recursive processing mechanism allows the original data to complete multi-level redundancy reduction and error-resistance processing locally. After the original data frame is denoised with a sliding window to remove high-frequency jitter, it is written with a timestamp to ensure time traceability. Differential linear coding then replaces the absolute value with the difference between adjacent samples, reducing entropy from an information-theoretic perspective and creating conditions for compression. Recursive processing establishes feedback between the differential vector and the historical state, allowing single-point errors to spread into a detectable pattern in the coding sequence. Combined with the subsequent cyclic redundancy check, it can be accurately located and corrected at the terminal. Thirdly, cyclic redundancy compression not only assumes the traditional verification function, but also reduces the bit length through a reversible sliding window compression algorithm, significantly reducing wireless bandwidth usage. The compressed output error-corrected compressed data block is structurally composed of a header information area, a data area, and a tail reserved area. The header information area stores the uncompressed length, the order of the generating polynomial, and the zero-padding length, providing complete context for terminal decompression and recovery. Link security is reinforced through a two-phase mechanism: a handshake phase generates a dynamic session key and binds it to a unique identification code. During the communication phase, an integrity check field and a replay protection counter are embedded in each frame header to prevent man-in-the-middle attacks and frame replay. Upon receiving the error-corrected compressed data block, the remote control terminal first verifies integrity using the cyclic redundancy check field, then performs differential inverse encoding and recursive inverse operations to recover the time series data. A threshold strategy is then used to fuse and judge multi-source information. When a sensor value crosses a critical range or a combination of multiple indicators triggers a logic threshold, a control command is immediately generated and transmitted back through the established secure channel.

[0040] The microcontroller constantly monitors the downlink channel. Once it captures a control command that matches its own identification code, it unpacks and parses the target parameters, actuating the actuator within milliseconds. Depending on the task, the actuator implements precise physical control using methods such as relay switching, stepper motor positioning, or pulse-width modulation dimming. It also records the start and end times of the action, feedback sensor readings, and result flags in an execution status log. This log is written to non-volatile memory and sent with the next batch of data blocks, allowing remote terminals to simultaneously monitor the on-site execution results, forming a closed-loop chain of data, decisions, actions, and feedback. If the log accumulates multiple consecutive execution failures, the microcontroller triggers an automatic rollback: resetting the wireless communication unit and re-handshaking to ensure that the abnormal state is promptly isolated. Overall, the present invention introduces lightweight edge computing on the MCU side, and pre-positions denoising, encoding, compression, encryption and other processing to the data source, which not only significantly reduces the wireless link overhead, but also improves the anti-interference and error correction capabilities; combined with the strategic judgment and dynamic regulation of the remote terminal, it constitutes a remote monitoring system suitable for complex environments such as industry, agriculture and buildings. While ensuring low power consumption and small size, it achieves comprehensive performance of high real-time, high reliability and high security, fully reflecting the core principles and implementation points of remote monitoring technology based on MCU.

[0041] Furthermore, in remote monitoring scenarios, actuators are located in unmanned, frontline locations. If an action fails and is not promptly repaired, the monitoring loop will fail. To ensure long-term autonomous operation of the system, the MCU logs the results of each control instruction after executing it and maintains a consecutive failure counter in the background. When the cumulative number of execution failures for the same instruction category in the log reaches a set threshold, the MCU immediately triggers an automatic rollback process: first, it stops the current task scheduling, resets the session registers of the wireless communication unit, and then forces the system to transition to the initial handshake phase, re-negotiating the dynamic session key and unique identification code with the remote control terminal. During the handshake, the MCU also reports the latest fault summary, allowing the remote control terminal to detect field anomalies and update the threshold policy. This mechanism enables the remote monitoring system to proactively disconnect unreliable channels, reestablish the encrypted channel, and refresh authentication information when potential hardware failures, link anomalies, or environmental interference are detected. This prevents the continued issuance of erroneous instructions or the injection of spurious data, ensuring data reliability and control security between field equipment and remote terminals. This automatic rollback design eliminates the window for manual intervention while providing the terminal with precise fault location information, enabling remote monitoring to maintain high availability, autonomy, and reliability in complex environments. Thresholds can be dynamically issued by the remote control terminal and adaptively adjusted based on the aging of on-site equipment or changing operating conditions, ensuring that oversensitivity or sluggishness are promptly corrected. Furthermore, the consecutive failure counter is automatically reset after a successful handshake and receipt of an acknowledgment frame, preventing false rollback triggers.

[0042] Furthermore, in remote monitoring scenarios, the sensor acquisition unit continuously generates raw data frames. If they are not deeply processed on the edge side, a large amount of wireless bandwidth will be occupied and the risk of link errors will be amplified. The present invention uses a single-chip microcomputer to locally execute the five-level cascade algorithm of step 3 to achieve redundancy reduction, error resistance and timing reordering of high-density data, laying a safe, reliable and low-latency foundation for the remote monitoring closed loop. First, step 3.1 divides the data block to be processed into equal-length data segments, and generates an irreducible polynomial index for each data segment on the Galois field. The significance of this is to decompose the continuous time series stream into independent mathematical entities and provide a one-to-one corresponding modular polynomial constraint for subsequent finite field differential coding. The irreducible polynomial index not only ensures the independence of the operation space of each data segment, but also provides a core random factor for the subsequent solution of the coprime interleaving depth, preventing data pattern collisions in large-scale monitoring networks.

[0043] Proceeding to step 3.2, the MCU performs finite field differential encoding on each data segment, generating a set of adjoint polynomial coefficients. Differential encoding converts the absolute amplitudes between adjacent samples into differential quantities, significantly reducing data entropy. The adjoint polynomial coefficients establish a complete table of differential polynomial coefficients for each data segment, ensuring that the differential information remains reversible within the finite field. This mechanism ensures that the encoded differential vector maintains stable statistical properties even under extreme fluctuations in the field environment, facilitating the capture of redundancy by the back-end compression algorithm.

[0044] Step 3.3 establishes a bidirectional mapping between the time domain and the Galois field using the coprime interleaving depth, rearranging the differenced data segments into an interleaving matrix. The coprime interleaving depth is derived from the irreducible polynomial index of each data segment and the fixed row number threshold of the system parameter table, maintaining a greatest common divisor of 1. The generation of the interleaving matrix evenly disperses the originally continuous data sequence in space. Any burst error, after being mapped into the matrix, diffuses simultaneously in both the row and column dimensions, effectively increasing the time interleaving redundancy of the physical channel. In remote monitoring applications, wireless links are susceptible to multipath fading and transient shielding. The cross-domain diffusion capability provided by the coprime interleaving matrix significantly reduces the probability of full-frame distortion.

[0045] Then, step 3.4 is performed to calculate the Reed-Solomon redundancy check vectors for the interleaved matrix column by column. This generates a set of check vectors and appends them to the interleaved matrix, resulting in a check interleaved matrix. Column-level Reed-Solomon check utilizes this error-correcting code to provide excellent correction performance for burst errors, allowing for the correction of consecutive byte errors at once. Appending the check vectors directly to new rows imbues the entire matrix with strong error correction capabilities without disrupting the original column order. For remote monitoring systems that require 24 / 7 operation, even if electromagnetic interference or weather conditions on-site degrade signal quality, the Reed-Solomon redundancy check vectors can still accurately restore the original differential vectors at the remote end.

[0046] After completing the checksum enhancement, proceed to step 3.5. The MCU linearly reconcatenates the check interleaving matrix and the Reed-Solomon redundancy check vector by row, performs binary cyclic redundancy compression, and finally outputs the error-corrected compressed data block to the transmit buffer. During the row reordering process, the original multidimensional structure of the interleaved matrix is ​​flattened into a one-dimensional bit stream, preparing for subsequent compression. Binary cyclic redundancy compression combines the dual functions of cyclic redundancy check (CRC) and sliding window entropy coding. CRC adds an overall check bit to the bit stream for end-to-end integrity verification; sliding window entropy coding detects repetitive patterns in real time based on the bit stream symbol distribution and replaces them with short codes, thereby compressing the payload length to half of its original size or even less. When outputting the error-corrected compressed data block, the MCU writes contextual information such as the uncompressed length, the order of the generating polynomial, and the trailing zero padding length into the header field to ensure that the remote control terminal can successfully restore the complete bit stream during the decoding phase. The sending buffer area shares dual-port storage with the wireless communication unit. Once the cache ready flag is set, the wireless communication unit will pull the error-corrected compressed data block and upload it along with the unique identification code through a secure channel.

[0047] In summary, by embedding a five-stage processing chain—Galois field operations, differential coding, coprime interleaving, Reed-Solomon error correction, and cyclic redundancy compression—into the MCU, the remote monitoring system completes denoising, redundancy reduction, and error-resistant packaging before the data leaves the field, significantly reducing the burden on the wireless link and significantly improving data security and reliability. After receiving the error-corrected compressed data blocks, the remote control terminal performs decompression, deinterleaving, decoding, and inverse differencing in reverse order, rapidly reconstructing high-fidelity time series data and achieving a closed-loop, fully integrated process from real-time perception to decision-making and control.

[0048] Furthermore, in remote monitoring applications, field sensors often generate data at a non-constant rate. Directly pushing these raw byte streams to the wireless link not only makes it difficult to ensure real-time performance, but also makes it difficult to locate bit errors due to inconsistent packet lengths. To this end, the present invention implements step 3.1 on the MCU side. Through strict byte-level segmentation and a Galois field irreducible polynomial indexing mechanism, this provides a unified and verifiable mathematical foundation for subsequent differential encoding, interleaving, and Reed-Solomon checks, fundamentally improving the robustness and traceability of the remote monitoring channel.

[0049] The MCU first reads the system parameter table and locks the threshold for the length of a single data segment. This threshold is set to a fixed value in bytes. Its selection takes into account the minimum frame length of the wireless communication unit, the sensor sampling interval, and the edge computing load. This ensures that the data uploaded in each frame has a stable payload size and that the encoded on-chip operations are predictable within the clock cycle. If the total number of bytes in the data block to be processed is not divisible by the threshold, the MCU pads the end of the data block with zero bytes until the divisibility condition is met. This ensures that all segment lengths are consistent, avoiding fragmentation at the link layer due to variable-length frames, thereby reducing the delay jitter during retransmission of the remote monitoring system.

[0050] Next, the MCU intercepts the data blocks sequentially from the first byte according to the threshold, obtains several data segments in turn, and allocates continuous storage blocks for each segment in the internal buffer, recording the first address and the last address. The use of continuous address mapping enables subsequent Galois field operations to use the addressing logic directly on the chip without the need for additional data movement, ensuring the low power consumption characteristics of edge nodes in remote monitoring scenarios. Subsequently, the MCU calls the finite field operation library in the firmware, regards each data segment as a sequence of Galois field elements, and maps the sequence in sequence to the order coefficients of the Galois field polynomial, with the highest order coefficient corresponding to the first byte of the data segment and the lowest order coefficient corresponding to the last byte of the data segment. This mapping method maintains the order of the original time series, allowing the polynomial to retain both causal order and algebraic encapsulation within the finite field, facilitating the subsequent derivation of differential coding and coprime interleaving depth.

[0051] To generate a unique and low-cost index for each data segment, the microcontroller uses a fast Euclidean algorithm to calculate the greatest common factor of the polynomial and all candidate polynomials of degree no greater than half within a Galois field. If the greatest common factor is a constant, the polynomial is irreducible within the current finite field, indicating the absence of lower-order factors and can be used to construct a high-strength differential linear coding modular polynomial. If the test result indicates reducibility, the microcontroller incrementally corrects the lowest-order coefficient by a preset increment and retests until the polynomial is determined to be irreducible. This "search-and-correct" strategy eliminates the need to store a large prime polynomial lookup table on-site, enabling real-time, batch generation of irreducible modular polynomials for segmented data. This saves flash memory space and avoids the security risks associated with leaking pre-generated tables.

[0052] Once irreducibility is confirmed, the microcontroller generates a unique serial number based on the combined information of the polynomial order and coefficients, and writes this serial number into the segment header identification area of ​​the corresponding data segment as the irreducible polynomial index. This serial number has a dual meaning in the entire transmission link: first, the remote control terminal can use it to directly reconstruct the finite field operation environment and perform inverse operations and error correction verification on the received data; second, the index itself participates in the calculation of the coprime interleaving depth, ensuring the randomness in the row and column mapping during cross-segment interleaving, thereby increasing the spread of burst errors. For this reason, step 3.1 not only completes the conventional byte neat segmentation, but also adds a rigorous algebraic fingerprint to the remote monitoring system through mathematical irreducibility, making each data segment a unique and verifiable operation unit in the entire network.

[0053] Through a series of fine-grained operations—threshold segmentation, zero-value padding alignment, continuous storage block mapping, Galois field polynomial construction, and irreducible index generation—step 3.1 establishes a bridge from physical data to algebraic entities for the remote monitoring system. This not only ensures the consistency of uploaded data in size, structure, and timing, but also provides high-quality initial conditions for subsequent algorithms such as differential encoding, interleaving, and error correction compression. This enables the system to maintain low latency, high accuracy, and verifiability even in long-term unattended environments, achieving truly reliable remote monitoring.

[0054] Furthermore, in remote monitoring systems, the MCU not only handles the real-time collection and preliminary cleaning of sensor data, but must also perform entropy reduction and error-resistance processing locally in the information-theoretic sense, ensuring that high-value time series information can be delivered securely, reliably, and with low latency to the remote control terminal even in environments with unstable wireless links and limited bandwidth. To this end, the present invention introduces a fine-grained algorithm flow based on Galois field differential coding and adjoint polynomial construction in step 3.2, enabling each data segment to have an independent and reversible finite field representation, and providing a highly recognizable and highly diffusible mathematical structure for subsequent interleaving and error correction.

[0055] After step 3.1 completes the segmentation and generates an irreducible polynomial index for each data segment, the MCU immediately proceeds to step 3.2. First, the MCU calls in each data segment and its corresponding irreducible polynomial index in turn, and establishes a one-to-one temporary mapping table in the internal register. This mapping table uses the first address of the data segment as the key and the irreducible polynomial index as the value, ensuring that subsequent operations can retrieve the correct modular polynomial in a constant time. Since remote monitoring sites often deploy a variety of heterogeneous sensors, the data segments come from diverse sources and have different frequencies. This mapping table structure avoids the addressing overhead caused by frequent context switching, providing solid support for the MCU to maintain real-time task scheduling in high-concurrency scenarios.

[0056] Next, the MCU uses the irreducible polynomial index as the modulus polynomial to perform a Galois field subtraction operation on the current data segment in byte order: the MCU writes the first byte of the data segment directly into the first element of the differential vector. Starting from the second byte, the MCU calculates the difference between the current byte and the previous byte using Galois field subtraction, and writes the calculation results into the subsequent elements of the differential vector in sequence. The length of the differential vector is strictly equal to the length of the data segment, and all elements are limited to the corresponding Galois field range. The essence of this step is to perform a high-pass filter on a finite field to eliminate the DC component within the data segment, thereby reducing the statistical entropy of the subsequent compression algorithm. When the remote monitoring system detects slowly changing environmental variables, the differential operation will generate a large number of low-amplitude symbols, allowing the cyclic redundancy compression stage to express the same information with shorter codewords, greatly saving wireless channel resources.

[0057] After completing the differential vector calculation, the microcontroller uses the differential vector elements as coefficients to sequentially construct Galois field polynomials of the same order. The highest-order coefficient corresponds to the first element of the differential vector, and the lowest-order coefficient corresponds to the last element of the differential vector. Together with the irreducible polynomial, they form a pair of adjoint polynomials. The existence of adjoint polynomials not only provides reversible encapsulation for each segment of data, but also amplifies the error diffusion distance during recursive processing and coprime interleaving, thereby improving detectability and repairability during remote decoding. In remote monitoring scenarios, link noise exhibits the dual characteristics of burstiness and randomness. After the introduction of adjoint polynomials, even if a single-point error invades the differential vector, it will diffuse to a higher order after polynomial mapping, facilitating subsequent error correction logic positioning.

[0058] If the highest-order coefficient of the adjoint polynomial is zero in the Galois field, the microcontroller processes it according to the normalization rules: the microcontroller searches for the first non-zero coefficient from high order to low order, and raises the coefficient and its corresponding power to the highest order position; for the intermediate coefficients that are moved, the microcontroller inserts a zero-value placeholder in the original position to ensure that the order of the polynomial remains unchanged. This normalization process solves the problem of leading zeros that may appear in the measured data, and avoids decoding failures caused by order mismatch during the inverse operation of the remote control terminal. After the normalization is completed, the microcontroller generates a group of adjoint polynomial coefficient groups according to the order of the coefficients of each order of the adjoint polynomial, and writes them into the end-of-segment marker area of ​​the data segment using continuous storage blocks. The fixed layout of the end-of-segment marker area enables the wireless communication unit to directly move the encoding results in DMA mode without traversal or splicing, further reducing the bus occupancy time.

[0059] Through the chained operations described above, step 3.2 not only implements Galois field differential encoding and adaptive normalization of the original data, but also inserts verifiable adjoint polynomial metadata at the segment level, establishing a dual association between data content and algebraic fingerprints. After receiving the error-corrected compressed data block, the remote control terminal can rapidly reconstruct the finite field environment based on the irreducible polynomial index at the segment header and the adjoint polynomial coefficient set at the segment tail, performing differential inverse operations and error location. Any tampering or misrepresentation will be revealed as a polynomial mismatch during the reconstruction process, safeguarding the integrity and security of the remote monitoring link. Thus, step 3.2 performs a deep edge computing preprocessing on the MCU side, laying a solid algebraic foundation for subsequent coprime interleaving, Reed checksum, and cyclic redundancy compression. This ensures that the remote monitoring system can maintain a low-latency, highly reliable, and secure data closed loop even in complex electromagnetic environments, frequent scene switching, and long periods of unattended operation.

[0060] Furthermore, in the remote monitoring link, burst errors often show the characteristics of time domain aggregation. If they are uploaded directly without being broken up, the entire segment of data will be concentratedly damaged in the same wireless frame, and unrecoverable errors will easily occur during decoding. To this end, the present invention implements the interleaving rearrangement of the dual dimensions of time domain and Galois field through step 3.3 on the microcontroller side, so that the differential vector elements are evenly distributed in two-dimensional space before transmission, greatly improving the error diffusion distance, thereby significantly increasing the remote error correction success rate. This step first counts the number of data segments in the current batch and the byte length of a single data segment; then, the number of rows of the interleaving matrix is ​​determined based on the fixed row number threshold in the system parameter table, and the number of data segments is directly used as the number of columns, thereby applying for continuous row-first storage blocks in the internal memory at one time, avoiding fragmentation caused by multiple dynamic allocations, and improving the memory utilization of the remote monitoring node at a high sampling frequency.

[0061] To assign independent, non-overlapping write paths to each column of data segments, the microcontroller sequentially scans the irreducible polynomial index and the leading coefficient of the corresponding adjoint polynomial coefficient group for each data segment. The algebraic sum of these two values, modulo the byte length of the individual data segment, is then added to the integer value of one to obtain a candidate interleaving depth. This candidate value is strongly correlated with the data itself, effectively preventing the depth parameter from being predicted, thereby suppressing bulk data corruption caused by malicious replay attacks on wireless links. If the greatest common divisor of the candidate interleaving depth and the number of rows in the interleaving matrix is ​​not equal to one, the microcontroller increments the candidate interleaving depth until it is coprime with the number of rows in the interleaving matrix. This coprime relationship ensures the traversability of the write mapping in the row dimension, preventing the time pointer from falling into short-term loops during the scan process and ensuring that each differential vector element covers a different row address in the matrix. The resulting coprime interleaving depth is logged to the system log. When the remote control terminal needs to perform an inverse mapping, it can directly reference this value for Galois field read mapping without recalculation.

[0062] The MCU then establishes a time pointer for time-domain mapping, sequentially traversing the differential vector elements of each data segment starting from zero. For the first write operation, the MCU multiplies the time pointer value by the coprime interleaving depth and takes the modulus of the number of rows in the interleaving matrix, using the result as the target row address. The time pointer takes the modulus of the number of columns in the interleaving matrix to obtain the target column address. By calculating the double remainder of this row and column address, the MCU writes the current differential vector element into the target cell of the interleaving matrix. After the write is complete, the time pointer increments by one, and the above mapping process is repeated until all differential vector elements have been written. Because the coprime interleaving depth ensures that the row address generation sequence and the row number are congruently mapped, all elements are quasi-randomly distributed in the matrix space. This distribution can maximize the diffusion of consecutive errors to multiple column vectors and check rows when the wireless channel is subject to sudden interference, allowing the subsequent Reed-Solomon redundancy check to correct more byte errors with fewer redundant symbols. For remote monitoring systems that require stable operation 24 / 7, this interleaving method effectively reduces the probability of full-frame loss due to environmental noise, building shadows, or multipath fading, ensuring that remote control terminals can still restore complete, continuous, and time-correct monitoring data under complex working conditions.

[0063] Furthermore, the interleaving matrix adopts a row-first storage layout, consistent with the wireless communication unit's direct memory access channel. This allows for the subsequent Reed-Solomon column check process without the need for additional transposition, reducing the number of memory copies within the MCU and lowering bus power consumption. The selection of the coprime interleaving depth is performed entirely locally on the MCU, without relying on external lookup tables. This not only saves flash memory space but also prevents attackers from exploiting fixed parameters and exposing the link structure. Through this series of designs, step 3.3 builds a "data buffer firewall" for the remote monitoring system that balances real-time and security. Error scattering and spatial balancing are performed at the source, providing ideal input for the subsequent column-level Reed-Solomon check and row-level cyclic redundancy compression. This keeps the wireless transmission error rate within the correctable range without sacrificing sampling frequency, fully meeting the stringent remote monitoring requirements for high reliability, low latency, and long-term self-healing.

[0064] Furthermore, in the actual application of remote monitoring, the single-chip microcomputer must not only upload the field sampling data after encapsulating it through differential coding, coprime interleaving and Reed-Solomon redundancy check, but also perform local self-checking on the reversibility of the entire interleaved write mapping to prevent write misalignment caused by register flips, power outages or peripheral bus interference, thereby propagating unrecoverable structural errors on the link. To this end, after completing the generation of the interleaved matrix, the present invention introduces a set of Galois field read mapping verification processes. The core idea is to construct an additional read depth that is also coprime with the number of rows of the interleaved matrix for the coprime interleaving depth used in the write phase, and traverse the matrix in reverse. Finally, the read differential vector is compared with the original differential vector head and tail check code. If they are completely consistent, it indicates that the write-read mapping is bidirectionally reversible.

[0065] First, in the interrupt callback when writing to the interleaved matrix is ​​complete, the microcontroller reads the coprime interleaving depth that has just been archived in the system log and directly performs an integer addition operation within the arithmetic unit, setting the result as the Galois field read depth. Since the coprime interleaving depth is already coprime with the number of rows in the interleaved matrix, simply adding one will not destroy its coprime property, and it remains coprime with the number of rows under most actual row values. This design avoids the delay caused by the additional search algorithm and gains valuable processing time for the strict "millisecond-level" packet cycle requirements in remote monitoring scenarios. At the same time, the read depth and write depth differ only by a minimum positive integer, ensuring that the cycle length of the read mapping sequence and the write mapping sequence remains equal to the number of matrix rows, and no duplication or omissions will occur.

[0066] The microcontroller then clears the dedicated read registers and initializes the read pointer to zero. As the read pointer increments, it modulo the number of rows of the interleaved matrix, using the Galois field read depth as a multiplier, to obtain the current row address. The pointer modulo the number of columns of the interleaved matrix to obtain the column address. This same modulo-multiplication mapping follows the same formula used to generate row addresses during the write phase, differing only in the multiplication factor. Because the read depth is coprime to the number of rows, the modulo-multiplication sequence must cover all row addresses after traversing the number of rows - 1 times, thus achieving a complete, one-to-one readout sequence. The microcontroller performs a single-cycle direct addressing of each mapped address, loading the differential vector elements stored in that cell into an on-chip register and reassembling them into a differential vector sequence according to the column ordering rules recorded during the write. During the readout process, the microcontroller performs no decoding or verification, ensuring that the time-domain sequence is precisely aligned with the original write order. This approach significantly reduces the computational effort, lowering the on-chip computing power and power consumption, and aligning with the design goal of remote monitoring nodes that emphasizes long-term, low-power operation.

[0067] Once all elements have been reassembled, the MCU immediately extracts the checksum fields reserved at the beginning and end of the differential vector and compares them bit by bit with the original checksum stored in the high-priority register before writing. If the two checksums are identical, the write-read mapping is determined to be flawless at both the byte and timing levels. If any discrepancies are detected, the MCU writes a checksum failure flag to the system log and triggers a soft interrupt, pausing the current batch of data upload until the coprime depth calculation and interleaved write are re-executed before attempting again. Through this "local closed-loop self-test," the system can detect and isolate potential misalignments before data leaves the field, significantly reducing the probability of large blocks of data being discarded due to structural errors at the remote terminal.

[0068] It is worth emphasizing that in the long-distance wireless transmission environment of the remote monitoring link, any irreversible bit dislocation will be magnified into a column alignment error during the deinterleaving and error correction process, thereby affecting the decoding success rate of the entire column Reed-Solomon checksum. By dynamically generating the Galois field read depth and verifying the bidirectional mapping, the present invention enables the single-chip microcomputer to have the ability to quickly diagnose and self-heal on the edge side; even if the scale of the interleaving matrix is ​​expanded due to on-site needs, as long as the row number threshold remains a fixed constant in the system parameter table, the above-mentioned mutual primacy and reversibility still hold, fully demonstrating the advantage of decoupling the algorithm from the hardware configuration. Therefore, the reversibility verification of step 3.3 is not only a self-consistent test of the correctness of the internal calculations of the single-chip microcomputer, but also an important technical grasp for the remote monitoring system to ensure data integrity, improve the link fault tolerance rate, and reduce the number of manual inspections, providing a solid reliability guarantee for unmanned monitoring tasks in extreme environments.

[0069] In remote monitoring scenarios, wireless links are prone to continuous byte-level errors due to factors such as multipath fading, weather disturbances, and electromagnetic interference. Without strong error-correction coding embedded in the MCU, once data is damaged in the air, the remote control terminal cannot recover the original information through simple retransmission or parity checks. Step 3.4 is the core error correction module added to the edge node by this invention. Its function is to further encapsulate the differential vectors, which have been scattered by coprime interleaving, into a Reed-Solomon redundancy check structure with "multi-byte correction" capabilities, thereby significantly improving the self-recovery capability of the remote monitoring link.

[0070] The single chip first calls each column vector of the interleaving matrix in turn, and regards the jth column vector as the Galois field GF(2 8 ) and mapped to a message polynomial of length n Where n is the number of rows in the interleaving matrix, d i，j The corresponding element of the differential vector with row index i and column index j is the polynomial variable x. By preserving the order of "first element mapping to highest-order coefficient," the message polynomial fully captures the timing information of the column vector within a finite field, ensuring that the original column data can be unambiguously reconstructed once the remote end completes decoding. This is particularly important for remote monitoring that requires millisecond-level time synchronization.

[0071] Next, the MCU calls the Reed-Solomon encoding library in the firmware, sets the number of redundant check symbols to t bytes, and selects the primitive element α in the same Galois field to construct the generating polynomial The order of the generating polynomial is t. Here, α is fixed to the value in the system parameter table to ensure that all edge nodes and remote terminals work in the same finite domain, avoiding the hidden danger of codeword incompatibility when cross-node collaboration. After setting the generating polynomial, the microcontroller generates the polynomial D for each message. j (x) uniformly performs the standard Reed-Solomon encoding process of left shifting t bits and modulo division g(x), and obtains the check polynomial R j (x) = x t ·D j (x)modg(x).

[0072] The modulo division operation here is essentially multiplying the message polynomial by x t Then take the remainder in the ideal spanned by the generating polynomial, and the remainder It provides the ability to simultaneously detect and correct up to For clustered errors common in remote monitoring wireless links, this multi-byte error correction capability is far superior to single-byte parity and CRC.

[0073] Then the microcontroller forms the encoded polynomial C j(x) = x t D j (x)+R j (x), and R j The coefficient sequence of (x) {r k，j}Organize into a Reed-Solomon redundancy check vector P with a fixed length of t in the order from high to low order j This vector is directly appended to the end of the original j-th column vector, increasing the column vector length from n to n+t. This "column vector expansion" approach, rather than creating a new independent check area, allows the interleaved matrix to maintain row-first contiguous storage in physical layout. Subsequent row reordering and cyclic redundancy compression can be processed in a single stream in DMA mode, eliminating the need for additional copying, effectively reducing MCU bus usage and power consumption.

[0074] After all columns have been appended, the microcontroller reassembles them in its internal memory in a row-first manner, resulting in a parity matrix S with n+t rows and the same number of columns as the original interleaving matrix. Row-first reassembly ensures the spatial locality of the matrix, allowing subsequent row-vector-level cyclic redundancy compression to be scanned naturally in sequence without encountering cache failures caused by cross-row and cross-column jumps. It is worth noting that because the previous step ensures that the interleaving depth is coprime with the number of rows, the addition of t rows does not disrupt the congruence traversal of the write mapping; the remote terminal only needs to read n+t rows during the inverse operation to share a completely one-to-one corresponding interleaving mapping sequence.

[0075] By introducing the Reed-Solomon redundancy check vector, the present invention upgrades the differential vector from "only relying on CRC error detection" to a highly reliable codeword that is "error-correctable and error-detectable"; through column-vector level processing and row-first re-joining, the coding computation is evenly distributed to each data segment, avoiding the real-time dead zone caused by "exhausting computing power for large blocks of data at once". Ultimately, when the check interleaving matrix is ​​transmitted over a wireless link, even if it is subject to continuous interference of up to t bytes, it can be completely restored at the remote control terminal, providing accurate and coherent time series data for closed-loop control decisions. This mechanism improves the survivability of the remote monitoring system in the face of extreme channel conditions from the source, reduces the number of retransmissions, shortens the fault detection response time, and provides all-weather, low-maintenance, and highly reliable data protection for industrial sites, smart agriculture and other scenarios.

[0076] In the remote monitoring link, although the data has a certain error correction capability after being interleaved and Reed-Solomon redundancy check, it still needs to add an extremely low-cost but very efficient integrity protection before leaving the microcontroller. Step 3.5 uses cyclic redundancy check to finally encapsulate the data that has undergone multi-level preprocessing, so that when it passes through a wireless channel with a complex noise environment and high uncertainty, it can achieve high-probability error detection and rapid positioning with minimal bit overhead, thereby further shortening the total response time of the remote monitoring system. Specifically, the microcontroller first reads each row vector s of the check interleaving matrix S in turn. i ={s i，0 , s i，1 ,...,s i，m-1} and seamlessly concatenate in strict accordance with the order of "row order from top to bottom, column order from left to right", constructing a one-dimensional sequence b = {b0, b1, ..., b L-1}, b i×m+j =s i，j This linearization operation converts the two-dimensional matrix into a continuous address space, facilitating subsequent direct storage into the wireless communication unit's transmit buffer and maximizing the efficiency of on-chip DMA transfers. Furthermore, row-first mapping preserves the uniform error diffusion characteristics of pre-order coprime interleaving, providing a more random input sequence for CRC checking.

[0077] Then, the MCU reads the cyclic redundancy check generator polynomial g according to the system parameter table. c (x) = x c +g c-1 x c-1 +…+g1x+g0, where c is the polynomial order and all coefficients g k The generating polynomial is consistent throughout the remote monitoring network, allowing the remote control terminal to directly reproduce the same CRC environment after receiving the data without additional negotiation. The microcontroller then treats the byte sequence b as a message polynomial consisting of 8-bit little-endian elements. And shift left by c bits to get x c ·B(x). Divide the polynomial modulo g over GF(2) c (x) can get the remainder where {z k} is a cyclic redundancy check vector of length c. Since both division and XOR can be quickly completed in the logic shifter and ALU combination logic, the operation can be completed within the MCU clock cycle and will not block the real-time sampling beat of remote monitoring. After appending r(x) to the end of the message polynomial, the encoded polynomial C(x) = x is formed. cB(x)+r(x), the corresponding bit stream only increases c bits compared to the original message, but mathematically establishes the relationship between C(x) and g c The congruence relationship between (x) and (x) enables the remote control terminal to instantly determine whether any bit flips occurred during transmission of the entire frame of data with a single modular division. If the terminal detects a non-zero remainder, it can immediately request a retransmission without having to initiate the more computationally expensive Reed-Solomon decoding process, thereby keeping exception handling latency to milliseconds. If CRC verification passes, the index and coefficient combination information previously left at the segment header and footer is then used to perform deinterleaving and differential inverse operations. Error correction decoding can then be performed under the premise that integrity has been confirmed, ensuring that back-end decisions are based on highly reliable data.

[0078] It is worth emphasizing that most remote monitoring nodes are deployed in power, petrochemical, or outdoor agricultural environments, and the equipment has long been limited by power consumption budgets and communication charges. Step 3.5 trades extremely low redundancy overhead for significant error detection capabilities, realizing a hierarchical reliability strategy of "error detection first, error correction second, and retransmission last." Together with the multi-layer fault-tolerant system formed by the previous steps, it not only reduces the repeated retransmission of large-size data packets in harsh channels, but also avoids errors triggering erroneous actions at the execution layer, thereby improving the overall security and economy of the system. In other words, by reasonably embedding the cyclic redundancy check after the row sequence splicing of the interleaving matrix and before wireless transmission, the present invention ensures that the remote monitoring data reaches the client while ensuring the extremely low occupancy of on-chip resources, while laying a solid and reliable bit-level foundation for back-end policy judgment and on-site execution.

[0079] The bit stream length corresponding to the encoded polynomial C(x) is 8L+c bits. In order to reduce redundancy, the single-chip microcontroller calls the binary cyclic redundancy compression algorithm in the firmware: starting from the most significant bit, a sliding window is used to scan the encoded bit stream. If a continuous repeated segment that is completely consistent with the feedback pattern of the generating polynomial is detected, a one-bit marker 1 followed by an unsigned exponent - a Golomb code is used to indicate the number of times the segment is repeated; if the window content does not match the feedback pattern, a one-bit marker 0 is output and the bits are passed through byte by byte as is; this process performs entropy compression on highly redundant cyclic segments while ensuring decoding reversibility, thereby shortening the overall code length. After compression, the bit sequence e = {e0, e1, ..., e Q-1}, where Q ≤ 8L + c; the MCU reassembles e into a byte stream E using eight-bit alignment. If the last bit is less than eight, it pads the least significant bit with zeros and records the number of padding bits δ. Finally, the MCU writes a four-byte header to the head of the transmit buffer, which contains, in order, the uncompressed bit length 8L + c, the generator polynomial order c, the number of padding bits δ, and the header's own cyclic redundancy check value. It then continuously writes the compressed data byte stream E, forming an error-corrected compressed data block and awaiting upload scheduling by the wireless communication unit.

[0080] The following example illustrates a complete sampling-encoding-reporting-verification process in a remote monitoring scenario for a smart greenhouse. For demonstration purposes, all values ​​are small enough to be easily calculated manually; in actual deployments, the ratio can be increased based on bandwidth and computing power requirements. The MCU model used is the STM32F411, with a main frequency of 100MHz, 128KB of on-chip SRAM, and an on-chip finite field arithmetic library operating on the Galois field GF(2 8 ), using the primitive polynomial x 8 +x 4 +x 3 +x 2 +1 (hexadecimal representation 0x11D). The wireless communication unit is a LoRa-WAN Class A node with a maximum payload of 51 bytes. The system parameter table gives: Single data segment length threshold L seg = 8 bytes; interleaving matrix fixed row number threshold n = 8; Reed-Solomon redundant symbol number t = 4; cyclic redundancy check generator polynomial order c = 16, generator polynomial; g c (x) = x 16 +x 12 +x 5 +1(CRC-CCITT).

[0081] The sensor combination (temperature, humidity, light, and carbon dioxide) is subjected to sliding window denoising and millisecond-level timestamp marking to generate a 16-byte data block to be processed: 60, 62, 65, 67, 68, 6A, 6D, 70, 5A, 5C, 5D, 5F, 62, 64, 66, and 69. The hexadecimal byte order is temperature first and then humidity, arranged in that order.

[0082] The data block length of 16 bytes is divisible by the threshold of 8, so there is no need to fill it with zeros. The microcontroller intercepts the data sequentially from the first byte and obtains two segments: Each segment in GF(2 8 ) is considered as a polynomial coefficient vector, with the highest order corresponding to the first byte. For segment 0, construct f0(x)=x 7 +x 5 +x 4 +x 3 +x 2 +x+1. The fast Euclidean algorithm takes the greatest common factor of all candidate polynomials with an order ≤ 4, yielding only the constant 1. Therefore, f0(x) is irreducible. The microcontroller generates the serial number 50. The same method is used for segment 1 to obtain the irreducible polynomial f1(x) and the serial number 51. Both serial numbers are written into the identification area of ​​their respective segment headers.

[0083] Difference vector of segment 0

[0084] The same processing is performed on segment 1 to obtain {5A, 02, 01, 02, 03, 02, 02, 03};

[0085] The differential vectors are mapped to polynomials of the same order h0(x) and h1(x). The highest order coefficient d0 = 60≠0 in segment 0 does not need to be normalized; the same applies to segment 1. k}Write the segment tail identification area sequentially to complete the archiving of the accompanying polynomial coefficient group.

[0086] The number of segments in this batch of data is m=2, and the microcontroller directly takes the number of columns m. Scan the segment header sequence number and the first item of the accompanying coefficient group: Select the first term 7; gcd(7, 8) = 1, and the depth and the number of rows are coprime. Record the coprime interleaving depth d = 7. Increment the time pointer τ from 0, and perform row = (τ·d) mod 8 and column = τ mod 2 on each differential element until the 8×2 interleaving matrix A is fully populated with 16 elements.

[0087] Build the message polynomial for the column 0 vector {a0, ..., a7} Assume that the number of redundant symbols t = 4, and the primitive element α is the field generator. Generator polynomial g(x) = (x-α 0 )(x-α 1 )(x-α 2 )(x-α 3 ); calculate R0(x)=x 4 D0(x) mod g(x); obtain the coefficient vector {A4, 7B, C5, 1E}. The same method is used for column 1 to obtain {B1, 6A, 29, D4}. Each vector is appended to form an extended column, increasing the number of interleaving matrix rows to n + t = 12, forming the parity check interleaving matrix S.

[0088] The MCU linearizes S in row-first order, generating a sequence of L = (8 + 4) × 2 = 24 bytes: 60, 5A, 02, 02, 03, 01, 02, 03, 5A, 02, 01, 02, 03, 02, 02, 03, A4, B1, 7B, 6A, C5, 29, 1E, D4; the message polynomial is Shift left 16 bits and then use g c (x) modulo division to obtain the remainder r(x) = x 16 B(x)modg c (x) = B4C3 16 =x 15 +x 13 +x 12 +x 10 +x 9 +x 1 +x 0 ; The vector {B4, C3} is appended to the end of the sequence to generate the final coding polynomial C(x) = x 16B(x)+r(x); the length of the encoded bit stream is 24×8+16=208 bits, which is still within the range of LoRa single packet carrying capacity.

[0089] The wireless communication unit uploads 26 bytes (24-byte payload + 2-byte CRC) over LoRaWAN at once. The remote control terminal replicates the CRC polynomial and performs a modulo division on the received 208-bit bit stream. If the remainder is 0, the frame is considered complete. Then, an inverse mapping is performed using a coprime interleaving depth of 7, the column vector is extracted, and Reed-Solomon decoding is performed using the same g(x). Any consecutive bit errors up to 4 bytes are automatically corrected. After decoding, an inverse differential operation is performed to restore the original temperature and humidity sequence for policy decisions.

[0090] A single acquisition-editing-transmission process takes about 3ms on the MCU side, accounting for 0.3% of the MCU's CPU time. The actual packet length is increased by 62% compared to the original 16 bytes in exchange for double-layer error correction and whole-frame error detection. The upload success rate is increased from 88% to 99.7% in a measured humid steel structure greenhouse environment, fully demonstrating the high reliability, low occupancy and rapid implementation of the present invention's solution in remote monitoring.

[0091] like Figure 2 The schematic diagram of the differential linear encoding and interleaving matrix rearrangement principle, shown in Figure 2, details the core processing flow of the data block to be processed. First, the microcontroller divides the data block into equal-length segments according to the fixed-length threshold set in the system parameter table, forming several equal-length segments, such as data segments D1, D2, D3, and D4. Each data segment is allocated a contiguous storage block in the internal buffer, and the corresponding starting and ending addresses are recorded. During the finite field differential encoding stage, the microcontroller sequentially loads each data segment and its corresponding irreducible polynomial index, establishing a one-to-one temporary mapping table in the internal register. Using the irreducible polynomial index as the modulus polynomial, the microcontroller performs a Galois field subtraction operation on the current data segment in byte order. Specifically, the first byte of the data segment, D1, is directly written into the first element of the difference vector. Starting from the second byte, the microcontroller uses Galois field subtraction to calculate the difference between the current byte and the previous byte, namely, D2-D1, D3-D2, and D4-D3, and writes the result to the subsequent elements of the difference vector. The length of the differential vector is equal to the length of the data segment, and all elements are confined to the corresponding Galois field. During the interleaving matrix rearrangement process, the microcontroller determines the number of rows in the interleaving matrix based on the fixed row number threshold set in the system parameter table, and directly uses the number of data segments as the number of columns in the interleaving matrix. By scanning the irreducible polynomial index of each data segment and the leading coefficient of the corresponding adjoint polynomial coefficient group, a candidate interleaving depth is calculated and ensured to be coprime with the number of rows in the interleaving matrix, ultimately forming a coprime interleaving depth. Using time pointers for time domain mapping, the differential vector elements are rearranged to the corresponding positions in the interleaving matrix according to specific mapping rules, forming an interleaving matrix structure with error correction capabilities.

[0092] As Figure 3 shown, the Reed-Solomon redundancy check vector generation effect diagram reveals the construction process of the check interleaving matrix and its relationship with the associated polynomial coefficient array. The check interleaving matrix is composed of the original data part and the check code part, where the original data part contains the interleaved and rearranged matrix elements M11, M12, M13, M14, etc. These elements are orderly arranged in row-column structure to form a complete data matrix. In the check vector generation process, the single-chip microcomputer calculates the Reed-Solomon redundancy check vector according to the column of the interleaving matrix. The specific operation is to perform a specific algebraic operation on the matrix elements of each column to generate the corresponding check codes P1, P2, P3, etc. These check codes have strong error correction capability and can detect and correct various error types that may occur during transmission. The generation of the check vector follows the mathematical principles of Reed-Solomon encoding, and the redundancy information is generated in the finite field through polynomial operation. The associated polynomial coefficient array plays a key role in the entire process, and the coefficient array 1, the coefficient array 2, the coefficient array 3, and the coefficient array 4 correspond to the associated polynomial coefficient information of different data segments. These coefficient arrays not only participate in the differential encoding process, but also provide necessary parameter support for the generation of check vectors. The single-chip microcomputer generates the corresponding coefficient array according to the order of the coefficients of the associated polynomial of each order, writes the data segment tail identification area using the continuous storage block, and ensures the integrity of the data. Finally, the single-chip microcomputer re-linearly splices the check interleaving matrix and the Reed-Solomon redundancy check vector according to the row, and performs binary cyclic redundancy compression processing. This process not only realizes the effective compression of data, but also enhances the reliability of data transmission, ensures the maintenance of real-time while maximizing the error propagation distance and minimizing the redundancy, and forms a compressed data block with strong error correction capability.

[0093] Although the specific embodiments of the present application are described above, those skilled in the art should understand that these specific embodiments are only illustrative, and those skilled in the art can make various omissions, replacements and changes to the details of the above-mentioned method and system without departing from the principles and essence of the present application. For example, combining the above-mentioned method steps, performing substantially the same function in substantially the same way to achieve substantially the same result according to the same method is within the scope of the present application. Therefore, the scope of the present application is only limited by the appended claims.

Claims

1. A remote monitoring system based on a single chip microcomputer, characterized in that: The system includes: a single-chip microcomputer, a sensor acquisition unit, a wireless communication unit, and an actuator. When the single-chip microcomputer, the sensor acquisition unit, and the system are initialized, the wireless communication unit and the actuator are powered on in sequence. After the single-chip microcomputer completes a hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with a remote control terminal. After the handshake is completed, the single-chip microcomputer writes a unique identity code and enters a standby state. The single-chip microcomputer polls the sensor acquisition unit according to a preset sampling period to obtain raw data frames. The raw data frames are subjected to sliding window denoising and time stamping to generate and temporarily store data blocks to be processed. The single-chip microcomputer performs recursive processing based on differential linear coding and cyclic redundancy compression on the data blocks to maximize the error propagation distance and minimize redundancy while maintaining real-time performance, and outputs error-corrected compressed data blocks. The wireless communication unit reads the error-corrected compressed data blocks and uploads them to the remote control terminal via a secure channel. The remote control terminal parses the error-corrected compressed data blocks, generates and returns control instructions based on a threshold strategy, and receives the control instructions. After receiving the control instructions, the single-chip microcomputer drives the actuator to operate and records an execution status log.

2. A control method for implementing the single chip microcomputer-based remote monitoring system according to claim 1, characterized in that: The method comprises: Step 1: Power on the MCU, sensor acquisition unit, wireless communication unit, and actuator in sequence. After the MCU completes the hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is completed, the MCU writes a unique identification code and enters the standby state. Step 2: The MCU polls the sensor acquisition unit according to the preset sampling period to obtain the raw data frame; performs sliding window denoising and timestamp marking on the raw data frame to generate the data block to be processed and temporarily stores it; Step 3: The MCU performs recursive processing based on differential linear coding and cyclic redundancy compression on the data block to be processed, maximizing the error propagation distance and minimizing redundancy while maintaining real-time performance, and outputs a compressed data block with error correction. Step 4: The wireless communication unit reads the error-corrected compressed data block and uploads it to the remote control terminal through a secure channel. The remote control terminal parses the error-corrected compressed data block, generates a control instruction based on the threshold strategy, and transmits it back. After receiving the control instruction, the microcontroller drives the actuator to operate and records the execution status log.

3. The control method of the remote monitoring system based on the single chip microcomputer according to claim 2, characterized in that: The method further includes: Step 5: when the number of execution failures recorded in the execution status log reaches a set value, the single chip microcomputer automatically rolls back to Step 1 to re-handshake.

4. The control method of the remote monitoring system based on the single chip microcomputer according to claim 3, characterized in that: Step 3 specifically includes: Step 3.1: Divide the data block to be processed into data segments of equal length; the MCU generates an irreducible polynomial index for each data segment on the Galois field; Step 3.2: Perform finite field differential encoding on each data segment to generate a set of adjoint polynomial coefficients; Step 3.3: Use the coprime interleaving depth to establish a bidirectional mapping between the time domain and the Galois field, and rearrange the differenced data segments into an interleaving matrix; Step 3.4: Calculate the Reed-Solomon redundancy check vector for each column of the interleaving matrix, generate a check vector group, and append it to the interleaving matrix to obtain a check interleaving matrix; Step 3.5: The MCU linearly reconcatenates the check interleaving matrix and the Reed-Solomon redundancy check vector row by row, performs binary cyclic redundancy compression, and outputs the error-corrected compressed data block to the transmit buffer.

5. The control method of the remote monitoring system based on the single chip microcomputer according to claim 4, characterized in that: Step 3.1 specifically includes: the single chip microcomputer reads the system parameter table, obtains the threshold value of the length of a single data segment, which is set to a fixed value in bytes; if the total number of bytes of the data block to be processed cannot be divided by the threshold value, the single chip microcomputer fills zero-value bytes at the end of the data block to be processed until the divisibility condition is met; the single chip microcomputer intercepts the data block to be processed in sequence from the first byte according to the threshold value, obtains several data segments in sequence, and allocates a continuous storage block for each data segment in the internal buffer, and records the first address and the last address; the single chip microcomputer calls the finite field operation library in the firmware, regards the single data segment as a sequence of Galois field elements, and maps the sequence in sequence to the order system of Galois field polynomials The highest-order coefficient corresponds to the first byte of the data segment, and the lowest-order coefficient corresponds to the last byte of the data segment; the single-chip microcomputer calls the fast Euclidean algorithm to calculate the greatest common factor of the polynomial and all candidate polynomials whose order is not greater than half of it in the Galois field; if the greatest common factor is a constant term, the polynomial is determined to be an irreducible polynomial; if the test result shows that the polynomial is reducible, the single-chip microcomputer incrementally corrects the lowest-order coefficient according to the preset increment and re-executes the test until it is determined to be an irreducible polynomial; the single-chip microcomputer generates a unique serial number based on the combination information of the polynomial order and coefficients; and writes the serial number as the irreducible polynomial index into the segment header identification area of ​​the corresponding data segment.

6. The control method of the remote monitoring system based on the single chip microcomputer according to claim 5, characterized in that: Step 3.2 specifically includes: the single chip calls in each data segment and its corresponding irreducible polynomial index in turn, and establishes a one-to-one corresponding temporary mapping table in the internal register; the single chip uses the irreducible polynomial index as the modulus polynomial to perform the Galois field subtraction operation on the current data segment in byte order: the single chip writes the first byte of the data segment directly into the first element of the differential vector; starting from the second byte, the single chip calculates the difference between the current byte and the previous byte by Galois field subtraction, and writes the calculation results into the subsequent elements of the differential vector in turn; the length of the differential vector is equal to the length of the data segment, and all elements are limited to the corresponding Galois field range; the single chip uses the differential vector elements as coefficients, and constructs the differential vector in order. Create a Galois field polynomial of the same order, with the highest order coefficient corresponding to the first element of the difference vector and the lowest order coefficient corresponding to the last element of the difference vector, which together with the irreducible polynomial form a pair of adjoint polynomials; if the highest order coefficient of the adjoint polynomial is zero in the Galois field, the microcontroller performs normalization processing according to the following rules: the microcontroller searches for the first non-zero coefficient from high order to low order, and promotes the coefficient and its corresponding power to the highest order position; for the moved intermediate coefficients, the microcontroller inserts a zero value placeholder in the original position to ensure that the order of the polynomial remains unchanged; the microcontroller generates a group of adjoint polynomial coefficients according to the order of the coefficients of each order of the adjoint polynomial, and uses a continuous storage block to write into the data segment tail marker area.

7. The control method of the remote monitoring system based on the single chip microcomputer according to claim 6, characterized in that: Step 3.3 specifically includes: counting the number of data segments in the current batch and the byte length of a single data segment; determining the number of rows of the interleaving matrix according to the fixed row number threshold set in the system parameter table; using the number of data segments directly as the number of columns of the interleaving matrix, and allocating continuous row-first storage blocks for the interleaving matrix in the internal memory; the single-chip microcomputer sequentially scans the irreducible polynomial index of each data segment and the first coefficient of the corresponding adjoint polynomial coefficient group, and takes the modulo the algebraic sum of the two with the byte length of a single data segment, and then adds the integer value 1 to obtain the candidate interleaving depth; if the greatest common factor of the candidate interleaving depth and the number of rows of the interleaving matrix is ​​not equal to one, the single-chip microcomputer sequentially increases the candidate interleaving depth until it is equal to the number of rows of the interleaving matrix. until the numbers are mutually prime; the final interleaving depth is recorded as the mutually prime interleaving depth and archived in the system log; the single chip microcomputer establishes a time pointer for time domain mapping, and sequentially traverses the differential vector elements of each data segment starting from the value zero; for the first write operation, the single chip microcomputer multiplies the time pointer value by the mutually prime interleaving depth, and takes the remainder of the number of rows of the interleaving matrix, and the result is used as the target row address; the time pointer takes the remainder of the number of columns of the interleaving matrix to obtain the target column address; the single chip microcomputer writes the current differential vector element into the unit corresponding to the target row address and the target column address of the interleaving matrix based on this; after the write is completed, the time pointer is incremented by one, and the cycle continues until all differential vector elements are written, and the interleaving matrix is ​​obtained.

8. The control method of the remote monitoring system based on the single chip microcomputer according to claim 7, characterized in that: To verify the reversibility of the time-domain write mapping, the microcontroller separately calculates the read depth of the Galois field for Galois field mapping. The read depth is set to the coprime interleaving depth plus an integer value of one. Since the coprime interleaving depth is coprime with the number of rows of the interleaving matrix, the read depth of the Galois field and the number of rows of the interleaving matrix also remain coprime. The microcontroller applies the same multiplication-remainder mapping rule of the Galois field read depth to the row address of the interleaving matrix in an incrementing manner of the read pointer, reads out the previously written elements row by row, and reorganizes them into a differential vector sequence in the register to obtain the interleaving matrix. By checking that the head and tail check codes of the differential vector are consistent with the original differential vector, it is confirmed that the bidirectional mapping is correct.

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