High-speed AES decryption method, device and equipment based on FPGA and medium

Abstract

The invention relates to a high-speed AES (Advanced Encryption Standard) decryption method, device and equipment based on an FPGA (Field Programmable Gate Array) and a medium, which are characterized in that on the basis of the characteristic that front and back rounds of a calculation module are irrelevant in a decryption process, the traditional processing of a group of ciphertexts is improved into serial processing of four groups of ciphertexts in the same time by fully utilizing an idle time sequence of the calculation module, namely, the decryption calculation of the four groups of ciphertexts is completed, and the decryption efficiency is improved. Compared with a traditional full-parallel scheme, the AES decryption speed can be greatly improved, the resource occupation is only one fourth of that of the traditional full-parallel scheme, and therefore the application requirement of the AES in the field of high-speed data real-time processing of satellites is met.

Description

Technical Field

[0001] The present invention belongs to the technical field of data decryption, and relates to a high-speed AES decryption method, device, equipment and medium based on FPGA. Background Art

[0002] Satellite data transmission links are used to transmit payload data collected onboard to the ground via high-speed links. Because this data is often valuable, decryption is desirable. AES, a common commercial decryption method, is widely used in various scenarios. However, when applied to high-speed communications, decryption processing speeds cannot keep up with air interface data transmission rates, resulting in low adoption for high-speed, real-time satellite data processing. To improve AES decryption speed, direct full parallelization or clock-increasing are commonly employed. Full parallelization results in excessive resource overhead, while clock-increasing, while not significantly increasing resources, degrades overall timing, limiting its potential improvement. High-speed encrypted transmission between satellite and ground typically addresses this issue through post-process decryption, but this can result in delayed data processing. Therefore, to meet the application requirements of AES for high-speed, real-time satellite data processing, the question of how to effectively improve AES decryption speed remains a pressing technical challenge. Summary of the Invention

[0003] In response to the problems existing in the above-mentioned traditional methods, the present invention proposes a high-speed AES decryption method based on FPGA, an FPGA device with high-speed AES decryption function, a computer device and a computer-readable storage medium, which can more effectively improve the AES decryption speed and meet the application requirements of AES in the field of high-speed data real-time processing in satellites.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a high-speed AES decryption method based on FPGA is provided, comprising the steps of:

[0006] Generate all the keys required for AES decryption through the AES key expansion module in the FPGA chip and cache them in RAM;

[0007] If the current round of decryption is the first round of decryption, after reading the first round key from the RAM, the serial decryption logic module in the FPGA chip performs round key addition, row shift and byte replacement on the four sets of input ciphertexts according to the first round key; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shift logic and byte replacement logic. The round key addition logic is configured as a serial round key addition operation, the column obfuscation logic is configured as a serial column obfuscation transformation operation, the row shift logic is configured as a serial row shift transformation operation, and the byte replacement logic is configured as a serial byte replacement operation.

[0008] If the current round of decryption is the intermediate round after the first round, the serial decryption logic module serially performs round key addition, column confusion, row shift, and byte replacement on the four sets of pre-processed data according to the secret key corresponding to the intermediate round after reading the secret key corresponding to the intermediate round from RAM;

[0009] When performing final round decryption on the data, the round key addition logic is used to perform round key addition on the four groups of pre-processed data according to the final round key read from the RAM.

[0010] In another aspect, an FPGA device with high-speed AES decryption function is provided, comprising:

[0011] AES key expansion module, used to generate all the keys required for AES decryption and cache them in RAM;

[0012] A serial decryption logic module is used to read the first-round key from the RAM and then serially perform round key addition, row shift, and byte replacement on the four sets of input ciphertexts according to the first-round key when the current round of decryption is the first-round decryption; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shift logic, and byte replacement logic. The round key addition logic is configured to perform a serial round key addition operation, the column obfuscation logic is configured to perform a serial column obfuscation transformation operation, the row shift logic is configured to perform a serial row shift transformation operation, and the byte replacement logic is configured to perform a serial byte replacement operation;

[0013] The serial decryption logic module is further configured to, when the current round of decryption is the intermediate round decryption subsequent to the first round, read the secret key corresponding to the intermediate round from the RAM and serially perform round key addition, column obfuscation, row shifting, and byte replacement on the four sets of pre-processed data according to the secret key corresponding to the intermediate round;

[0014] The serial decryption logic module is also used to perform round key addition on the four groups of pre-processed data according to the final round secret key read from the RAM through the round key addition logic when performing the final round decryption on the data.

[0015] On the other hand, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned FPGA-based high-speed AES decryption method when executing the computer program.

[0016] On the other hand, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned FPGA-based high-speed AES decryption method are implemented.

[0017] One of the above technical solutions has the following advantages and beneficial effects:

[0018] The above-mentioned FPGA-based high-speed AES decryption method, device, equipment and medium are based on the characteristic that there is no correlation between the front and rear wheels of the computing module during the decryption process. By making full use of the idle timing of the computing module, the traditional processing of one group of ciphertexts (i.e., a group of payload data to be decrypted collected on the satellite) is improved to serial processing of four groups of ciphertexts in the same time, that is, the decryption calculation of four groups of ciphertexts is completed. Compared with the traditional full-parallel solution, it can not only greatly improve the AES decryption speed, but also reduce the resource usage to only one-fourth of the traditional full-parallel solution, thereby meeting the application requirements of AES in the field of high-speed data real-time processing of satellites. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 Schematic diagram of a high-speed AES decryption method based on FPGA in one embodiment;

[0021] Figure 2 A schematic diagram of the AES128 key expansion process in one embodiment;

[0022] Figure 3 A schematic diagram of the AES128 decryption process in one embodiment;

[0023] Figure 4 A schematic diagram of a cyclic operation control process for AES decryption in one embodiment;

[0024] Figure 5 1. AES128 decryption process diagram of an embodiment using the high-speed AES decryption method;

[0025] Figure 6A schematic diagram of an idle period for round key addition in one embodiment;

[0026] Figure 7 A schematic diagram of utilizing the idle time of each logic module to improve operating efficiency in one embodiment;

[0027] Figure 8 This is an overall schematic diagram of the improved decryption process in one embodiment;

[0028] Figure 9 A schematic diagram of a three-way parallel decryption design in one embodiment;

[0029] Figure 10 A schematic diagram of the module framework of an FPGA device with high-speed AES decryption function in one embodiment. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0031] It should be noted that the reference to "embodiment" in this document means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0032] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0033] The decryption of the AES decryption algorithm consists of N rounds, and the number of rounds depends on the key length: for example, a 16-byte key (AES128) corresponds to 10 rounds, a 24-byte key (AES192) corresponds to 12 rounds, and a 32-byte key (AES256) corresponds to 14 rounds. The first N-1 rounds consist of four different transformations: byte substitution (SubBytes), row shift (ShiftRows), column confusion (MixColumns), and round key addition (AddRoundKey). Among them, byte substitution is to use an S-box to complete the byte-to-byte substitution of the group. Row shift is a simple byte shift within a row. Column confusion is to use the field GF(2 8 ) is a substitute for the arithmetic properties on the ciphertext. The round key addition is the bitwise exclusive OR XOR of the current group and a part of the extended key. In the AES encryption and decryption process, each step of the decryption algorithm corresponds to the inverse operation of the encryption algorithm, and the order of all encryption and decryption operations is exactly the opposite. The key for each round in encryption and decryption is obtained by the seed key through the key expansion algorithm. The 16-byte ciphertext, ciphertext and round key in the encryption and decryption algorithm are all represented by a 4×4 matrix. The specific detailed knowledge of the above AES can be understood by referring to the AES itself and its related explanations known in the art, and will not be elaborated one by one in this manual.

[0034] The currently used AES decryption algorithm requires multiple rounds of calculations, and each round strictly follows the four steps of round key addition, column obfuscation, row shifting, and byte replacement. Each round has time overhead, which makes it difficult to increase the speed of the decryption algorithm. To increase the decryption speed, the operating clock is often increased or multiple modules are used in parallel. Increasing the processing clock to increase the decryption speed has limited improvement capabilities, and too high a clock frequency can easily lead to FPGA timing degradation. Using multiple modules in parallel will lead to a rapid increase in resource overhead.

[0035] Existing patent CN201310047034 provides an ultra-high-speed FPGA-based AES processor and its implementation method. By compressing the number of operational steps, it reduces the number of clock cycles required for each decryption group. The present invention, based on the principle of decoherence between the front and rear cycles of the computational module during decryption (assuming the four clocks are considered four channels, there is no correlation between the four channels; however, the same channel does have correlation due to the iterative process), rationally utilizes processing time gaps to achieve a rate increase while maintaining the original algorithm architecture, resource overhead, and process. To further increase decryption speed, the present invention's solution can also add resources to one or more decryption branches to decrypt more ciphertext groups. In contrast, the existing patent CN201310047034 only increases the decryption capacity of one ciphertext group per additional decryption branch. The present invention's solution maximizes performance when decrypting consecutive ciphertext blocks. The solution of the present invention is applicable to data decryption in a scenario where the FPGA-based high-speed AES encryption method corresponding to the FPGA-based high-speed AES decryption method described below is adopted. The FPGA-based high-speed AES decryption method is the reverse process of the FPGA-based high-speed AES encryption method.

[0036] In one embodiment, Figure 1 As shown, a high-speed AES decryption method based on FPGA is provided, which may include the following steps S10 to S16:

[0037] S10, generates all the keys required for AES decryption through the AES key expansion module in the FPGA chip and caches them in RAM;

[0038] S12, if the current round of decryption is the first round of decryption, after reading the first round key from the RAM, the serial decryption logic module in the FPGA chip serially performs round key addition, row shift and byte replacement on the four sets of input ciphertexts according to the first round key; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shift logic and byte replacement logic, the round key addition logic is configured as a serial round key addition operation, the column obfuscation logic is configured as a serial column obfuscation transformation operation, the row shift logic is configured as a serial row shift transformation operation, and the byte replacement logic is configured as a serial byte replacement operation;

[0039] S14, if the current round of decryption is an intermediate round of decryption after the first round, after reading the secret key corresponding to the intermediate round from RAM, the serial decryption logic module serially performs round key addition, column obfuscation, row shifting, and byte replacement on the four sets of pre-processed data according to the secret key corresponding to the intermediate round;

[0040] S16, when performing final round decryption on the data, round key addition is performed on the four groups of pre-processed data according to the final round key read from the RAM through the round key addition logic.

[0041] It can be understood that, first, the AES key expansion module is used to generate the key required for AES decryption. The specific process is as follows Figure 2 As shown (wherein, in each of the figures containing ST_IDLE and IDLE, ST_IDLE and IDLE both represent idle states), it should be noted that, for the convenience of intuitive display and explanation, the following mainly uses AES128 as an example for explanation, and other AES decryption algorithms are similar. Since AES128 decryption requires ten rounds of processing, each round corresponds to a round of secret keys, so when the AES key is expanded, ten secret keys actually need to be generated, plus the original session key, a total of 11 secret keys. Since AES128 decryption is a serial calculation, a serial process is also used when generating the extended key. All generated secret keys are cached in RAM, and the required secret keys can be read directly from RAM when used for decryption, thereby saving time overhead.

[0042] Next is the AES decryption process. Taking AES128 as an example, the AES128 decryption module (i.e. the serial decryption logic module mentioned above) is used to decrypt the input ciphertext according to the secret key generated by the AES128 secret key expansion. The specific process can be as follows: Figure 3 As shown, to conserve resources, the AES128 decryption module is reused, including the final round key addition calculation. Eleven rounds of decryption are performed, all reusing the same round key addition logic. In the first round of decryption, only round key addition, row shift, and byte substitution operations are performed; in the final round of decryption, only round key addition is performed. Decryption rounds are performed sequentially, and the keys required for each round are read from RAM.

[0043] The AES decryption process described above shows that the main cost of AES decryption is the round decryption process. If the time cost of each module in the round decryption (i.e., the logic modules corresponding to round key addition, column obfuscation, row shifting, and byte replacement) is 1 clock, then the total cost of AES128-round decryption is 40 clocks. To increase the processing speed of decryption, a more direct approach is to share the AES key expansion process and then run multiple decryption processes in parallel according to actual needs. If the speed needs to be increased by 2 times, then one more AES decryption module can be run in parallel, but the resource cost of the round decryption will double. Alternatively, the decryption processing clock can be directly doubled, but the performance improvement of this approach is relatively limited, and it is difficult to shorten the decryption time by increasing the processing clock indefinitely.

[0044] Therefore, neither of the two direct processing methods mentioned above is an ideal way to increase the decryption processing speed. In order to increase the decryption processing speed, you can also appropriately increase the resources, but if the speed increase multiplier and the resource multiplier are the same, the resource consumption will still be too high, which is not the best solution.

[0045] The AES decryption process has four serial calculation steps: round key addition, column confusion, row shift and byte replacement. These four steps are cycled 11 times (taking AES128 as an example) to complete the decryption of a set of ciphertexts. The entire process control can be regarded as follows Figure 4 Assuming that round key addition, column shuffling, row shifting, and byte replacement each take up one clock, the total time overhead for the 11 rounds of key operations is 3 (first round) + 4*9 (middle rounds) + 1 (last round) = 40. A set of ciphertext data requires 40 clocks to decrypt. Assuming there are 60 sets of ciphertext data, the total time overhead is 40*60 = 2400 clocks.

[0046] This embodiment notes that during round decryption, the round key addition, column obfuscation, row shifting, and byte replacement processes are sequential serial processes. Furthermore, the first and second rounds of decryption in the intermediate rounds have no data correlation, except for the different secret keys. Therefore, this embodiment can fully utilize its timing based on this characteristic: that is, in the serial decryption logic module, the remaining three clocks of each logic are serially utilized. This significantly accelerates processing speed under the same resource conditions. If simple parallel processing is used (such as simply adding parallel decryption branches as in traditional technology), then although the processing speed is improved, the resource overhead is at least quadrupled. It should be noted that the improvement requirements of the present invention originate from satellite data transmission links. Since data is decrypted frame by frame, it can support serial input of ciphertext.

[0047] Assuming that the clock overhead of round key addition, column obfuscation, row shift, and byte replacement each takes up one clock, then in hardware implementation, ciphertext 1 is input on the first clock, ciphertext 2 on the second clock, ciphertext 3 on the third clock, and ciphertext 4 on the fourth clock. These four clocks are input serially. On the output side, the first ciphertext group is output as plaintext at the 41st clock, the second ciphertext group is output as plaintext at the 42nd clock, and the fourth ciphertext group is output as plaintext at the 44th clock. That is, 44 clocks are required to complete the decryption of four ciphertext groups, and the average decryption time for each ciphertext group is 11 clocks. In this way, the four steps of one round of decryption can now be executed simultaneously in four rounds of decryption. Therefore, assuming there are 60 ciphertext groups, the time overhead of the entire 11 rounds of key operations is 44*(60 / 4)=660 clocks.

[0048] A complete new process design for AES128 decryption can be achieved by Figure 5 The process architecture shown can complete the decryption of 4 groups of ciphertexts in 44 clocks, and the decryption time experienced by each group of ciphertexts is 41 clocks. Among them, in order to decrypt 4 groups of ciphertexts at the same time, the 4 groups of ciphertexts need to be input serially in time, resulting in 44 clocks required to complete the process from input of all ciphertexts to decryption output for 4 groups of ciphertexts. The round key addition logic, column obfuscation logic, row shift logic and byte replacement logic used in the FPGA chip to implement round key addition, column obfuscation, row shift and byte replacement respectively are all modularly designed. Taking the conventional decryption design as an example, Figure 6 The decryption of one ciphertext takes 40 clocks, with the first round taking 3 clocks and the next ten rounds taking 9*4+1=37, for a total of 40 clocks. However, the round key addition logic enters an idle state after completing the round key addition operation in the middle round, and needs to wait 3 clocks before it can be used again. Therefore, the round key addition logic has an idle period of 3 clocks.

[0049] Based on the non-correlation of calculations between rounds (i.e., as long as the exact input is provided, the output is fixed), this embodiment fully utilizes the idle time of each logic module (i.e., by serially using the remaining three clocks of each module through time multiplexing, one logic module completes four calculations within four serial input clocks) to improve the operation efficiency. Figure 7 The specific improvement measures are as follows:

[0050] Depend on Figure 7 It can be seen that the entire operation process fully utilizes the timing characteristics of each logic module. When using this improved scheme, one set of ciphertext can be decrypted within every 41 clocks. At the same time, the decryption of four sets of ciphertext requires serial input to the corresponding module with one clock interval between each set, resulting in a total of 44 clocks required to complete the decryption of four sets of ciphertext, an average of 11 clocks per set. The characteristic of this scheme is good timing performance. Under almost the same resource consumption conditions, the decryption speed is increased by nearly 4 times.

[0051] The above-mentioned FPGA-based high-speed AES decryption method is based on the characteristic that there is no correlation between the front and rear wheels of the computing module during the decryption process. By making full use of the idle timing of the computing module, it improves the traditional processing of one group of ciphertexts (i.e., the payload data to be decrypted collected on the satellite) to serial processing of four groups of ciphertexts in the same time, that is, completing the decryption calculation of four groups of ciphertexts. Compared with the traditional fully parallel scheme, it can not only greatly improve the AES decryption speed, but also reduce the resource usage to only one-quarter of the traditional fully parallel scheme, thus meeting the application requirements of AES in the field of high-speed data real-time processing of satellites.

[0052] In one embodiment, the serial decryption logic modules configured in the FPGA chip include N parallel ones; N is a positive integer not less than 2.

[0053] It is understandable that if the decryption speed needs to be further improved, the decryption speed can be improved by adopting the method of parallel decryption branches. For example, one more AES decryption branch can be used in parallel to achieve this goal. For example, three AES decryption modules can be used in parallel. Then, the three AES decryption modules can complete the decryption of 12 groups of ciphertexts in the same amount of time.

[0054] Specifically, if the decryption speed is still insufficient, further consideration could be given to using parallel processing. For example, using three parallel AES decryption modules, with 60 ciphertexts and considering that every four ciphertexts are serially fed into one AES decryption module, the time overhead for decrypting 60 ciphertexts is 44*(60 / 4 / 3)=220 clocks. From this, it can be deduced that for 60 ciphertexts, the average decryption time per ciphertext is 3.67 clocks. When using the above-mentioned parallel multi-channel AES decryption module design, compared to the traditional single-channel decryption solution with multi-channel parallel decryption, this embodiment achieves the same decryption speed target with only one-quarter of the resource usage of the traditional solution, achieving a significant improvement, such as decryption of high-speed satellite data transmission.

[0055] If a higher rate is required, multi-path expansion can be supported. That is, a single-path AES decryption can support the decryption of 4 groups of ciphertexts. The number of decrypted ciphertext blocks increased by 4*N, where N is the number of parallel decryption paths. The use of multi-path expansion forms a serial-parallel mesh decryption network, which can quickly expand decryption while moderately increasing resources. The decryption speed is increased by 4N. The overall AES decryption process can be summarized as follows: Figure 8 As shown, the design of the corresponding three-way parallel AES decryption module can be as follows Figure 9 As shown in Figure 2, the overall decryption speed can be as follows: (1) Single-channel AES decryption module, decrypting one set of ciphertext every 41 clocks, and each round of operation can serially input four sets of ciphertext for processing. (2) Three-channel parallel decryption, decrypting three sets of ciphertext every 41 clocks.

[0056] In one embodiment, AES decryption includes AES128 decryption, AES192 decryption, and AES256 decryption.

[0057] It's understandable that the above examples illustrate AES128 decryption. As the theoretical analysis above shows, AES192 and AES256 decryption use 12 and 14 rounds, respectively. Therefore, the same logic applies to AES192 and AES256 decryption. Using this solution, AES192 decryption takes 4*11+1+4=49 seconds, while AES256 decryption takes 4*13+1+4=57 seconds.

[0058] It should be understood that although Figure 1 The steps in the diagram are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0059] In one embodiment, Figure 10 As shown, an FPGA device with high-speed AES decryption functionality is provided, which may include an AES key expansion module 11 and a serial decryption logic module 13. The AES key expansion module 11 is configured to generate all keys required for AES decryption and cache them in RAM. The serial decryption logic module 13 is configured to, when the current round of decryption is the first round, read the first round key from RAM and then serially perform round key addition, row shift, and byte replacement on four sets of input ciphertexts based on the first round key. The serial decryption logic module 13 includes round key addition logic, column obfuscation logic, row shift logic, and byte replacement logic. The round key addition logic is configured to perform serial round key addition operations, the column obfuscation logic is configured to perform serial column obfuscation transformation operations, the row shift logic is configured to perform serial row shift transformation operations, and the byte replacement logic is configured to perform serial byte replacement operations. The serial decryption logic module 13 is also configured to, when the current round of decryption is an intermediate round after the first round, read the key corresponding to the intermediate round from RAM and then serially perform round key addition, column obfuscation, row shift, and byte replacement on the four sets of pre-processed data based on the key corresponding to the intermediate round. The serial decryption logic module 13 is further configured to perform round key addition on the four groups of pre-processed data according to the final round key read from the RAM through the round key addition logic when performing final round decryption on the data.

[0060] The FPGA device with high-speed AES decryption function of this embodiment is based on the characteristic that there is no correlation between the front and rear wheels of the computing module during the decryption process. By fully utilizing the idle timing of the computing module, the device is improved from the traditional processing of one group of ciphertexts (i.e., a group of payload data collected on the satellite to be decrypted) to serial processing of four groups of ciphertexts in the same time, that is, completing the decryption calculation of the four groups of ciphertexts. Compared with the traditional fully parallel solution, it can not only greatly improve the AES decryption speed, but also reduce the resource usage to only one-fourth of the traditional fully parallel solution, thereby meeting the application requirements of AES in the field of high-speed real-time data processing of satellites.

[0061] In one embodiment, the serial decryption logic modules include N parallel modules; N is a positive integer not less than 2.

[0062] In one embodiment, AES decryption includes AES128 decryption, AES192 decryption, and AES256 decryption.

[0063] It is understood that the explanation of the various features of the above-mentioned FPGA device with high-speed AES decryption function can be understood in the same way as the corresponding explanations in the various embodiments of the above-mentioned FPGA-based high-speed AES decryption method. Each module in the above-mentioned FPGA device with high-speed AES decryption function can be implemented in whole or in part by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of a device with data processing function in hardware form, or can be stored in the memory of the aforementioned device in software form, so that the processor can call and execute the operations corresponding to the above modules. The aforementioned device can be, but is not limited to, various types of FPGA chips or encryption and decryption devices existing in the art.

[0064] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following processing steps are implemented: generating all keys required for AES decryption through an AES key expansion module in an FPGA chip and caching them in RAM; if the current round of decryption is the first round of decryption, after reading the first round key from RAM, serially performing round key addition, row shifting, and byte replacement on four sets of input ciphertexts according to the first round key through a serial decryption logic module in the FPGA chip; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shifting logic, and byte replacement logic. The round key addition logic is configured as a serial round key addition operation, the column obfuscation logic is configured as a serial column obfuscation transformation operation, the row shift logic is configured as a serial row shift transformation operation, and the byte replacement logic is configured as a serial byte replacement operation; if the current round decryption is an intermediate round decryption after the first round, then after reading the secret key corresponding to the intermediate round from the RAM, the serial decryption logic module performs round key addition, column obfuscation, row shift and byte replacement serially on the four groups of pre-processed data according to the secret key corresponding to the intermediate round; when the final round decryption is performed on the data, the round key addition logic performs round key addition on the four groups of pre-processed data according to the final round key read from the RAM.

[0065] In one embodiment, when executing the computer program, the processor may further implement the additional steps or sub-steps in each embodiment of the above-mentioned FPGA-based high-speed AES decryption method.

[0066] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following processing steps are implemented: all keys required for AES decryption are generated by an AES key expansion module in an FPGA chip and cached in RAM; if the current round of decryption is the first round of decryption, after reading the first round key from RAM, the serial decryption logic module in the FPGA chip performs round key addition, row shift and byte replacement on the four sets of input ciphertexts according to the first round key; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shift logic and byte replacement logic, and the round key addition is performed. The logic is configured as a serial round key addition operation, the column obfuscation logic is configured as a serial column obfuscation transformation operation, the row shift logic is configured as a serial row shift transformation operation, and the byte replacement logic is configured as a serial byte replacement operation; if the current round of decryption is an intermediate round decryption after the first round, then after reading the secret key corresponding to the intermediate round from RAM, the serial decryption logic module performs round key addition, column obfuscation, row shift and byte replacement serially on the four groups of pre-processed data according to the secret key corresponding to the intermediate round; when the final round of decryption is performed on the data, the round key addition logic performs round key addition on the four groups of pre-processed data according to the final round key read from RAM.

[0067] In one embodiment, when the computer program is executed by a processor, it can also implement the additional steps or sub-steps in each embodiment of the above-mentioned FPGA-based high-speed AES decryption method.

[0068] Those skilled in the art will appreciate that all or part of the processes in the above-described embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-described methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, abbreviated as RDRAM) and interface dynamic random access memory (DRDRAM).

[0069] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of the present invention. Therefore, the scope of the present invention shall be determined by the appended claims.

Claims

1. A high-speed AES decryption method based on FPGA, characterized in that: Including steps: Generate all the keys required for AES decryption through the AES key expansion module in the FPGA chip and cache them in RAM; If the current round of decryption is the first round of decryption, after reading the first round key from the RAM, the serial decryption logic module in the FPGA chip serially performs round key addition, row shift and byte replacement on the four sets of input ciphertexts according to the first round key; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shift logic and byte replacement logic, the round key addition logic is configured for serial round key addition operation, the column obfuscation logic is configured for serial column obfuscation transformation operation, the row shift logic is configured for serial row shift transformation operation, and the byte replacement logic is configured for serial byte replacement operation; If the current round of decryption is an intermediate round of decryption after the first round, after reading the secret key corresponding to the intermediate round from the RAM, the serial decryption logic module serially performs round key addition, column obfuscation, row shifting, and byte replacement on the four groups of pre-processed data according to the secret key corresponding to the intermediate round; When final round decryption is performed on the data, round key addition is performed on the four groups of pre-processed data using the final round key read from the RAM through the round key addition logic.

2. The high-speed AES decryption method based on FPGA according to claim 1, characterized in that: The serial decryption logic modules configured in the FPGA chip include N parallel ones; N is a positive integer not less than 2.

3. The high-speed AES decryption method based on FPGA according to claim 1 or 2, characterized in that: The AES decryption includes AES128 decryption, AES192 decryption and AES256 decryption.

4. An FPGA device with high-speed AES decryption function, characterized in that: include: AES key expansion module, used to generate all the keys required for AES decryption and cache them in RAM; a serial decryption logic module, configured to, when the current round of decryption is the first round of decryption, read the first round key from the RAM and then serially perform round key addition, row shift, and byte replacement on the four sets of input ciphertexts according to the first round key; the serial decryption logic module includes round key addition logic, column obfuscation logic, row shift logic, and byte replacement logic, the round key addition logic is configured to perform a serial round key addition operation, the column obfuscation logic is configured to perform a serial column obfuscation transformation operation, the row shift logic is configured to perform a serial row shift transformation operation, and the byte replacement logic is configured to perform a serial byte replacement operation; The serial decryption logic module is further configured to, when the current round of decryption is an intermediate round of decryption subsequent to the first round, read the secret key corresponding to the intermediate round from the RAM and serially perform round key addition, column obfuscation, row shifting, and byte replacement on the four groups of pre-processed data according to the secret key corresponding to the intermediate round; The serial decryption logic module is further configured to perform round key addition on four groups of pre-processed data according to the final round key read from the RAM through the round key addition logic when performing final round decryption on the data.

5. The FPGA device with high-speed AES decryption function according to claim 4, characterized in that: The serial decryption logic modules include N parallel modules; N is a positive integer not less than 2.

6. The FPGA device with high-speed AES decryption function according to claim 4 or 5, characterized in that: The AES decryption includes AES128 decryption, AES192 decryption and AES256 decryption.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the FPGA-based high-speed AES decryption method according to any one of claims 1 to 3 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the FPGA-based high-speed AES decryption method according to any one of claims 1 to 3 are implemented.

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