A physical design method suitable for high-performance atomic-level computing chips

Abstract

The application relates to the field of integrated circuit design, and discloses a physical design method suitable for a high-performance atomic-level computing chip. The application firstly analyzes RTL code, carries out module division, and generates required memories; then carries out logic synthesis, sets up different path groups for the memory-to-register path, and gives different weights; in the layout and wiring stage, according to the algorithm function and data flow direction of each module, top layout planning, module layout planning, power supply and ground planning, layout, clock tree synthesis, wiring and design rule checking are realized; then physical verification, timing analysis, power consumption and voltage drop analysis are carried out, and through sufficient iteration optimization, it is ensured that the final design meets the timing, power consumption and voltage drop requirements. The application focuses on the physical design of the high-performance atomic-level computing chip, effectively deals with the challenges of high computing intensity, high design complexity, large chip scale and high power consumption, and improves the reliability of the chip on the basis of ensuring high performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a physical design method suitable for high-performance atomic-level computing chips. Background Technology

[0002] Atomic-level computing is widely used in numerous fields such as physics, chemistry, biology, materials science, energy, and geology. Its core requirements include molecular dynamics simulations and first-principles calculations based on density functional theory. Currently, atomic-level computing primarily relies on central processing units (CPUs) and graphics processing units (GPUs). However, mainstream CPUs and GPUs generally employ the von Neumann (vN) architecture. In this architecture, the storage and computation units are separated, resulting in a significant portion of computation time and power consumption being spent on frequent data transfers between these units. This creates substantial "memory walls" and "power walls," severely hindering improvements in computational efficiency.

[0003] To overcome this bottleneck, designing Application Specific Integrated Circuit (ASIC) chips using a non-von Neumann (NvN) architecture has become an effective solution. However, due to the extremely high requirements of atomic-level computing algorithms for data capacity, computational accuracy, and operating speed, ASIC chip design faces challenges such as computational intensity, high design complexity, large chip size, and high power consumption. In the physical design phase, numerous difficulties arise in timing convergence, physical verification, and power management. Furthermore, atomic-level computing typically exhibits pipelined characteristics, meaning that even a small error at any stage of the computation process can lead to a decrease in the accuracy of the final result. Therefore, higher demands are placed on the reliability and robustness of the physical design. Summary of the Invention

[0004] To address the aforementioned technical challenges in the physical design of atomic-level computing chips, this invention proposes a physical design method suitable for high-performance atomic-level computing chips. This invention provides a stable and efficient physical design process that improves chip reliability while ensuring high performance. The technical solution to achieve the objectives of this invention is as follows:

[0005] A physical design method suitable for high-performance atomic-level computing chips, comprising the following steps:

[0006] S1, RTL code analysis, determining the partitioning scheme of each sub-module in the hierarchical design, statistically analyzing the ports of each module and their data interaction relationships, organizing them into a module interaction relationship diagram, and determining the type, bit width and depth of the memory required for each sub-module according to storage requirements; at the same time, classifying the memory according to the type of stored data and the memory read and write cycle.

[0007] S2, Logic Synthesis: Considering the large number of high-width memories in atomic-level computing chips, the timing optimization of the memory-to-register path can easily become a bottleneck. Therefore, based on the memory read / write cycle size obtained in step S1, different path groups are established for each memory-to-register path and assigned different weights. Logic synthesis is then performed so that the tool can optimize each path group to different degrees.

[0008] S3, Placement and Routing: Using automatic placement and routing tools such as INNOWUS / ICC2, combined with the module port and data interaction information obtained in step S1 and the netlist obtained in step S2, the top-level placement planning is completed to achieve precise alignment of the ports of each sub-module. When planning the placement within each sub-module, a reasonable placement plan is formulated based on the algorithm function and data flow of each module. Memory with the same or related computational data sources is placed in close proximity, and memory that interacts with module ports is placed near the ports. Simultaneously, a reasonable power and ground network is planned, setting corresponding power line widths and spacing rules according to different modules, regions, and levels. During the placement phase, placement blockage is set according to the characteristics of different modules, especially for computationally intensive modules, where local density needs to be controlled to avoid congestion. If significant congestion occurs, the placement is re-executed. In the clock tree synthesis phase, a clock network is constructed using cells with appropriate voltage thresholds. While ensuring the clock offset meets the target, high-voltage threshold cells are prioritized to reduce clock network power consumption, and different insertion delays are set based on the memory read / write cycle size obtained in step S1. If the generated clock tree does not meet the requirements, it is regenerated. During the routing phase, enable OCV (on-chip variation) settings, perform a rough timing analysis, and check the timing report. If significant violations are found, timing repairs are performed. Simultaneously, a design rule check (DRC) is performed to check for errors such as short circuits and open circuits. If errors are found, they are repaired and rerouting is performed. In the first iteration, each step of step S3 must be executed completely. Subsequent iterations will proceed to the corresponding sub-steps of step S3 based on the types of errors or violations found in steps S4 to S6.

[0009] S4, Physical Verification: Using the Calibre tool, perform DRC, LVS, ANT, and ERC checks on each module and the top layer of the atomic-level computing chip. If errors are found, the report is imported into the automatic placement and routing tool, and processed according to the error type: if the error is caused by routing, return to the routing stage in step S3 for repair; if the error is caused by the device, return to the placement stage in step S3 for avoidance.

[0010] S5, Timing Analysis: Using timing analysis tools such as Prime Time, perform timing checks on setup and hold times across multiple process corners to ensure that timing results across multiple process corners simultaneously meet requirements. If timing violations exceed the repairable range, classify the violation paths and return to step S3 to set specific path groups, assigning different weights for optimization. If timing violations are within the repairable range, use tools such as Prime Time and ICExplorer-XTop for timing optimization, import the optimization results into the automatic placement and routing tool, and iterate using ECO techniques.

[0011] S6. Power consumption and voltage drop analysis: Use tools such as Redhawk / Voltus / PTPX to analyze power consumption, understand its composition, identify entry points for reducing power consumption and perform targeted optimizations. Simultaneously, check if the voltage drop is within a reasonable range, identify areas with severe voltage drop and perform targeted optimizations. If the corresponding indicators are not met, return to the corresponding sub-step of step S3 for iteration.

[0012] Compared with existing technologies, the main advantages of this invention are: it fully leverages the capabilities of Electronic Design Automation (EDA) tools such as automatic placement and routing, effectively avoiding problems such as high-width memory path bottlenecks and computationally intensive pipeline structures that atomic-level computing chips may encounter in the early stages of physical design, and ensuring the high performance and high stability of atomic-level computing chips through a complete verification system including physical verification, multi-process corner timing verification, and power consumption and power integrity analysis. Attached Figure Description

[0013] Figure 1 This is an operation flowchart of the present invention;

[0014] Figure 2 This is a schematic diagram illustrating the interaction between the chip modules in an embodiment of the present invention;

[0015] Figure 3 This is a flowchart of step S3 in an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of chip layout planning in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] This invention relates to a physical design method suitable for high-performance atomic-level computing chips, such as... Figure 1 As shown, this method first analyzes the RTL code to clarify the hierarchical division and memory selection; then it proceeds to logic synthesis to obtain a timing-converged netlist; next, it completes placement and routing; finally, it performs physical verification, timing analysis, and power consumption and voltage drop analysis on the completed placement and routing design. If the performance indicators are found to be unsatisfactory, it returns to the placement and routing stage for iteration. This embodiment uses an atomic-level computing chip for molecular dynamics simulation as an example for specific illustration:

[0019] 1. RTL code analysis clarified the hierarchical division of the molecular dynamics chip, classifying the functional modules mainly into computational and communication modules, with the computational module designed for a frequency of 1 GHz. Port statistics for each module were compiled, and module interaction diagrams were created (e.g., ...). Figure 2 (As shown). Based on the SMIC 28nm HKCP process, the required SRAM memory is generated using the ARM Memory Compiler, determining the bit width and depth of the SRAM required by each submodule to meet storage requirements. The memory is categorized: for example, the SRAM of module ③ is divided into three categories based on the data type: interpolation parameters for forward calculation, interpolation parameters for backward calculation, and intermediate results. Simultaneously, the memory is divided into three intervals according to read / write cycles: 400 ps~500 ps, ​​500 ps~600 ps, ​​and 600 ps~700 ps.

[0020] 2. Logic Synthesis: Based on the memory read / write cycle intervals defined in Step 1, calculate the ratio of the read / write cycle to the target clock cycle. Using the `group_path` command in the Design Compiler, create path groups for memory-to-register paths in different read / write cycle intervals (representing different levels of criticality) and assign them differentiated weights; higher criticality results in higher weights. Perform logic synthesis.

[0021] 3. Layout and wiring, such as Figure 3 As shown, using the automatic placement and routing tool INNOVUS, based on the module port and data interaction information obtained in step 1 and combined with the netlist obtained in step 2, a top-level floorplan is designed to precisely align the sub-module ports according to the data flow direction (see schematic diagram). Figure 4(As shown); Combining the storage data type classification in step 1 (such as the three types of SRAM in module ③) with the algorithm functions and data flow of each module, memory with the same or related computational data sources is placed in close proximity, and memory that interacts with the module ports is placed closer to the ports; power ground network planning is carried out, and rules are set differently. In computationally intensive modules (such as matrix multiplication units), high-layer metal wiring power networks are used, standard cell wiring resources are reserved, and the top-layer metal density is increased to suppress voltage drop; during layout, different placement blockages are set according to the different characteristics of each module, such as setting dense small-area placements for high pin density modules (such as serial-to-parallel conversion modules). For the Blockage array, for compute-intensive modules, a local density limit of 70% is set, and Instance_padding is set to 1.5 to control local density. If congestion occurs, the above settings are adjusted and the layout is rearranged until the congestion is eliminated. During clock tree synthesis, cells with appropriate voltage thresholds are used to construct the clock network. While ensuring that the clock offset meets the requirements, cells with higher voltage thresholds are used first to reduce the power consumption of the clock network. Different insertion delays are set according to the memory read / write cycle range: for example, the insertion delays for the memory ranges of 600 ps~700 ps, ​​500 ps~600 ps, ​​and 400 ps~500 ps are set to 100 ps, ​​80 ps, ​​and 60 ps, ​​respectively. During the routing stage, OCV settings are enabled to perform a rough timing analysis and check the Setup / Hold timing. If violations exceed the threshold (e.g., Setup violations greater than 300 ps, ​​or Hold violations greater than 200 ps), timing repair is performed, and DRC errors such as short circuits and open circuits are checked and repaired.

[0022] 4. Physical verification: Use Calibre to perform DRC, LVS, ANT, and ERC checks on the module and top layer. If errors are found, import the report into INNVOUS for analysis: if it is a routing error such as metal spacing, return to the routing stage in step S3 for repair; if it is a rule error caused by components, return to the placement stage in step 3 for avoidance.

[0023] 5. Timing Analysis: Use the Prime Time tool for static timing analysis under multiple different process corners, such as ffg_v0p99_125c and ssg_v0p81_-40c, to perform timing checks on Setup and Hold. If Setup / Hold violations exceed 100 ps: Analyze the violation path characteristics, return to step 3, set high-weight path groups for these paths, and re-optimize. If violations are less than 100 ps: Use the IC Explorer-XTop tool for timing optimization. Repair Setup by changing the threshold voltage and device size, and repair Hold by inserting delay cells. Then return to the routing stage in step 3, import the corresponding scripts into INNAVUS, and reroute using the ecoRoute command.

[0024] 6. Power consumption and voltage drop analysis: Use Voltus to perform power consumption analysis to understand the composition of power consumption. For example, if it is found that due to the high flip-flop rate of the molecular dynamics chip, the power consumption of the clock network accounts for as much as 70% in a large number of modules, then it is necessary to return to the clock tree synthesis stage in step 3 to improve the structure of the clock network, reduce the number of clock stages, and reduce the number of clock units; check whether the voltage drop exceeds the threshold (set to 5% here). If it exceeds the threshold, return to the power ground planning stage in step 3, re-plan the power ground network, and insert decap units in the areas with severe voltage drop.

[0025] Repeatedly execute steps 3 to 6 until all physical verifications are passed, all target process corner timings converge, and power consumption and voltage drop meet the standards, at which point the physical design is complete.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Referring to the description of these embodiments, those skilled in the art should be able to understand and make relevant modifications or substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A physical design method suitable for high performance atomic scale computing chips, characterized by, Comprise the following steps: S1, determine the partitioning scheme of each sub-module in the hierarchical design of the atomic computing chip, count the module ports and their data interaction relationship, organize the module interaction relationship diagram, and determine the type, bit width and depth of the memory required by each sub-module according to the storage requirement; at the same time, according to the type of storage data and the read-write period of the memory, the memory is classified; S2, logic synthesis, according to the memory read-write period size obtained in step S1, different path groups are set up for each memory to register and different weights are given, and then the Design Compiler synthesis tool is used for logic synthesis, so that the tool optimizes each path group to different degrees; S3, layout and wiring, using the INNOVUS automatic layout and wiring tool, combining the module port and data interaction obtained in step S1 and the netlist obtained in step S2, completing the top-level layout planning, module layout planning, power supply and ground planning, layout, clock tree synthesis, wiring, design rule check (DRC); S4, physical verification, using Calibre tool, DRC, LVS, ANT, ERC checking of each module and top layer of atomic computing chip; S5, timing analysis, using Prime time timing analysis tool, establishing time and holding time timing check under multiple different process angles to ensure that the timing results of multiple process angles meet the requirements at the same time; S6, power consumption and voltage drop analysis, using Redhawk tool to analyze the power consumption composition, to determine the cutting point of reducing power consumption and to optimize it, and to check whether the voltage drop is within a reasonable range, and to optimize the area with serious voltage drop.

2. The physical design method for high performance atomic scale computing chip as claimed in claim 1 wherein: In the step S3, when performing top-level layout planning, according to the module port and data interaction information obtained in step S1, the precise alignment of each sub-module port is realized; When performing module layout planning, according to the algorithm function and data flow direction of each module, the memories with the same or related computing data sources are placed in the same position, and the memories interacting with the module ports are placed near the ports.

3. The physical design method for high performance atomic scale computing chip of claim 1, wherein: In the step S3, when performing power supply and ground planning, according to different modules, regions and levels, the corresponding power line width and spacing rules are set; when performing layout, according to different module characteristics, placement blockage is set; for computing-intensive modules, local density needs to be controlled to avoid congestion; if there is a lot of congestion, the layout needs to be re-performed.

4. The physical design method for high performance atomic scale computing chip of claim 1, wherein: In the step S3, when performing clock tree synthesis, the clock network is constructed by using units with appropriate voltage threshold, high voltage threshold units are selected to reduce the power consumption of the clock network under the premise of ensuring that the clock skew meets the target, and different sizes of inserted delay are set according to the memory read-write period size obtained in step S1; if the generated clock tree does not meet the requirements, the clock tree needs to be re-generated.

5. The physical design method for high performance atomic scale computing chip of claim 1, wherein: In the step S3, when performing wiring, the OCV (on chip variation) related settings are enabled, the rough timing analysis is performed, and the timing report is checked; If the timing violation is found to be large, timing repair is performed; when DRC check is performed, whether there is short circuit, open circuit and other errors is checked, if the error is found, repair is performed and rewiring is performed.

6. The physical design method for high performance atomic scale computing chips as recited in claim 1, wherein: When the first iteration of layout and wiring is performed, the whole process of step S3 is completely performed, and in subsequent iterations, according to the error or violation type found in steps S4 to S6, the corresponding stage of step S3 is entered for iteration.

7. The method for physical design of high performance atomic scale computing chips as recited in claim 1, wherein: In step S4, when DRC, LVS, ANT, ERC check is performed, if the error is found, the report is imported into the INNOVUS automatic layout and wiring tool, and the error type is classified and processed; if it is a wiring error, it is returned to the wiring stage in step S3 for repair; if it is a device error, it is returned to the layout stage in step S3 for avoidance.

8. The method for physical design of high performance atomic scale computing chips as recited in claim 1, wherein: In step S5, if the timing violation exceeds the repairable range, the violation path is classified, and step S3 is returned to set a specific path group and give different weights for optimization; if the timing violation is within the repairable range, Prime time, ICExplorer-XTop tools are used for timing optimization, the optimization results are imported into the automatic layout and wiring tool, and ECO means is used for iteration.

9. The method for physical design of high performance atomic scale computing chips as recited in claim 1, wherein: In step S6, the power consumption composition is analyzed, which is divided into combinational logic, timing logic, clock network and memory according to the power consumption source, and is divided into leakage power consumption, short circuit power consumption and flip power consumption according to the power consumption type, two kinds of power consumption classification are analyzed, and the modules with large power consumption ratio are optimized; the methods of using encrypted power supply ground network, reducing local standard cell density and adding decap unit are used to optimize the voltage drop serious area.

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