Clock circuit with jitter output, clock management circuit and chip

Abstract

The invention discloses a clock circuit with jitter output, a clock management circuit and a chip, and relates to the technical field of integrated circuits. The clock circuit with jitter output comprises a delay circuit, a shift register and a digital logic operation module, wherein the delay circuit comprises N cascaded delay units, the input end of the first-stage delay unit is connected with an original clock signal, and the original clock signal is delayed stage by stage through the N delay units in sequence; the shift register is connected with the output end of the last stage of delay unit and is used for carrying out frequency division on a delay signal output by the last stage of delay unit; and the digital logic operation module is respectively connected with the output end of each stage of delay unit in the delay circuit and the output end of the shift register, and is used for combining output clock signals with different frequencies. By adopting the clock circuit, EMI can be effectively reduced, meanwhile, the circuit design is simplified, and the application range of the clock circuit is expanded.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a clock circuit with jitter output, a clock management circuit and a chip. Background Art

[0002] With the significant increase in demand for automotive microcontroller units (MCUs) and other consumer electronic integrated circuits (ICs), electromagnetic interference (EMI) is becoming an increasingly serious problem. To prevent EMI from affecting or disrupting the normal operation of other electronic devices, various departments and organizations have proposed or developed regulations or standards related to EMI from electronic products. Products that meet these regulations or standards are collectively referred to as electromagnetic compatibility (EMC). For IC chips, reducing the rate of change of current (di / dt) and voltage (dv / dt) is particularly important. Fixed-frequency outputs in circuits with oscillators are particularly prone to EMI, especially in phase-locked loop (PLL) circuits.

[0003] In related technologies, PLL circuits usually use a spread spectrum clock (SSCG) method as a technical means to reduce EMI, such as Figure 1 As shown, the spread spectrum control circuit includes a FRAC_TRIWAVE generator, an SDM modulator and an adder, wherein the FRAC_TRIWAVE generator generates a triangular wave signal with a modulation period of 32KHz (such as Figure 2 The SSCG method uses a quantized signal (as shown in Figure 1) and is fed into the SDM modulator. The SDM modulator quantizes the input signal, generating a corresponding bit stream signal that is superimposed with the division ratio N. This bit stream serves as the feedback divider signal for controlling the PLL, completing the PLL's spread spectrum function. However, implementing the SSCG method requires multiple additional modules and a complex structure, increasing the difficulty of circuit design, implementation, and debugging while also requiring more chip area. Furthermore, the SSCG method's modulation frequency range and jitter control are limited by system design, making it difficult to meet the flexible requirements of specific scenarios. Summary of the Invention

[0004] Based on this, it is necessary to provide a clock circuit with jitter output, a clock management circuit and a chip with a simple structure to address the above technical problems.

[0005] A clock circuit with jitter output, comprising a delay circuit, a shift register, and a digital logic operation module; wherein the delay circuit comprises N cascaded delay units, wherein the input end of the first-stage delay unit is connected to the original clock signal, and the original clock signal is sequentially delayed by the N delay units;

[0006] The shift register is connected to the output end of the last-stage delay unit and is used to divide the frequency of the delayed signal output by the last-stage delay unit;

[0007] The digital logic operation module is respectively connected to the output end of each stage of delay unit in the delay circuit and the output end of the shift register, and is used for combining output clock signals with different frequencies through logic operation.

[0008] In the above solution, the shift register includes N cascaded D flip-flops, wherein:

[0009] The clock input terminal of the first-stage D flip-flop is connected to the output terminal of the last-stage delay unit;

[0010] In two adjacent D flip-flops, the data input terminal and the inverting output terminal of the upper-level flip-flop are connected and connected to the clock input terminal of the lower-level D flip-flop.

[0011] In the above scheme, the falling edge of the signal at the clock input terminal is the trigger source of each stage of the D flip-flop.

[0012] In the above scheme, the frequency of the output signal of the D flip-flop of the Nth stage is the frequency of the delayed signal input to the shift register.

[0013] In the above solution, the digital logic operation module is used to perform logic operations on the signal output from the inverting output terminal of the D flip-flop in the shift register, the delayed signal output from the delay circuit and the original clock signal.

[0014] In the above solution, the original clock signal is at least a phase-locked loop clock.

[0015] In the above solution, the frequency of the output clock signal changes periodically.

[0016] In the above solution, the delay unit is based on a combination of resistors and capacitors.

[0017] A clock management circuit comprises a clock generation circuit for generating an original clock signal and a clock circuit with jitter output according to any one of the above solutions.

[0018] A chip comprises the clock circuit with jitter output according to any one of the above solutions.

[0019] The above-mentioned clock circuit, clock management circuit and chip with jitter output delay the original clock signal step by step through N cascaded delay units included in the delay circuit, and then perform spectrum spread processing on the delayed signal through the digital logic circuit, so that the signal frequency changes and a jittered output clock signal is generated, thereby effectively reducing EMI. At the same time, it simplifies the circuit design, significantly reduces the occupied area, and is easier to integrate into IC design. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of a spread spectrum control circuit used in a PLL circuit in the related art;

[0021] Figure 2 Schematic diagram of a triangular wave signal generated by a FRAC_TRIWAVE generator in the related art;

[0022] Figure 3 is a basic block diagram of a clock circuit with jitter output in one embodiment;

[0023] Figure 4 1 is a schematic structural diagram of a delay circuit in one embodiment;

[0024] Figure 5 Schematic diagram of the structure of a shift register in one embodiment;

[0025] Figure 6 Schematic diagram of the structure of a digital logic operation module in one embodiment.

[0026] Reference numerals: delay circuit 10 , delay unit 101 , digital logic circuit 20 , shift register 201 , digital logic operation module 202 , D flip-flop 301 . DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0028] The following describes in detail the implementation details of the technical solutions of the embodiments of the present application.

[0029] In one embodiment, Figure 3 As shown, Figure 3 The basic block diagram of the clock circuit with jitter output is shown, wherein the clock circuit with jitter output includes a delay circuit 10, a shift register 201 and a digital logic operation module 202. The working principle of the clock circuit is described in detail below.

[0030] The delay circuit 10 includes N delay units 101, which form a cascade structure, that is, the N delay units 101 are connected in series, and the output of each delay unit 101 is connected to the input of the next delay unit 101. Figure 3 The output of the first-stage delay unit 101 is connected to the input of the second-stage delay unit 101, the output of the second-stage delay unit 101 is connected to the input of the third-stage delay unit 101, and so on. The input of the first-stage delay unit 101 is connected to the original clock signal Fvco, that is, the stable clock signal output by the clock generation circuit.

[0031] When the original clock signal Fvco is input into the first-stage delay unit 101, a fixed or adjustable delay is introduced into the signal. This delay is determined by the design of each delay unit 101. The delayed signal output by the first-stage delay unit 101 maintains the same waveform as the original clock signal Fvco, but its rising and falling edges are delayed by a fixed time ΔT relative to the original clock signal Fvco. Assuming the original clock signal Fvco has a period of T, after passing through the first-stage delay unit 101, the output delayed signal still has a period of T, but its phase is shifted by ΔT relative to the original clock signal Fvco. This delayed signal is passed as input to the next-stage delay unit 101, where it is further delayed by the same or different amounts. This process continues step by step, with the signal being delayed by a fixed time relative to the previous delay signal in each stage of delay unit 101 until it has passed through all N delay units 101, forming a set of delayed clock signals with different phases on the time axis.

[0032] In practical applications, the number N of cascaded delay units 101 depends on application requirements. For example, generating clock signals with more phases requires more delay units 101. Cascaded delay units 101 can generate multiple signals with different phases (e.g., 0°, 45°, 90°, etc.). It should be noted that delay circuit 10 can strictly control the delay so that the maximum frequency delay of the delayed signal output by delay circuit 10 does not exceed 3% or the set jitter range, thereby improving EMI suppression.

[0033] In one embodiment, the original clock signal Fvco is at least a phase-locked loop clock. That is, the original clock signal Fvco is not only a clock signal output by a phase-locked loop, but can also be a clock signal output by any clock generation circuit, such as a crystal oscillator, a clock generator, or other digital circuits. Based on this, a clock circuit with a jittered output can be used in a variety of clock signal output scenarios to reduce electromagnetic interference, thus expanding its applicability.

[0034] In one embodiment, Figure 4As shown, Figure 4 FIG1 shows a schematic diagram of the structure of a delay circuit. The delay unit 101 in the delay circuit 10 can be based on a combination of resistors and capacitors, i.e., an RC delay unit, which implements a circuit for signal delay by combining resistor R and capacitor C. The basic principle is to introduce delay by utilizing the charge and discharge characteristics of a capacitor. Specifically, when the input signal changes, the voltage change of capacitor C is not instantaneous, but changes gradually over time. This change causes the output signal to be delayed relative to the input signal.

[0035] It should be noted that, in addition to the RC delay unit, the delay unit 101 can also be implemented in other ways (such as a transmission delay line, a programmable delay unit, etc.).

[0036] The shift register 201 and the digital logic operation module 202 are used to divide and combine the delayed signal to generate an output clock signal Fvco_out with different frequencies. To facilitate the description and understanding of the circuit structure and the connection relationship between the components, the shift register 201 and the digital logic operation module 202 are collectively referred to as the digital logic circuit 20 in this embodiment. The shift register 201 and the digital logic operation module 202 are both used to process the delayed signal output by the delay circuit 10 and realize signal interaction with each output terminal in the delay circuit 10. In order to simplify the connection relationship between the various components shown in the drawings, Figure 1 In the figure, a modular representation is adopted to integrate the shift register 201 and the digital logic operation module 202 into the digital logic circuit 20 , and the connection lines between the digital logic circuit 20 and the delay circuit 10 are used to uniformly illustrate the actual circuit connection.

[0037] Shift register 201 is a sequential logic circuit comprising multiple cascaded flip-flops for storing and shifting input signals. It is connected to the output of the final delay unit 101 and acts as a frequency divider for the delayed signal. Specifically, shift register 201 performs shifting operations based on the rising or falling edges of the input delayed signal. Whenever a valid edge is detected, the input signal bits are sequentially shifted between the flip-flops at each stage, thereby achieving frequency division of the delayed signal. For example, if the length of shift register 201 is 4, it can achieve frequency division of the input signal by 1 / 2, 1 / 4, 1 / 8, and so on, generating multiple frequency-divided signals of different frequencies.

[0038] In practical applications, by dividing the frequency of the input delayed signal through the shift register 201 , multiple low-frequency signals can be extracted from a high-frequency signal, thereby facilitating the subsequent digital logic unit to combine signals of different frequencies.

[0039] In one embodiment, Figure 5 As shown, Figure 5A schematic diagram of the specific structure of a shift register 201 is shown. It should be noted that Figure 5 The shift register 201 in FIG. 1 includes three D flip-flops 301 (i.e., N=3). In practical applications, the specific value of N can be designed according to actual needs. This is only used as an example. The shift register 201 includes N cascaded D flip-flops 301. Each D flip-flop 301 is a basic sequential logic unit. The D flip-flop 301 has a data input terminal D, a clock input terminal CLK, an output terminal Q, and an inverted output terminal. The data input terminal is used to receive the data to be stored, the clock input terminal is used to receive the clock signal and control the latching timing of the data, the output terminal stores and outputs the latched data, and the reverse output terminal outputs a signal opposite to Q.

[0040] The specific connection between the N D flip-flops 301 is described in detail below. Figure 5 The clock input terminal CLK of the first-stage D flip-flop 301 is connected to the output terminal of the last-stage delay unit 101, and receives the delayed signal as the clock signal. In the case where the delay circuit 10 includes three delay units 101, the delayed signal clk_dly3 output by the third-stage delay unit 101 is used as the input signal of the clock input terminal CLK of the first-stage D flip-flop 301. Based on this, when the clock edge of the delayed signal arrives, the first-stage D flip-flop 301 will latch the signal state of its data input terminal D to the output terminal Q, and output the signal state at the inverted output terminal Q. Generates the opposite signal.

[0041] In the adjacent two-stage D flip-flop 301, the data input terminal D of the upper stage flip-flop is connected to its inverting output terminal Then it is connected to the clock input terminal CLK of the next stage D flip-flop 301. Here, the reverse output terminal of the previous stage flip-flop is connected. Connected to its own data input terminal D, forming a feedback loop. This feedback makes the output state Q of the trigger flip-flop flip between high and low levels every time the clock edge arrives. At the same time, the reverse output terminal of the previous trigger It also serves as the clock input signal CLK for the next stage flip-flop. Therefore, the clock signal frequency of the next stage flip-flop is half the frequency of the output signal of the previous stage flip-flop.

[0042] In one embodiment, since the output signal Q of each D flip-flop 301 flips once every time a clock edge arrives, the frequency of its output signal is half the frequency of the input clock signal. By cascading multiple D flip-flops 301, multi-level frequency division of the input signal can be achieved. Figure 5As shown, the frequency of the output signal qb2 of the first-stage D flip-flop 301 is 1 / 2 of the frequency of the delayed signal output by the last-stage delay unit 101, the frequency of the output signal qb4 of the second-stage D flip-flop 301 is 1 / 4 of the frequency of the delayed signal, and the frequency of the output signal qb8 of the third-stage D flip-flop 301 is 1 / 8 of the frequency of the delayed signal. By analogy, after passing through N stages of D flip-flops 301, the frequency of the output signal is 1 / 2 of the frequency of the input delayed signal.

[0043] Among them, Figure 5 The reset signal (Rstb) in the D flip-flop 301 is used to asynchronously reset the outputs of all D flip-flops 301.

[0044] In one embodiment, the falling edge of the clock input terminal CLK of each stage of the D flip-flop 301 is the trigger source of the D flip-flop 301, that is, at the moment when the input signal of the clock input terminal CLK changes from a high level (logic 1) to a low level (logic 0), the D flip-flop 301 will update the output terminal Q according to the state of the data input terminal D and generate a positive signal at the inverted output terminal Q. Generates the opposite signal. Figure 5 As shown, it is assumed that the clock input terminal CLK of the first-stage D flip-flop 301 inputs the delayed signal clk_dly3, and the falling edge of the delayed signal clk_dly3 is used as the trigger source; the inverting output terminal of the first-stage D flip-flop 301 The flip generates the qb2 signal, which is connected to the clock input terminal CLK of the second-stage D flip-flop 301. The falling edge of the qb2 signal triggers the second-stage D flip-flop 301; the inverting output terminal of the second-stage D flip-flop 301 The flip generates a qb4 signal, which is connected to the clock input terminal CLK of the third-stage D flip-flop 301 . The third-stage D flip-flop 301 is triggered by the falling edge of the qb4 signal.

[0045] Digital logic operation module 202 is a circuit that performs logical operations. It is typically composed of different digital logic operation units, including basic logic gates (such as AND gates, OR gates, and NOT gates) and combinational logic circuits, and is used to perform logical operations on input signals. Here, digital logic operation module 202 is connected to the output of delay circuit 10 and the output of shift register 201 respectively. By performing logical operations (such as AND, OR, XOR, etc.) on these signals, it can extract the rising and falling edge information of each clock signal, and then combine them to generate an output clock signal Fvco_out with different phase and frequency jitter characteristics.

[0046] In practical applications, by adjusting the delay amount of each delay unit in the delay circuit 10, setting the length of the shift register 201, and configuring the logical operation rules of the digital logic operation module 202, a multi-phase jitter clock signal that meets different requirements can be flexibly generated. While the generated output clock signal Fvco_out maintains the basic frequency period, its phase contains a certain amount of random jitter, which manifests as a slight frequency deviation (jitter), thereby achieving spectrum broadening. This design is flexible, scalable, and efficient, and can be extended to any fixed-frequency clock output circuit, thus expanding its applicability.

[0047] It should be noted that the outputs of the shift register 201 and the digital logic operation module 202 only depend on the logic state of the input and are not affected by the amplitude or waveform of the input signal.

[0048] exist Figure 3 The clock circuit shown, by delaying, dividing, and performing combinatorial logic processing on the original clock signal Fvco, can spread a specific frequency into multiple frequency points, thereby generating an output clock signal Fvco_out with certain jitter characteristics, without requiring the original clock signal Fvco to be modulated using a specific method. Because the output clock signal Fvco_out undergoes spread spectrum processing, the signal's energy is dispersed over a wider frequency range, thereby reducing peak power density and electromagnetic interference. At the same time, the jittered output clock signal Fvco_out, due to its dispersed spectrum, can better resist external interference and improve system reliability. To verify the operating performance of the clock circuit, the jittered output clock signal Fvco_out generated by the digital logic operation module 202 was tested, showing that the transmission power at a fixed frequency point can be reduced by at least -6dB, resulting in a significant EMI reduction effect.

[0049] In one embodiment, the operating principle of digital logic operation module 202 is described in detail in conjunction with the specific structure of shift register 201. Digital logic operation module 202 receives three types of signals as input: the inverted output signal of each D flip-flop 301 in shift register 201, the delayed signal output by each delay unit 101 in delay circuit 10, and the original clock signal Fvco. The inverted output signal of D flip-flop 301 is a divided or shifted signal with different frequency or phase characteristics; the delayed signal is used to extract edge information of the clock signal or adjust the signal phase; and the original clock signal Fvco is used in logical operations to provide the clock's base frequency.

[0050] It is understandable that the rising edge and falling edge of the clock signal are very important characteristics in the sequential circuit, which are used to control the latching and transmission of data. The digital logic operation module 202 can extract the rising edge and falling edge information of the clock signal by performing a logical operation on the input signal, thereby combining the output clock signal Fvco_out of different frequencies. Among them, by performing a logical operation (such as an XOR operation) on the original clock signal Fvco and the delayed signal, the rising edge of the clock signal can be extracted. The result of the XOR operation will generate a narrow pulse at the moment when the clock signal changes from a low level to a high level, indicating a rising edge. Similarly, by performing a logical operation on the original clock signal Fvco and the delayed signal, the falling edge of the clock signal can be extracted. For example, after the original clock signal Fvco is inverted and an XOR operation is performed on the delayed signal, a narrow pulse indicating a falling edge can be generated.

[0051] The extracted rising and falling edge signals can be logically operated with other signals (such as the original clock signal Fvco) to generate clock signals of different frequencies. For example, performing an AND operation on multiple signals can generate a clock signal with a lower frequency; performing an OR operation on multiple signals can generate a square wave signal with a 50% duty cycle. The final output clock signal Fvco_out is a combination of the results of multiple logical operations. Its characteristics (such as frequency, phase, duty cycle, etc.) depend on the characteristics of the input signals and the rules of the logical operation.

[0052] For example, in a feasible implementation, the specific structure of the digital logic operation module 202 is as follows: Figure 6 As shown, the digital logic operation module processes three delayed signals (clk_dly1, clk_dly2, clk_dly3) and three output signals (qb2, qb4, qb8) of the D flip-flops 301, wherein Figure 6 The digital logic operation module 202 includes five NAND gates, which perform logic operations on input signals to generate output clock signals Fvco_out of different frequencies.

[0053] The first NAND gate takes the original clock signal Fvco and the inverted output signals qb2, qb4, and qb8 of the D-type flip-flop as inputs. These four signals are ANDed together, and the result is then negated. The output of this NAND gate represents a narrow pulse signal with a low frequency, which is correlated with the logic states of the original clock signals Fvco, qb2, qb4, and qb8. By using the frequency-dividing characteristics of the D-type flip-flop output signals qb2, qb4, and qb8, specific edge information of the original clock signal Fvco can be extracted.

[0054] The second NAND gate takes the inverted output signals qb2 and qb4 of the D-type flip-flop and the delayed signal clk_dly1 as inputs. These three signals are ANDed together, and the result is negated. The output of this NAND gate represents a narrow pulse signal whose frequency and phase are determined by the combination of qb4, qb2, and clk_dly1. The delay characteristics of the delayed signal clk_dly1 allow the rising or falling edge of the clock signal to be extracted. For example, when both the delayed signal clk_dly1 and the inverted output signal qb2 are high, a narrow pulse is generated, representing a rising edge.

[0055] The third NAND gate takes the inverted output signal qb2 of the D-type flip-flop and the delayed signal clk_dly2 as inputs. These two signals are then NANDed and the result negated. The output of this NAND gate represents a narrow pulse signal whose frequency and phase are determined by the combination of clk_dly2 and qb2. The delay characteristics of the delayed signal clk_dly2 allow the falling edge of the clock signal to be detected. For example, when both the delayed signal clk_dly2 and the inverted output signal qb2 are high, a narrow pulse is generated, indicating a falling edge.

[0056] The fourth NAND gate takes the D-flip-flop output signal q2 and the delayed signal clk_dly3 as inputs, performs an AND operation on these two signals, and then negates the result. The output of this NAND gate represents a narrow pulse signal whose frequency and phase are determined by the combination of ck_dly3 and q2. By using the delay characteristics of the delayed signal clk_dly3, a specific edge of the clock signal can be extracted.

[0057] The fifth NAND gate takes the input signals from the outputs of the previous four NAND gates, performs an AND operation on them, and then inverts the result. The output clock signal Fvco_out of this NAND gate is a combination of multiple narrow pulses, with a frequency and phase determined by the logic states of all the input signals.

[0058] In the digital logic operation module 202 , logic operations are performed on the input signal to extract the rising edge and falling edge information of the clock signal, thereby generating an output clock signal Fvco_out with different frequencies and phases by combining the rising edge and falling edge information.

[0059] In one embodiment, the output clock signal Fvco_out is generated through logical combination operations performed by the digital logic operation module 202. The frequency variation of the output clock signal Fvco_out is derived from the combinational logic of the input signals of the digital logic operation module 202. The input signals of the digital logic operation module 202 have different frequencies or phases, and through logical operations, different combination signals of different frequencies can be generated. Within each original clock signal cycle, the digital logic operation module 202 combines and generates an output signal combination of corresponding frequencies based on the states of the input signals. As the input signals change, the frequency of the output clock signal Fvco_out also changes accordingly. Based on this, the frequency of the output clock signal Fvco_out varies periodically. In a complete cycle, the output clock signal Fvco_out traverses multiple frequency points. Within each original clock signal cycle, the state of the input signal of the digital logic operation module 202 changes once, and the frequency of the output clock signal Fvco_out also changes accordingly. After all states have been traversed, the frequency of the output clock signal Fvco_out cycles through the original clock signal Fvco_out.

[0060] Taking the delay circuit 10 including three cascaded delay units 101 and the shift register 201 including three cascaded D registers as an example, refer to Figure 4 、 Figure 5 and Figure 6 , there are 3 reverse output signals (qb2, qb4, qb8) in the clock circuit, and their state combination can represent a 3-bit binary number, with a total of 8 states (respectively: 000, 001, 010, 011, 100, 101, 110, 111). In each original clock signal cycle, the digital logic operation module 202 will output an output clock signal Fvco_out of a corresponding frequency at 8 valid frequency points based on the state combination of the input signal. After all state combinations are traversed, that is, after traversing 8 frequency points, the frequency of the output clock signal Fvco_out cycles once. The waveform of the output clock signal is finally obtained, in which the original clock signal Fvco of 160MHz can be broken up into 8 frequency clock outputs, and 8 cycles constitute one cycle.

[0061] In practical applications, the state changes of the reverse output signals qb2, qb4, and qb8 are carried out according to the binary counting rules, among which the reverse output signal qb2 has the highest frequency and its state is flipped once in each original clock signal cycle; the reverse output signal qb4 has a lower frequency and its state is flipped once in every two original clock signal cycles; the reverse output signal qb8 has the lowest frequency and its state is flipped once in every four original clock signal cycles.

[0062] In the above embodiment, the clock circuit with jitter output is not only applicable to PLL clock output, but any clock output is also applicable to this circuit to reduce EMI. In particular, the original clock signal Fvco passes through N stages of delay units in the delay circuit to generate an output frequency delay. The output delay signal of each stage is processed by a digital logic circuit to generate output clock signals of different frequencies. The delay size can be strictly controlled so that the maximum frequency delay does not exceed 3% or a set range, resulting in a significant EMI reduction effect and a simple circuit structure.

[0063] In one embodiment, a clock management circuit is provided. The clock management circuit may include a clock generation circuit and a clock circuit with a jittered output. The clock generation circuit is used to generate a raw clock signal Fvco and may be a PLL circuit, a crystal oscillator circuit, an RC oscillator, etc. The clock circuit with a jittered output herein is defined as described above and will not be further elaborated here.

[0064] In one embodiment, a chip is provided. The chip includes the limitations of the clock circuit with jitter output described above.

[0065] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0067] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A clock circuit with jitter output, characterized in that: The invention comprises a delay circuit, a shift register and a digital logic operation module; wherein the delay circuit comprises N cascaded delay units, the input end of the first-stage delay unit is connected to the original clock signal, and the original clock signal is sequentially delayed by the N delay units; The shift register is connected to the output end of the last-stage delay unit and is used to divide the frequency of the delayed signal output by the last-stage delay unit; The digital logic operation module is respectively connected to the output end of each stage of delay unit in the delay circuit and the output end of the shift register, and is used for combining output clock signals with different frequencies through logic operation.

2. The clock circuit with jitter output according to claim 1, wherein: The shift register comprises N cascaded D flip-flops, wherein: The clock input terminal of the first-stage D flip-flop is connected to the output terminal of the last-stage delay unit; In two adjacent D flip-flops, the data input terminal and the inverting output terminal of the upper-level flip-flop are connected and connected to the clock input terminal of the lower-level D flip-flop.

3. The clock circuit with jitter output according to claim 1, wherein: The falling edge of the signal at the clock input is the trigger source of each stage of D flip-flop.

4. The clock circuit with jitter output according to claim 2, wherein: The frequency of the output signal of the D flip-flop of the Nth stage is the frequency of the delayed signal input to the shift register.

5. The clock circuit with jitter output according to claim 2, wherein: The digital logic operation module is used to perform logic operations on the signal output from the inverting output terminal of the D flip-flop in the shift register, the delayed signal output from the delay circuit and the original clock signal.

6. The clock circuit with jitter output according to claim 1, wherein: The original clock signal is at least a phase-locked loop clock.

7. The clock circuit with jitter output according to claim 1, wherein: The frequency of the output clock signal changes periodically.

8. The clock circuit with jitter output according to claim 1, wherein: The delay unit is based on a resistor and capacitor combination.

9. A clock management circuit, characterized in that: The invention comprises a clock generating circuit for generating an original clock signal and the clock circuit with jitter output according to any one of claims 1 to 8.

10. A chip, characterized in that: A clock circuit with jitter output comprising any one of claims 1 to 8.

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