Driving circuit

Abstract

A novel semiconductor device and a drive circuit are provided. The first terminal of the first transistor is connected to the first terminal of the second transistor and the first wiring, and the gate of the first transistor is connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. A second terminal of the fifth transistor is connected to a gate of the fifth transistor, a first terminal of the third transistor, and a first terminal of the first capacitor, a second terminal of the third transistor and a second terminal of the fourth transistor are connected to a second wiring, and a second terminal of the first transistor is connected to a third wiring. A second terminal of the second transistor is connected to the fourth wiring, a gate of the third transistor and a gate of the fourth transistor are connected to the fifth wiring, and a second terminal of the first capacitor is connected to the sixth wiring.

Description

Technical Field

[0001] One embodiment of the present invention relates to a driving circuit.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc. relates to an object, a method, a driving method or a manufacturing method. One embodiment of the present invention relates to a process, a machine, a product or a composition. More specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, etc., there can be cited semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, computing processing devices, electronic computers, electronic equipment, systems including them, their driving methods or their manufacturing methods. Background Art

[0003] Display devices are used for various purposes. Examples of large-scale display devices include home television devices and PIDs (Public Information Displays) for digital signage. Examples of small-scale display devices include portable information terminals such as smartphones and tablet terminals, wearable devices such as devices for VR (Virtual Reality) and devices for AR (Augmented Reality). In addition, by giving the display device functions other than display, the display device can be made more functional and with higher added value. For example, research and development of display devices with touch panel functions is underway.

[0004] Furthermore, circuits for driving display devices have been developed, and Patent Document 1 discloses an example of a driving circuit that can be used for a display device.

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2013-211088 Summary of the Invention

[0006] One of the objects of one embodiment of the present invention is to provide a driving circuit with high reliability or a semiconductor device including the driving circuit. Another object of one embodiment of the present invention is to provide a driving circuit with high operating stability or a semiconductor device including the driving circuit. Another object of one embodiment of the present invention is to provide a driving circuit with improved operating speed or a semiconductor device including the driving circuit. Another object of one embodiment of the present invention is to provide a driving circuit with reduced occupied area or a semiconductor device including the driving circuit. Another object of one embodiment of the present invention is to provide a driving circuit with reduced power consumption or a semiconductor device including the driving circuit. Another object of one embodiment of the present invention is to provide a driving circuit capable of improving the performance of a display device or a semiconductor device including the driving circuit. Another object of one embodiment of the present invention is to provide a novel driving circuit or a semiconductor device including the driving circuit.

[0007] Furthermore, the inclusion of the aforementioned objectives does not preclude the existence of other objectives. A person skilled in the art can naturally derive and extract other objectives from the description of this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily achieve all objectives (the aforementioned objectives and other objectives). (1)

[0009] One embodiment of the present invention is a driving circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor, wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor and a first wiring, the gate of the first transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor, the second terminal of the fifth transistor is electrically connected to the gate of the fifth transistor, the first terminal of the third transistor, and the first terminal of the first capacitor, the second terminal of the third transistor and the second terminal of the fourth transistor are electrically connected to the second wiring, the second terminal of the first transistor is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the fourth wiring, the gate of the third transistor and the gate of the fourth transistor are electrically connected to the fifth wiring, the second terminal of the first capacitor is electrically connected to the sixth wiring, the fifth wiring has a function of transmitting a first clock signal, and the sixth wiring has a function of transmitting a second clock signal having a phase different from that of the first clock signal. (2)

[0011] In the above (1), the above-mentioned driving circuit may also include: a first circuit, wherein the first circuit may also include a first terminal and a second terminal, the first terminal of the first circuit may also be electrically connected to the first terminal of the third transistor, the second terminal of the first circuit may also be electrically connected to the gate of the second transistor, the fourth wiring may also have the function of transmitting the first potential, the third wiring may also have the function of transmitting a second potential greater than the first potential, and the first circuit may also have the function of outputting the first potential to the first terminal of the first circuit according to the first clock signal and the second clock signal, the function of putting the first terminal of the first circuit in a high impedance state, the function of outputting the first potential to the second terminal of the first circuit, and the function of outputting the second potential to the second terminal of the first circuit. (3)

[0013] In the above (1), the above-mentioned driving circuit may also include: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, wherein the gate of the sixth transistor may also be electrically connected to the first terminal of the ninth transistor, the first terminal of the tenth transistor and the gate of the eleventh transistor, the first terminal of the sixth transistor may also be electrically connected to the first terminal of the seventh transistor, the second terminal of the seventh transistor may also be electrically connected to the first terminal of the eighth transistor and the gate of the second transistor, the first terminal of the eleventh transistor may also be electrically connected to the first terminal of the twelfth transistor, the second terminal of the eleventh transistor may also be electrically connected to the first terminal of the third transistor, the gate of the eighth transistor and the gate of the tenth transistor may also be electrically connected to the first terminal of the fourth transistor, the second terminal of the sixth transistor may also be electrically connected to the sixth wiring, the gate of the seventh transistor may also be electrically connected to the sixth wiring, the second terminal of the eighth transistor may also be electrically connected to the fourth wiring, the second terminal of the ninth transistor may also be electrically connected to the third wiring, the gate of the ninth transistor may also be electrically connected to the fifth wiring, the second terminal of the tenth transistor may also be electrically connected to the fifth wiring, the second terminal of the twelfth transistor may also be electrically connected to the fourth wiring, and the gate of the twelfth transistor may also be electrically connected to the sixth wiring. (4)

[0015] In any of the above (1) to (3), the channel width of the first transistor may be larger than the channel width of the fifth transistor.

[0016] According to one embodiment of the present invention, a highly reliable driving circuit or a semiconductor device including the driving circuit can be provided. In addition, according to one embodiment of the present invention, a driving circuit with high operating stability or a semiconductor device including the driving circuit can be provided. In addition, according to one embodiment of the present invention, a driving circuit with improved operating speed or a semiconductor device including the driving circuit can be provided. In addition, according to one embodiment of the present invention, a driving circuit with a reduced occupied area or a semiconductor device including the driving circuit can be provided. In addition, according to one embodiment of the present invention, a driving circuit with reduced power consumption or a semiconductor device including the driving circuit can be provided. In addition, according to one embodiment of the present invention, a driving circuit capable of improving the performance of a display device or a semiconductor device including the driving circuit can be provided. In addition, according to one embodiment of the present invention, a novel driving circuit or a semiconductor device including the driving circuit can be provided.

[0017] Furthermore, the description of the aforementioned effects does not preclude the existence of other effects. A person skilled in the art can naturally derive and extract other effects from the descriptions in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all the effects (the aforementioned effects and other effects). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit diagram illustrating a configuration example of a drive circuit;

[0019] Figure 2 is a circuit diagram illustrating a configuration example of a drive circuit;

[0020] Figure 3 is a timing diagram illustrating an example of operation of the drive circuit;

[0021] Figure 4 is a circuit diagram illustrating an example of operation of the drive circuit;

[0022] Figure 5 is a circuit diagram illustrating an example of operation of the drive circuit;

[0023] Figure 6 is a circuit diagram illustrating an example of operation of the drive circuit;

[0024] Figure 7 is a circuit diagram illustrating an example of operation of the drive circuit;

[0025] Figure 8 is a circuit diagram illustrating an example of operation of the drive circuit;

[0026] Figure 9 is a circuit diagram illustrating an example of operation of the drive circuit;

[0027] Figure 10is a circuit diagram illustrating a configuration example of a drive circuit;

[0028] Figure 11 is a circuit diagram illustrating a configuration example of a drive circuit;

[0029] Figure 12 is a circuit diagram illustrating a configuration example of a drive circuit;

[0030] Figure 13 is a circuit diagram illustrating a configuration example of a drive circuit;

[0031] Figure 14 is a circuit diagram illustrating a configuration example of a drive circuit;

[0032] Figure 15 is a circuit diagram illustrating a configuration example of a drive circuit;

[0033] Figure 16 is a circuit diagram illustrating a configuration example of a drive circuit;

[0034] Figure 17 is a circuit diagram illustrating a configuration example of a drive circuit;

[0035] Figure 18 is a circuit diagram illustrating a configuration example of a drive circuit;

[0036] Figure 19 is a circuit diagram illustrating a configuration example of a drive circuit;

[0037] Figure 20 is a circuit diagram illustrating a configuration example of a drive circuit;

[0038] Figure 21 is a circuit diagram illustrating a configuration example of a drive circuit;

[0039] Figure 22 is a circuit diagram illustrating a configuration example of a drive circuit;

[0040] Figure 23 is a circuit diagram illustrating a configuration example of a drive circuit;

[0041] Figure 24 is a circuit diagram illustrating a configuration example of a drive circuit;

[0042] Figure 25 is a circuit diagram illustrating a configuration example of a drive circuit;

[0043] Figure 26 is a timing diagram illustrating an example of operation of the drive circuit;

[0044] Figure 27 is a circuit diagram illustrating an example of operation of the drive circuit;

[0045] Figure 28 is a circuit diagram illustrating an example of operation of the drive circuit;

[0046] Figure 29 is a circuit diagram illustrating an example of operation of the drive circuit;

[0047] Figure 30 is a circuit diagram illustrating an example of operation of the drive circuit;

[0048] Figure 31 is a circuit diagram illustrating an example of operation of the drive circuit;

[0049] Figure 32 is a circuit diagram illustrating an example of operation of the drive circuit;

[0050] Figure 33 is a circuit diagram illustrating a configuration example of a drive circuit;

[0051] Figure 34 is a circuit diagram illustrating a configuration example of a drive circuit;

[0052] Figure 35 is a circuit diagram illustrating a configuration example of a drive circuit;

[0053] Figure 36 is a circuit diagram illustrating a configuration example of a drive circuit;

[0054] Figure 37 is a circuit diagram illustrating a configuration example of a drive circuit;

[0055] Figure 38 is a circuit diagram illustrating a configuration example of a drive circuit;

[0056] Figure 39 is a circuit diagram illustrating a configuration example of a drive circuit;

[0057] Figure 40 is a circuit diagram illustrating a configuration example of a drive circuit;

[0058] Figure 41 is a circuit diagram illustrating a configuration example of a drive circuit;

[0059] Figure 42A and Figure 42B is a block diagram illustrating an example of the structure of a semiconductor device;

[0060] Figures 43A to 43C is a circuit diagram illustrating an example of the structure of a semiconductor device;

[0061] Figure 44A is a top view illustrating an example of the structure of a transistor, Figure 44B and Figure 44C is a cross-sectional view illustrating a structural example of a transistor;

[0062] Figure 45A is a top view illustrating an example of the structure of a transistor, Figure 45B and Figure 45C is a cross-sectional view illustrating a structural example of a transistor;

[0063] Figure 46A is a top view illustrating an example of the structure of a transistor, Figure 46B is a cross-sectional view illustrating a structural example of a transistor;

[0064] Figure 47A is a top view illustrating an example of the structure of a transistor, Figure 47B and Figure 47C is a cross-sectional view illustrating a structural example of a transistor;

[0065] Figure 48A is a top view illustrating an example of the structure of a transistor, Figure 48B and Figure 48C is a cross-sectional view illustrating a structural example of a transistor;

[0066] Figures 49A to 49D is a cross-sectional view illustrating an example of a method for depositing a metal oxide;

[0067] Figures 50A to 50D is a cross-sectional view illustrating an example of a method for depositing a metal oxide;

[0068] Figure 51 is a top view illustrating an example of the structure of a semiconductor device;

[0069] Figure 52A and Figure 52B is a cross-sectional view illustrating an example of the structure of a semiconductor device;

[0070] Figures 53A to 53D is a top view illustrating an example of the structure of a semiconductor device;

[0071] Figure 54A is a perspective view illustrating a structural example of a display device, Figures 54B to 54F is a top view illustrating an example of pixel arrangement;

[0072] Figure 55 is a cross-sectional view illustrating a structural example of a display device;

[0073] Figure 56A and Figure 56B is a cross-sectional view illustrating a structural example of a display device;

[0074] Figure 57A and Figure 57B is a cross-sectional view illustrating a structural example of a display device;

[0075] Figure 58is a perspective view illustrating a structural example of a display device;

[0076] Figure 59 is a cross-sectional view illustrating a structural example of a display device;

[0077] Figures 60A to 60D is a diagram showing an example of an electronic device;

[0078] Figures 61A to 61F is a diagram showing an example of an electronic device;

[0079] Figures 62A to 62G is a diagram showing an example of an electronic device;

[0080] Figures 63A1 to 63A7 and Figures 63B1 to 63B6 It is a diagram illustrating electrical connections. DETAILED DESCRIPTION

[0081] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, for example, a circuit including a semiconductor element (such as a transistor, a diode, or a diode, etc.) or a device including the circuit, etc. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are electronic circuits including semiconductor elements, chips including electronic circuits, electronic components containing chips in packages, or electronic devices equipped with electronic components, etc. In addition, for example, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, computing devices, electronic computers or electronic devices, etc. are themselves semiconductor devices, and sometimes include semiconductor devices.

[0082] The embodiments are described with reference to the accompanying drawings. Note that the embodiments may be implemented in a variety of different forms. Therefore, those skilled in the art will readily appreciate that the embodiments and their details may be modified in a variety of ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0083] In addition, in this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structures are shown in one embodiment, these structures can be appropriately combined and regarded as one mode of the present invention.

[0084] Note that with respect to the drawings illustrating the embodiments, in the structure of the invention, the same symbols are sometimes used in common in different drawings to represent the same parts or parts with the same function, thereby omitting repeated descriptions. In addition, in the drawings, when representing parts with the same function, the same hatching is sometimes used, for example, without adding special symbols. For example, in a stereogram or a top view (also called a "plan view"), for the sake of clarity, the illustration of some constituent elements is sometimes omitted. For example, the description of some hidden lines in the drawings is sometimes omitted. In addition, for example, the description of hatching, etc. in the drawings is sometimes omitted.

[0085] In the drawings, dimensions, layer thicknesses, or regions are sometimes exaggerated for clarity of explanation. Therefore, the drawings are not limited to, for example, the dimensions or aspect ratios shown in the drawings. In addition, in the drawings, ideal examples are schematically shown to aid understanding of the present invention, and therefore, the present invention is not limited to, for example, the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in actual circuit operation, for example, voltage or current may be uneven due to noise or timing deviation, but this is sometimes not reflected in the drawings for ease of understanding.

[0086] In this specification and the accompanying drawings, components are categorized by function and presented as independent components. However, categorization of components by function is difficult, as a single circuit may be involved in multiple functions, or multiple circuits may be involved in a single function. Therefore, the components shown in this specification and the accompanying drawings are not limited to the components described herein, and appropriate wording may be used.

[0087] In this specification and the accompanying drawings, when the same reference numeral is used for multiple components and it is necessary to distinguish them, an identification symbol such as "A," "b," "_1," "[n]," or "[m,n]" may be added to the reference numeral. Furthermore, when describing content common to multiple components assigned an identification symbol or when it is not necessary to distinguish them, the components may be described without the identification symbol.

[0088] Note that in this specification, etc., the term "on-state" or "turn-on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are electrically short-circuited, or a state in which current can flow between the source and drain (also referred to as a state in which current can flow). For example, the following states are sometimes referred to as "on-state" or "turn-on state": a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage; or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Furthermore, the term "non-conducting state," "off-state," or "off-state" of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected. For example, the following states are sometimes referred to as "non-conducting state," "off-state," or "turn-off state": a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage; or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage.

[0089] In this specification, the voltage between the gate and source (gate-source) (unless otherwise specified, the potential of the source is used as a reference) is sometimes referred to as the "gate voltage," the voltage between the drain and source (drain-source) (unless otherwise specified, the potential of the source is used as a reference) is sometimes referred to as the "drain voltage," and the voltage between the back gate and source (back gate-source) (unless otherwise specified, the potential of the source is used as a reference) is sometimes referred to as the "back gate voltage." Furthermore, the current flowing between the drain and source (unless otherwise specified, the direction from the drain to the source is considered positive) is sometimes referred to as the "drain current." Note that descriptions of n-channel transistors such as "high gate voltage," "high drain voltage," and "high back gate voltage" can be appropriately converted to descriptions of p-channel transistors such as "low gate voltage," "low drain voltage," and "low back gate voltage." Furthermore, descriptions such as low gate voltage, low drain voltage, and low back gate voltage of an n-channel transistor can be appropriately converted to descriptions such as high gate voltage, high drain voltage, and high back gate voltage of a p-channel transistor.

[0090] In addition, unless otherwise specified in this specification, the "off-state current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification, the off-state current and the current flowing between the gate and the source and drain (also called gate leakage current) are sometimes collectively referred to as leakage current.

[0091] In addition, in this specification, etc., one of the source and drain of a transistor (also referred to as two input and output terminals) is sometimes referred to as the first terminal, and the other of the source and drain of the transistor is sometimes referred to as the second terminal. In other words, a transistor includes at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. In addition, one terminal of a capacitor (also referred to as one of a pair of terminals) is sometimes referred to as the first terminal, and the other terminal of the capacitor (also referred to as the other of a pair of terminals) is sometimes referred to as the second terminal. In addition, one terminal of a display element is sometimes referred to as the first terminal, and the other terminal of the display element is sometimes referred to as the second terminal. In addition, one terminal of a liquid crystal element is sometimes referred to as the first terminal, and the other terminal of the liquid crystal element is sometimes referred to as the second terminal. In addition, one terminal of a light-emitting element is sometimes referred to as the first terminal, and the other terminal of the light-emitting element is sometimes referred to as the second terminal. In addition, one terminal of a light-receiving element is sometimes referred to as the first terminal, and the other terminal of the light-receiving element is sometimes referred to as the second terminal. In addition, one of the anode and cathode of a diode (also referred to as one of a pair of terminals) is sometimes referred to as the first terminal, and the other of the anode and cathode of the diode (also referred to as the other of a pair of terminals) is sometimes referred to as the second terminal.

[0092] Implementation Method 1

[0093] A driver circuit according to one embodiment of the present invention will be described with reference to the accompanying drawings. At least a portion of the driver circuit according to one embodiment of the present invention can be used in a semiconductor device such as a display device.

[0094] <Configuration Example of Driving Circuit>

[0095] Figure 1 and Figure 2 This is a circuit diagram illustrating a driving circuit according to one embodiment of the present invention.

[0096] like Figure 1 As shown, the driving circuit 100 includes a transistor M11 , a transistor M12 , a transistor M13 , a transistor M14 , a transistor M15 and a capacitor C11 .

[0097] One of the source and drain of transistor M11 is connected to one of the source and drain of transistor M12 and wiring OUTL. The gate of transistor M11 is connected to one of the source and drain of transistor M14 and one of the source and drain of transistor M15. The other of the source and drain of transistor M15 is connected to the gate of transistor M15, one of the source and drain of transistor M13, and one terminal of capacitor C11. The other of the source and drain of transistor M13 and the other of the source and drain of transistor M14 are connected to wiring SPL. The other of the source and drain of transistor M11 is connected to wiring VL1. The other of the source and drain of transistor M12 is connected to wiring VL2. The gate of transistor M13 and the gate of transistor M14 are connected to wiring CKL1. The other terminal of capacitor C11 is connected to wiring CKL2.

[0098] The wiring connected to the other of the source and drain of transistor M15 and one terminal of capacitor C11 is sometimes referred to as node NDA. Furthermore, the wiring connected to one of the source and drain of transistor M15 and the gate of transistor M11 is sometimes referred to as node NDB. Furthermore, the wiring connected to the gate of transistor M12 is sometimes referred to as node NDC. Note that nodes and wiring can also be interchangeably referred to as wiring.

[0099] In the driver circuit 100, each transistor (transistor M11 to transistor M15, etc.) is an n-channel transistor or a p-channel transistor. Here, each transistor is described as an n-channel transistor. The on-state current of an n-channel transistor is larger than that of a p-channel transistor. Therefore, by using n-channel transistors, the operating speed of the driver circuit 100 can be increased. In addition, compared with p-channel transistors, the channel width required for an n-channel transistor to obtain the same degree of on-state current is smaller. Therefore, by using n-channel transistors, the occupied area of ​​the driver circuit 100 can be reduced.

[0100] Note that when p-channel transistors are used as each transistor, the following descriptions regarding the relationship between voltage signs and potentials can be appropriately changed. For example, "high potential" can be appropriately changed to "low potential," and "low potential" can be appropriately changed to "high potential." Furthermore, for example, "increasing the potential" can be appropriately changed to "decreasing the potential," and "decreasing the potential" can be appropriately changed to "increasing the potential."

[0101] Wiring CKL1, for example, has the function of transmitting a first clock signal. Wiring CKL2, for example, has the function of transmitting a second clock signal having a different phase from that of the first clock signal. Alternatively, wiring CKL2, for example, has the function of transmitting a second clock signal having a different timing of potential change from that of the first clock signal. Alternatively, wiring CKL2, for example, has the function of transmitting a second clock signal having a different rising timing from that of the first clock signal. Alternatively, wiring CKL2, for example, has the function of transmitting a second clock signal having a different falling timing from that of the first clock signal. Wiring VL1, for example, has the function of transmitting a potential H. Wiring VL2, for example, has the function of transmitting a potential L that is lower than potential H. In this case, the difference between potential H and potential L is preferably greater than the threshold voltage of the transistor included in the driver circuit 100. Wiring SPL, for example, has the function of transmitting a trigger signal. Wiring OUTL, for example, has the function of transmitting an output signal.

[0102] Here, wiring CKL1 can also be said to have, for example, the function of transmitting a first clock signal supplied from a circuit external to the driver circuit 100 to the gates of transistors M13 and M14, respectively. Wiring CKL2 can also be said to have, for example, the function of transmitting a second clock signal supplied from a circuit external to the driver circuit 100 to the other terminal of capacitor C11. Wiring VL1 can also be said to have, for example, the function of transmitting a potential H supplied from a circuit external to the driver circuit 100 to the other of the source and drain of transistor M11. Wiring VL2 can also be said to have, for example, the function of transmitting a potential L supplied from a circuit external to the driver circuit 100 to the other of the source and drain of transistor M12. Wiring SPL can also be said to have, for example, the function of transmitting a trigger signal (sometimes also called a start pulse signal) supplied from a circuit external to the driver circuit 100 or an output signal from wiring OUTL supplied to another driver circuit 100 to the other of the source and drain of transistor M13 and the other of the source and drain of transistor M14, respectively. In addition, it can be said that the wiring OUTL has a function of transmitting an output signal supplied from the driving circuit 100 to a pixel provided outside the driving circuit 100 , for example.

[0103] Note that, for example, either the potential H or the potential L is supplied to the gate of the transistor M12 (equivalent to the node NDC).

[0104] In the driver circuit 100 , the potential of the wiring VL1 is supplied to the wiring OUTL via the transistor M11 , and the potential of the wiring VL2 is supplied to the wiring OUTL via the transistor M12 , based on signals supplied to the wirings CKL1 , CKL2 , and SPL and the potential of the node NDC.

[0105] Here, for example, when the driving circuit 100 is used in a display device, the wiring OUTL is connected to the pixel. Therefore, the on-state current of each of the transistors M11 and M12 is preferably greater than the on-state current of each of the transistors M13 to M15. By increasing the on-state current of each of the transistors M11 and M12, the time required to change the potential of the wiring OUTL (i.e., the rise time and the fall time) can be shortened, and the operating speed of the driving circuit can be increased, thereby achieving high-speed display device. To this end, for example, by making the channel width of each of the transistors M11 and M12 greater than the channel width of each of the transistors M13 to M15, the on-state current can be increased, thereby achieving high-speed display device. In addition, for example, by making the channel length of each of the transistors M11 and M12 less than the channel length of each of the transistors M13 to M15, the on-state current can be increased, thereby achieving high-speed display device.

[0106] As will be described in detail later, during operation of the driver circuit 100, as the potential of the wiring OUTL increases, the gate voltage (the voltage between the gate and the source) of the transistor M11 gradually decreases. Therefore, to increase the on-state current of the transistor M11, for example, the channel width of the transistor M11 may be made larger than the channel width of the transistor M12. Furthermore, the channel length of the transistor M11 may be made larger than the channel length of the transistor M12.

[0107] like Figure 2 As shown, the driving circuit 100 may further include a circuit 110. The circuit 110 includes a terminal OTA and a terminal OTB. The terminal OTA is connected to one of the source and the drain of the transistor M13. The terminal OTB is connected to the gate of the transistor M12.

[0108] The circuit 110 has at least the function of outputting a first potential to the terminal OTA, the function of placing the terminal OTA in a high impedance state, the function of outputting a second potential to the terminal OTB, and the function of outputting a third potential to the terminal OTB. In addition, the circuit 110 may also have the function of placing the terminal OTB in a high impedance state. The first potential is, for example, the same as the potential supplied to the wiring VL2 (for example, potential L), or a potential that can turn off the transistor M15. The second potential is a potential greater than the first potential, for example, the same as the potential supplied to the wiring VL1 (for example, potential H), or a potential that can turn on the transistor M12. The third potential is, for example, the same as the first potential, the potential supplied to the wiring VL2 (for example, potential L), or a potential that can turn off the transistor M12. At this time, the circuit 110 can output an arbitrary potential to each of the terminals OTA and OTB or place each of the terminals OTA and OTB in a high impedance state based on the signal supplied to the wiring CKL1 and the signal supplied to the wiring CKL2. Therefore, it can be said that the circuit 110 can operate in synchronization with a signal supplied to the wiring CKL1 and a signal supplied to the wiring CKL2 , for example.

[0109] An operation example of the driving circuit 100 and a specific configuration example and operation example of the circuit 110 will be described later.

[0110] In one embodiment of the present invention, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor constituting the driver circuit 100. Furthermore, as the semiconductor, in addition to a single semiconductor whose main component is composed of a single element (for example, silicon or germanium), a compound semiconductor (for example, silicon germanium or gallium arsenide) or an oxide semiconductor can also be used.

[0111] For example, as a transistor constituting the driving circuit 100, a transistor including silicon in a channel formation region (Si transistor) or a transistor including an oxide semiconductor in a channel formation region (OS transistor) can be used, or both Si transistors and OS transistors can be used.

[0112] Various transistors can be used as transistors constituting the driving circuit 100. For example, a MOS field effect transistor, a junction field effect transistor, or a bipolar transistor can be used.

[0113] In addition, transistors of various structures can be used as transistors constituting the driving circuit 100. For example, transistors of various structures such as top gate type (such as planar type and staggered type), bottom gate type (such as inverted planar type and inverted staggered type), dual gate type (a structure in which gates are arranged on both sides (such as top and bottom) of a channel formation region), FIN type (fin type), TRI-GATE type (triple gate type) and GAA type (all around gate) can be used. In addition, for example, vertical transistors (transistors having a longitudinal component (also called a height direction or a direction perpendicular to the formed surface) in the channel length direction) can be used.

[0114] In addition, in one embodiment of the present invention, a transistor has the function of controlling conduction or non-conduction between a source connection object and a drain connection object. For example, transistor M11 has the function of controlling conduction or non-conduction between wiring VL1 and wiring OUTL. For example, transistor M12 has the function of controlling conduction or non-conduction between wiring VL2 and wiring OUTL. For example, transistor M13 has the function of controlling conduction or non-conduction between wiring SPL and node NDA. For example, transistor M14 has the function of controlling conduction or non-conduction between wiring SPL and node NDB. For example, transistor M15 has the function of controlling conduction or non-conduction between node NDA and node NDB. Note that one embodiment of the present invention is not limited to this.

[0115] In one embodiment of the present invention, the on-state or off-state of a transistor is controlled by the potential of the object to which the gate is connected. For example, the on-state or off-state of transistor M11 is controlled by the potential of node NDB. For example, the on-state or off-state of transistor M12 is controlled by the potential of node NDC. For example, the on-state or off-state of transistor M13 is controlled by the potential of wiring CKL1 (for example, the first clock signal). For example, the on-state or off-state of transistor M14 is controlled by the potential of wiring CKL1 (for example, the first clock signal). For example, the on-state or off-state of transistor M15 is controlled by the potential of node NDA. Note that one embodiment of the present invention is not limited to this.

[0116] In one embodiment of the present invention, a transistor has the function of supplying the potential of one of its source and drain terminals to the other of its source and drain terminals, or the function of supplying the potential of the other of its source and drain terminals to the other of its source and drain terminals. In other words, the potential of one of the transistor's source and drain terminals is supplied to the other of its source and drain terminals via the transistor's channel formation region. Alternatively, the potential of the other of its source and drain terminals is supplied to the other of its source and drain terminals via the transistor's channel formation region. For example, transistor M11 has the function of supplying the potential of wiring VL1 to wiring OUTL. For example, transistor M12 has the function of supplying the potential of wiring VL2 to wiring OUTL. For example, transistor M13 has the function of supplying the potential of wiring SPL to node NDA. For example, transistor M14 has the function of supplying the potential of wiring SPL to node NDB. For example, transistor M15 has the function of supplying the potential of node NDA to node NDB. In this case, the supplied potential may differ from the potential corresponding to the threshold voltage of the transistor. Note that one embodiment of the present invention is not limited to this.

[0117] Note that a structural example of a transistor that can be used in the driver circuit 100 will be described in Embodiment 2 later.

[0118] [Work Examples]

[0119] Next, an operation example of the driving circuit 100 will be described.

[0120] Figure 3 1 is a timing chart illustrating an example of the operation of the driving circuit 100 . Figures 4 to 9 This is a circuit diagram illustrating an example of the operation of the driving circuit 100. Note that, here, as an example, Figure 2 The operation of the driving circuit 100 is shown.

[0121] In driver circuit 100, wiring CKL1, wiring CKL2, and wiring SPL all serve as signal lines. The potential of each signal supplied to wiring CKL1, wiring CKL2, and wiring SPL is either potential L (sometimes simply referred to as "L") or potential H (sometimes simply referred to as "H"), which is greater than potential L. In this case, the difference between potential H and potential L is greater than the threshold voltage of the transistor. Note that potential L can be, for example, ground potential.

[0122] The wiring VL1 and the wiring VL2 are both used as power supply lines. Here, the wiring VL1 is supplied with a potential H, and the wiring VL2 is supplied with a potential L.

[0123] In addition, a signal may be supplied to at least one of the wiring VL1 and the wiring VL2. In other words, at least one of the wiring VL1 and the wiring VL2 may be used as a signal line.

[0124] In order to facilitate understanding of the description, the potential supplied to each wiring is set to the potential L or the potential H, but different potentials may be supplied to each wiring.

[0125] Furthermore, when describing operations, when potential changes, rise and fall times occur due to loads (parasitic capacitance and resistance) such as wiring. Furthermore, even if the timing of two different operations is shown as identical, this does not necessarily mean that the timing is exactly the same. For example, even if a slight time lag due to signal delays in wiring is included, the timing may be considered identical.

[0126] In order to facilitate understanding of the description, each period may be shown with the same length in a timing chart, but the time length of each period may be different.

[0127] Figure 3 The timing diagrams shown here illustrate the potentials supplied to wiring CKL1, wiring CKL2, and wiring SPL during each operating period. Furthermore, the diagrams show the potentials H, L, or high impedance (indicated by "Hi-Z" in the figures) at terminals OTA and OTB included in circuit 110. Furthermore, the diagrams show changes in the potentials of nodes NDA, NDB, and NDC. Furthermore, the diagrams show changes in the potential of wiring OUTL.

[0128] in addition, Figures 4 to 9 The circuit conditions at each operating time are shown (the potential of each wiring and each node, the state of each transistor, the current flowing through each wiring and each node, etc.). For example, the potentials of wiring CKL1, wiring CKL2, wiring SPL, wiring VL1, wiring VL2, node NDA, node NDB, node NDC, and wiring OUTL are shown. At this time, sometimes symbols representing the potential (also called potential symbols) such as "H" or "L" are recorded with border lines adjacent to each wiring. In particular, sometimes the border line is thickened when the potential changes, and the border line is recorded as a dotted line when in a floating state. In addition, sometimes an "×" symbol is attached to overlap with the transistor in the off state. In addition, sometimes a dotted arrow is attached along each wiring to show the direction of current flow (or the direction of positive charge movement).

[0129] In addition, the threshold voltage of the transistor M11 is sometimes referred to as Vt11, the threshold voltage of the transistor M12 is sometimes referred to as Vt12, the threshold voltage of the transistor M13 is sometimes referred to as Vt13, the threshold voltage of the transistor M14 is sometimes referred to as Vt14, and the threshold voltage of the transistor M15 is sometimes referred to as Vt15.

[0130] In order to facilitate understanding of the description, when a potential change occurs due to capacitive coupling of a capacitor, the description may be given without considering the influence of parasitic capacitance.

[0131] Just before entering period T11, both wiring CKL1 and wiring CKL2 are supplied with a potential of L, and wiring SPL is supplied with a potential of H. Furthermore, terminal OTA is in a high-impedance state, and terminal OTB outputs a potential of L. Therefore, transistors M13 and M14 are both in an off state, and nodes NDA and NDB are both in a floating state. At this time, the potential of node NDA is "potential H - Vt13," and the potential of node NDB is a value exceeding "potential H + Vt11." Therefore, transistor M15 is in an off state, and transistor M11 is in an on state. Furthermore, the potential of node NDC is at a potential of L, and transistor M12 is in an off state. Therefore, the potential of wiring VL1 is supplied to wiring OUTL via transistor M11, so the potential of wiring OUTL is at a potential of H. Figure 4 Note that in the following description, unless otherwise specified, the previous state is maintained.

[0132] During period T11, a potential of H is supplied to wiring CKL1, and a potential of L is supplied to wiring SPL. Furthermore, a potential of L is output to terminal OTA, or terminal OTA is in a high-impedance state. In either case, transistor M13 is turned on, and the potential of node NDA is at a potential of L. Furthermore, transistor M14 is turned on, and the potential of node NDB is at a potential of L. Consequently, transistor M11 is turned off. Furthermore, a potential of L is output to terminal OTB, or terminal OTB is in a high-impedance state. In either case, the potential of node NDC remains at a potential of L, and transistor M12 remains in an off state. Consequently, wiring OUTL is in a floating state, and the potential of wiring OUTL remains at a potential of H. Figure 5 Here, the terminal OTA is in a high impedance state and the potential L is output to the terminal OTB.

[0133] During period T12, a potential of L is supplied to wiring CKL1, a potential of H is supplied to wiring CKL2, and a potential of H is supplied to wiring SPL. Furthermore, a potential of L is output to terminal OTA. At this time, transistor M13 is in an off state. At this time, although a potential of H is supplied to wiring CKL2, a potential of L is output to terminal OTA. Therefore, the potential of node NDA does not rise due to capacitive coupling through capacitor C11, but remains at a potential of L. Furthermore, transistor M14 is in an off state, and node NDB is in a floating state. At this time, the potential of node NDB remains at a potential of L, and transistor M11 remains in an off state. Furthermore, a potential of H is output to terminal OTB. Consequently, the potential of node NDC becomes a potential of H, and transistor M12 becomes an on state. Consequently, the potential of wiring VL2 is supplied to wiring OUTL via transistor M12, causing the potential of wiring OUTL to become a potential of L. Figure 6 The circuit status at this time is shown.

[0134] During period T13, wiring CKL1 is supplied with a potential of H, and wiring CKL2 is supplied with a potential of L. Furthermore, terminal OTA enters a high-impedance state. Consequently, transistor M13 is turned on and continues to rise until the potential of node NDA reaches "potential H - Vt13." Furthermore, transistor M14 is turned on and continues to rise until the potential of node NDB reaches "potential H - Vt14." Consequently, transistor M11 is turned on. Furthermore, terminal OTB is output with a potential of L. Consequently, the potential of node NDC reaches potential L, and transistor M12 is turned off. Consequently, the potential of wiring VL1 is supplied to wiring OUTL via transistor M11. At this point, when the potential of wiring OUTL rises to a value obtained by subtracting Vt11 from the potential of node NDB, transistor M11 is turned off. In other words, the potential of wiring OUTL rises to "potential H - Vt14 - Vt11." Figure 7 The circuit status at this time is shown.

[0135] For example, by increasing the potential of the wiring CKL1 to a value greater than "potential H+Vt13", the potential of the node NDA can be increased to potential H. Furthermore, by increasing the potential of the wiring CKL1 to a value greater than "potential H+Vt14", the potential of the node NDB can be increased to potential H. Furthermore, for example, if the potential of the node NDB can be increased to a value exceeding "potential H+Vt11" due to the increase in the potential of the wiring OUTL, the potential of the wiring OUTL can be increased to potential H without turning off the transistor M11.

[0136] During period T14, wiring CKL1 is supplied with a potential of L, and wiring CKL2 is supplied with a potential of H. Furthermore, terminal OTA remains in a high-impedance state. Consequently, transistor M13 is turned off, and node NDA becomes floating. Furthermore, transistor M14 is turned off, and node NDB becomes floating. At this time, since wiring CKL2 is supplied with a potential of H, the potential of node NDA rises due to capacitive coupling through capacitor C11. Here, when the potential of node NDA rises by ΔV1, the potential of node NDA becomes "potential H - Vt13 + ΔV1." Furthermore, transistor M15 is turned on, and the potential of node NDB rises to a value obtained by subtracting Vt15 from the potential of node NDA. In other words, the potential of node NDB becomes "potential H - Vt13 + ΔV1 - Vt15." At this time, when the potential increase value ΔV1 at node NDA satisfies the condition "ΔV1 > Vt11 + Vt13 + Vt15," the potential at node NDB exceeds "potential H + Vt11," and transistor M11 turns on. Alternatively, a potential of L is output to terminal OTB, or terminal OTB enters a high-impedance state. In either case, the potential at node NDC remains at L, and transistor M12 remains off. Consequently, the potential of wiring VL1 is supplied to wiring OUTL via transistor M11, causing the potential of wiring OUTL to rise to H. Figure 8 Here, the state of the circuit at this time is shown. Here, the state where the potential L is output to the terminal OTB is shown.

[0137] During period T15, potential H is supplied to wiring CKL1, and potential L is supplied to wiring CKL2. Furthermore, terminal OTA remains in a high-impedance state. Consequently, since potential L is supplied to wiring CKL2, the potential of node NDA decreases due to capacitive coupling through capacitor C11. At this point, for example, the potential of node NDA reaches "potential H - Vt13." Furthermore, even if the potential of node NDA drops to a value below "potential H - Vt13," transistor M13 turns on, causing the potential to rise, reaching "potential H - Vt13." Furthermore, since the potential of node NDB is greater than that of node NDA, transistor M15 turns off. Furthermore, since the potential of node NDB is greater than that of wiring CKL1, transistor M14 remains off. Consequently, node NDB becomes floating. At this point, the potential of node NDB remains at "potential H - Vt13 + ΔV1 - Vt15," and transistor M11 remains on. Furthermore, potential L is output to terminal OTB, or terminal OTB enters a high-impedance state. In either case, the potential of the node NDC remains at potential L, and the transistor M12 remains off. Therefore, the potential of the wiring VL1 is supplied to the wiring OUTL via the transistor M11, and the potential of the wiring OUTL remains at potential H. Figure 9Here, the state of the circuit at this time is shown. Here, the state where the potential L is output to the terminal OTB is shown.

[0138] After the period T15, the operation in the period T14 and the operation in the period T15 are repeated.

[0139] Figure 3 The timing diagram shown shows the periods between periods T11 to T15. For example, to clearly illustrate the following situation, the periods between periods T11 to T15 are shown: when the potential change timing (rise time and fall time) of each wiring occurs, the potential of wiring CKL1 drops from potential H to potential L, and then the potential of wiring CKL2 begins to rise from potential L to potential H. After the potential of wiring CKL2 drops from potential H to potential L, the potential of wiring CKL1 begins to rise from potential L to potential H. Therefore, the periods between periods T11 to T15 are preferably short. Alternatively, periods T11 to T15 may be continuous without providing a period between periods T11 to T15.

[0140] A driver circuit according to one embodiment of the present invention can, for example, set the potential of node NDB to a value exceeding "potential H + Vt11" during period T14, thereby increasing the gate voltage of transistor M11. This allows the potential of wiring OUTL to rise to potential H. Furthermore, the rate at which the potential of wiring OUTL rises can be increased. In other words, the rise time of the potential of wiring OUTL can be shortened. Consequently, the operating speed of the driver circuit can be increased, enabling a higher-speed display device. Furthermore, for example, even if the load on wiring OUTL increases, the gate voltage of transistor M11 can be increased, thereby suppressing a decrease in the operating speed of the driver circuit. This allows for higher resolution and larger screens of display devices. Furthermore, for example, even if the power supply voltage used to operate the driver circuit is reduced (e.g., equivalent to the potential difference between potential H and potential L), the gate voltage of transistor M11 can be increased, thereby suppressing a decrease in the operating speed of the driver circuit. Consequently, low power consumption of the display device can be achieved. Furthermore, for example, even if the channel width of transistor M11 is reduced, the gate voltage of transistor M11 can be increased, thereby suppressing a decrease in the operating speed of the driver circuit. Therefore, the area occupied by the driving circuit can be reduced, thereby achieving a narrow frame of the display device.

[0141] Furthermore, for example, during period T15, the potential of node NDB can be maintained at a value exceeding "potential H + Vt11." Consequently, transistor M11 can be maintained in an on state, and potential H can continue to be supplied to wiring OUTL. In other words, potential H can continue to be supplied to wiring OUTL without causing wiring OUTL to enter a floating state. Consequently, the effects of noise on wiring OUTL can be reduced, thereby stabilizing the operation of the display device.

[0142] Furthermore, for example, the potential of node NDB can be kept constant or kept small during periods T14 and T15. This prevents changes in the potential of node NDB from being transmitted to wiring OUTL via the gate capacitance of transistor M11 (the capacitance between the gate and one of the source and drain electrodes), thereby preventing noise from being generated in wiring OUTL. This stabilizes the operation of the display device. Furthermore, for example, even if the channel width of transistor M11 is increased, the potential of node NDB can be kept constant or kept small, thereby suppressing noise from being generated in wiring OUTL. Therefore, the channel width of transistor M11 can be increased, thereby increasing the on-state current. This increases the rate at which the potential of wiring OUTL rises. In other words, the rise time of the potential of wiring OUTL can be shortened. This increases the operating speed of the driver circuit, thereby achieving a higher-speed display device. Furthermore, for example, even if the load on wiring OUTL is increased, the channel width of transistor M11 can be increased, thereby suppressing a decrease in the operating speed of the driver circuit. This enables higher resolution and larger screen sizes for display devices.

[0143] Furthermore, for example, during period T14, the potential of node NDB can be made lower than the potential of node NDA. Consequently, the voltage applied between the terminals of transistors M11 and M14 connected to node NDB can be reduced. This can suppress damage and degradation of the transistors, thereby improving the reliability of the display device.

[0144] By adopting a structure in which the other terminal of capacitor C11 is connected to wiring CKL2 without passing through the source and drain of the transistor (it can also be said that the other terminal of capacitor C11 is directly connected to wiring CKL2), compared to a structure in which the other terminal of capacitor C11 is connected to wiring CKL2 through the source and drain of the transistor (it can also be said that the other terminal of capacitor C11 is indirectly connected to wiring CKL2), for example, the rise time of the potential of the other terminal of capacitor C11 can be shortened during period T14. Here, when the rise time of the potential of the other terminal of capacitor C11 becomes shorter, the rise time of the potential of node NDA becomes shorter. When the rise time of the potential of node NDA becomes shorter, the rise time of the potential of node NDB becomes shorter. When the rise time of the potential of node NDB becomes shorter, the timing at which transistor M11 becomes on becomes earlier. The earlier the timing at which transistor M11 becomes on, the shorter the rise time of the potential of wiring OUTL. Therefore, the operating speed of the driver circuit can be improved, and the display device can be made faster.

[0145] In addition, by adopting a structure in which the other terminal of capacitor C11 is connected to wiring CKL2 without passing through the source and drain of the transistor, the electrostatic capacitance of capacitor C11 can be reduced compared to a structure in which the other terminal of capacitor C11 is connected to wiring CKL2 through the source and drain of the transistor. For example, when the rise time of the potential of the other terminal of capacitor C11 or the rise time of the potential of node NDA is the same, the electrostatic capacitance of capacitor C11 can be reduced. Here, when the electrostatic capacitance of capacitor C11 is small, the area in which the pair of electrodes (also referred to as a pair of terminals or a pair of conductive layers) of capacitor C11 overlap with each other can be reduced. Therefore, the area occupied by the drive circuit can be reduced, thereby achieving a narrow frame of the display device.

[0146] Here, by connecting the other terminal of capacitor C11 to wiring CKL2 without passing through the source and drain of the transistor, the capacitance of capacitor C11 can be reduced. Therefore, the overlapping area of ​​the pair of electrodes of capacitor C11 can be smaller than the area of ​​the channel formation region of transistor M11. The overlapping area of ​​the pair of electrodes of capacitor C11 can be smaller than the area of ​​the channel formation region of transistor M12. However, if the capacitance of capacitor C11 is too small, ΔV1, which corresponds to the potential rise value of node NDA, becomes smaller. Therefore, the overlapping area of ​​the pair of electrodes of capacitor C11 can be larger than the area of ​​the channel formation region of transistor M13. The overlapping area of ​​the pair of electrodes of capacitor C11 can be larger than the area of ​​the channel formation region of transistor M14. The overlapping area of ​​the pair of electrodes of capacitor C11 can be larger than the area of ​​the channel formation region of transistor M15. Furthermore, the overlapping area of ​​the pair of electrodes of capacitor C11 can be larger than the sum of the areas of the channel formation regions of transistors M13, M14, and M15.

[0147] The driver circuit according to one embodiment of the present invention can achieve at least one of the aforementioned effects by adding transistors M13, M15, and capacitor C11 to the driver circuit composed of transistors M11, M12, and M14. Therefore, the driver circuit according to one embodiment of the present invention can be said to have a structure with fewer circuit elements, such as transistors and capacitors, wiring, and signals. This can reduce the area occupied by the driver circuit, thereby achieving a narrower frame for the display device.

[0148] [Deformation Example 1]

[0149] The driving circuit according to one embodiment of the present invention is not limited to the above-described configuration, and can have various configurations.

[0150] Figure 10 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 10 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 10 The illustrated drive circuit 100 further includes a transistor M16. The other of the source and drain of transistor M15 is connected to the gate of transistor M15, one terminal of capacitor C11, and one of the source and drain of transistor M16. The other of the source and drain of transistor M16 is connected to one of the source and drain of transistor M13. The gate of transistor M16 is connected to wiring VL1.

[0151] By adopting this structure, for example, it is possible to prevent a large voltage from being applied to transistor M13 and transistors included in circuit 110 during period T14, thereby suppressing damage and degradation of these transistors. Consequently, reliability can be improved. Furthermore, by increasing the amplitude of the signal supplied to wiring CKL2, for example, thereby increasing the potential rise value ΔV1 corresponding to each of nodes NDA and NDB, it is possible to increase the gate voltage of transistor M11 while preventing a large voltage from being applied to transistor M13 and transistors included in circuit 110. This can improve operating speed.

[0152] Note that since the potential of the node NDA is higher than the potential of the node NDB, it is particularly preferable to provide the transistor M16.

[0153] [Variation Example 2]

[0154] Figure 11 It is an explanation Figure 10 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 11 The driving circuit 100 shown is Figure 10 The difference of the driving circuit 100 shown is that Figure 11 The illustrated drive circuit 100 further includes a transistor M17. The gate of transistor M11 is connected to one of the source and drain of transistor M15 and one of the source and drain of transistor M17. The other of the source and drain of transistor M17 is connected to one of the source and drain of transistor M14. The gate of transistor M17 is connected to wiring VL1.

[0155] By adopting this structure, for example, it is possible to prevent a high voltage from being applied to transistor M14 during periods T14 and T15, thereby suppressing damage and degradation of the transistor. Consequently, reliability can be improved. Furthermore, by increasing the amplitude of the signal supplied to wiring CKL2, for example, thereby increasing the potential rise value ΔV1 corresponding to each of nodes NDA and NDB, it is possible to increase the gate voltage of transistor M11 while preventing a large voltage from being applied to transistor M14. This can improve operating speed.

[0156] As described above, when the capacitance of capacitor C11 is too small, ΔV1, which corresponds to the potential rise value of node NDA, becomes smaller. Therefore, the overlapping area of ​​the pair of electrodes of capacitor C11 can be made larger than the area of ​​the channel formation region of transistor M16. The overlapping area of ​​the pair of electrodes of capacitor C11 can be made larger than the area of ​​the channel formation region of transistor M17. Furthermore, the overlapping area of ​​the pair of electrodes of capacitor C11 can be made larger than the sum of the areas of the channel formation regions of transistors M13, M14, M15, M16, and M17.

[0157] Note that since the potential of the node NDB is smaller than that of the node NDA, Figure 10 By not providing the transistor M17 as in the structure shown, the number of transistors can be reduced, thereby achieving miniaturization.

[0158] [Variation Example 3]

[0159] Figure 12 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 12 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 12 The illustrated drive circuit 100 includes transistors M15a and M15b in place of transistor M15. In this case, one of the source and drain of transistor M15b is connected to the gate of transistor M11. The other of the source and drain of transistor M15b is connected to the gate of transistor M15b and one of the source and drain of transistor M15a. The other of the source and drain of transistor M15a is connected to the gate of transistor M15a and one terminal of capacitor C11.

[0160] By adopting this structure, for example, during period T14, the potential of node NDB can be made even lower than the potential of node NDA. Consequently, the voltage applied to each of transistors M11 and M14 can be reduced, thereby suppressing damage and degradation of these transistors. Consequently, reliability can be improved. Furthermore, for example, during period T15, charge is less likely to leak from node NDB to node NDA, making it easier to maintain the potential of node NDB. This stabilizes operation.

[0161] [Variation Example 4]

[0162] Figure 13 It is an explanation Figure 12 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 13The driving circuit 100 shown is Figure 12 The driving circuit 100 shown differs in the connection of the transistor M15b. Here, the gate of the transistor M15b is connected to the gate of the transistor M15a.

[0163] By adopting this structure, for example, a region serving as the gate of the transistor M15a and a region serving as the gate of the transistor M15b can be provided in one conductive layer. Figure 12 Compared with the structure shown, the number of through holes can be reduced and the layout area can be reduced, so miniaturization can be achieved.

[0164] [Variation Example 5]

[0165] Figure 14 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 14 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 14 The driving circuit 100 shown includes a transistor M15p, which is a p-channel transistor, instead of the transistor M15. In this case, the gate of the transistor M15p is connected to one of the source and the drain of the transistor M15p.

[0166] By adopting this structure, for example, p-channel transistors are less likely to leak charge in the off state (or have a smaller off-state current) than n-channel transistors, making it easier to maintain the potential of node NDB. This stabilizes the operation.

[0167] [Variation Example 6]

[0168] Figure 15 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 15 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 15 The driving circuit 100 shown further includes a capacitor C12. In this case, one terminal of the capacitor C12 is connected to the gate of the transistor M11, and the other terminal of the capacitor C12 is connected to one of the source and the drain of the transistor M11.

[0169] With this configuration, for example, during period T13, capacitor C12 functions as a bootstrap capacitor, allowing the potential of node NDB to rise as the potential of wiring OUTL rises. At this time, by increasing the potential of node NDB to a value exceeding "potential H + Vt11," transistor M11 remains on, allowing the potential of wiring OUTL to rise to potential H. This shortens the time it takes for the potential of wiring OUTL to reach potential H, thereby improving operating speed.

[0170] Note that, although not shown, one terminal of capacitor C12 can also be connected to the other of the source and drain of transistor M15 (i.e., node NDA). In this case, for example, during period T13, as the potential of wiring OUTL rises, the potential of node NDA rises to a value exceeding "potential H + Vt11 + Vt15." While transistor M11 remains on, the potential of wiring OUTL can be raised to potential H. Therefore, the time it takes for the potential of wiring OUTL to reach potential H can be shortened, thereby improving operating speed.

[0171] [Variation Example 7]

[0172] Figure 16 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 16 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 16 The driving circuit 100 shown includes a transistor M18 instead of the capacitor C11. In this case, the gate of the transistor M18 is connected to the other of the source and drain of the transistor M15. One of the source and drain of the transistor M18 is connected to the wiring CKL2.

[0173] In addition, the other of the source and the drain of the transistor M18 may be connected to one of the source and the drain of the transistor M18 or an arbitrary wiring (for example, the wiring VL1 or the wiring VL2 ).

[0174] By adopting this structure, for example, a channel is formed in the channel formation region of the transistor M18 during the period T13 to the period T15, so that the gate capacitance of the transistor M18 can be used as a capacitor instead of the capacitor C11. Here, in order to increase the potential rise value ΔV1 corresponding to the node NDA during the period T14, the electrostatic capacitance of the capacitor C11 is preferably large. In order to increase the electrostatic capacitance of the capacitor C11, for example, the layout area of ​​the capacitor C11 can be increased. Alternatively, in order to increase the electrostatic capacitance while suppressing the increase in the layout area of ​​the capacitor C11, for example, a conductive layer can be added to reduce the thickness of the dielectric or a dielectric with a high relative dielectric constant can be used. On the other hand, these methods lead to an increase in process costs. Therefore, by using the gate capacitance of the transistor M18 as a capacitor instead of the capacitor C11 and using the gate insulating film as a dielectric, it is easy to increase the electrostatic capacitance per unit area. Therefore, with Figure 2 Compared with the structure shown in the figure, the layout area can be reduced, thereby achieving miniaturization.

[0175] Furthermore, for example, during periods T11 and T12, a potential L is applied to the gate of transistor M18. At this time, transistor M18 is turned off, and therefore a channel is not formed in the channel formation region of transistor M18. Since a channel is not formed in the channel formation region of transistor M18, the gate capacitance of transistor M18 decreases. Thus, by reducing the gate capacitance of transistor M18, the current required for charging and discharging wiring CKL2 and node NDA can be reduced, or the time required for charging and discharging can be shortened. Consequently, power consumption can be reduced or operating speed can be increased. Furthermore, by reducing the gate capacitance of transistor M18, changes in the potential of node NDA associated with changes in the potential of wiring CKL2 can be suppressed. This prevents malfunctions and stabilizes operation.

[0176] [Variation Example 8]

[0177] Figure 17 It is an explanation Figure 16 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 17 The driving circuit 100 shown is Figure 16 The driving circuit 100 shown is different in the connection of the transistor M18. Here, the gate of the transistor M18 is connected to the wiring CKL2. One of the source and drain of the transistor M18 is connected to one of the source and drain of the transistor M15.

[0178] In addition, the other of the source and the drain of the transistor M18 may be connected to one of the source and the drain of the transistor M18 or an arbitrary wiring (for example, the wiring VL1 or the wiring VL2 ).

[0179] By adopting this structure, Figure 16Similarly to the structure shown, the gate capacitance of the transistor M18 can be used as a capacitor instead of the capacitor C11. Therefore, since the electrostatic capacitance per unit area can be easily increased, miniaturization can be achieved.

[0180] Note that when the gate voltage of the transistor M18 exceeds the threshold voltage, a channel is formed in the channel formation region of the transistor M18, whereby the gate capacitance of the transistor M18 can be used as a capacitor. Figure 16 Connect transistor M18 as shown in the structure or as Figure 17 Alternatively, the transistor M18 may be connected as shown in FIG. Figure 16 transistors connected as shown in the figure and transistor M18 Figure 17 Both transistors are connected as shown in the transistor M18.

[0181] [Variation Example 9]

[0182] Figure 18 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 18 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 18 The driving circuit 100 shown in the figure further includes a transistor M18. In this case, the gate of the transistor M18 is connected to the other of the source and drain of the transistor M15. One of the source and drain of the transistor M18 is connected to the wiring CKL2. In other words, Figure 18 The driving circuit 100 shown is a combination of Figure 2 The driving circuit 100 and Figure 16 The structure of the driving circuit 100 is shown.

[0183] Note that although not shown, it is also possible to Figure 17 The transistor M18 is connected as shown in FIG. Figure 2 The driving circuit 100 and Figure 17 The structure of the driving circuit 100 is shown.

[0184] By adopting this structure, the advantages of the capacitor C11, which easily stabilizes the electrostatic capacitance, and the transistor M18, which easily increases the electrostatic capacitance per unit area, can be achieved. This can achieve stable operation and miniaturization.

[0185] [Variation Example 10]

[0186] Figure 19 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 19 The driving circuit 100 shown is Figure 2 The differences of the driving circuit 100 shown are: Figure 19 The illustrated drive circuit 100 further includes a transistor M18 and a capacitor C11. The gate of transistor M18 is connected to the other of the source and drain of transistor M15. One of the source and drain of transistor M18 is connected to wiring CKL2. The other terminal of capacitor C11 is connected to the other of the source and drain of transistor M18.

[0187] By adopting this structure, for example, transistor M18 is turned on during periods T13 to T15, thereby achieving the effect of changing the potential of node NDA due to capacitive coupling through capacitor C11. In this case, the gate capacitance of transistor M18 is connected in parallel with the electrostatic capacitance of capacitor C11, increasing the electrostatic capacitance. This increases the amount of change in the potential of node NDA due to capacitive coupling, thereby increasing operating speed.

[0188] Furthermore, for example, by turning off transistor M18 during periods T11 and T12, capacitor C11 can be disabled. This reduces the current required to charge and discharge wiring CKL2 and node NDA, or shortens the time required for charging and discharging. This reduces power consumption and increases operating speed. Furthermore, changes in the potential of node NDA associated with changes in the potential of wiring CKL2 can be suppressed. This prevents malfunctions and stabilizes operation.

[0189] [Variation Example 11]

[0190] Figure 20 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 20 The driving circuit 100 shown is Figure 2 The driving circuit 100 shown is different in the connection of the transistor M13. Here, the other of the source and drain of the transistor M13 is connected to one of the source and drain of the transistor M14.

[0191] By adopting this structure, the parasitic capacitance between wiring CKL1 and wiring SPL can be reduced. As will be explained in detail later, for example, when multiple driver circuits 100 are used in the gate driver portion of a display device, wiring SPL of a driver circuit 100 in one row may be connected to wiring OUTL of a driver circuit 100 in the previous row. Therefore, by reducing the parasitic capacitance between wiring CKL1 and wiring SPL, the generation of noise caused by the signal supplied to wiring CKL1 being transmitted to wiring SPL (i.e., wiring OUTL in the previous row) via this parasitic capacitance can be suppressed. This stabilizes operation.

[0192] Furthermore, for example, during period T14, the potential difference between the source and drain of transistor M13 (also referred to as the drain voltage) can be reduced. This can suppress degradation of transistor M13, thereby improving reliability. Furthermore, charge leakage from node NDA through transistor M13 can be reduced, thereby maintaining the potential of node NDA. This can stabilize operation.

[0193] For example, in addition to Figure 20 In addition to the structure shown, Figure 11 The structure shown may also include a transistor M17. In this case, the other of the source and drain of the transistor M13 is connected to one of the source and drain of the transistor M14 and the other of the source and drain of the transistor M17.

[0194] [Variation Example 12]

[0195] Figure 21 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 21 The driving circuit 100 shown is Figure 2 The driving circuit 100 shown is different in the connection of the transistor M14. Here, the other of the source and the drain of the transistor M14 is connected to one of the source and the drain of the transistor M13.

[0196] By adopting this structure, the parasitic capacitance between the wiring CKL1 and the wiring SPL can be reduced. Figure 20 Similarly, in the structure shown, by reducing the parasitic capacitance between the wiring CKL1 and the wiring SPL, the signal supplied to the wiring CKL1 can be prevented from being transmitted to the wiring SPL (ie, the wiring OUTL of the previous row) through the parasitic capacitance and generating noise, thereby stabilizing the operation.

[0197] Furthermore, for example, during periods T14 and T15, the potential difference between the source and drain of transistor M14 can be reduced. This can suppress degradation of transistor M14, thereby improving reliability. Furthermore, charge leakage from node NDB through transistor M14 can be reduced, maintaining the potential of node NDB. This stabilizes operation.

[0198] In addition, for example, Figure 21 In addition to the structure shown, Figure 10 or Figure 11 In this case, the other of the source and drain of the transistor M14 is connected to one of the source and drain of the transistor M13 and the other of the source and drain of the transistor M16.

[0199] [Variation Example 13]

[0200] Figure 22 It is an explanation Figure 2 A circuit of a modified example of the driving circuit 100 shown. Figure 22 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 22 The driving circuit 100 shown further includes a transistor M10. Here, the gate of the transistor M10 is connected to the other of the source and drain of the transistor M15. One of the source and drain of the transistor M10 is connected to one of the source and drain of the transistor M11. The other of the source and drain of the transistor M10 is connected to the other of the source and drain of the transistor M11.

[0201] With this configuration, for example, during periods T13 and T14, the potential of wiring VL1 is supplied to wiring OUTL via transistor M11 and also to wiring OUTL via transistor M10. Therefore, the rising time of the potential of wiring OUTL can be shortened, thereby increasing the operating speed.

[0202] [Variation Example 14]

[0203] Figure 23 It is an explanation Figure 2 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 23 The driving circuit 100 shown is Figure 2 The difference of the driving circuit 100 shown is that Figure 23The illustrated driver circuit 100 includes transistors M12a, M12b, and M12c in place of transistor M12. In this case, one of the source and drain of transistor M12a is connected to one of the source and drain of transistor M11, the gate of transistor M12c, and wiring OUTL. The other of the source and drain of transistor M12a is connected to one of the source and drain of transistor M12b and one of the source and drain of transistor M12c. The gate of transistor M12a and the gate of transistor M12b are connected to node NDC (i.e., terminal OTB of circuit 110). The other of the source and drain of transistor M12b is connected to wiring VL2. The other of the source and drain of transistor M12c is connected to wiring VL1.

[0204] With this structure, when the potential of wiring OUTL is at potential H, transistor M12c is turned on, and the potential of wiring VL1 is supplied to the other of the source and drain of transistor M12a and one of the source and drain of transistor M12b via transistor M12c. At this time, denoting the threshold voltage of transistor M12c as Vt12c, the potentials of the other of the source and drain of transistor M12a and one of the source and drain of transistor M12b are "potential H - Vt12c." Therefore, the potential difference between the source and drain of transistor M12a can be kept below potential H, and the potential difference between the source and drain of transistor M12b can be kept below potential H. This suppresses transistor degradation, thereby improving reliability.

[0205] Furthermore, the potential difference between the source and drain of transistor M12a can be made smaller than potential H, and the potential difference between the source and drain of transistor M12b can be made smaller than potential H. This can increase the value of potential H while suppressing transistor degradation. Thus, by increasing the value of potential H and increasing ΔV1, which corresponds to the potential rise caused by capacitive coupling of capacitor C11, the potentials of nodes NDA and NDB can be increased, thereby increasing the on-state current of transistor M11. This can improve operating speed.

[0206] Furthermore, for example, when both transistors M12a and M12b are in the off state, charge leakage from the wiring OUTL through the transistor M12a can be reduced, thereby maintaining the potential of the wiring OUTL, thereby stabilizing the operation.

[0207] [Variation Example 15]

[0208] Figure 24 It is an explanation Figure 11 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 24 The driving circuit 100 shown is Figure 11The differences of the driving circuit 100 shown are: Figure 24 The driving circuit 100 shown includes a switch S12 instead of the transistor M12, a switch S13 instead of the transistor M13, and a switch S14 instead of the transistor M14. Note that the circuit 110 is omitted.

[0209] As described above, one embodiment of the present invention may have a configuration in which at least a part of the transistors constituting the driver circuit 100 is replaced with other elements serving as switches.

[0210] Note that although not shown, a rectifying element such as a diode may be included instead of transistor M15. In this case, the rectifying element is connected so that current can flow only from one terminal of capacitor C11 (node ​​NDA) to the gate of transistor M11 (node ​​NDB).

[0211] In addition, the modified examples of the driving circuit 100 shown or not shown above can be applied to Figure 1 The driving circuit 100 is shown.

[0212] In addition, two or more of the modified examples of the driving circuit 100 shown or not shown above may be applied to Figure 1 and Figure 2 The driving circuit 100 is shown.

[0213] Furthermore, the driving circuit 100 described above or not shown can solve the problem of providing at least a novel driving circuit simply by adopting the circuit structure.

[0214] <Specific Example of Driving Circuit>

[0215] Next, the circuit 110 will be described.

[0216] The circuit 110 and its modified examples described below can be applied to the driving circuit 100 shown or not shown above.

[0217] Figure 25 It is an explanation Figure 2 , etc. are circuit diagrams of specific configuration examples of the circuit 110 included in the driving circuit 100.

[0218] like Figure 25 As shown, the circuit 110 includes, for example, a transistor M21 , a transistor M22 , a transistor M23 , a transistor M24 , a transistor M25 , a transistor M26 , and a transistor M27 , and may also include a capacitor C22 .

[0219] The gate of transistor M21 is connected to one of the source and drain of transistor M24, one of the source and drain of transistor M25, the gate of transistor M26, and one terminal of capacitor C22. One of the source and drain of transistor M21 is connected to one of the source and drain of transistor M22 and the other terminal of capacitor C22. The other of the source and drain of transistor M22 is connected to one of the source and drain of transistor M23 and the gate of transistor M12 via terminal OTB. One of the source and drain of transistor M26 is connected to one of the source and drain of transistor M27. The other of the source and drain of transistor M26 is connected to one of the source and drain of transistor M13 via terminal OTA. The gate of transistor M23 and the gate of transistor M25 are respectively connected to one of the source and drain of transistor M14. The other of the source and drain of transistor M21 is connected to wiring CKL2. The gate of transistor M22 is connected to wiring CKL2. The other of the source and drain of transistor M23 is connected to wiring VL2. The other of the source and drain of transistor M24 is connected to wiring VL1. The gate of transistor M24 is connected to wiring CKL1. The other of the source and drain of transistor M25 is connected to wiring CKL1. The other of the source and drain of transistor M27 is connected to wiring VL2. The gate of transistor M27 is connected to wiring CKL2. Capacitor C22 may also be a parasitic capacitance between the gate and one of the source and drain of transistor M21.

[0220] A wiring connected to the gate of the transistor M21 and one terminal of the capacitor C22 is sometimes referred to as a node NDD.

[0221] [Work Examples]

[0222] Figure 26 It is an explanation Figure 25 The timing chart of the operation example of the driving circuit 100 is shown. Figures 27 to 32 1 is a circuit diagram illustrating an example of operation of the driving circuit 100. Note that the above Figure 3 Since the description of the operation examples shown in FIG. 1 and FIG. 2 is omitted, the operation of the circuit 110 will be mainly described here.

[0223] exist Figure 26 In the timing diagram shown, except Figure 3 In addition to the timing chart shown, the potential change of the node NDD is also shown.

[0224] Note that sometimes, the threshold voltage of transistor M21 is recorded as Vt21, the threshold voltage of transistor M22 is recorded as Vt22, the threshold voltage of transistor M23 is recorded as Vt23, the threshold voltage of transistor M24 is recorded as Vt24, the threshold voltage of transistor M25 is recorded as Vt25, the threshold voltage of transistor M26 is recorded as Vt26, and the threshold voltage of transistor M27 is recorded as Vt27.

[0225] Immediately before entering period T11, transistors M22, M24, and M27 are all off, while transistors M23 and M25 are both on. Therefore, the potential of node NDD is L, and transistors M21 and M26 are both off. Consequently, transistors M26 and M27 are both off, and terminal OTA is in a high-impedance state. Furthermore, since the potential of wiring VL2 is supplied to terminal OTB via transistor M23, a potential of L is outputted from terminal OTB. Figure 27 Note that in the following description, unless otherwise specified, the previous state is maintained.

[0226] During period T11, transistor M24 is turned on, while transistors M23 and M25 are turned off. Consequently, the potential of node NDD reaches "potential H - Vt24," and transistors M21 and M26 are turned on. Consequently, terminal OTA remains in a high-impedance state, while terminal OTB is in a high-impedance state. Figure 28 The circuit status at this time is shown.

[0227] During period T12, transistor M24 is turned off, while transistors M22 and M27 are both turned on. Consequently, the potential of wiring CKL2 is supplied to terminal OTB via transistors M21 and M22. Furthermore, node NDD becomes floating. At this time, capacitor C22 functions as a bootstrap capacitor, causing the potential of node NDD to rise due to capacitive coupling through capacitor C22. When the potential of node NDD rises by ΔV2, the potential of node NDD becomes "potential H - Vt24 + ΔV2." Furthermore, the potential of wiring VL2 is supplied to terminal OTA via transistors M27 and M26. Consequently, potential L is output to terminal OTA, and "potential H - Vt22" is output to terminal OTB. The "potential H - Vt22" output to terminal OTB is greater than the threshold voltage of transistor M12, turning transistor M12 on. Figure 29 The circuit status at this time is shown.

[0228] During period T13, transistors M23, M24, and M25 are all turned on, while transistors M22 and M27 are both turned off. Consequently, the potential of node NDD reaches "potential H - Vt24." Consequently, transistor M27 is turned off, and terminal OTA enters a high-impedance state. Furthermore, because the potential of wiring VL2 is supplied to terminal OTB via transistor M23, a potential L is outputted from terminal OTB. Figure 30 The circuit status at this time is shown.

[0229] During period T14, transistor M24 is turned off, while transistors M22 and M27 are both turned on. Consequently, the potential of node NDD reaches L, and transistors M21 and M26 are both turned off. Consequently, transistor M26 is turned off, and terminal OTA maintains a high impedance state. Furthermore, since the potential of wiring VL2 is supplied to terminal OTB via transistor M23, the potential L continues to be output to terminal OTB. Figure 31 The circuit status at this time is shown.

[0230] During period T15, transistor M24 is turned on, while transistors M22 and M27 are turned off. At this point, the potential applied to the gate of transistor M25 (i.e., the potential of node NDB) exceeds "potential H + Vt25," causing the potential of node NDD to reach potential H. Consequently, transistors M21 and M26 are both turned on. Consequently, transistor M27 is turned off, and terminal OTA maintains a high impedance state. Furthermore, since the potential of wiring VL2 is supplied to terminal OTB via transistor M23, potential L continues to be output to terminal OTB. Figure 32 The circuit status at this time is shown.

[0231] [Deformation Example 1]

[0232] The driving circuit according to one embodiment of the present invention is not limited to the above-described configuration, and can have various configurations.

[0233] Figure 33 It is an explanation Figure 25 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 33 The driving circuit 100 shown is Figure 25 The difference of the driving circuit 100 shown is that Figure 33The illustrated drive circuit 100 further includes a transistor M28. In this case, the gate of transistor M21 is connected to one of the source and drain of transistor M28 and one terminal of capacitor C22. The other of the source and drain of transistor M28 is connected to one of the source and drain of transistor M24, one of the source and drain of transistor M25, and the gate of transistor M26. The gate of transistor M28 is connected to wiring VL1.

[0234] By adopting such a structure, for example, a large voltage can be prevented from being applied to each of the transistors M24, M25, and M26 during the period T12, thereby suppressing damage and degradation of these transistors.

[0235] [Variation Example 2]

[0236] Figure 34 It is an explanation Figure 33 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 34 The driving circuit 100 shown is Figure 33 The difference of the driving circuit 100 shown is that Figure 34 The driving circuit 100 shown also includes a transistor M16 and a transistor M17. In this case, the other of the source and drain of the transistor M15 is connected to the gate of the transistor M15, one terminal of the capacitor C11, and one of the source and drain of the transistor M16. The other of the source and drain of the transistor M16 is connected to one of the source and drain of the transistor M13 and the other of the source and drain of the transistor M26 via the terminal OTA. The gate of the transistor M16 is connected to the wiring VL1. In addition, the gate of the transistor M11 is connected to one of the source and drain of the transistor M15 and one of the source and drain of the transistor M17. The other of the source and drain of the transistor M17 is connected to one of the source and drain of the transistor M14, the gate of the transistor M23, and the gate of the transistor M25. The gate of the transistor M17 is connected to the wiring VL1. It can also be said that Figure 34 The driving circuit 100 shown is a combination of Figure 11 The driving circuit 100 and Figure 33 The structure of the driving circuit 100 is shown.

[0237] By adopting this structure, for example, a large voltage can be prevented from being applied to each of the transistors M24, M25, and M26 during period T12, thereby suppressing damage and degradation of these transistors. Furthermore, a large voltage can be prevented from being applied to each of the transistors M13 and M26 during period T14, thereby suppressing damage and degradation of these transistors. Furthermore, a large voltage can be prevented from being applied to each of the transistors M14, M23, and M25 during periods T14 and T15, thereby suppressing damage and degradation of these transistors. Consequently, reliability can be improved.

[0238] [Deformation Example 3]

[0239] Figure 35 It is an explanation Figure 25 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 35 The driving circuit 100 shown is Figure 25 The driver circuit 100 shown differs in the connections of transistors M21 and M22. Here, one of the source and drain of transistor M21 is connected to one of the source and drain of transistor M23, the other terminal of capacitor C22, and the gate of transistor M12 via terminal OTB. The other of the source and drain of transistor M21 is connected to one of the source and drain of transistor M22. The other of the source and drain of transistor M22 is connected to wiring CKL2.

[0240] By adopting this structure, it is possible to suppress the generation of noise caused by the signal supplied to the wiring CKL2 being transferred to the terminal OTB via the gate capacitance of the transistor M22, thereby achieving stable operation.

[0241] [Variation Example 4]

[0242] Figure 36 It is an explanation Figure 25 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 36 The driving circuit 100 shown is Figure 25 The driving circuit 100 shown is different in the connection of the transistor M23 and the transistor M25. Here, the gate of the transistor M23 and the gate of the transistor M25 are connected to one of the source and the drain of the transistor M13.

[0243] By adopting this structure, for example, during period T15, the voltage applied to each of transistors M23 and M25 can be reduced, thereby suppressing damage and degradation of these transistors. For example, the period during which the potential applied to the gates of transistors M23 and M25 increases can be shortened, thereby suppressing degradation of the transistors. Consequently, reliability can be improved.

[0244] [Variation Example 5]

[0245] Figure 37 It is an explanation Figure 25 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 37 The driving circuit 100 shown is Figure 25 The driving circuit 100 shown is different in the connection of the transistor M24. Here, the other of the source and the drain of the transistor M24 is connected to the wiring CKL1.

[0246] By adopting this structure, for example, during period T14, the voltage applied to transistor M24 can be reduced, thereby suppressing damage and degradation of the transistor. For example, by changing the potential of the other of the source and drain of transistor M24, the period during which the potential difference between the source and drain becomes large can be shortened, thereby suppressing degradation of the transistor. As a result, reliability can be improved.

[0247] [Variation Example 6]

[0248] Figure 38 It is an explanation Figure 25 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 38 The driving circuit 100 shown is Figure 25 The driving circuit 100 shown in FIG. 1 differs in the connections of transistors M26 and M27. Here, one of the source and drain of transistor M26 is connected to wiring VL2. The other of the source and drain of transistor M26 is connected to one of the source and drain of transistor M27. The other of the source and drain of transistor M27 is connected to one of the source and drain of transistor M13.

[0249] By adopting this structure, the potential changes of the node NDA and the node NDD can be suppressed from influencing each other through the gate capacitance of the transistor M26, thereby stabilizing the operation.

[0250] [Variation Example 7]

[0251] Figure 39 It is an explanation Figure 25 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 39 The driving circuit 100 shown is Figure 25 The driving circuit 100 shown is different in the connection of the transistor M12. Here, the other of the source and the drain of the transistor M12 is connected to the wiring VL3.

[0252] By adopting this structure, for example, by making the potential supplied to wiring VL3 greater than the potential supplied to wiring VL2, the gate voltage of transistor M12 can be reduced to less than 0V during periods T13 to T15, thereby reliably turning off the transistor. This stabilizes operation. Furthermore, by making the potential supplied to wiring VL3 lower than the potential supplied to wiring VL2, for example, the gate voltage of transistor M12 can be increased during period T12, thereby increasing the on-state current. Consequently, the fall time of the potential of wiring OUTL can be shortened, thereby increasing operating speed.

[0253] [Variation Example 8]

[0254] Figure 40 It is an explanation Figure 34 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 40 The driving circuit 100 shown is Figure 34 The differences of the driving circuit 100 shown are: Figure 40 The driving circuit 100 shown includes a switch S13 instead of the transistor M13, a switch S14 instead of the transistor M14, a switch S22 instead of the transistor M22, a switch S23 instead of the transistor M23, a switch S24 instead of the transistor M24, a switch S25 instead of the transistor M25, and a switch S27 instead of the transistor M27.

[0255] As described above, one embodiment of the present invention may have a configuration in which at least a part of the transistors constituting the driver circuit 100 is replaced with other elements serving as switches.

[0256] [Variation Example 9]

[0257] Figure 41 It is an explanation Figure 34 FIG. 1 is a circuit diagram of a modified example of the driving circuit 100 shown in FIG. Figure 41 The driving circuit 100 shown is Figure 34 The difference of the driving circuit 100 shown is that Figure 41 The illustrated driving circuit 100 includes p-channel transistors instead of n-channel transistors.

[0258] Thus, one embodiment of the present invention may have a configuration in which the transistors constituting the driver circuit 100 are replaced with p-channel transistors. In this case, the magnitude relationship of the potentials in the above description may be appropriately modified and referred to during the operation of the driver circuit 100.

[0259] In addition, two or more of the above-mentioned modified examples shown or not shown may be applied to Figure 25 The driving circuit 100 is shown.

[0260] Furthermore, the driving circuit 100 described above or not shown can solve the problem of providing at least a novel driving circuit simply by adopting the circuit structure.

[0261] Furthermore, one embodiment of the present invention includes a configuration in which at least one of the gate, source, and drain of one or more transistors is not connected to any wiring or is connected to any wiring. Furthermore, one embodiment of the present invention includes a configuration in which no input is given to one or more wirings or any signal or potential is given to one or more wirings.

[0262] <Structural Example of Semiconductor Device>

[0263] Next, a semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. At least a portion of a driver circuit according to one embodiment of the present invention can be used in this semiconductor device. Furthermore, at least a portion of this semiconductor device can be used in a display device or the like.

[0264] Figure 42A This is a block diagram illustrating a structural example of a semiconductor device according to one embodiment of the present invention.

[0265] like Figure 42A As shown, semiconductor device 160 includes a pixel portion 162, a gate driver portion 163, and a source driver portion 164. Pixel portion 162 includes, for example, a plurality of pixels 161 arranged in a matrix of m rows and n columns (m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2).

[0266] The pixel 161 may include a functional element. Here, for example, when the functional element is a display element such as a liquid crystal element or a light-emitting element, the semiconductor device 160 is used as a display device (sometimes also referred to as an output device). In addition, for example, when the functional element is a light-receiving element, the semiconductor device 160 is used as an imaging device (sometimes also referred to as an input device). In addition, the pixel 161 may include both a display element and a light-receiving element. In this case, the semiconductor device 160 is used as both a display device and an imaging device (sometimes also referred to as an input-output device).

[0267] exist Figure 42A , the pixel 161 arranged in the first row and first column is denoted as pixel 161[1,1], the pixel 161 arranged in the first row and nth column is denoted as pixel 161[1,n], the pixel 161 arranged in the mth row and first column is denoted as pixel 161[m,1], and the pixel 161 arranged in the mth row and nth column is denoted as pixel 161[m,n]. Note that the pixel 161 arranged in the uth row and vth column (u is an integer from 1 to m, and v is an integer from 1 to n) is sometimes denoted as pixel 161[u,v]. Note that when describing the common content of multiple pixels 161, identification symbols such as "[u,v]" are sometimes not added.

[0268] The semiconductor device 160 includes m gate lines 165 arranged in parallel with each other, and the potentials of these m gate lines 165 are controlled by a circuit included in the gate driver unit 163. The potential of one gate line 165 is supplied to n pixels 161 arranged in the row direction. Note that one gate line 165 may include multiple wirings depending on the structure of the pixel 161.

[0269] The semiconductor device 160 also includes n source lines 166 arranged in parallel with each other, and the potentials of these n gate lines 166 are controlled by a circuit included in the source driver section 164. The potential of one source line 166 is supplied to m pixels 161 arranged in the column direction. Note that one source line 166 may include multiple wirings depending on the structure of the pixel 161.

[0270] The circuit in the gate driver portion 163 is used as, for example, a scan line driver circuit (also sometimes referred to as a gate line driver circuit, a gate driver, a scan driver, or a row driver).

[0271] The circuit in the source driver section 164 is used as, for example, a signal line driver circuit (sometimes also referred to as a source line driver circuit, a source driver, a data driver, or a column driver).

[0272] Figure 42B It is a block diagram illustrating a modified example of the semiconductor device 160 . Figure 42B The semiconductor device 160 is shown with Figure 42A The semiconductor device 160 shown is different in that it includes two gate driver units 163 arranged opposite to each other with a pixel unit 162 interposed therebetween. Figure 42B In the structure shown, the potentials of m gate lines 165 are controlled by two gate driver units 163. By adopting this structure, for example, the actual wiring load (parasitic capacitance and parasitic resistance) can be reduced to Figure 42A The load of the wiring of the semiconductor device 160 is reduced to one fourth of that shown. As a result, for example, a display device using the semiconductor device 160 can achieve higher speed, higher definition, higher resolution, narrower frame, and larger screen.

[0273] In one embodiment of the present invention, various transistors can be used as transistors constituting the semiconductor device 160. For example, a Si transistor, an OS transistor, or both a Si transistor and an OS transistor can be used.

[0274] OS transistors can be freely arranged on a silicon substrate provided with Si transistors, for example, and thus can be easily integrated. In addition, OS transistors can be manufactured using the same manufacturing equipment as Si transistors, allowing for low-cost manufacturing.

[0275] Therefore, in the semiconductor device 160, for example, Si transistors including a portion of a silicon substrate may be used as transistors constituting the source driver portion 164, and OS transistors provided on the silicon substrate may be used as transistors constituting the gate driver portion 163 and the pixel portion 162. Alternatively, OS transistors may be used as at least a portion of the transistors constituting the source driver portion 164, and Si transistors may be used as at least a portion of the transistors constituting the gate driver portion 163 and the pixel portion 162.

[0276] Furthermore, Si transistors comprising a portion of the silicon substrate may be used to provide various circuits (which may also include arithmetic circuits and memory circuits) for controlling the operation of the semiconductor device 160. Therefore, one embodiment of the present invention may employ a structure in which, for example, an OS transistor is provided on a silicon substrate on which the Si transistor is provided, and a display element or a light-receiving element is provided on the layer on which the OS transistor is provided.

[0277] In one embodiment of the present invention, the gate driver unit 163 may use at least a portion of the aforementioned drive circuit 100 .

[0278] [Example of Gate Driver Section Configuration]

[0279] Figure 43A 16 is a circuit diagram illustrating an example of how a plurality of drive circuits 100 are connected to each other in the gate driver unit 163 . Figure 43B 1 is a circuit block corresponding to the driving circuit 100 .

[0280] In order to drive the pixels 161 arranged in a matrix of m rows and n columns row by row, the gate driver unit 163 includes at least m driving circuits 100 (driving circuit 100[1] to driving circuit 100[m]). Figure 43A Typically, the circuit blocks in FIG. 1 show the driver circuit 100[u-1] in the u-1th row, the driver circuit 100[u] in the u-th row, and the driver circuit 100[u+1] in the u+1th row. Furthermore, when describing common features of the m driver circuits 100, identifying symbols such as "[u]" may not be added.

[0281] The wiring SPL (wiring SPL[u]) of the driver circuit 100 (driver circuit 100[u]) in the u-th row is connected to the wiring OUTL (wiring OUTL[u-1]) of the driver circuit 100 (driver circuit 100[u-1]) in the u-1th row. The wiring OUTL (wiring OUTL[u]) of the driver circuit 100 (driver circuit 100[u]) in the u-th row is connected to the wiring SPL (wiring SPL[u+1]) of the driver circuit 100 (driver circuit 100[u+1]) in the u+1th row. The wiring CKL2 of the driver circuit 100 (driver circuit 100[u-1]) in the u-1th row, the wiring CKL1 of the driver circuit 100 (driver circuit 100[u]) in the u-th row, and the wiring CKL2 of the driver circuit 100 (driver circuit 100[u+1]) in the u+1th row are all connected to the wiring CKL_1. The wiring CKL1 of the driver circuit 100 in the u-1th row (driver circuit 100[u-1]), the wiring CKL2 of the driver circuit 100 in the uth row (driver circuit 100[u]), and the wiring CKL1 of the driver circuit 100 in the u+1th row (driver circuit 100[u+1]) are all connected to the wiring CKL_2.

[0282] By adopting such a structure, the gate driver section 163 can sequentially supply signals to each of the m wirings OUTL (wiring OUTL[1] to wiring OUTL[m]).

[0283] [Structure example of pixel portion]

[0284] Figure 43C 16 is a circuit diagram illustrating a pixel 161A using a light-emitting element LD as a functional element as an example of the pixel 161 included in the semiconductor device 160 .

[0285] Figure 43C Typically, the pixel 161A[u,v] in the u-th row and the v-th column and the driving circuit 100[u] in the u-th row are shown.

[0286] Pixel 161A[u,v] includes a transistor M31, a transistor M32, a transistor M33, and a light-emitting element LD. One of the source and drain of transistor M33 is connected to one terminal of light-emitting element LD. The other of the source and drain of transistor M33 is connected to one of the source and drain of transistor M32. The gate of transistor M33 is connected to wiring GLb[u] corresponding to gate line 165. The other terminal of light-emitting element LD is connected to wiring CATH. The other of the source and drain of transistor M32 is connected to wiring ANO. The gate of transistor M32 is connected to a wiring supplied with a potential corresponding to the potential of one of the source and drain of transistor M31. The other of the source and drain of transistor M31 is connected to wiring SL[v] corresponding to source line 166. The gate of transistor M31 is connected to wiring GLa[u] corresponding to gate line 165.

[0287] The wiring OUTL[u] is connected to the wiring GLb[u], for example. Note that although not shown, the wiring OUTL[u] may also be connected to the wiring GLa[u], for example.

[0288] The light emitting element LD emits light with a light emission intensity corresponding to the amount of current flowing through the light emitting element LD. As the light emitting element LD, for example, an organic EL element can be used.

[0289] Transistor M32 can vary its drain current depending on the potential supplied to its gate. Therefore, in pixel 161A[u, v], transistor M32 controls the amount of current flowing through light-emitting element LD. In other words, transistor M32 controls the luminous intensity of light-emitting element LD. In this specification and other documents, a transistor having a function similar to transistor M32 is sometimes referred to as a drive transistor.

[0290] The transistor M31 is used as a switch to control whether or not a data potential is written to the pixel 161A[u,v]. The transistor M33 is used as a switch to control whether or not a current flows through the light emitting element LD.

[0291] Note that although not shown in the figure, the following structure can also be adopted: one of the source and drain of the transistor M32 is connected to one terminal of the light-emitting element LD, the other of the source and drain of the transistor M32 is connected to one of the source and drain of the transistor M33, and the other of the source and drain of the transistor M33 is connected to the wiring ANO.

[0292] Although not shown, the pixel 161A[u,v] may further include a transistor, thereby providing, for example, a function of correcting variations in the threshold voltage of the driving transistor.

[0293] In one embodiment of the present invention, various transistors can be used as transistors constituting the pixel 161A[u,v]. For example, an OS transistor can be used.

[0294] OS transistors have a characteristic of extremely low off-state current. Therefore, for example, it is preferable to use OS transistors as transistors used as switches in pixel 161A. This can reduce the frequency of data rewriting, thereby reducing power consumption.

[0295] Note that one embodiment of the present invention is not limited to the structural examples and working examples described in this embodiment. The contents described in this embodiment can be appropriately combined and implemented. In addition, the contents described in this embodiment can be appropriately combined and implemented with the contents described in other embodiments.

[0296] Implementation Method 2

[0297] In this embodiment, a transistor which is one embodiment of the present invention is described. At least part of the transistor described in this embodiment can be applied to the driver circuit and semiconductor device described in Embodiment 1 above, for example.

[0298] <Transistor Structure Example 1>

[0299] Figure 44A is a top view of transistor 200A. Figure 44B It is along Figure 44A A cross-sectional view along the dot-dash line A1-A2 in FIG. Figure 44C It is along Figure 44A The cross-section of the dotted line A3-A4 in FIG. Figure 44A In the top view of FIG, some components are omitted for clarity. Sometimes, some components are also omitted in other top views.

[0300] The transistor 200A includes an insulating layer 202 over a substrate 201, and a semiconductor layer 203 over the insulating layer 202. Furthermore, an insulating layer 204 is provided over the insulating layer 202 and the semiconductor layer 203. Furthermore, a conductive layer 205 is provided over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have a region that overlaps with each other via the insulating layer 204.

[0301] The semiconductor layer 203 includes a region 203a serving as one of the source and drain regions of the transistor 200A, a channel formation region 203b, and a region 203c serving as the other of the source and drain regions. In the semiconductor layer 203, the region overlapping with the conductive layer 205 serves as the channel formation region 203b. Therefore, the conductive layer 205 serves as the gate electrode of the transistor 200A. Furthermore, the insulating layer 204 serves as the gate insulating film of the transistor 200A.

[0302] In the semiconductor layer 203, the length of the channel formation region 203b in the X direction (equivalent to the distance between the region 203a and the region 203c in the channel formation region 203b) is the channel length Lch of the transistor 200A (see FIG. Figure 44A and Figure 44B ). In addition, in the semiconductor layer 203, the length of the channel formation region 203b in the Y direction (equivalent to the length of the portion of the channel formation region 203b where the region 203a and the region 203c face each other) is the channel width Wch of the transistor 200A (see Figure 44A and Figure 44C ).

[0303] Furthermore, an insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. Furthermore, an opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203a of the semiconductor layer 203. Furthermore, an opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203c of the semiconductor layer 203.

[0304] Furthermore, a conductive layer 208a is provided on the insulating layer 206 and within the opening 207a, and a conductive layer 208b is provided on the insulating layer 206 and within the opening 207b. The conductive layer 208a is in contact with the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Furthermore, the conductive layer 208b is in contact with the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a serves as one of the source and drain electrodes of the transistor 200A, and the conductive layer 208b serves as the other of the source and drain electrodes of the transistor 200A.

[0305] Furthermore, an insulating layer 209 is provided over the insulating layer 206 and the conductive layer 208 (the conductive layer 208 a and the conductive layer 208 b ).

[0306] <Transistor Structure Example 2>

[0307] Figure 45A 2 is a top view of transistor 200B. Transistor 200B is a modified example of transistor 200A. Therefore, to avoid duplication of description, transistor 200B will be mainly described with respect to the differences between transistor 200A and transistor 200B.

[0308] Figure 45B It is along Figure 45A A cross-sectional view along the dot-dash line A1-A2 in FIG. Figure 45C It is along Figure 45A A cross-sectional view along the dot-dash line A3-A4 in FIG.

[0309] The difference between transistor 200B and transistor 200A is that a conductive layer 219 is included between substrate 201 and insulating layer 202. Conductive layer 219 overlaps with channel formation region 203b via insulating layer 202. Therefore, insulating layer 202 is used as a back gate insulating film of transistor 200B, and conductive layer 219 is used as a back gate electrode of transistor 200B. In addition, the thickness of insulating layer 202 can be different or uniform between the area overlapping with conductive layer 219 and the area not overlapping with conductive layer 219. In addition, conductive layer 219 can also extend across the end of channel formation region 203b. In addition, although not shown, an insulating layer can also be provided between substrate 201 and conductive layer 219.

[0310] Here, in a transistor including a back gate, the gate and back gate of the transistor are arranged so as to sandwich the channel formation region of the semiconductor layer. The back gate can have the same function as the gate. When the gate is used to control the on and off states of the transistor, the potential of the back gate can be the same as the potential of the gate. Alternatively, any potential can be used.

[0311] For example, when turning on a transistor, applying the potential that turns on the transistor to both the gate and back gate can further increase the on-state current compared to applying the potential to only one of them. For example, by connecting the gate and back gate, the gate and back gate can always be kept at the same potential. Furthermore, by controlling the back gate potential independently of the gate, the threshold voltage of the transistor can be adjusted.

[0312] Alternatively, a constant potential such as a ground potential may be supplied to the back gate. Since the gate and the back gate are formed by a conductive layer or the like, by using the gate and the back gate to clamp the channel formation region of the semiconductor layer, the electric field generated outside the transistor is not easily applied to the channel formation region (also referred to as "electric field shielding effect"). Therefore, by providing a back gate in the transistor, the transistor can be operated stably. In addition, by providing a back gate in the transistor, the unevenness of characteristics between multiple transistors is reduced. By providing a back gate in the transistor, the reliability of the transistor can be improved. Therefore, the reliability of the semiconductor device including the transistor can be improved. Note that although the electric field shielding effect can be obtained when one or both of the gate and the back gate are in an electrically floating state (also referred to as a "floating state"), this effect can be improved by supplying a potential to the gate and the back gate.

[0313] <Transistor Structure Example 3>

[0314] Figure 46A is a top view of transistor 200C. Figure 46B It is along Figure 46AA cross-sectional view along the dot-dash line A1-A2 in FIG.

[0315] In the transistor 200C, an insulating layer 202 is provided over a substrate 201, and a conductive layer 255 is provided over the insulating layer 202. Furthermore, an insulating layer 257 is provided over the conductive layer 255, an insulating layer 258 is provided over the insulating layer 257, and an insulating layer 259 is provided over the insulating layer 258. In this specification and other documents, the insulating layer 257, the insulating layer 258, and the insulating layer 259 are sometimes collectively referred to as an insulating layer 256 or a spacer layer. Furthermore, a conductive layer 261 is provided over the insulating layer 259.

[0316] An opening 262 is provided in the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 in a region overlapping a portion of the conductive layer 255. A semiconductor layer 263 is provided in contact with an inner wall of the opening 262.

[0317] Furthermore, semiconductor layer 263 has a region overlapping with the bottom of opening 262 and a region overlapping with the inner wall of opening 262. In other words, semiconductor layer 263 has a region in contact with insulating layer 256 in opening 262. Furthermore, semiconductor layer 263 has a region in contact with conductive layer 255 and a region in contact with conductive layer 261 in opening 262.

[0318] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0319] Insulating layer 264 and conductive layer 265 both have regions overlapping opening 262. In opening 262, semiconductor layer 263 has a region overlapping conductive layer 265 with insulating layer 264 interposed therebetween and a region overlapping the inner wall of opening 262 (side surface of insulating layer 256).

[0320] Furthermore, an insulating layer 266 is included on the insulating layer 264. The top surface of the insulating layer 266 is preferably flat. Alternatively, the top surface height (position in the Z direction) of the insulating layer 266 and the conductive layer 265 may be aligned. For example, the flatness of the top surface of the insulating layer 266 can be improved by performing a chemical mechanical polishing (CMP) process. Furthermore, by performing a CMP process, the top surface height of the insulating layer 266 and the conductive layer 265 can be aligned. CMP can reduce surface irregularities on the sample, thereby improving coverage of the insulating layer and conductive layer to be formed later.

[0321] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 preferably use a conductive material that converts the oxide semiconductor to an n-type state. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Furthermore, another conductive material may be provided so as to overlap with the nitrogen-containing conductive material.

[0322] When an oxide semiconductor is used as the semiconductor layer 263, an insulating material containing oxygen and having reduced hydrogen is preferably used as the insulating layer 258. For example, a material containing silicon and oxygen may also be used. Specifically, silicon oxide or silicon oxynitride may be used. Hydrogen is an impurity element in an oxide semiconductor, so when the semiconductor layer 263 of the oxide semiconductor is in contact with the insulating layer 258 containing reduced hydrogen, the semiconductor layer 263 is not easily converted to an n-type. In addition, when the semiconductor layer 263 of the oxide semiconductor is in contact with the insulating layer 258 containing oxygen, the oxygen vacancies in the semiconductor layer 263 are reduced, the characteristics of the transistor are stabilized, and the reliability is improved.

[0323] When an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 may also contain excess oxygen. In this specification, excess oxygen refers to oxygen released by heating. A material from which oxygen is released by heating refers to a material in which the amount of oxygen released, calculated as oxygen atoms, is 1.0×10 18 atoms / cm 3 above, preferably 1.0×10 19 atoms / cm 3 More than 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0324] In addition, when a material containing excess oxygen is used for the insulating layer 258, a material that is not easily permeable to oxygen is preferably used for the insulating layer 257 and the insulating layer 259. As a material that is not easily permeable to oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material that is not easily permeable to oxygen for the insulating layer 257 and the insulating layer 259, excess oxygen contained in the insulating layer 258 is not easily separated from the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure can be adopted in which an insulating layer containing silicon and oxygen (insulating layer 258) is included between two insulating layers containing silicon and nitrogen (insulating layer 257, insulating layer 259).

[0325] Furthermore, when an oxide semiconductor is used as the semiconductor layer 263, a material containing hydrogen can also be used as the insulating layer 257 and the insulating layer 259. As a result, hydrogen is supplied to the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259, and each region in the semiconductor layer 263 becomes n-type. Consequently, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of the source region and the drain region. Furthermore, the region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0326] Conductive layer 261 is used as one of the source electrode and drain electrode of transistor 200C. Conductive layer 255 is used as the other of the source electrode and drain electrode of transistor 200C. In other words, transistor 200C is a transistor in which the source electrode and drain electrode are arranged in the Z direction. In other words, the source electrode and drain electrode of transistor 200C are arranged at different heights. In other words, the source electrode and drain electrode of transistor 200C are arranged at different positions in the Z direction. This type of transistor is also called a "vertical channel transistor", "vertical channel transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)".

[0327] In the above structure, in the VFET transistor 200C, the length of the side surface of the insulating layer 258 when viewed in the X direction or the Y direction is the channel length Lch (here, the channel length L1) of the transistor 200C (see Figure 46B ). Therefore, the channel length Lch of the transistor 200C is determined by the thickness t1 of the insulating layer 258.

[0328] Alternatively, insulating layer 257 and insulating layer 259 may be made of a material that contains no hydrogen or very little hydrogen. For example, silicon nitride or silicon oxynitride containing very little hydrogen may be used. In this case, the region of semiconductor layer 263 in contact with insulating layer 257 and the region of semiconductor layer 263 in contact with insulating layer 259 are not converted to n-type. Therefore, the region of semiconductor layer 263 in contact with conductive layer 261 serves as one of the source and drain regions. Furthermore, the region of semiconductor layer 263 in contact with conductive layer 255 serves as the other of the source and drain regions. Furthermore, the region of semiconductor layer 263 in contact with insulating layer 258 serves as a channel formation region.

[0329] In this case, the total length of the side surfaces of insulating layer 257, insulating layer 258, and insulating layer 259 when viewed in the X direction or the Y direction is the channel length Lch (here, channel length L2) of transistor 200C. Therefore, the channel length Lch of transistor 200C is determined by the total thickness t2 of insulating layer 257, insulating layer 258, and insulating layer 259. In this way, transistor 200C has a channel formation region along the side surfaces of insulating layer 256.

[0330] Since the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 when viewed from the Z direction is equal to the channel width Wch of the transistor 200C (see FIG. Figure 46A ). As the perimeter, for example, the perimeter at a position half the thickness t1 or half the thickness t2 of the insulating layer 258 can be obtained. Note that, as needed, the perimeter at any position of the opening 262 can also be set as the channel width Wch. For example, the perimeter at the bottom of the opening 262 can also be set as the channel width Wch, or the perimeter at the top of the opening 262 can also be set as the channel width Wch. In addition, Figure 46A , the outline (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle, but the present invention is not limited to this. For example, the outline of the opening 262 when viewed from the Z direction may be an ellipse or a rectangle.

[0331] The channel length Lch of the transistor 200C is preferably at least smaller than the channel width Wch of the transistor 200C. The channel length Lch may be, for example, 0.1 to 0.99 times the channel width Wch, and preferably 0.5 to 0.8 times.

[0332] Furthermore, in order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed in the opening 262, the taper angle θ of the inner wall of the opening 262, i.e., the taper angle θ of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, can be set to be greater than 45 degrees and less than 90 degrees, more preferably greater than 50 degrees and less than 75 degrees. The taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface of the layer and the side surface (see Figure 46B ).

[0333] Compared to transistors (also called planar transistors) in which the channel formation region, source region, and drain region are arranged separately on the XY plane, vertical transistors can reduce the area occupied by the device. Furthermore, the use of vertical transistors in semiconductor devices can reduce the area occupied by the device. The use of vertical transistors in semiconductor devices can achieve high integration of semiconductor devices.

[0334] In addition, the channel length of the planar transistor is limited by the exposure limit of the photolithography, making it difficult to further miniaturize. On the other hand, in a vertical transistor, the channel length can be set according to the thickness of the insulating layer 256 or the insulating layer 258. Therefore, the channel length of the transistor can be set to be very fine, that is, below the exposure limit of the photolithography (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm or below 10nm, and above 1nm or above 5nm). As a result, the on-state current of the transistor 200C increases, thereby improving the frequency characteristics. By adopting a vertical transistor, a semiconductor device with a fast operating speed can be provided.

[0335] <Transistor Structure Example 4>

[0336] Figure 47A is a top view of transistor 200D. Figure 47B It is along Figure 47A A cross-sectional view along the dot-dash line A1-A2 in FIG. Figure 47C It is along Figure 47A The cross-sectional view of the dotted line A3-A4 in FIG. Note that Figure 47B is a cross-sectional view of the transistor 200D in the channel length direction. Figure 47C It is a cross-sectional view of the transistor 200D in the channel width direction.

[0337] like Figures 47A to 47CAs shown, the transistor 200D includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, a conductive layer 542a and a conductive layer 542b disposed separately on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b with an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, the insulating layer 580, and the insulating layer 550. Here, as shown in FIG. Figure 47B and Figure 47C As shown, the height of the top surface of the conductive layer 560 is consistent with the height of the top surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. In the following, the semiconductor layers 520a, 520b, and 520c are sometimes collectively referred to as the semiconductor layer 520. In addition, the conductive layers 542a and 542b are sometimes collectively referred to as the conductive layer 542.

[0338] like Figures 47A to 47C As shown, the insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layers 542a and 542b, and the insulating layer 580. The insulating layer 554 has a region in contact with the top surface and side surfaces of the conductive layer 542a, the top surface and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layers 520a and 520b, and the top surface of the insulating layer 524.

[0339] The conductive layer 542a serves as one of the source and drain electrodes of the transistor 200D. The conductive layer 542b serves as the other of the source and drain electrodes of the transistor 200D. The region of the semiconductor layer 520 that overlaps with the conductive layer 560 serves as a channel formation region of the transistor 200D. Thus, the conductive layer 560 serves as the gate electrode of the transistor 200D. Furthermore, the insulating layer 550 serves as a gate insulating film for the transistor 200D.

[0340] Here, the channel formation region of the transistor 200D is formed between a region used as one of the source region and the drain region and a region used as the other of the source region and the drain region in the semiconductor layer 520. Therefore, the distance between the conductive layer 542a and the conductive layer 542b can be set to the channel length Lch of the transistor 200D (see Figure 47A and Figure 47B ). In addition, the length of the portion where the conductive layer 542a and the conductive layer 542b face each other can be set to the channel width Wch of the transistor 200D (see Figure 47A and Figure 47C ).

[0341] Note that in the transistor 200D, three layers of semiconductor layer 520a, semiconductor layer 520b, and semiconductor layer 520c are stacked in and near the channel formation region, but the structure is not limited to this. For example, a two-layer structure of semiconductor layer 520b and semiconductor layer 520c or a stacked structure of four or more layers may be employed. Furthermore, semiconductor layer 520a, semiconductor layer 520b, and semiconductor layer 520c may each have a stacked structure of two or more layers.

[0342] For example, in the case of using an oxide semiconductor that is one of the metal oxides as the semiconductor layer 520, when the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide may have the same composition as that of the semiconductor layer 520b, and the second metal oxide may have the same composition as that of the semiconductor layer 520a.

[0343] The conductive layer 560 is formed so as to be embedded in the opening formed in the insulating layer 580 and in the region sandwiched between the conductive layer 542a and the conductive layer 542b. Here, the conductive layer 560, the conductive layer 542a, and the conductive layer 542b are arranged in a self-aligned manner relative to the opening formed in the insulating layer 580. That is, in the transistor 200D, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductive layer 560 can be formed without providing room for position alignment, so that the area occupied by the transistor 200D can be reduced. As a result, the area occupied by the semiconductor device can be reduced. Furthermore, the integration density of the semiconductor device can be increased.

[0344] like Figures 47A to 47C As shown, conductive layer 560 includes conductive layer 560a disposed on insulating layer 550 and conductive layer 560b disposed on conductive layer 560a, inside the opening formed in insulating layer 580. Insulating layer 550 and conductive layer 560 are disposed so as to be embedded inside the opening formed in insulating layer 580. Furthermore, in transistor 200D, conductive layer 560 has a two-layer stacked structure, but this is not limiting. For example, conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0345] The transistor 200D includes an insulating layer 202 disposed on a substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. Furthermore, a semiconductor layer 520a is disposed on the insulating layer 524.

[0346] Furthermore, an insulating layer 574 and an insulating layer 581 serving as interlayer films are provided over the transistor 200D. The insulating layer 574 is provided in contact with the top surfaces of the conductive layer 560 , the insulating layer 550 , the semiconductor layer 520 c , and the insulating layer 580 .

[0347] When an oxide semiconductor is used as the semiconductor layer 520, an insulating layer having a function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules) may be used as the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 may be used as the insulating layer 522, the insulating layer 554, and the insulating layer 574. In addition, an insulating layer having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) may be used as the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 may be used as the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, silicon nitride, silicon oxynitride, or the like may be used as the insulating layer 522, the insulating layer 554, and the insulating layer 574.

[0348] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated from the upper layer of the insulating layer 574 and the lower layer of the insulating layer 522 by the insulating layer 522 and the insulating layer 574, respectively. Thus, impurities such as hydrogen and excess oxygen contained in the upper layer of the insulating layer 574 and the lower layer of the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0349] Figure 47B An example is shown in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) is provided to be connected to the transistor 200D and to function as a plug. Furthermore, an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided to contact the side surfaces of the conductive layer 545 functioning as a plug. Specifically, the insulating layers 541a and 541b are provided to contact the inner walls of the two openings formed in the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. Figure 47B In the embodiment, a first conductive layer of the conductive layer 545 is provided in contact with a side surface of the insulating layer 541 , and a second conductive layer of the conductive layer 545 is provided inside the first conductive layer of the conductive layer 545 .

[0350] Here, the height of the top surface of the conductive layer 545 can be substantially the same as the height of the top surface of the insulating layer 581. Furthermore, the transistor 200D shows a structure in which a first conductive layer 545 and a second conductive layer 545 are stacked, but the present invention is not limited thereto. For example, the conductive layer 545 may have a single-layer structure or a stacked structure of three or more layers.

[0351] Furthermore, the thickness of the region of the semiconductor layer 520b that does not overlap with the conductive layer 542 is sometimes thinner than the thickness of the region that overlaps with the conductive layer 542. This thin region is formed by removing a portion of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that becomes the conductive layer 542 is deposited on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this case, by removing this low-resistance region between the conductive layers 542a and 542b in the semiconductor layer 520b, the formation of a channel in this region can be suppressed.

[0352] Next, the detailed structure of the transistor 200D will be described.

[0353] The conductive layer 505 is arranged so as to have a region overlapping with the conductive layer 560 via the semiconductor layer 520. In addition, by providing the conductive layer 505 so as to be embedded in the insulating layer 516, the unevenness of the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, thereby improving coverage with layers formed in subsequent steps.

[0354] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided so as to contact the bottom and inner wall of the opening provided in the insulating layer 516. The conductive layer 505b is provided so as to be embedded in the recess formed in the conductive layer 505a. Here, the height of the top surface of the conductive layer 505b is lower than the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. The conductive layer 505c is provided so as to contact the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. Here, the height of the top surface of the conductive layer 505c is the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layer 505a and the conductive layer 505c.

[0355] When an oxide semiconductor is used as the semiconductor layer 520, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (such as NO, NO, or NO), or copper atoms may be used as the conductive layers 505a and 505c. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) may be used.

[0356] By using a conductive material that has the function of inhibiting the diffusion of hydrogen as the conductive layer 505a and the conductive layer 505c, it is possible to prevent impurities such as hydrogen contained in the conductive layer 505b from diffusing into the semiconductor layer 520 through the insulating layer 524 and the like. In addition, by using a conductive material that has the function of inhibiting the diffusion of oxygen as the conductive layer 505a and the conductive layer 505c, it is possible to prevent the conductive layer 505b from being oxidized and having its conductivity reduced. As conductive materials that have the function of inhibiting the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. can be used. Thus, the conductive layer 505a can be a single layer or a stack of these conductive materials. For example, titanium nitride can be used as the conductive layer 505a.

[0357] Alternatively, the conductive layer 505b can be formed using a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten can be used for the conductive layer 505b.

[0358] When the conductive layer 560 is used as a gate electrode, the conductive layer 505 is used as a back gate electrode. In addition, the insulating layer 522 and the insulating layer 524 are used as a back gate insulating film.

[0359] Note that the conductive layer 505 can also be used as a gate electrode. In this case, the conductive layer 560 serves as a back gate electrode. In addition, the insulating layers 522 and 524 serve as gate insulating films, and the insulating layer 550 serves as a back gate insulating film.

[0360] The conductive layer 505 may be larger than the channel formation region in the semiconductor layer 520. In particular, as Figure 47C As shown, the conductive layer 505 may extend to a region outside the end portion intersecting the channel width direction of the semiconductor layer 520. That is, outside the side surface of the semiconductor layer 520 in the channel width direction, the conductive layer 505 and the conductive layer 560 may overlap with the insulating layer interposed therebetween.

[0361] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 serving as the gate electrode and the electric field of the conductive layer 505 serving as the back gate electrode.

[0362] The conductive layer 505 may extend over the end portion of the semiconductor layer 520 to function as a wiring. However, the present invention is not limited thereto, and a conductive layer functioning as a wiring may be provided under the conductive layer 505.

[0363] The insulating layer 514 can be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the transistor 200D from the substrate side. Therefore, the insulating layer 514 can be formed using an insulating material that has a function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrous oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., it does not easily allow impurities to pass through). Alternatively, an insulating material that has a function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., it does not easily allow oxygen to pass through) can be used.

[0364] For example, aluminum oxide or silicon nitride can be used as the insulating layer 514. This can suppress diffusion of impurities such as water and hydrogen from the substrate side relative to the insulating layer 514 to the transistor 200D side. Alternatively, diffusion of oxygen contained in the insulating layer 524 or the like to the substrate side relative to the insulating layer 514 can be suppressed.

[0365] As the insulating layer 516, the insulating layer 580, and the insulating layer 581 serving as the interlayer film, an insulating material having a lower dielectric constant than the insulating layer 514 can be used. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulating layer 516, the insulating layer 580, and the insulating layer 581, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used.

[0366] Here, the insulating layer 524 in contact with the semiconductor layer 520 may contain excess oxygen. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 can be reduced, thereby improving the reliability of the transistor 200D.

[0367] like Figure 47C As shown, the thickness of the region of the insulating layer 524 that does not overlap with the insulating layer 554 or the semiconductor layer 520b may be thinner than that of other regions. The thickness of the region of the insulating layer 524 that does not overlap with the insulating layer 554 or the semiconductor layer 520b may be thick enough to diffuse the oxygen.

[0368] As with the insulating layer 514 and the like, a material that functions as a barrier insulating film to prevent impurities such as water and hydrogen from entering the transistor 200D from the substrate side can be used for the insulating layer 522. For example, a material having lower hydrogen permeability than that of the insulating layer 524 can be used for the insulating layer 522. By surrounding the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water and hydrogen can be prevented from entering the transistor 200D from the outside.

[0369] Furthermore, a material that has a function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., a material that does not readily allow oxygen to permeate) can be used as the insulating layer 522. For example, a material having lower oxygen permeability than the insulating layer 524 can be used as the insulating layer 522. By providing the insulating layer 522 with a function of inhibiting the diffusion of oxygen, the amount of oxygen that diffuses from the semiconductor layer 520 to the substrate side can be reduced. Furthermore, the reaction between the conductive layer 505 and oxygen contained in the insulating layer 524 or the semiconductor layer 520 can be suppressed.

[0370] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, can be used as the insulating layer 522. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 serves as a layer that prevents oxygen from being released from the semiconductor layer 520 and impurities such as hydrogen from entering the semiconductor layer 520 from the surrounding area of ​​the transistor 200D.

[0371] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulating layer. Alternatively, the insulating layer may be nitrided. Furthermore, a structure in which the insulating layer, silicon oxide, silicon oxynitride, or silicon nitride are stacked may be employed. For example, the insulating layer 522 may comprise a three-layer structure of silicon nitride, silicon oxide, and aluminum oxide stacked in this order.

[0372] As the insulating layer 522, for example, an insulating layer containing a material with a high relative dielectric constant (high-k) (such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST)) can also be used in a single layer or a stacked layer. With the miniaturization and high integration of transistors, problems such as gate leakage current sometimes occur due to the thinning of the gate insulating film. By using a material with a high relative dielectric constant as the insulating layer used as the gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0373] In addition, the insulating layer 522 and the insulating layer 574 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being made of the same material, and may be a stacked structure made of different materials.

[0374] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. When the semiconductor layer 520a is provided below the semiconductor layer 520b, diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b can be suppressed. When the semiconductor layer 520c is provided above the semiconductor layer 520b, diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b can be suppressed.

[0375] Furthermore, when an oxide semiconductor is used as the semiconductor layer 520, a stacked structure of multiple oxide layers having different atomic ratios of metal atoms can be employed. For example, when the semiconductor layer 520 contains at least indium (In) and element M, the atomic ratio of element M in semiconductor layer 520a to all elements constituting semiconductor layer 520a can be made higher than the atomic ratio of element M in semiconductor layer 520b to all elements constituting semiconductor layer 520b. Furthermore, the atomic ratio of element M to In in semiconductor layer 520a can be made higher than the atomic ratio of element M to In in semiconductor layer 520b. The semiconductor layer 520c can also use a metal oxide that can be used for either semiconductor layer 520a or semiconductor layer 520b.

[0376] The energy level of the conduction band bottom of semiconductor layer 520a and semiconductor layer 520c can be higher than the energy level of the conduction band bottom of semiconductor layer 520b. In other words, the electron affinity of semiconductor layer 520a and semiconductor layer 520c can be lower than the electron affinity of semiconductor layer 520b. In this case, a metal oxide that can be used for semiconductor layer 520a can be used as semiconductor layer 520c. Specifically, the atomic ratio of element M in semiconductor layer 520c to all elements constituting semiconductor layer 520c can be higher than the atomic ratio of element M in semiconductor layer 520b to all elements constituting semiconductor layer 520b. Furthermore, the atomic ratio of element M to In in semiconductor layer 520c can be higher than the atomic ratio of element M to In in semiconductor layer 520b.

[0377] Here, the energy level of the conduction band bottom at the junction of semiconductor layer 520a, semiconductor layer 520b, and semiconductor layer 520c changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of semiconductor layer 520a, semiconductor layer 520b, and semiconductor layer 520c changing continuously or being continuously joined. As a result, the defect state density of the mixed layer formed at the interface between semiconductor layer 520a and semiconductor layer 520b, and at the interface between semiconductor layer 520b and semiconductor layer 520c can be reduced.

[0378] Specifically, when the semiconductor layer 520a and the semiconductor layer 520b, and the semiconductor layer 520b and the semiconductor layer 520c, have a common element other than oxygen, a mixed layer with a low defect state density can be formed. For example, when the semiconductor layer 520b is indium gallium zinc oxide (In-Ga-Zn oxide), the semiconductor layer 520a and the semiconductor layer 520c can be made of In-Ga-Zn oxide, gallium zinc oxide (Ga-Zn oxide), gallium oxide, or the like. In addition, the semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide that does not contain In can be used as the semiconductor layer 520c.

[0379] Specifically, a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4 or a ratio close to it, or an atomic ratio of 1:1:0.5 or a ratio close to it, can be used as the semiconductor layer 520a. Furthermore, a metal oxide having an atomic ratio of In:Ga:Zn = 4:2:3 or a ratio close to it, 3:1:2 or a ratio close to it, or 1:1:1 or a ratio close to it, can be used as the semiconductor layer 520b. Furthermore, a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4 or a ratio close to it, In:Ga:Zn = 4:2:3 or a ratio close to it, Ga:Zn = 2:1 or a ratio close to it, or Ga:Zn = 2:5 or a ratio close to it, can be used as the semiconductor layer 520c. In addition, as specific examples of the case where the semiconductor layer 520c has a stacked structure, there can be cited a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or its vicinity and Ga:Zn=2:1 [atomic ratio] or its vicinity, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or its vicinity and Ga:Zn=2:5 [atomic ratio] or its vicinity, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or its vicinity and gallium oxide, etc.

[0380] At this time, the main path for carriers is semiconductor layer 520b. By making semiconductor layer 520a and semiconductor layer 520c have the above-mentioned structure, the defect state density at the interface between semiconductor layer 520a and semiconductor layer 520b and the interface between semiconductor layer 520b and semiconductor layer 520c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, so that transistor 200D can obtain a large on-state current and high frequency characteristics. In addition, when semiconductor layer 520c adopts a stacked structure, in addition to the effect of reducing the defect state density at the interface between semiconductor layer 520b and semiconductor layer 520c, it is possible to suppress the diffusion of constituent elements contained in semiconductor layer 520c to the insulating layer 550 side. More specifically, when semiconductor layer 520c has a stacked structure, because the oxide that does not contain In is located above the stacked structure, In that would diffuse to the insulating layer 550 side can be suppressed. The insulating layer 550 is used as a gate insulating film, so in the case of In diffusion, it will lead to poor characteristics of the transistor. Thus, by providing the semiconductor layer 520c with a stacked-layer structure, a highly reliable semiconductor device can be provided.

[0381] Conductive layers 542 (conductive layer 542a and conductive layer 542b) serving as a source electrode and a drain electrode are provided over the semiconductor layer 520b. When an oxide semiconductor is used as the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or a conductive material that maintains conductivity even when absorbing oxygen.

[0382] The region of the semiconductor layer 520 in contact with the conductive layer 542 serves as a source region or a drain region of the transistor 200D. Here, the region between the conductive layer 542a and the conductive layer 542b is formed so as to overlap with the opening formed in the insulating layer 580. Therefore, the conductive layer 560 can be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0383] The insulating layer 550 serves as a gate insulating film. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having pores. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 550.

[0384] As with the insulating layer 524, an insulating material having a reduced concentration of impurities such as water and hydrogen can be used for the insulating layer 550. The insulating layer 550 can have a thickness of 1 nm to 20 nm.

[0385] Furthermore, a metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses diffusion of oxygen from the insulating layer 550 to the conductive layer 560. Thus, oxidation of the conductive layer 560 due to oxygen in the insulating layer 550 can be suppressed.

[0386] Although Figures 47A to 47C The middle conductive layer 560 has a two-layer structure, but may also be a single-layer structure or a stacked structure of three or more layers.

[0387] The conductive layer 560a can be made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, or NO), or copper atoms. Alternatively, a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) can be used.

[0388] By providing the conductive layer 560a with a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity caused by oxidation of the conductive layer 560b due to oxygen contained in the insulating layer 550. As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide can be used.

[0389] Conductive layer 560b can be made of a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, since conductive layer 560 also functions as wiring, a highly conductive layer can be used. Furthermore, conductive layer 560b can have a stacked-layer structure, for example, a stacked-layer structure of titanium or titanium nitride and the aforementioned conductive materials.

[0390] like Figure 47B and Figure 47C As shown, in the region of the semiconductor layer 520b that does not overlap with the conductive layer 542, that is, the channel formation region of the semiconductor layer 520, the side surfaces of the semiconductor layer 520 are covered by the conductive layer 560. This allows the electric field of the conductive layer 560, which serves as the gate electrode of the transistor 200D, to easily affect the side surfaces of the semiconductor layer 520. This improves the on-state current and frequency characteristics of the transistor 200D.

[0391] As with the insulating layer 514, an insulating material that inhibits the infiltration of impurities such as water and hydrogen into the transistor 200D can be used as the insulating layer 554. For example, an insulating material having lower hydrogen permeability than the insulating layer 524 can be used as the insulating layer 554. Figure 47B and Figure 47CAs shown, the insulating layer 554 is provided so as to be in contact with the side surfaces of the semiconductor layer 520c, the top surface and side surfaces of the conductive layer 542a, the top surface and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layers 520a and 520b, and the top surface of the insulating layer 524. With this structure, hydrogen contained in the insulating layer 580 can be prevented from entering the semiconductor layer 520.

[0392] Furthermore, an insulating material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., that does not readily allow oxygen to permeate) can be used as the insulating layer 554. For example, an insulating material having lower oxygen permeability than the insulating layer 580 or the insulating layer 524 can be used as the insulating layer 554.

[0393] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layer 554 can be deposited by sputtering. By depositing the insulating layer 554 by sputtering in an atmosphere containing oxygen, oxygen can be added to the vicinity of the region of the insulating layer 524 that is in contact with the insulating layer 554. As a result, oxygen can be supplied from this region through the insulating layer 524 to the semiconductor layer 520. Here, by giving the insulating layer 554 a function of suppressing oxygen diffusion upward, oxygen can be prevented from diffusing from the semiconductor layer 520 to the insulating layer 580. In addition, by giving the insulating layer 522 a function of suppressing oxygen diffusion downward, oxygen can be prevented from diffusing from the semiconductor layer 520 to the substrate side. In this way, oxygen is supplied to the channel formation region in the semiconductor layer 520. As a result, oxygen vacancies in the semiconductor layer 520 can be reduced, and the normally-on state of the transistor can be suppressed.

[0394] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium can be deposited as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) can be used.

[0395] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 via the insulating layer 554. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies can be used as the insulating layer 580. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they easily form regions containing oxygen that is released by heating.

[0396] As with the insulating layer 514 and the like, an insulating material that functions as a barrier insulating film to prevent impurities such as water and hydrogen from entering the insulating layer 580 from above can be used as the insulating layer 574. For example, the insulating material that can be used for the insulating layer 514 or the insulating layer 554 can be used as the insulating layer 574.

[0397] Figures 47A to 47C An example is shown in which an insulating layer 581 serving as an interlayer film is provided over the insulating layer 574. As with the insulating layer 524 and the like, an insulating material having a reduced concentration of impurities such as water and hydrogen can be used for the insulating layer 581.

[0398] Conductive layer 545a and conductive layer 545b are respectively disposed in two openings formed in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554. Conductive layer 545a and conductive layer 545b are disposed so as to sandwich conductive layer 560. Furthermore, the top surfaces of conductive layer 545a and conductive layer 545b may be at the same height as the top surface of insulating layer 581.

[0399] Insulating layer 541a is provided so as to contact the inner wall of one of the two openings formed in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554. A first conductive layer of conductive layer 545a is formed so as to contact the side surface of insulating layer 541a. Conductive layer 542a is located at least partially at the bottom of the opening, and conductive layer 545a is in contact with conductive layer 542a. Similarly, insulating layer 541b is provided so as to contact the inner wall of the other of the two openings formed in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554. A first conductive layer of conductive layer 545b is formed so as to contact the side surface of insulating layer 541b. Conductive layer 542b is located at least partially at the bottom of the opening, and conductive layer 545b is in contact with conductive layer 542b.

[0400] The conductive layer 545a and the conductive layer 545b can be formed using a conductive material mainly composed of tungsten, copper, or aluminum. Alternatively, the conductive layer 545a and the conductive layer 545b may each have a stacked structure of two or more layers.

[0401] When a stacked-layer structure is employed as the conductive layer 545, the conductive layer in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581 can be a conductive layer having the function of inhibiting the diffusion of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 520 from the upper layer of the insulating layer 581 through the conductive layers 545a and 545b.

[0402] The insulating layers 541a and 541b can be any insulating layer that can be used for the insulating layer 554. Since the insulating layers 541a and 541b are provided in contact with the insulating layer 554, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 520 from the insulating layer 580 or the like through the conductive layers 545a and 545b. Furthermore, the insulating layers 541a and 541b can prevent oxygen contained in the insulating layer 580 from being absorbed by the conductive layers 545a and 545b.

[0403] <Transistor Structure Example 5>

[0404] Figures 48A to 48C Show Figures 47A to 47C A modified example of the transistor 200D is shown. Figure 48A 200E is a top view of a transistor 200E which is a modified example of the transistor 200D. Figure 48B It is along Figure 48A A cross-sectional view along the dot-dash line A1-A2 in FIG. Figure 48C It is along Figure 48A The transistor 200E is a modified example of the transistor 200D, so the differences between the transistor 200E and the transistor 200D will be mainly described.

[0405] Transistor 200E has a structure similar to transistor 200D without the semiconductor layer 520c and the conductive layer 505c. By reducing the number of transistor components, production costs can be reduced. Reducing the number of transistor components shortens the manufacturing process, thereby improving manufacturing yield.

[0406] Furthermore, the transistor 200E includes a region where the insulating layer 554 is in contact with the insulating layer 522 outside the semiconductor layer 520, and the side surfaces of the insulating layer 524 are covered by the insulating layer 554. When an oxide semiconductor is used as the semiconductor layer 520, covering the side surfaces of the insulating layer 524 with the insulating layer 554 can prevent oxygen from diffusing from the semiconductor layer 520 through the insulating layer 524 to the outside and can also prevent excess oxygen from being supplied to the semiconductor layer 520 from the side of the insulating layer 524.

[0407] Furthermore, an insulating layer may be provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like can be used as the insulating layer. Providing this insulating layer can suppress oxygen from desorption from the semiconductor layer 520 toward the insulating layer 550, excessive oxygen from the insulating layer 550 toward the semiconductor layer 520, and oxidation of the conductive layer 542.

[0408] <Transistor Constituent Materials>

[0409] Next, constituent materials that can be used for the transistor 200 (the transistor 200A, the transistor 200B, the transistor 200C, the transistor 200D, and the transistor 200E) are described.

[0410] [Substrate]

[0411] When the transistor is provided on a substrate, there is no particular limitation on the material used for the substrate. The material used for the substrate can be determined according to the purpose and in consideration of the presence or absence of light transmittance and the heat resistance to withstand heat treatment. As the substrate, for example, an insulating substrate, a semiconductor substrate or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate such as borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.) can be used. In addition, as the substrate, a semiconductor substrate, a flexible substrate, a resin substrate, etc. can also be used.

[0412] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, examples include semiconductor substrates having an insulator region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Furthermore, the semiconductor substrate may be either a single crystal semiconductor or a polycrystalline semiconductor.

[0413] Examples of the conductive substrate include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, examples include substrates having a conductive layer or semiconductor layer provided on an insulating substrate, substrates having a conductive layer or insulating layer provided on a semiconductor substrate, and substrates having a semiconductor layer or insulating layer provided on a conductive substrate.

[0414] As materials for flexible substrates or resin substrates, for example, polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aromatic polyamide, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofiber, etc. can be used.

[0415] By using the above materials as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials as a substrate, a semiconductor device with high impact resistance can be provided. Furthermore, by using the above materials as a substrate, a semiconductor device that is not easily damaged can be provided. Alternatively, a substrate having components disposed on these substrates can be used. Components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0416] 〔Insulation layer〕

[0417] Inorganic insulating films can be used as insulating layers (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 257, insulating layer 258, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 516, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of the inorganic insulating film include oxide insulating films, nitride insulating films, oxynitride insulating films, and nitride oxide insulating films. Examples of the oxide insulating film include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of the nitride insulating film include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Furthermore, organic insulating films may also be used as insulating layers included in semiconductor devices.

[0418] Note that in this specification, etc., "oxynitride" refers to a material containing more oxygen than nitrogen, while "nitride oxide" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen. The content of each element can be measured using, for example, Rutherford backscattering spectroscopy (RBS).

[0419] For example, with the miniaturization and high integration of transistors, problems such as gate leakage current sometimes occur due to the thin filmization of the gate insulating film. By using a material with a high relative dielectric constant (high-k) for the insulating layer used as the gate insulating film of the insulating layer 204, the insulating layer 202, etc., it is possible to achieve low voltage when the transistor is working while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the gate insulating film can be reduced. In addition, by using a material with a high relative dielectric constant for the insulating layer used as the dielectric of the capacitor, the electrostatic capacitance per unit area can be increased. On the other hand, by using a material with a low relative dielectric constant for the insulating layer used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material can be selected according to the function of the insulating layer. In addition, the material with a low relative dielectric constant is also a material with a large dielectric strength.

[0420] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0421] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than those mentioned above, for example, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0422] 〔Conductive layer〕

[0423] As the conductive layers used in the transistor 200 (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 255, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.), it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. As the alloy containing the above metal elements as a component, a nitride or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, a nitride containing tungsten, titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Alternatively, a semiconductor with high conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0424] In addition, it is preferred to use a conductive material that is not easily oxidized, a conductive material with a function of suppressing oxygen diffusion, or a material that absorbs oxygen and maintains conductivity. As such a material, a conductive material containing nitrogen such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum can be cited. In addition, a conductive material containing oxygen such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel can be cited. In addition, a material containing metal elements such as titanium, tantalum or ruthenium can be cited. Note that as a conductive material containing oxygen, a material containing tungsten oxide and indium oxide, a material containing titanium oxide and indium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide can be cited. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0425] Furthermore, as a material having high electrical conductivity, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0426] Alternatively, a plurality of conductive layers formed from the above-mentioned materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0427] For example, in the transistor 200A or the transistor 200B, when an oxide semiconductor, which is one of the metal oxides, is used for the semiconductor layer 203, a stacked-layer structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen can be employed as the conductive layer 205, the conductive layer 219, and other conductive layers serving as gate electrodes. In this case, the conductive material containing oxygen can also be provided on the side of the semiconductor layer 203. By providing the conductive material containing oxygen on the side of the semiconductor layer 203, oxygen released from the conductive material can be easily supplied to the channel formation region of the semiconductor layer 203.

[0428] In addition, when an oxide semiconductor such as one of the metal oxides is used as the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, a conductive material that is not easily oxidized, a conductive material that maintains low resistance even when oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has a function of inhibiting oxygen diffusion can be used as the conductive layers 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b that are in contact with the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. As a result, a decrease in the conductivity of the conductive layers 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b can be suppressed.

[0429] By using a conductive material containing oxygen for the conductive layers 208a, 208b, 255, 261, 542a, and 542b, conductivity can be maintained even when the conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, it is preferable to use an insulating layer containing excess oxygen as the insulating layer in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, because this allows the conductive layers 208a, 208b, 255, 261, 542a, and 542b to maintain conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like can be used as the conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0430] Semiconductor layer

[0431] As the semiconductor layer (semiconductor layer 203, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.

[0432] Semiconductors composed of a single element or compound semiconductors can also be used as semiconductor layers. Examples of semiconductors composed of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide, silicon carbide, and silicon germanium. In addition, examples of compound semiconductors include organic semiconductors and nitride semiconductors. Oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0433] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS).

[0434] For example, in transistor 200A or transistor 200B, by using silicon for semiconductor layer 203 and including phosphorus or arsenic as an n-type dopant in regions 203a and 203c of semiconductor layer 203, the transistor can be used as an n-type transistor. Alternatively, by including boron as a p-type dopant in regions 203a and 203c of semiconductor layer 203, the transistor can be used as a p-type transistor. Note that when both n-type and p-type dopants are included in regions 203a and 203c of semiconductor layer 203, the conductivity type with the higher doping concentration tends to be exhibited.

[0435] In addition, as the semiconductor layer, a two-dimensional material that functions as a semiconductor can also be used. Two-dimensional materials are also called layered materials, which is a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked together through bonds such as van der Waals bonds that are weaker than covalent bonds and ionic bonds. Layered materials have high conductivity in the unit layer, that is, they have high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0436] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing oxygen group elements (elements belonging to Group 16). In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0437] Alternatively, an oxide semiconductor, such as a metal oxide, may be used as the semiconductor layer. In this case, the band gap of the metal oxide is preferably greater than 2.0 eV, more preferably greater than 2.5 eV. Using a metal oxide with a wide band gap as the semiconductor layer can significantly reduce the off-state current of the transistor. The low off-state current of the OS transistor can reduce the power consumption of the semiconductor device.

[0438] Here, in the channel formation region of a transistor using an oxide semiconductor as a semiconductor layer, it is preferable that the number of oxygen vacancies or the impurity concentration (for example, the concentration of hydrogen, nitrogen, and metal elements) is small compared to the source region and the drain region. In addition, hydrogen near the oxygen vacancies may form V O H (hydrogen enters the defect in the oxygen vacancy) and generates electrons that become carriers, so V O The number of H is preferably small. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0439] In addition, the source region and the drain region preferably have more oxygen vacancies and more V compared to the channel formation region of the transistor. O H or a higher impurity concentration. Thus, the source region and the drain region are n-type regions with a higher carrier concentration and lower resistance than the channel formation region of the transistor.

[0440] Note that an oxide semiconductor will be described in detail in Embodiment 3 to be described later.

[0441] Note that the contents described in this embodiment mode can be implemented in combination as appropriate. In addition, the contents described in this embodiment mode can be implemented in combination as appropriate with the contents described in other embodiment modes and the like.

[0442] Implementation 3

[0443] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention is described.

[0444] <Oxide Semiconductor Layer>

[0445] The oxide semiconductor layer preferably includes a crystalline metal oxide. Examples of crystalline metal oxide structures include a CAAC (c-axis aligned crystal) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. Using a crystalline metal oxide in the oxide semiconductor layer can reduce the defect state density in the oxide semiconductor layer. This can improve the reliability of a transistor using the oxide semiconductor layer, thereby improving the reliability of a semiconductor device including the transistor.

[0446] The oxide semiconductor layer preferably contains a metal oxide having a CAAC structure. The CAAC structure refers to a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected on the ab plane in a manner such that the plurality of microcrystals are not oriented. In addition, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that the metal atoms are arranged in layers in the crystal portion. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having a layered crystal portion.

[0447] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED), or by combining a plurality of these methods.

[0448] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material included in the oxide semiconductor layer. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a non-single crystal semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a partially crystalline region). Crystallinity in the oxide semiconductor layer can sometimes suppress degradation of transistor characteristics.

[0449] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. Furthermore, the metal oxide preferably contains at least indium (In). Furthermore, the metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Furthermore, element M is a metal element or semimetal element having a high bonding energy with oxygen, for example, a metal element or semimetal element having a higher bonding energy with oxygen than indium. Element M specifically includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When element M is gallium, the metal oxide preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and “metal elements” described in this specification and the like may include semi-metal elements.

[0450] Examples of the metal oxide include indium oxide. Examples of the metal oxide include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (also referred to as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). In addition, indium tin oxide (also referred to as ITSO) containing silicon oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), and the like can be cited.

[0451] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide (also referred to as the indium (In) content), the transistor can obtain a large on-state current and high frequency characteristics.

[0452] In addition, the metal oxide may also contain one or more of the metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more of the metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Thus, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As such metal elements, specifically yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0453] Furthermore, the metal oxide may contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field-effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0454] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0455] Furthermore, by increasing the ratio of the number of atoms of the element M to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Consequently, carrier generation due to oxygen vacancies is suppressed, thereby enabling the realization of a transistor with a low off-state current. Furthermore, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0456] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0457] [Manufacturing method]

[0458] The oxide semiconductor layer can be manufactured by forming a metal oxide using a single deposition method or by forming a metal oxide using at least two deposition methods. For example, the oxide semiconductor layer can be manufactured by forming a metal oxide using either a first deposition method or a second deposition method, or by forming a metal oxide using both the first deposition method and the second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods may also be referred to as a Hybrid OS.

[0459] The oxide semiconductor layer can be manufactured by the following process: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. In this case, it is preferred to use a deposition method that causes less damage to the formed surface as the first deposition method compared to the second deposition method. When a deposition method that causes less damage to the formed surface is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the formed surface of the oxide semiconductor layer can be suppressed. In addition, impurities such as silicon can be suppressed from mixing into the second layer, thereby improving the crystallinity of the oxide semiconductor layer.

[0460] As the first deposition method, for example, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a wet method, etc. can be cited. As the CVD method, for example, a plasma enhanced CVD (PECVD) method, a thermal CVD method, a photo CVD method, an organometallic CVD (MOCVD) method, etc. can be cited. As the wet method, for example, a spraying method can be cited. Compared with the sputtering method described later, the ALD method and the CVD method can suppress damage to the formed surface, so they are suitable for use in the first deposition method.

[0461] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma ALD method (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0462] ALD deposits atoms layer by layer, resulting in the following benefits: extremely thin deposition; deposition on high-aspect-ratio structures or surfaces with large steps; deposition with minimal defects such as pinholes; deposition with high coverage; and deposition at low temperatures. Furthermore, PEALD utilizes plasma, enabling deposition at lower temperatures and is therefore sometimes preferred. Note that some precursors used in ALD contain elements such as carbon and chlorine. Therefore, films deposited using ALD may contain higher amounts of elements such as carbon and chlorine than films deposited using other deposition methods. Note that these elements can be quantitatively determined using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that when ALD is used, either or both of a high substrate temperature during deposition and impurity removal treatment are employed, the amount of carbon and chlorine contained in the film may be lower than when ALD is used without these conditions.

[0463] Unlike deposition methods that deposit particles released from a target material, ALD forms a film through a reaction on the surface of the substrate. Therefore, ALD is less susceptible to the shape of the substrate and offers excellent step coverage. In particular, ALD's excellent step coverage and thickness uniformity make it suitable for coating surfaces with high-aspect-ratio openings.

[0464] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Furthermore, because it doesn't use plasma, thermal CVD is a deposition method that reduces plasma damage to the substrate. Furthermore, thermal CVD eliminates plasma damage during deposition, resulting in films with fewer defects.

[0465] Examples of the second deposition method include sputtering and pulsed laser deposition (PLD) methods. The metal oxide formed by the second deposition method tends to have a CAAC structure.

[0466] Here, as the first layer, a metal oxide having a microcrystalline structure or an amorphous structure, for example, with lower crystallinity than a CAAC structure, may be formed. Even in such cases, by forming a second layer (e.g., CAAC) with higher crystallinity on the first layer with lower crystallinity, or by forming such a layer and heat-treating it, the crystallinity of the first layer may be improved with the second layer as a core. This can improve the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface being formed.

[0467] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can be crystallized using the crystals of the second layer as nuclei or seeds. Thus, even if the deposition method for the third layer is not a deposition method that easily achieves crystallinity, the third layer can be crystallized. For example, when the third layer is formed using a deposition method that has higher coverage than the second layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer.

[0468] As an example, the oxide semiconductor layer can be manufactured by the following process: after forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and then forming a metal oxide as a third layer using the first deposition method. Specifically, the ALD method can be used as the first deposition method, and the sputtering method can be used as the second deposition method. The ALD method is a deposition method with excellent coverage compared to the sputtering method. When the ALD method is used as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with a high aspect ratio.

[0469] Reference Figures 49A to 49D and Figures 50A to 50D An example of a method for manufacturing the semiconductor layer 230 will be described.

[0470] When a metal oxide film is deposited by sputtering, alloying of the components contained in the metal oxide film with the components contained in the layer on the formed surface occurs due to damage caused by sputtered particles on the formed surface or energy applied to one side of the substrate by the sputtered particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed area even when the heat treatment described later is performed. When an oxide semiconductor layer having an alloyed area is used in a transistor, there is concern that it will have a negative impact on the initial characteristics or reliability of the transistor. Therefore, it is preferred to suppress the alloying of the components contained in the metal oxide film with the components contained in the layer on the formed surface.

[0471] Thus, first, a semiconductor layer 230a ( Figure 49A Then, a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering ( Figure 49B ).

[0472] In the manufacturing method of the oxide semiconductor layer shown in this embodiment, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 using a deposition method that causes less damage to the formed surface, thereby suppressing the alloying of the components contained in the semiconductor layer 230 and the components contained in the layer 229, thereby further improving the crystallinity of the semiconductor layer 230.

[0473] By adopting the above structure, the thickness of the alloyed region can be reduced or the alloyed region can be reduced to a degree that is difficult to observe. For example, the thickness of the alloyed region can be reduced to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figure 49A and Figure 49B An example is shown in which no alloyed region is formed between the layer 229 and the semiconductor layer 230 a .

[0474] Note that the thickness of the alloyed region can sometimes be calculated by performing linear analysis of the composition of the region and its vicinity using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0475] For example, a linear analysis using EDX is performed on the above-mentioned region and its vicinity, with the direction perpendicular to the formed surface of the semiconductor layer 230a as the depth direction. Then, in the distribution of the quantitative values ​​of each element in the depth direction obtained with respect to the analysis, the depth at which the quantitative value of the metal (In when the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a but not the main component of the layer on which the surface is formed reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the semiconductor layer 230a. In addition, the depth at which the quantitative value of the element (for example, Si) that is the main component of the layer on which the surface is formed but not the main component of the semiconductor layer 230a reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the layer on which the surface is formed. Thus, the thickness of the alloyed region can be calculated.

[0476] In the oxide semiconductor layer, when the thickness of the alloyed region is observed using EDX analysis, for example, the thickness is greater than or equal to 0 nm and less than or equal to 3 nm, preferably greater than or equal to 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 0 nm and less than or equal to 1 nm, and further preferably greater than or equal to 0 nm and less than 0.3 nm.

[0477] For example, when a silicon oxide layer is used as the layer 229 and the semiconductor layer 230 formed on the layer 229 is subjected to SIMS analysis, the depth at which the silicon concentration reaches 50% of the maximum concentration in the layer 229 is regarded as the interface, and the silicon concentration is reduced to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the slit is formed and the interface is considered as the thickness t_s2. The thickness t_s2 is preferably 3 nm or less, more preferably 2 nm or less.

[0478] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0479] Furthermore, by reducing the thickness of the alloyed region, a CAAC structure can be formed near the formed surface. Here, near the formed surface refers to, for example, a region that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm, in the vertical direction from the formed surface of the semiconductor layer 230.

[0480] Note that a CAAC structure can sometimes be observed near the formed surface during TEM observation. For example, when observing a cross section of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers parallel to the formed surface can be observed near the formed surface.

[0481] In addition, when the semiconductor layer 230a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure having lower crystallinity than the CAAC structure may be formed. Figure 49A In the illustrated stage of fabrication, semiconductor layer 230 a sometimes includes regions having a lower crystallinity than semiconductor layer 230 b .

[0482] The semiconductor layer 230 b preferably has a composition suitable for forming a CAAC structure.

[0483] When the semiconductor layer 230b is formed by sputtering, a mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Furthermore, during the formation of the semiconductor layer 230b, sputtered particles or energy applied to the substrate by the sputtered particles may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may serve as nuclei, causing at least a portion of the semiconductor layer 230a to crystallize.

[0484] When the semiconductor layer 230b is deposited by sputtering, the substrate is preferably heated. When forming a metal oxide, a metal oxide with high crystallinity may be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide.

[0485] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b by the ALD method ( Figure 49C When the semiconductor layer 230 c is formed using the ALD method, the formation method of the semiconductor layer 230 a may be referred to.

[0486] When semiconductor layer 230c is formed on semiconductor layer 230b having a CAAC structure using ALD, semiconductor layer 230c may be epitaxially grown with semiconductor layer 230b serving as a core. As a result, when semiconductor layer 230c is formed, it may include a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed throughout semiconductor layer 230c.

[0487] Then, a heat treatment process may be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the semiconductor layer 230c may be improved. In addition, when the region is formed only below the semiconductor layer 230c after deposition by the ALD method, the region may be expanded to the upper part of the semiconductor layer 230c by the heat treatment process ( Figure 49D ) That is, by performing this heat treatment, a region having a CAAC structure in the semiconductor layer 230c may be formed throughout the entire semiconductor layer 230c.

[0488] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is converted to CAAC by the heat treatment step ( Figure 49D ). It is expected that when depositing semiconductor layer 230b, the mixed layer 231 formed in semiconductor layer 230a will be used as a nucleus or seed crystal, thereby increasing the possibility of easily achieving CAAC. In semiconductor layer 230a, the larger the CAAC area, the better. Preferably, the vicinity of layer 229 is also CAACized.

[0489] Furthermore, since CAAC is applied from the upper portion of the semiconductor layer 230a toward the lower portion thereof, CAAC can be applied even near the layer 229, regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, a semiconductor layer 230a with high crystallinity can be formed. Therefore, the method for manufacturing an oxide semiconductor layer described in this embodiment is particularly suitable when the layer to be formed has an amorphous structure.

[0490] Notice, Figures 49A to 49D is a cross-sectional view illustrating a method for depositing a metal oxide. Figures 49A to 49D It can also be regarded as a schematic diagram of the deposition model of metal oxides. Figures 49A to 49D As shown, the crystallinity of semiconductor layer 230a and semiconductor layer 230c is improved by using semiconductor layer 230b, which has high crystallinity, as a core or seed. Specifically, the crystallinity of semiconductor layer 230a may be improved by heat treatment during or after deposition of semiconductor layer 230b. Furthermore, the crystallinity of semiconductor layer 230c may be improved by heat treatment during or after deposition of semiconductor layer 230c. Note that this heat treatment has the function of assisting in improving crystallinity.

[0491] Thus, in the deposition method of the metal oxide shown in this embodiment, the crystallinity of the upper and lower oxide semiconductors (here, the semiconductor layer 230a and the semiconductor layer 230c) can be improved by using the semiconductor layer 230b (for example, CAAC) with high crystallinity as a core or seed. As a result, the crystallinity of the entire oxide semiconductor can be improved. In other words, the upper and lower oxide semiconductors are solid-phase epitaxially grown using the semiconductor layer 230b as a core or seed, thereby forming an oxide semiconductor with high crystallinity. The oxide semiconductor formed by this deposition method, here the CAAC film, can be called axial growth (AxialGrowth) CAAC (AG CAAC). Note that, Figures 50A to 50D The structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c is shown, but the present invention is not limited thereto. For example, the structure including the semiconductor layer 230a and the semiconductor layer 230b may also be referred to as AG CAAC.

[0492] In the semiconductor layer 230 , the region having the CAAC structure preferably exists widely throughout the entire layer. Figure 50A The semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are all crystallized. In this case, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Furthermore, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be described as a single layer, with no clear interface. The semiconductor layer 230 may also be described as a single layer.

[0493] In addition, a portion of the semiconductor layer 230 a or the semiconductor layer 230 c may not be crystallized. Figure 50B The illustrated example shows a state in which the semiconductor layer 230 a is not crystallized near the interface with the layer 229 . Figure 50C The semiconductor layer 230 c is shown in a state where the vicinity of the surface is not crystallized. Figure 50D The semiconductor layer 230 a and the vicinity of the interface with the layer 229 and the vicinity of the surface of the semiconductor layer 230 c are not crystallized.

[0494] By improving the crystallinity of the oxide semiconductor layer, the initial characteristics (especially on-state current) of the transistor using the oxide semiconductor layer can be suppressed, thereby realizing a transistor suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0495] The oxide semiconductor layer described in this embodiment has high crystallinity throughout the entire layer. Consequently, it may be difficult to identify the boundaries between the stacked films of semiconductor layer 230a, semiconductor layer 230b, and semiconductor layer 230c in the semiconductor layer 230. In particular, after heat treatment, it is difficult to identify the boundaries between the stacked films. To confirm the presence of boundaries between the stacked films, for example, a TEM can be used.

[0496] Here, by using a metal oxide with a high In content in a transistor, the field-effect mobility of the transistor can be improved. On the other hand, oxide semiconductors with a high In content have a tendency to polycrystallize. Using a metal oxide with a polycrystalline structure in a transistor has a negative impact on the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals reflecting the orientation of the crystals in the semiconductor layer 230b are formed, thereby suppressing polycrystallization.

[0497] In this case, the lattice mismatch between the crystals in semiconductor layer 230b and the crystals in semiconductor layer 230a or semiconductor layer 230c is preferably small. As a result, semiconductor layer 230a or semiconductor layer 230c can form crystals that reflect the orientation of the crystals in semiconductor layer 230b. In this case, for example, when observing a cross section of semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers parallel to the surface on which they are formed can be observed in semiconductor layer 230a or semiconductor layer 230c.

[0498] Note that the crystal structure of semiconductor layer 230a or semiconductor layer 230c is not particularly limited as long as the lattice mismatch between the crystals of semiconductor layer 230b and the crystals of semiconductor layer 230a or semiconductor layer 230c is small. The crystal structure of semiconductor layer 230a or semiconductor layer 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0499] 〔composition〕

[0500] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. Sputtering, for example, can be used to form the semiconductor layer 230b. For example, the semiconductor layer 230b preferably contains zinc. The inclusion of zinc allows for a highly crystalline metal oxide. Furthermore, the semiconductor layer 230b preferably contains element M in addition to zinc. When the semiconductor layer 230b contains element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. This can improve the reliability of transistors using oxide semiconductor layers. Specifically, the semiconductor layer 230b can be made of a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:1.2 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:0.5 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:2 or a composition thereof, an atomic ratio of In:M:Zn = 4:2:3 or a composition thereof, an atomic ratio of In:M:Zn = 1:3:2 or a composition thereof, or an atomic ratio of In:M:Zn = 1:3:4 or a composition thereof. The composition thereof is preferably within a range of ±30% of the desired atomic ratio. Furthermore, the element M is preferably one or more of gallium, aluminum, and tin.

[0501] In addition, the semiconductor layer 230b may have a structure that does not contain the element M. For example, In-Zn oxide may be used. Specifically, a composition of In:Zn = 1:1 [atomic ratio] or a composition close thereto, a composition of In:Zn = 2:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn = 4:1 [atomic ratio] or a composition close thereto. Alternatively, the semiconductor layer 230b may not contain the elements M and Zn. For example, indium oxide may be used. In addition, a structure containing a trace amount of the element M may be used. For example, a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or a composition close thereto, or a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or a composition close thereto. In addition, for example, a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or a composition close thereto, or a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or a composition close thereto may be used.

[0502] The semiconductor layers 230a and 230c can be formed using a metal oxide having a high ratio of indium. The semiconductor layers 230a and 230c can be formed using, for example, an ALD method. Furthermore, it is particularly preferred to use a metal oxide having a high ratio of indium relative to element M. Using a metal oxide having a high ratio of indium can increase the on-state current and improve frequency characteristics when the oxide semiconductor layer is used in a transistor.

[0503] Alternatively, the semiconductor layers 230a and 230c may have a structure that does not contain the element M. For example, an In-Zn oxide may be used. Specifically, a composition of In:Zn = 1:1 [atomic ratio] or thereabouts, a composition of In:Zn = 2:1 [atomic ratio] or thereabouts, or a composition of In:Zn = 4:1 [atomic ratio] or thereabouts may be used. Alternatively, the semiconductor layers 230a and 230c may not contain the elements M and Zn. For example, indium oxide may be used. Alternatively, the semiconductor layers 230a and 230c may have a structure that contains a trace amount of the element M. Specifically, a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or thereabouts, a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or thereabouts, a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or thereabouts, or a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or thereabouts may be used.

[0504] In addition, the crystallinity of the oxide semiconductor can be improved by increasing the atomic ratio of zinc contained in the oxide semiconductor. In particular, it is preferable to adopt a structure in which the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by the ALD method and the semiconductor layer 230b is formed by the sputtering method, the zinc contained in the semiconductor layer 230a sometimes diffuses into the semiconductor layer 230b. Note that this diffusion is caused by heat treatment during or after sputtering. When zinc diffuses from the semiconductor layer 230a to the semiconductor layer 230b, the crystallinity can be improved in the semiconductor layer 230b. In addition, when zinc diffuses from the semiconductor layer 230a to the semiconductor layer 230b, lateral growth of a crystalline portion with c-axis orientation can be achieved in the semiconductor layer 230b to promote CAAC.

[0505] Furthermore, the semiconductor layer 230 a and the semiconductor layer 230 c can be said to be metal oxides having a higher In content than the semiconductor layer 230 b .

[0506] Alternatively, for example, semiconductor layers 230a and 230c may use metal oxides with a higher Ga ratio than semiconductor layer 230b. For example, semiconductor layers 230a and 230c preferably use metal oxides with a composition of In:Ga:Zn = 1:1:1 (atomic ratio) or approximately thereabouts, a composition of In:Ga:Zn = 1:3:2 (atomic ratio) or approximately thereabouts, or a composition of In:Ga:Zn = 1:3:4 (atomic ratio) or approximately thereabouts. Increasing the Ga ratio can, for example, increase the band gap of semiconductor layers 230a and 230c relative to that of semiconductor layer 230b. Consequently, semiconductor layer 230b is sandwiched between semiconductor layers 230a and 230c, which have larger band gaps, and semiconductor layer 230b primarily serves as a current path. When semiconductor layer 230b is sandwiched between semiconductor layers 230a and 230c, trap levels at and near the interface of semiconductor layer 230b can be reduced. Thus, an embedded channel transistor in which the channel is far away from the insulating layer interface can be realized, thereby improving the field effect mobility.

[0507] Furthermore, even if the semiconductor layers 230a and 230c have compositions that make it difficult to form a CAAC structure when formed as a single layer, crystal growth can be performed using the semiconductor layer 230b as a core, thereby achieving a CAAC structure throughout the oxide semiconductor layer including the semiconductor layers 230a and 230c. Alternatively, a CAAC structure can be formed across a region including at least a portion of each of the semiconductor layers 230a and 230c, as well as a region of the semiconductor layer 230b.

[0508] In particular, even when the semiconductor layer 230a and the semiconductor layer 230c have a high In ratio, crystallinity suitable for use as a semiconductor layer in a transistor can be achieved. In the oxide semiconductor layer described in this embodiment, the following effects can be simultaneously achieved: improving the on-state characteristics of the transistor by increasing the In ratio, and improving reliability by adopting a highly crystalline CAAC structure.

[0509] Note that the composition of the semiconductor layer 230 a may be different from the composition of the semiconductor layer 230 c .

[0510] Alternatively, the semiconductor layer 230 a and the semiconductor layer 230 c may be made of a metal oxide having the same composition as that of the semiconductor layer 230 b .

[0511] In this way, by using the oxide semiconductor layer with a CAAC structure formed by the two deposition methods mentioned above in the channel formation region of the transistor, a transistor with excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) , a transistor with high reliability, etc.) can be realized.

[0512] Note that when analyzing the composition of the metal oxide used in the semiconductor layer 230, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of multiple of these methods can be used for analysis. Note that the actual content of an element with a low content may differ from the content obtained through analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained through analysis may be lower than the actual content.

[0513] 〔Crystallinity〕

[0514] The level of crystallinity of the oxide semiconductor layer can be evaluated using, for example, crystal orientation.

[0515] The crystal orientation can be determined using the Fast Fourier Transform (FFT) pattern obtained by performing a Fast Fourier Transform (FFT) on the TEM image. Specifically, the FFT pattern is used to determine the direction of the crystal axis. The FFT pattern obtained by FFT processing reflects the same reciprocal lattice spatial information as the electron beam diffraction pattern.

[0516] By performing FFT processing on each region of the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a graph showing the crystal orientation can be formed. Specifically, two spots with high intensity are confirmed in the FFT pattern of the region having a layered crystal portion. The direction of the crystal axis of the region can be known from the angle of the line segment connecting the two spots.

[0517] The c-axis orientation ratio can be calculated by calculating the ratio of the region oriented along the c-axis in a graph showing the crystal orientation.

[0518] In the oxide semiconductor layer, the c-axis orientation ratio can be calculated, for example, by observing a cross section or a plane of the oxide semiconductor layer using a TEM. Furthermore, the region in which the FFT is performed (also referred to as the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region in which the FFT is performed is not limited to a circle.

[0519] In the oxide semiconductor layer, for example, when the proportion of the region whose difference from the c-axis is within 20° is calculated as the c-axis orientation ratio, the c-axis orientation ratio is greater than 60%, preferably greater than 70%, more preferably greater than 80%, further preferably greater than 90%, and even more preferably greater than 95%.

[0520] Furthermore, the c-axis orientation ratios of the region deposited as semiconductor layer 230a, the region deposited as semiconductor layer 230b, and the region deposited as semiconductor layer 230c can be Rc1, Rc2, and Rc3, respectively. Both Rc2 and Rc3 are 60% or greater, preferably 70% or greater, more preferably 80% or greater, even more preferably 90% or greater, and even more preferably 95% or greater. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0521] Note that in the semiconductor layer 230 , the boundaries between the semiconductor layers 230 a , 230 b , and 230 c may not be clearly observed after manufacturing.

[0522] The semiconductor layer 230 can be divided into three regions, namely, a first region, a second region, and a third region, sequentially from the layer 229. Each region is a layered region.

[0523] The first region, the second region, and the third region all have a CAAC structure. Furthermore, the c-axis orientation ratio of the third region is preferably higher than that of the first region. Furthermore, the c-axis orientation ratio of the second region is preferably higher than that of the first region. Furthermore, the c-axis orientation ratios of the second and third regions are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0524] The first region is located within a range of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located within a range of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0525] In addition, the thickness of the layer in each region is, for example, uniform.

[0526] Note that the contents described in this embodiment mode can be implemented in combination as appropriate. In addition, the contents described in this embodiment mode can be implemented in combination as appropriate with the contents described in other embodiment modes and the like.

[0527] Implementation 4

[0528] In this embodiment, an example of a layout in which the transistor described in Embodiment 2 is used in the driver circuit described in Embodiment 1 will be described.

[0529] <Layout Example>

[0530] Figure 51 It is shown as the structure above Figure 25 The transistors of the driving circuit 100 shown use Figures 44A to 44C FIG. 2 is a top view of an example of a layout of a transistor 200A.

[0531] Figure 52A It is along Figure 51 A cross-sectional view along the dot-dash line A1-A2 in FIG. Figure 52B It is along Figure 51 A cross-sectional view along the dot-dash line A3-A4 in FIG.

[0532] Figure 51 The semiconductor layer os01, semiconductor layer os02, semiconductor layer os04, semiconductor layer os05, semiconductor layer os06, semiconductor layer os07, semiconductor layer os08, and semiconductor layer os09 are shown, which correspond to the semiconductor layer 203 on the insulating layer 202. In addition, the conductive layer ge01, conductive layer ge02, conductive layer ge03, conductive layer ge04, conductive layer ge05, conductive layer ge06, conductive layer ge07, conductive layer ge08, conductive layer ge09, conductive layer ge10, conductive layer ge11, and conductive layer ge12 are shown, which correspond to the conductive layer 205 on the insulating layer 204. In addition, conductive layer me01, conductive layer me02, conductive layer me03, conductive layer me04, conductive layer me05, conductive layer me06, conductive layer me09, conductive layer me10, conductive layer me11, conductive layer me12, conductive layer me13, conductive layer me14, conductive layer me15, conductive layer me16, conductive layer me17, conductive layer me18, conductive layer me19, conductive layer me20, conductive layer me21, and conductive layer me22 are shown, which are equivalent to the conductive layer 208 on the insulating layer 206.

[0533] Semiconductor layer os01 and semiconductor layer os02 each include a region serving as a channel formation region for transistor M11 and a region serving as a channel formation region for transistor M12. Semiconductor layer os04 includes a region serving as a channel formation region for transistor M15. Semiconductor layer os05 includes a region serving as a channel formation region for transistor M26 and a region serving as a channel formation region for transistor M27. Semiconductor layer os06 includes a region serving as a channel formation region for transistor M13 and a region serving as a channel formation region for transistor M14. Semiconductor layer os07 includes a region serving as a channel formation region for transistor M24 and a region serving as a channel formation region for transistor M25. Semiconductor layer os08 includes a region serving as a channel formation region for transistor M21 and a region serving as a channel formation region for transistor M22. Semiconductor layer os09 includes a region serving as a channel formation region for transistor M23.

[0534] Conductive layer ge01 includes a region serving as the gate of transistor M11, a region serving as the gate of transistor M23, a region serving as the gate of transistor M25, and a region serving as node NDB. Conductive layer ge02 includes a region serving as the gate of transistor M12 and a region serving as node NDC. Conductive layer ge03 includes a region serving as wiring VL2a, which is equivalent to wiring VL2. Conductive layer ge04 includes a region serving as wiring SPL. Conductive layer ge05 includes a region serving as the gate of transistor M27, a region serving as the other terminal of capacitor C11, and a region serving as wiring CKL2. Conductive layer ge06 includes a region serving as the gate of transistor M15 and a region serving as node NDA. Conductive layer ge07 includes a region serving as the gate of transistor M21, a region serving as the gate of transistor M26, a region serving as one terminal of capacitor C22, and a region serving as node NDD. Conductive layer ge08 includes a region serving as wiring VL2b, which is equivalent to wiring VL2. Conductive layer ge09 includes a region serving as the gate of transistor M13, a region serving as the gate of transistor M14, a region serving as the gate of transistor M24, and a region serving as wiring CKL1. Conductive layer ge10 includes a region serving as the gate of transistor M22 and a region serving as wiring CKL2. Conductive layer ge11 includes a region serving as wiring CKL1. Conductive layer ge12 includes a region serving as wiring VL2b, which is equivalent to wiring VL2.

[0535] Conductive layer me01 includes a region serving as one of the source and drain of transistor M11, a region serving as one of the source and drain of transistor M12, and a region serving as wiring OUTL. Conductive layer me02 includes a region serving as the other of the source and drain of transistor M11, and a region serving as wiring VL1a equivalent to wiring VL1. Conductive layer me03 includes a region serving as wiring VL2a equivalent to wiring VL2. Conductive layer me04 includes a region serving as the other of the source and drain of transistor M12, and a region serving as wiring VL2a equivalent to wiring VL2. Conductive layer me05 includes a region serving as wiring SPL. Conductive layer me06 includes a region serving as one of the source and drain of transistor M13, a region serving as the other of the source and drain of transistor M15, a region serving as the other of the source and drain of transistor M26, a region serving as one terminal of capacitor C11, and a region serving as node NDA. Conductive layer me09 has a region serving as the other of the source and drain of transistor M27 and a region serving as wiring VL2b equivalent to wiring VL2. Conductive layer me10 has a region serving as one of the source and drain of transistor M15 and a region serving as node NDB. Conductive layer me11 has a region serving as the other of the source and drain of transistor M13, a region serving as the other of the source and drain of transistor M14, and a region serving as wiring SPL. Conductive layer me12 has a region serving as one of the source and drain of transistor M14 and a region serving as node NDB. Conductive layer me13 has a region serving as wiring CKL1. Conductive layer me14 has a region serving as wiring CKL2. Conductive layer me15 has a region serving as wiring VL2b equivalent to wiring VL2. Conductive layer me16 has a region serving as the other of the source and drain of transistor M24 and a region serving as wiring VL1b equivalent to wiring VL1. Conductive layer me17 includes a region serving as one of the source and drain of transistor M21, a region serving as one of the source and drain of transistor M22, and a region serving as the other terminal of capacitor C22. Conductive layer me18 includes a region serving as the other of the source and drain of transistor M21 and a region serving as wiring CKL2. Conductive layer me19 includes a region serving as one of the source and drain of transistor M24, a region serving as one of the source and drain of transistor M25, and a region serving as node NDD. Conductive layer me20 includes a region serving as the other of the source and drain of transistor M25 and a region serving as wiring CKL1. Conductive layer me21 includes a region serving as the other of the source and drain of transistor M23 and a region serving as wiring VL2b, which is equivalent to wiring VL2.The conductive layer me22 has a region serving as the other of the source and the drain of the transistor M22 , a region serving as one of the source and the drain of the transistor M23 , and a region serving as the node NDC.

[0536] Conductive layer ME03 is connected to conductive layer GE03 in an opening provided in insulating layer 206. Conductive layer ME04 is connected to conductive layer GE03 in an opening provided in insulating layer 206. Conductive layer ME05 is connected to conductive layer GE04 in an opening provided in insulating layer 206. Conductive layer ME06 is connected to conductive layer GE06 in an opening provided in insulating layer 206. Conductive layer ME09 is connected to conductive layer GE08 in an opening provided in insulating layer 206. Conductive layer ME10 is connected to conductive layer GE01 in an opening provided in insulating layer 206. Conductive layer ME11 is connected to conductive layer GE04 in an opening provided in insulating layer 206. Conductive layer ME12 is connected to conductive layer GE01 in an opening provided in insulating layer 206. Conductive layer ME13 is connected to conductive layer GE09 in an opening provided in insulating layer 206. Furthermore, conductive layer me13 is connected to conductive layer ge11 in an opening provided in insulating layer 206. Conductive layer me14 is connected to conductive layer ge05 in an opening provided in insulating layer 206. Furthermore, conductive layer me14 is connected to conductive layer ge10 in an opening provided in insulating layer 206. Conductive layer me15 is connected to conductive layer ge08 in an opening provided in insulating layer 206. Furthermore, conductive layer me15 is connected to conductive layer ge12 in an opening provided in insulating layer 206. Conductive layer me18 is connected to conductive layer ge10 in an opening provided in insulating layer 206. Conductive layer me19 is connected to conductive layer ge07 in an opening provided in insulating layer 206. Conductive layer me20 is connected to conductive layer ge11 in an opening provided in insulating layer 206. Conductive layer me21 is connected to conductive layer ge12 in an opening provided in insulating layer 206. The conductive layer me22 is connected to the conductive layer ge02 in the opening provided in the insulating layer 206 . Figure 51 and Figure 52B A via (Via) connecting the conductive layer me04 and the conductive layer ge03 to each other in the opening portion provided in the insulating layer 206 is shown.

[0537] The plurality of transistors 200A constituting each transistor of the driver circuit 100 may also share the continuously provided semiconductor layer 203 . Figure 51The following cases are shown: six transistors 200A share the semiconductor layer os01, six transistors 200A share the semiconductor layer os02, two transistors 200A share the semiconductor layer os05, two transistors 200A share the semiconductor layer os06, two transistors 200A share the semiconductor layer os07, and two transistors 200A share the semiconductor layer os08.

[0538] Here, in Figure 51 In the example, transistors M11 and M12 share semiconductor layers OS01 and OS02. For example, three of the six transistors 200A provided in semiconductor layer OS01 are transistors M11, and the remaining three are transistors M12. Furthermore, three of the six transistors 200A provided in semiconductor layer OS02 are transistors M11, and the remaining three are transistors M12. As an example, transistors M13 and M14 share semiconductor layer OS06. For example, one of the two transistors 200A provided in semiconductor layer OS06 is transistor M13, and the other is transistor M14. As an example, transistors M21 and M22 share semiconductor layer OS08. For example, one of the two transistors 200A provided in semiconductor layer OS08 is transistor M21, and the other is transistor M22. As an example, transistors M24 and M25 share semiconductor layer OS07. For example, one of the two transistors 200A provided in semiconductor layer OS07 is transistor M24, and the other is transistor M25. As an example, the transistor M26 and the transistor M27 share the semiconductor layer os05. For example, one of the two transistors 200A provided in the semiconductor layer os05 is the transistor M26, and the other is the transistor M27. Figure 52A The transistor M26 and the transistor M27 share the continuously arranged semiconductor layer os05. In this way, when multiple transistors 200A share the continuously arranged semiconductor layer 203, the area occupied by the transistors can be reduced. This can also reduce the area occupied by the gate driver unit 163, thereby achieving miniaturization.

[0539] Furthermore, the transistors 200A used to constitute each transistor of the driver circuit 100 may have a structure in which a plurality of transistors 200A are connected in parallel. Figure 51 In FIG, the transistor M11 has, for example, a structure in which six transistors 200A are connected in parallel. The transistor M12 has, for example, a structure in which six transistors 200A are connected in parallel. Figure 52B, two transistors 200A are shown as part of transistor M12. In this way, by adopting a structure in which multiple transistors 200A are connected in parallel, the actual channel width can be increased, thereby increasing the on-state current. In other words, the channel width of transistors M11 and transistor M12 can be made larger than the channel width of other transistors (transistors M13 to M15 and transistors M21 to M27, etc.), thereby increasing the on-state current. As a result, the time required to change the potential of wiring OUTL (i.e., rise time and fall time) can be shortened, thereby increasing the operating speed.

[0540] Notice, Figure 51 An example of a case where the channel width of transistor M11 is the same as the channel width of transistor M12 is shown, but the channel width of transistor M11 and the channel width of transistor M12 may be different. For example, the channel width of transistor M11 may be larger than the channel width of transistor M12. During the operation of drive circuit 100, as the potential of wiring OUTL rises, the gate voltage of transistor M11 gradually decreases, so it is preferable to increase the channel width of transistor M11 to increase the on-state current. For example, in Figure 53A In FIG, by changing the layout of the conductive layer ge01, the conductive layer ge02, the conductive layer me01, the conductive layer me02, and the conductive layer me04, a transistor M11 having a structure in which eight transistors 200A are connected in parallel and a transistor M12 having a structure in which four transistors 200A are connected in parallel are shown. That is, four of the six transistors 200A provided in the semiconductor layer os01 are transistors M11, and the remaining two are transistors M12. In addition, four of the six transistors 200A provided in the semiconductor layer os02 are transistors M11, and the remaining two are transistors M12. In addition, as an example, in Figure 53B , a semiconductor layer os03 is also included, and by changing the layout of the conductive layer ge01, a transistor M11 having a structure in which nine transistors 200A are connected in parallel and a transistor M12 having a structure in which six transistors 200A are connected in parallel are shown.

[0541] Here, in Figure 51 In the embodiment of the present invention, the channel length (i.e., the width of the conductive layer 205) and the channel width (i.e., the width of the semiconductor layer 203) of one transistor 200A among transistors M11 and transistor M12 are equal to the channel length and channel width of transistor 200A in the other transistors (transistors M13 to M15, and transistors M21 to M27, etc.). In this way, by adopting a structure in which multiple transistors with equal channel lengths and channel widths are connected in parallel to increase the on-state current of the transistors, it is possible to reduce the unevenness of the transistor characteristics.

[0542] Although not shown, to increase the on-state current of a transistor, the channel length of one transistor can be reduced or the channel width of one transistor can be increased. This can reduce the number of transistors connected in parallel to obtain the same on-state current, thereby reducing the area occupied by the transistor.

[0543] Capacitor C11 can use a portion of insulating layer 206 as a dielectric in a region where conductive layer ge05 and conductive layer me06 overlap each other. Capacitor C22 can use a portion of insulating layer 206 as a dielectric in a region where conductive layer ge07 and conductive layer me17 overlap each other. As an example, Figure 52A A capacitor C11 is shown in which a portion of the insulating layer 206 is used as a dielectric and a portion of each of the conductive layer ge05 and the conductive layer me06 is used as a pair of terminals (also referred to as a pair of electrodes or a pair of conductive layers).

[0544] in addition, Figure 53C The capacitor C11 and its surroundings are shown in the abstract. In this way, the layout can be made in a way that the conductive layer ge05 includes the conductive layer me06, or Figure 53D As shown in FIG, the conductive layer me06 is laid out in a manner including the conductive layer ge05. Figure 53C In the structure shown, the electric field concentration at the end of the conductive layer ge05 toward the insulating layer 206 can be suppressed. Therefore, the insulation breakdown of the insulating layer 206 is less likely to occur, so the reliability can be improved. In addition, for example, in Figure 53D In the structure shown, the capacitance between the side surface of the conductive layer ge05 and the side surface of the conductive layer me06 covering the conductive layer ge05 can also be used as the electrostatic capacitance. Therefore, the electrostatic capacitance per unit area can be easily increased, thereby achieving miniaturization.

[0545] Note that, although not shown, the capacitor may also have a structure in which, for example, a portion of each of the insulating layer 204 and the insulating layer 206 serves as a dielectric, and a portion of each of the semiconductor layer 203 and the conductive layer 208 serves as a pair of terminals. Alternatively, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, with a portion of each of the insulating layer 202 and the insulating layer 204 serving as a dielectric, and a portion of the conductive layer (not shown) and the conductive layer 205 serving as a pair of terminals. Alternatively, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, with a portion of the insulating layer 202 serving as a dielectric, and a portion of the conductive layer (not shown) and the semiconductor layer 203 serving as a pair of terminals.

[0546] Here, in Figure 51In the embodiment, the overlapping region of conductive layer 205 (conductive layers ge01 to ge12) and conductive layer 208 (conductive layers me01 to me06, and conductive layers me09 to me22) outside the region where capacitors C11 and C22 are located serves as a parasitic capacitor using a portion of insulating layer 206 as a dielectric. Therefore, the area of ​​capacitor C11 (i.e., the area of ​​the overlapping region of conductive layer ge05 and conductive layer me06) is preferably larger than the area of ​​the overlapping region of conductive layer 208 outside conductive layer ge05 and conductive layer me06, and preferably larger than the area of ​​the overlapping region of conductive layer 205 outside conductive layer ge05 and conductive layer me06. For example, the area of ​​capacitor C11 is preferably larger than the area of ​​the overlapping region of conductive layer ge05 and conductive layer me13. Furthermore, the area of ​​capacitor C22 (i.e., the area of ​​the region where conductive layer ge07 and conductive layer me17 overlap with each other) is preferably larger than the area of ​​the region where conductive layer ge07 and conductive layer 208 other than conductive layer me17 overlap with each other, and is preferably larger than the area of ​​the region where conductive layer 205 other than conductive layer ge07 overlaps with conductive layer me17. For example, the area of ​​capacitor C22 is preferably larger than the area of ​​the region where conductive layer ge07 and conductive layer me13 overlap with each other, is preferably larger than the area of ​​the region where conductive layer ge07 and conductive layer me14 overlap with each other, is preferably larger than the area of ​​the region where conductive layer ge07 and conductive layer me15 overlap with each other, and is preferably larger than the area of ​​the region where conductive layer ge07 and conductive layer me16 overlap with each other.

[0547] In addition, Figure 51 In the example, wiring VL1 includes wiring VL1a connected to the other of the source and drain of transistor M11 and wiring VL1b connected to the other of the source and drain of transistor M24. Wiring VL1a and wiring VL1b are connected to each other, for example, outside the driver circuit 100. This layout allows for efficient layout of transistors M11, M24, and wiring VL1 (wiring VL1a and wiring VL1b). Furthermore, wiring VL2 includes wiring VL2a connected to the other of the source and drain of transistor M12 and wiring VL2b connected to the other of the source and drain of transistor M23 and the other of the source and drain of transistor M27. Wiring VL2a and wiring VL2b are connected to each other, for example, outside the driver circuit 100. By adopting such a layout, the transistor M12 , the transistor M23 , the transistor M27 , and the wiring VL2 (the wiring VL2 a and the wiring VL2 b ) can be laid out efficiently.

[0548] Here, the potential of wiring VL1a is supplied to wiring OUTL connected to a row of pixels. At this point, the current flowing through wiring VL1a increases instantaneously, causing the voltage of wiring VL1a to drop significantly. To mitigate the impact of this voltage drop on wiring VL1a, it is preferable to increase the width of wiring VL1a. The same applies to wiring VL2a. Note that because large currents instantaneously flow through wiring VL1b, wiring VL2b, wiring CKL1, wiring CKL2, and the like, it is preferable to increase the widths of wiring VL1b, wiring VL2b, wiring CKL1, wiring CKL2, and the like. In this way, increasing the widths of wiring VL1a, wiring VL2a, wiring VL1b, wiring VL2b, wiring CKL1, wiring CKL2, and the like also increases the layout area. Therefore, by prioritizing increasing the widths of wirings with large instantaneous currents, the impact of voltage drops can be mitigated while suppressing the increase in layout area. Furthermore, by prioritizing increasing the widths of wirings with large instantaneous currents, the current density within the wirings can be reduced. This makes it less likely that disconnection or short circuit of wiring due to electromigration occurs, thereby improving reliability.

[0549] Specifically, the current flowing through wiring VL1a and wiring VL2a at each instant is greater than the current flowing through wiring VL1b, wiring VL2b, wiring CKL1, and wiring CKL2 at each instant. Therefore, the width of wiring VL1a can be made larger than the widths of wiring VL1b, wiring VL2b, wiring CKL1, and wiring CKL2. Alternatively, the width of wiring VL2a can be made larger than the widths of wiring VL1b, wiring VL2b, wiring CKL1, and wiring CKL2. This can suppress the increase in layout area while minimizing the impact of voltage drops on wiring VL1a and wiring VL2a.

[0550] For example, when the wiring width of wiring VL1a is increased, the overlap between the conductive layer me02 having an area used as wiring VL1a and the conductive layer ge01 having an area used as node NDB, the conductive layer ge02 having an area used as node NDC, and the conductive layer ge04 having an area used as wiring SPL becomes larger. Therefore, the increase in parasitic capacitance caused by the overlap of the two conductive layers may affect the operation of the circuit. Therefore, although not shown in the figure, in this case, in order to suppress the increase in parasitic capacitance, for example, in the area where each of the conductive layers ge01, ge02, and ge04 overlaps with the conductive layer me02, the wiring width of each of the conductive layers ge01, ge02, and ge04 may be selectively reduced, or an opening may be formed in each of the conductive layers ge01, ge02, and ge04. The same is true for wiring VL2a. In addition, the same is true for the case where other conductive layers that may form parasitic capacitances overlap with each other.

[0551] exist Figure 51 In this layout, the distance between conductive layer me13, which has an area serving as wiring CKL1, and conductive layer me14, which has an area serving as wiring CKL2, is greater than the distance between conductive layer me02, which has an area serving as wiring VL1a, and conductive layer me03, which has an area serving as wiring VL2a, and is also greater than the distance between conductive layer me16, which has an area serving as wiring VL1b, and conductive layer me15, which has an area serving as wiring VL2b. Furthermore, the distance between conductive layer me14, which has an area serving as wiring CKL2, and conductive layer me15, which has an area serving as wiring VL2b, is greater than the distance between conductive layer me02, which has an area serving as wiring VL1a, and conductive layer me03, which has an area serving as wiring VL2a, and is also greater than the distance between conductive layer me16, which has an area serving as wiring VL1b, and conductive layer me15, which has an area serving as wiring VL2b. This layout reduces the parasitic capacitance of wiring CKL1 and wiring CKL2. Since both wiring CKL1 and wiring CKL2 function to transmit clock signals, reducing the parasitic capacitance of wiring CKL1 and wiring CKL2 can reduce the load and increase the operating speed. Furthermore, the electrostatic capacitance between wiring VL1a and wiring VL2a can be increased. Since both wiring VL1a and wiring VL2a function to transmit a constant potential, increasing the electrostatic capacitance between wiring VL1a and wiring VL2a stabilizes the potential and achieves stable operation.

[0552] Note that one embodiment of the present invention is not limited to the structural examples and working examples described in this embodiment. The contents described in this embodiment can be appropriately combined and implemented. In addition, the contents described in this embodiment can be appropriately combined and implemented with the contents described in other embodiments.

[0553] Implementation 5

[0554] In this embodiment, a display device which is one embodiment of the present invention is described.

[0555] In addition, at least part of the driver circuit, semiconductor device, and the like described in Embodiment 1 can be used for the display device described in this embodiment, the module including the display device, and the like.

[0556] Here, as a module including the display device, there can be cited a module in which the display device is installed with a connector such as a flexible printed circuit (FPC) or TCP (Tape Carrier Package), or a module in which an integrated circuit (IC) is installed by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.

[0557] <Configuration Example of Display Device>

[0558] Figure 54A 1 is a perspective view showing a configuration example of a display device 400 according to one embodiment of the present invention.

[0559] The display device 400 has a structure in which a substrate 411 and a substrate 451 are bonded together. Figure 54A In FIG, the substrate 411 is indicated by a dotted line.

[0560] The display device 400 includes a display portion 452 , a circuit portion 454 a , a circuit portion 454 b , a connection portion 457 , a wiring portion 458 , and the like. Figure 54A The example in which the display device 400 is mounted with the IC chip 456 and the FPC 459 is shown. Figure 54A The structure shown is called a display module including the display device 400, an IC chip, and an FPC.

[0561] Furthermore, at least a portion of the semiconductor device 160 described in Embodiment 1 can be used in the display device 400. For example, at least a portion of the driver circuit 100 described in Embodiment 1 can be used in the circuit portions 454a and 454b. Furthermore, at least a portion of the pixel 161 described in Embodiment 1 can be used in the display portion 452.

[0562] The circuit portion 454a includes, for example, a scan line driver circuit (also referred to as a gate driver or a scan driver). In addition, the circuit portion 454b includes, for example, a signal line driver circuit (also referred to as a source driver or a data driver).

[0563] The wiring portion 458 has a function of supplying signals and power to the display portion 452 and the circuit portions 454a and 454b. These signals and power are input to the wiring portion 458 from outside the display device 400 through the FPC 459 or from the IC chip 456.

[0564] Figure 54AAn example of an IC chip 456 provided on a substrate 451 using a COG method or a COF method is shown. For example, an IC chip including one or both of a scan line driver circuit and a signal line driver circuit can be used as the IC chip 456. Note that the display device 400 and the display module do not necessarily need to be provided with an IC chip. Alternatively, the IC chip can be mounted on an FPC using a COF method or the like.

[0565] Alternatively, one or both of the IC chip 456 and the circuit portion 454a may constitute a scan line driver circuit. In this case, the IC chip 456 is sometimes referred to as a gate driver IC. Alternatively, one or both of the IC chip 456 and the circuit portion 454b may constitute a signal line driver circuit. In this case, the IC chip 456 is sometimes referred to as a source driver IC.

[0566] The display portion 452 is an image display region in the display device 400 , and includes a plurality of periodically arranged pixels 455 . Figure 54A An enlarged view of one pixel 455 is shown in FIG.

[0567] Figure 54A The pixel 455 shown includes a pixel 453R that presents red (R) light, a pixel 453G that presents green (G) light, and a pixel 453B that presents blue (B) light. By using the pixel 453R, the pixel 453G, and the pixel 453B to form a pixel 455, a full-color display can be achieved. The pixel 453R, the pixel 453G, and the pixel 453B are all used as sub-pixels. Figure 54A In the display device 400 shown, an example is shown in which pixels 453R, 453B, and 453G serving as subpixels are arranged in a stripe pattern. Note that the number of subpixels constituting a pixel 455 is not limited to three and may be four or more. For example, four subpixels each representing R, G, B, and white (W) light may be included. Alternatively, four subpixels each representing R, G, B, and yellow (Y) light may be included.

[0568] Note that in this specification, etc., the identification symbol "R" is sometimes attached to the components related to red light, the identification symbol "G" is attached to the components related to green light, and the identification symbol "B" is attached to the components related to blue light to describe their respective contents. In addition, these identification symbols are sometimes not attached to describe the common content between them. For example, when it is necessary to distinguish between multiple pixels 453, they are sometimes shown as pixel 453R, pixel 453G, or pixel 453B. In addition, when it is not necessary to distinguish between pixel 453R, pixel 453G, and pixel 453B, they are sometimes simply shown as pixel 453.

[0569] Each of the pixel 453R, the pixel 453G, and the pixel 453B includes a display element and a circuit (pixel circuit) for controlling driving of the display element.

[0570] The connection portion 457 is provided on the outside of the display portion 452. The connection portion 457 may be provided along one side or multiple sides of the display portion 452. There may also be one or more connection portions 457. Figure 54A In the example shown, the connection portion 457 is provided so as to surround the four sides of the display portion. The connection portion 457 connects the common electrode of the display element to the wiring portion 458, and a potential can be supplied to the common electrode.

[0571] The substrate 451 and the substrate 411 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. The substrate (herein, the substrate 411) on the side that extracts light from the display element is preferably made of a material that transmits the light. In addition, a polarizing plate can also be used as at least one of the substrate 451 and the substrate 411. In addition, a flexible material can be used as the substrate 451 and the substrate 411. This makes it possible to realize a flexible display (for example, a bendable display, a foldable display, a scroll display, a slidable display, and a retractable display).

[0572] The display device of one embodiment of the present invention may also have a touch panel function. For example, various detection elements (also called sensor elements) that can detect the approach or contact of a detection object such as a finger may be used in the display device.

[0573] Examples of sensor types include capacitance type, resistance film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.

[0574] Examples of electrostatic capacitance include surface capacitance and projected capacitance. Projected capacitance also includes self-capacitance and mutual capacitance. Mutual capacitance is preferred because it allows for simultaneous multi-point sensing.

[0575] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel has electrodes forming a detection element disposed on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0576] 〔Pixel arrangement〕

[0577] Figures 54B to 54F : is a top view illustrating pixel arrangement. In a display device according to one embodiment of the present invention, there is no particular limitation on pixel arrangement, and various arrangements can be adopted. As a pixel arrangement, for example, a stripe arrangement (see Figure 54B ), S stripe arrangement (refer to Figure 54C ), Delta arrangement (refer to Figure 54D ), zigzag arrangement (refer to Figure 54E ) and Pentile arrangement (refer to Figure 54F ) etc. In addition, for example, a mosaic arrangement, a Diamond arrangement, and a Bayer arrangement etc. can be cited.

[0578] In addition, Figures 54B to 54F , as the top surface shape of each sub-pixel (pixel 453R, pixel 453G and pixel 453B), for example, a triangle, a quadrangle (including a rectangle and a square), a pentagon and other polygons, shapes with rounded corners of these polygons, an ellipse and a circle, etc. can be cited. Here, the top surface shape of each sub-pixel is equivalent to the top surface shape of the display area of ​​the display element in each sub-pixel. The top surface shape and size of each sub-pixel can be determined independently. Note that the respective configurations of pixel 453R, pixel 453G and pixel 453B can be appropriately swapped. In addition, the respective arrangements of the display elements and pixel circuits can be the same or different.

[0579] 〔Display Component〕

[0580] Various elements can be used as display elements, for example, liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements using shutter or optical interference methods, or display elements using microcapsule, electrophoresis, electrowetting, or electronic powder fluid (registered trademark) methods can also be used. Furthermore, QLEDs (Quantum-dot LEDs) using light sources and color conversion technology using quantum dot materials can also be used.

[0581] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0582] Examples of display modes that can be used in liquid crystal devices include the vertical alignment (VA) mode, the FFS (Fringe Field Switching) mode, the IPS (In-Plane Switching) mode, the TN (Twisted Nematic) mode, the ASM (Axially Symmetrically Aligned Microcell) mode, the OCB (Optically Compensated Birefringence) mode, the FLC (Ferroelectric Liquid Crystal) mode, the AFLC (Anti-Ferroelectric Liquid Crystal) mode, the ECB (Electrically Controlled Birefringence) mode, and the guest-host mode. Examples of the VA mode include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced Super View) mode.

[0583] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLC), polymer-network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, isotropic, or blue phases, depending on the conditions. Both positive- and negative-tone liquid crystals can be used as liquid crystal materials.

[0584] Examples of light emitting elements include self-luminous light emitting elements such as LEDs (Light Emitting Diodes), organic EL (ElectroLuminescence) elements (also referred to as OLEDs (Organic LEDs)), and semiconductor lasers. Examples of LEDs include miniature LEDs and microLEDs.

[0585] Examples of the light-emitting substance contained in the light-emitting element include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0586] The light-emitting element can emit red, green, blue, cyan, magenta, yellow, or white light. Furthermore, the light-emitting element can also emit ultraviolet or infrared light. Furthermore, when the light-emitting element has an optical microcavity resonator (microcavity) structure, the color purity can be further improved.

[0587] Of a pair of electrodes included in a light-emitting element, one electrode functions as an anode (also referred to as an anode electrode), and the other electrode functions as a cathode (also referred to as a cathode electrode).

[0588] <Example of Cross-Sectional Structure of Display Device>

[0589] Figure 55 It is a cross-sectional view illustrating an example of a cross-sectional structure of a display device according to one embodiment of the present invention.

[0590] exist Figure 55 In the display device 490 shown, the structures shown in regions 490a, 490b, and 490c can be used in the display device 400. For example, the structure shown in region 490a can be used in the region where the pixels 453 are provided. The structure shown in region 490b can be used in the region where the circuit portions 454a and 454b are provided. The structure shown in region 490c can be used in the region where the FPC 459 is provided.

[0591] Region 490a corresponds to the region in which the pixel 161 described in Embodiment 1 is provided. That is, the transistors provided in region 490a correspond to the transistors included in the pixel 161 described in Embodiment 1 (such as the transistor M31, the transistor M32, and the transistor M33 included in the pixel 161A). Furthermore, region 490b corresponds to the region in which the driver circuit 100 described in Embodiment 1 is provided. That is, the transistors provided in region 490b correspond to the transistors included in the driver circuit 100 described in Embodiment 1 (such as the transistor M11, the transistor M12, the transistor M13, the transistor M14, and the transistor M15).

[0592] Display device 490 includes a substrate 351 (equivalent to substrate 451 described above) and a substrate 352 (equivalent to substrate 411 described above). Furthermore, an adhesive layer 342 is provided between substrates 351 and 352. Substrate 352 faces substrate 351 via adhesive layer 342. Note that region 490c does not include substrate 352 or adhesive layer 342.

[0593] An insulating layer 382 is provided on the substrate 352 side of the substrate 351. Transistors, light-emitting elements, and the like are provided over the insulating layer 382.

[0594] Here, as an example, a structure in which the transistor 200A described in Embodiment 2 is provided in both the region 490a and the region 490b is shown. Also, a structure in which the transistor 200B described in Embodiment 2 is provided in the region 490a is shown.

[0595] The transistors provided in each of the regions 490a and 490b are not limited to the structures of the transistors 200A and 200B. Transistors of various structures, such as the transistors 200C, 200D, and 200E described in Embodiment 2, may be provided in the regions 490a and 490b. In this case, transistors of a single structure may be provided, or two or more transistors of different structures may be provided.

[0596] In addition, the region 490c is provided with a conductive layer 384. The conductive layer 384 can be formed in the same process as the conductive layer 208 (the conductive layer 208a and the conductive layer 208b) in the transistor 200A and the transistor 200B.

[0597] An insulating layer 218 is provided to cover the transistor 200A and the transistor 200B.

[0598] In the region 490a, a pixel electrode 311 is provided on the insulating layer 218. The pixel electrode 311 is connected to the conductive layer 208b through openings provided in the insulating layer 218 and the insulating layer 209. Furthermore, an insulating layer 237 is provided on the insulating layer 218. The insulating layer 237 has a region that covers the end of the pixel electrode 311.

[0599] Furthermore, an EL layer 313 is provided so as to cover the insulating layer 237 and the pixel electrode 311. Furthermore, a common electrode 315 is provided so as to cover the EL layer 313. Furthermore, a protective layer 331 is provided so as to cover the common electrode 315.

[0600] The following region is used as the light-emitting element 330: the pixel electrode 311 and the common electrode 315 overlap with each other via the EL layer 313; the pixel electrode 311 is in contact with the EL layer 313; and the EL layer 313 is in contact with the common electrode 315. The pixel electrode 311 serves as one electrode (or first terminal) of the light-emitting element 330, and the common electrode 315 serves as the other electrode (or second terminal). The EL layer 313 has a function of emitting light with a brightness corresponding to the amount of current flowing between the pixel electrode 311 and the common electrode 315 through the EL layer 313.

[0601] The light-emitting element 330 corresponds to the light-emitting element LD included in the pixel 161A[u,v] described in the first embodiment.

[0602] A light shielding layer 317 is provided on the substrate 351 side of the substrate 352 .

[0603] In the region 490a, an opening is provided in the light shielding layer 317 so as to have a region overlapping with the light emitting element 330. Therefore, light emitted by the light emitting element 330 is emitted to the outside of the display device 490 through the opening provided in the light shielding layer 317. Figure 55 In the figure, the state is indicated by a dotted arrow and the word "light".

[0604] In the region 490c, the conductive layer 386 is provided on a portion of the insulating layer 218. The conductive layer 386 has a region in contact with the conductive layer 384 through an opening provided in the insulating layer 218 and the insulating layer 209.

[0605] Conductive layer 384 can be provided in the same layer as conductive layer 208a and conductive layer 208b. Therefore, conductive layer 384 can include the same material as conductive layer 208a and conductive layer 208b and be formed through the same process. For example, conductive layer 208a, conductive layer 208b, and conductive layer 384 can be formed by processing the same conductive film. In addition, conductive layer 386 can be provided in the same layer as pixel electrode 311. Therefore, conductive layer 386 can include the same material as pixel electrode 311 and be formed through the same process. For example, pixel electrode 311 and conductive layer 386 can be formed by processing the same conductive film. In region 490c, conductive layer 386 is exposed. As a result, conductive layer 386 can be connected to FPC 459 via connecting layer 388.

[0606] As the connection layer 388 , an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or the like can be used.

[0607] <Structural Example of Light-Emitting Element>

[0608] When the display device according to one embodiment of the present invention includes a light-emitting element, light-emitting elements having various structures can be used.

[0609] Figure 56A 、 Figure 56B 、 Figure 57A and Figure 57B Each of them is a cross-sectional view illustrating light-emitting elements having various structures.

[0610] [Structure Example 1]

[0611] Figure 56A Display device 490A shown includes light-emitting element 330R, light-emitting element 330G, and light-emitting element 330B between substrates 351 and 352. Light-emitting element 330R is a display element included in pixels that emit red light, light-emitting element 330G is a display element included in pixels that emit green light, and light-emitting element 330B is a display element included in pixels that emit blue light. Note that when describing the common features among light-emitting element 330R, light-emitting element 330G, and light-emitting element 330B, they are sometimes simply referred to as light-emitting element 330.

[0612] Note that in Figure 56A , the structure between the substrate 351 and the light-emitting element 330 and part of the structure between the substrate 352 and the light-emitting element 330 are omitted. The display device 490A includes, between the substrate 351 and the light-emitting element 330, for example, a transistor constituting a pixel circuit and an insulating layer 218 provided to cover the transistor.

[0613] Display device 490A employs an SBS (Side-by-Side) structure. The SBS structure is manufactured using a metal mask (or a high-definition metal mask). This allows for greater freedom in selecting the materials and structures of each light-emitting element. This allows for individual optimization of the materials and structures of each light-emitting element, facilitating improved luminous intensity and reliability.

[0614] The display device 490A adopts a top emission type. In a top emission type, transistors and the like can be arranged so as to overlap with the light-emitting region of a light-emitting element, thereby further improving the pixel aperture ratio compared to a bottom emission type.

[0615] A light emitting element 330R, a light emitting element 330G, and a light emitting element 330B are provided on the insulating layer 218 .

[0616] The light-emitting element 330R includes a pixel electrode 311R on the insulating layer 218 , an EL layer 313R on the pixel electrode 311R, and a common electrode 315 on the EL layer 313R. Figure 56AThe light emitting element 330R shown emits red (R) light. The EL layer 313R includes a light emitting layer that emits red light.

[0617] The light-emitting element 330G includes a pixel electrode 311G on the insulating layer 218 , an EL layer 313G on the pixel electrode 311G, and a common electrode 315 on the EL layer 313G. Figure 56A The light-emitting element 330G shown emits green (G) light. The EL layer 313G includes a light-emitting layer that emits green light.

[0618] The light-emitting element 330B includes a pixel electrode 311B on the insulating layer 218 , an EL layer 313B on the pixel electrode 311B, and a common electrode 315 on the EL layer 313B. Figure 56A The light-emitting element 330B shown emits blue (B) light. The EL layer 313B includes a light-emitting layer that emits blue light.

[0619] Note that in Figure 56A EL layer 313R, EL layer 313G, and EL layer 313B are shown as having the same thickness, but this is not limiting. EL layer 313R, EL layer 313G, and EL layer 313B may each have a different thickness. For example, the thicknesses are preferably set to enhance the optical path length of light emitted by EL layer 313R, EL layer 313G, and EL layer 313B. This allows for a microcavity structure to be implemented, thereby improving the color purity of light emitted from each light-emitting element.

[0620] Pixel electrode 311R is connected to a transistor (not shown) included in the pixel circuit corresponding to light-emitting element 330R via an opening provided in insulating layer 218 or the like. Similarly, pixel electrode 311G is connected to a transistor (not shown) included in the pixel circuit corresponding to light-emitting element 330G. Similarly, pixel electrode 311B is connected to a transistor (not shown) included in the pixel circuit corresponding to light-emitting element 330B.

[0621] Each end of pixel electrode 311R, pixel electrode 311G, and pixel electrode 311B is covered by an insulating layer 237. Insulating layer 237 serves as a partition. Insulating layer 237 can be formed using one or both of an inorganic insulating material and an organic insulating material to form a single-layer structure or a stacked-layer structure. Insulating layer 237 can use, for example, the material that can be used for insulating layer 218. Insulating layer 237 can electrically insulate the pixel electrode from the common electrode. Insulating layer 237 can also insulate adjacent light-emitting elements.

[0622] The common electrode 315 is a continuous film shared by the light-emitting elements 330R, 330G, and 330B. Note that, although not shown, the common electrode 315 shared by the plurality of light-emitting elements is connected to a conductive layer formed using the same material and process as the pixel electrodes 311R, 311G, and 311B in regions where no light-emitting elements are provided.

[0623] Of the pixel electrodes and the common electrode, the electrode on the light extraction side (here, the common electrode 315) is preferably a conductive film that transmits visible light. Furthermore, the electrodes on the non-light extraction side (here, the pixel electrodes 311R, 311G, and 311B) are preferably a conductive film that reflects visible light.

[0624] Alternatively, a conductive film that transmits visible light can be used as the electrode on the side that does not extract light. In this case, a reflective layer can be arranged opposite the EL layer with the conductive film interposed therebetween. This allows light emitted from the EL layer to be reflected by the reflective layer and extracted outside the display device.

[0625] As the material for forming a pair of electrodes (pixel electrode and common electrode) of the light-emitting element, metals, alloys, conductive compounds and mixtures thereof can be appropriately used. As such materials, specifically, metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium and neodymium and alloys suitably combined thereof can be cited. In addition, as such materials, indium tin oxide (also referred to as In-Sn oxide or ITO), In-Si-Sn oxide, indium zinc oxide (In-Zn oxide) and In-W-Zn oxide can be cited. In addition, as such materials, aluminum alloys (aluminum alloys) such as alloys of aluminum, nickel and lanthanum (Al-Ni-La), alloys of silver and magnesium and alloys of silver, palladium and copper (also referred to as Ag-Pd-Cu, APC) and silver alloys can be cited. Examples of the material include elements belonging to Group 1 or Group 2 of the periodic table (eg, lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys of appropriately combined elements, and graphene.

[0626] The light-emitting element preferably employs a microcavity structure. Thus, for example, one electrode of the light-emitting element (here, the common electrode 315) is preferably an electrode that is both transmissive and reflective to visible light (also known as a semi-transmissive-semi-reflective electrode), while the other electrodes of the light-emitting element (here, the pixel electrodes 311R, 311G, and 311B) are preferably electrodes that are reflective to visible light (also known as a reflective electrode). When the light-emitting element has a microcavity structure, the light emitted by the light-emitting layer can resonate between the two electrodes, thereby enhancing the light emitted from the light-emitting element.

[0627] For example, the transmittance of visible light (light with a wavelength of 400 nm or more and less than 750 nm) of the semi-transmissive-semi-reflective electrode is 40% or more. The reflectance of visible light of the semi-transmissive-semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of visible light of the reflective electrode is 40% or more and less than 100%, preferably 70% or more and less than 100%. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less.

[0628] The EL layer 313R, the EL layer 313G, and the EL layer 313B are all arranged in an island shape. Figure 56A In the example, the ends of the adjacent EL layers 313R overlap with the ends of the EL layers 313G, and the ends of the adjacent EL layers 313G overlap with the ends of the EL layers 313B. Although not shown, the ends of the adjacent EL layers 313R overlap with the ends of the EL layers 313B. When the island-shaped EL layers are deposited using a metal mask (or a high-definition metal mask), as shown in FIG. Figure 56A As shown, the ends of adjacent EL layers may overlap, but the present invention is not limited to this. In other words, adjacent EL layers may be separated without overlapping. Furthermore, adjacent EL layers may have both overlapping portions and separated portions without overlapping.

[0629] EL layer 313R, EL layer 313G, and EL layer 313B each include at least a light-emitting layer. The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light in a color such as blue, purple, bluish-purple, green, yellow-green, yellow, orange, or red can be used as appropriate. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0630] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0631] In addition to the light-emitting substance (guest material), the light-emitting layer may also contain one or more organic compounds (host material, auxiliary material, etc.). As the one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used. In addition, as the one or more organic compounds, a bipolar substance (a substance with high electron transport properties and hole transport properties) or a TADF material can also be used.

[0632] For example, the light-emitting layer preferably comprises a combination of a phosphorescent material, a hole transport material that easily forms an exciplex, and an electron transport material. By adopting such a structure, it is possible to efficiently obtain light emission by ExTET (Exciplex-Triplet Energy Transfer) that utilizes energy transfer from the exciplex to the luminescent substance (phosphorescent material). By selecting a combination of exciplexes that emit light with a wavelength overlapping with the absorption band on the lowest energy side of the luminescent substance, energy transfer can be smoothed, thereby efficiently obtaining light emission. By adopting the above structure, high efficiency, low voltage drive, and long life of the light-emitting element can be achieved at the same time.

[0633] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injection layer), a layer containing a hole-transporting material (hole-transport layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injection layer), a layer containing an electron-transporting material (electron-transport layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer). Furthermore, the EL layer may include one or both of a bipolar material and a TADF material.

[0634] The light-emitting element can use low molecular weight compounds or high molecular weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (vacuum vapor deposition, etc.), transfer, printing (inkjet, etc.), or coating (spin coating, etc.).

[0635] The light-emitting element can adopt a single structure (including a structure with only one light-emitting unit) or a series structure (including a structure with multiple light-emitting units). The light-emitting unit includes at least one light-emitting layer. The series structure has a structure in which multiple light-emitting units are connected in series through a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. By adopting a series structure, a light-emitting element that can emit light with high luminous intensity can be realized. In addition, the series structure can improve reliability because it can reduce the current required to obtain the same luminous intensity compared to the single structure. In addition, the series structure can also be called a stacked structure.

[0636] exist Figure 56A When a tandem structure is used as a light-emitting element, it is preferred that the EL layer 313R include multiple light-emitting units that emit red light, the EL layer 313G include multiple light-emitting units that emit gr...

Claims

1. A driving circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; a first capacitor; as well as a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring, wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first wiring, The gate of the first transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to the gate of the fifth transistor, the first terminal of the third transistor, and the first terminal of the first capacitor. The second terminal of the third transistor and the second terminal of the fourth transistor are electrically connected to the second wiring. The second terminal of the first transistor is electrically connected to the third wiring, A second terminal of the second transistor is electrically connected to the fourth wiring, The gate of the third transistor and the gate of the fourth transistor are electrically connected to the fifth wiring. The second terminal of the first capacitor is electrically connected to the sixth wiring. The fifth wiring is configured to transmit a first clock signal. Furthermore, the sixth wiring is configured to transmit a second clock signal having a phase different from that of the first clock signal.

2. The driving circuit according to claim 1, comprising: First circuit, The first circuit includes a first terminal and a second terminal, The first terminal of the first circuit is electrically connected to the first terminal of the third transistor, And the second terminal of the first circuit is electrically connected to the gate of the second transistor.

3. The driving circuit according to claim 2, wherein the fourth wiring is configured to transmit a first potential, The third wiring is configured to transmit a second potential greater than the first potential. And the first circuit is configured to output the first potential to the first terminal of the first circuit according to the first clock signal and the second clock signal, so that the first terminal of the first circuit is in a high impedance state, output the first potential to the second terminal of the first circuit, and output the second potential to the second terminal of the first circuit.

4. The driving circuit according to claim 1, wherein the first wiring is configured to transmit an output signal, And the second wiring is configured to transmit a start pulse signal.

5. The driving circuit according to claim 1, comprising: The second capacitor, wherein a first terminal of the second capacitor is electrically connected to the gate of the first transistor, And a second terminal of the second capacitor is electrically connected to the first terminal of the first transistor. 6 . The driving circuit according to claim 1 , wherein a channel width of the first transistor is larger than a channel width of the fifth transistor.

7. A driving circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; a first capacitor; as well as a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring, wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first wiring, The gate of the first transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to the gate of the fifth transistor, the first terminal of the third transistor, and the first terminal of the first capacitor. The second terminal of the third transistor and the second terminal of the fourth transistor are electrically connected to the second wiring. The second terminal of the first transistor is electrically connected to the third wiring, A second terminal of the second transistor is electrically connected to the fourth wiring, The gate of the third transistor and the gate of the fourth transistor are electrically connected to the fifth wiring. The second terminal of the first capacitor is electrically connected to the sixth wiring. The fifth wiring is configured to transmit a first clock signal. The sixth wiring is configured to transmit a second clock signal having a phase different from that of the first clock signal. The gate of the sixth transistor is electrically connected to the first terminal of the ninth transistor, the first terminal of the tenth transistor, and the gate of the eleventh transistor. The first terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor, The second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor and the gate of the second transistor. The first terminal of the eleventh transistor is electrically connected to the first terminal of the twelfth transistor, The second terminal of the eleventh transistor is electrically connected to the first terminal of the third transistor, The gate of the eighth transistor and the gate of the tenth transistor are electrically connected to the first terminal of the fourth transistor, A second terminal of the sixth transistor is electrically connected to the sixth wiring. The gate of the seventh transistor is electrically connected to the sixth wiring, A second terminal of the eighth transistor is electrically connected to the fourth wiring, A second terminal of the ninth transistor is electrically connected to the third wiring. The gate of the ninth transistor is electrically connected to the fifth wiring. A second terminal of the tenth transistor is electrically connected to the fifth wiring, A second terminal of the twelfth transistor is electrically connected to the fourth wiring, And the gate of the twelfth transistor is electrically connected to the sixth wiring.

8. The driving circuit according to claim 7, wherein the sixth transistor to the twelfth transistor are located in a first circuit, The fourth wiring is configured to transmit a first potential. The third wiring is configured to transmit a second potential greater than the first potential. And the first circuit is configured to output the first potential to the first terminal of the first circuit according to the first clock signal and the second clock signal, put the first terminal of the first circuit into a high impedance state, output the first potential to the second terminal of the first circuit, and output the second potential to the second terminal of the first circuit.

9. The driving circuit according to claim 7, wherein the first wiring is configured to transmit an output signal, And the second wiring is configured to transmit a start pulse signal.

10. The driving circuit according to claim 7, comprising: The second capacitor, wherein a first terminal of the second capacitor is electrically connected to the gate of the first transistor, And a second terminal of the second capacitor is electrically connected to the first terminal of the first transistor. 11 . The driving circuit according to claim 7 , wherein a channel width of the first transistor is larger than a channel width of the fifth transistor.

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