Timing controller and display device including same

Abstract

The invention relates to a timing controller and a display device including the same. The timing controller includes: a control signal generator configured to generate a plurality of control signals; an output pad unit including a plurality of output pads for outputting the plurality of control signals to the outside of the timing controller; and a plurality of transmission lines connecting the output pad unit to the control signal generator, in which the plurality of output pads are grouped into a plurality of sub-pad groups, and each of the plurality of sub-pad groups includes P number of output pads, and in which P represents the number of output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, the P output pads are electrically connected to each other. The P output pads are adjacent to each other in a first direction, and the output pad units are spaced apart from the control signal generator in a second direction crossing the first direction.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2024-0035058, filed on March 13, 2024, and the contents of that Korean Patent Application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a timing controller and a display device including the same. Background Art

[0003] The timing controller can provide control signals to the display panel through the pads. When the voltage difference between adjacent pads is large, a strong electric field can be generated between the adjacent pads, and thus charge can move. As a result, corrosion of the pads can occur. Since corrosion in the pads can cause increased resistance, disconnection, short circuits, joint defects, etc., corrosion can reduce the reliability of the display device.

[0004] The above-described contents are merely intended to help understand the background technology of the technical idea of ​​the present disclosure, and therefore cannot be understood as the contents corresponding to the prior art known to those skilled in the art in the field of the present disclosure. Summary of the Invention

[0005] Embodiments of the present disclosure are used to minimize corrosion of pads included in a timing controller. More specifically, embodiments of the present disclosure minimize corrosion of pads by reducing a voltage difference between adjacent pads of the timing controller.

[0006] According to an aspect of the present disclosure, a timing controller includes: a control signal generator configured to generate a plurality of control signals; an output pad unit including a plurality of output pads for outputting the plurality of control signals to the outside of the timing controller; and a plurality of transmission lines connecting the output pad unit to the control signal generator, wherein the plurality of output pads are grouped into a plurality of sub-pad groups, and each of the plurality of sub-pad groups includes P output pads, and wherein P represents the number of output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, the P output pads are electrically connected to each other, the P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction intersecting the first direction.

[0007] Each of the plurality of output pads included in the output pad unit may have a first length in the first direction and a second length in the second direction. The second length is longer than the first length.

[0008] The plurality of output pads included in the output pad unit are arranged into a plurality of rows and a plurality of columns. Each of the plurality of rows extends in a first direction, and the plurality of rows are spaced apart from each other in a second direction. Each of the plurality of columns extends in a second direction, and the plurality of columns are spaced apart from each other in the first direction. The output pads in each of the plurality of rows are spaced apart from each other by a third length in the first direction. The output pads in each of the plurality of columns are spaced apart from each other in the second direction by a fourth length that is longer than the third length.

[0009] The output pad unit may further include a plurality of dummy pads that do not output a control signal to the outside.

[0010] Each of the plurality of sub-pad groups may be connected to the control signal generator through a corresponding one of the plurality of transmission lines.

[0011] The plurality of sub-pad groups include a first sub-pad group and a second sub-pad group. The first sub-pad group and the second sub-pad group are adjacent to each other in a second direction. The plurality of transmission lines include a first transmission line connected to the first sub-pad group and a second transmission line connected to the second sub-pad group. At least a portion of the first transmission line overlaps with the second transmission line in a third direction perpendicular to the first and second directions.

[0012] The first sub-pad group outputs a first control signal among multiple control signals to the outside of the timing controller through a first transmission line, and the second sub-pad group outputs a second control signal among multiple control signals to the outside of the timing controller through a second transmission line, and the second control signal is different from the first control signal.

[0013] According to aspects of the present disclosure, a display device includes: a plurality of pixels connected to a plurality of gate lines; a gate driver configured to supply a plurality of gate signals to the plurality of pixels via the plurality of gate lines; a plurality of gate pads configured to transmit a plurality of control signals to the gate driver via a plurality of control lines; and a timing controller configured to supply the plurality of control signals to the plurality of gate pads. The timing controller includes: a control signal generator configured to generate a plurality of control signals; an output pad unit including a plurality of output pads for outputting the plurality of control signals to an outside of the timing controller; and a plurality of transmission lines connecting the output pad unit to the control signal generator, wherein the plurality of output pads are grouped into a plurality of sub-pad groups, and each of the plurality of sub-pad groups includes P output pads, and wherein P represents the number of output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, and the P output pads are electrically connected to each other. The P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction intersecting the first direction.

[0014] Each of the plurality of output pads included in the output pad unit may have a first length in the first direction and a second length in the second direction. The second length is longer than the first length.

[0015] The plurality of output pads included in the output pad unit are arranged into a plurality of rows and a plurality of columns. Each of the plurality of rows extends in a first direction, and the plurality of rows are spaced apart from each other in a second direction. Each of the plurality of columns extends in a second direction, and the plurality of columns are spaced apart from each other in the first direction. The output pads in each of the plurality of rows are spaced apart from each other by a third length in the first direction. The output pads in each of the plurality of columns are spaced apart from each other in the second direction by a fourth length that is longer than the third length.

[0016] The output pad unit may further include a plurality of dummy pads that do not output a control signal to the outside.

[0017] Each of the plurality of sub-pad groups may be connected to the control signal generator through a corresponding one of the plurality of transmission lines.

[0018] The plurality of sub-pad groups include a first sub-pad group and a second sub-pad group. The first sub-pad group and the second sub-pad group are adjacent to each other in a second direction. The plurality of transmission lines include a first transmission line connected to the first sub-pad group and a second transmission line connected to the second sub-pad group. At least a portion of the first transmission line overlaps with the second transmission line in a third direction perpendicular to the first and second directions.

[0019] The first sub-pad group outputs a first control signal among multiple control signals to the outside of the timing controller through a first transmission line, and the second sub-pad group outputs a second control signal among multiple control signals to the outside of the timing controller through a second transmission line, and the second control signal is different from the first control signal.

[0020] According to aspects of the present disclosure, a timing controller includes: a control signal generator configured to generate a plurality of control signals; an output pad unit including a plurality of output pads for outputting the plurality of control signals to an outside of the timing controller, wherein the plurality of output pads are grouped into a plurality of sub-pad groups, the plurality of sub-pad groups being arranged in a plurality of rows and a plurality of columns, and each of the plurality of sub-pad groups including P output pads, wherein P represents the number of output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, the P output pads being electrically connected to one another, and a plurality of transmission lines, each of the plurality of transmission lines connecting a corresponding group of the plurality of sub-pad groups to the control signal generator. The P output pads are adjacent to one another in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction intersecting the first direction. Each of the plurality of rows extends in the first direction, and the plurality of rows are spaced apart from one another in the second direction. Each of the plurality of columns extends in the second direction, and the plurality of columns are spaced apart from one another in the first direction.

[0021] P can be 3.

[0022] Each of the plurality of sub-pad groups comprises a first output pad, a second output pad, and a third output pad, the first output pad, the second output pad, and the third output pad being spaced apart from each other in a first direction and connected to each other, and the second output pad being disposed between the first output pad and the third output pad.

[0023] Each of the multiple transmission lines includes a first portion, two second portions, and a third portion, the first portion including a first output pad connected to a corresponding group of the multiple sub-pad groups, the two second portions respectively connecting the first output pad to the second output pad and connecting the third output pad to the second output pad, and the third portion electrically connected to the gate pad of the display panel.

[0024] Each of the plurality of output pads included in the output pad unit has a first length in the first direction and a second length in the second direction. The second length is longer than the first length.

[0025] The output pads in each of the plurality of rows are spaced apart from each other by a third length in the first direction. The output pads in each of the plurality of columns are spaced apart from each other by a fourth length in the second direction that is longer than the third length.

[0026] According to an embodiment of the present disclosure, corrosion of pads included in a timing controller can be minimized. More specifically, corrosion of the pads can be minimized by reducing a voltage difference between adjacent pads of the timing controller.

[0027] The effects according to the embodiment are not limited to the contents of the above examples, and further various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0029] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure;

[0030] Figure 2 It shows Figure 1 Schematic diagram of the timing controller;

[0031] Figure 3 It is shown that the Figure 1 a circuit diagram of one embodiment of a pixel in a display device;

[0032] Figure 4 It shows Figure 1 A schematic diagram of an output pad unit;

[0033] Figure 5 According to another embodiment Figure 1 A schematic diagram of an output pad unit;

[0034] Figure 6 According to yet another embodiment Figure 1 A schematic diagram of an output pad unit;

[0035] Figure 7 yes Figure 6 an enlarged view of a portion X;

[0036] Figure 8 It shows Figure 7 Figures of implementation methods;

[0037] Figure 9 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; and

[0038] Figure 10 It shows Figure 9 FIG2 is a diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure are described, and descriptions of other parts are omitted to avoid obscuring the subject matter of the present disclosure. In addition, the present disclosure may be embodied in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are intended to be described in sufficient detail so that those skilled in the art of the present disclosure can easily realize the technical spirit of the present disclosure.

[0040] Throughout the specification, when a part is "connected" to another part, the situation not only includes the situation that the part is "directly connected" to the other part, but also includes the situation that the part is "indirectly connected" to the other part and another element is inserted between the part and the other part. The terms used in this article are used to describe specific embodiments and are not intended to limit the present disclosure. Throughout the specification, when a certain part "includes...", unless otherwise stated, the situation means that the part can also include another component, without excluding another component. "At least any one of X, Y and Z" and "at least any one of the group consisting of X, Y and Z" can be interpreted as any combination of two or more of X, Y and Z (such as XYZ, XY, YZ and XZ). In this article, "and / or" includes all combinations of one or more in the corresponding configuration.

[0041] In this document, terms such as first and second may be used to describe various components, but the components are not limited to these terms. These terms are used to distinguish one component from another. Therefore, a first component can refer to a second component within a scope without departing from the scope disclosed herein.

[0042] For descriptive purposes, spatially relative terms such as "under," "over," and the like may be used herein to describe the relationship between one element or feature and another element(s) or feature(s) as shown in the accompanying drawings. In addition to the directions depicted in the accompanying drawings, spatially relative terms are intended to include other directions in use, operation, and / or manufacture. For example, when the device shown in the figures is inverted, elements described as being "under" other elements or features are positioned in a direction "over" the other elements or features. Thus, in an embodiment, the term "under" may include both directions, over and under. Additionally, the device may be facing other directions (e.g., rotated 90 degrees or in other directions), and therefore, the spatially relative terms used herein are interpreted accordingly.

[0043] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate idealized embodiments. Therefore, it is expected that shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown and should be construed to include variations in shape that may occur, for example, due to manufacturing. As described above, the shapes shown in the accompanying drawings may not represent the actual shapes of regions of the device, and the embodiments are not limited thereto.

[0044] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure.

[0045] Reference Figure 1, the display device DD may include a display panel DP, a gate driver GDV (or a gate driving circuit GDV), a data driver DDV (or a data driving circuit DDV), and a timing control unit TC (or a timing controller circuit TC).

[0046] The display panel DP may include a substrate SUB. The substrate SUB (or display panel DP) may include a display area DA that displays an image and a non-display area NDA surrounding the display area DA (e.g., an edge area of ​​the display area DA). Pixels PXL may be disposed on the display panel DP. A gate driver GDV, gate pads GPAD_G, data pads DPAD_G, voltage pads PPAD_G, signal lines, and the like may be disposed in the non-display area NDA. The non-display area NDA may include a pad area A_PAD located on one side of the display area DA. The gate pads GPAD_G, data pads DPAD_G, and voltage pads PPAD_G may be disposed in the pad area A_PAD.

[0047] The display panel DP may include gate lines S1 to Sn (where n is a positive integer), data lines D1 to Dm (where m is a positive integer), a gate pad GPAD_G, a data pad DPAD_G, and a voltage pad PPAD_G.

[0048] The gate lines S1 to Sn may extend longitudinally in a first direction DR1 and may be sequentially arranged along a second direction DR2 intersecting the first direction DR1. The data lines D1 to Dm may extend longitudinally in a second direction DR2 and may be sequentially arranged along the first direction DR1. Each of the pixels PXL may be connected to one of the gate lines S1 to Sn and one of the data lines D1 to Dm. The gate pad GPAD_G may be connected to a control line CL formed on the display panel DP and may transmit a control signal (e.g., a gate driver control signal) provided from the outside (e.g., a timing controller TC) to the control line CL. According to an embodiment, the gate pad GPAD_G may amplify the control signal (e.g., a gate driver control signal) provided from the outside and transmit the amplified control signal to the control line CL.

[0049] The gate pad GPAD_G may be configured to transmit a control signal (eg, a gate driver control signal) to the gate driver GDV through the control line CL. The gate driver control signal may include a start signal (or start pulse), a clock signal, etc. The gate driver control signal may be provided from the timing controller TC.

[0050] The data pad DPAD_G may be configured to transmit a data signal (or data voltage) to the data lines D1 to Dm. The data signal may be provided from the data driver DDV. According to an embodiment, the data signal (or data voltage) may be amplified in the data pad DPAD_G.

[0051] The power pad PPAD_G can transmit the first power voltage ELVDD to the pixel PXL through the first power line ELVDDL (see Figure 2 The power pad PPAD_G can transmit the second power voltage ELVSS to the pixel PXL through the second power line ELVSSL (see Figure 2 ). The first power voltage ELVDD and the second power voltage ELVSS may be power voltages required for the operation of the pixel PXL and may be provided from a power supply (not shown). The first power voltage ELVDD may have a voltage level higher than that of the second power voltage ELVSS.

[0052] The gate driver GDV may generate gate signals based on the gate driver control signal and provide the gate signals to the gate lines S1 to Sn.

[0053] The gate driver GDV may include an emission driver (not shown).

[0054] According to an embodiment, the gate driver GDV may be integrated with the pixel PXL and formed on the display panel DP. However, the embodiments of the present disclosure are not limited thereto. For example, the gate driver GDV may be implemented as an integrated circuit separated from the display panel DP and may be mounted on the panel drive circuit PDC. Figure 1 In the embodiment, the gate driver GDV is shown as being disposed in the non-display area NDA, but embodiments of the present disclosure are not limited thereto. In an embodiment, the gate driver GDV may be distributed in the display area DA (e.g., between the pixels PXL). For example, the gate driver GDV may include sub-gate drivers distributed between the pixels PXL.

[0055] The data driver DDV can receive data control signals and image data from the timing controller TC and generate data signals (or data voltages) corresponding to the image data. The data driver DDV can provide the generated data signals to the display panel DP. For example, the data driver DDV can generate data signals corresponding to the grayscale values ​​in the image data and provide the data signals to the data lines D1 to Dm via the data pads DPAD_G in units of pixel rows.

[0056] The data driver DDV may be mounted on the panel driving circuit PDC, may be connected to the timing controller TC, and may be connected to the data lines D1 to Dm through the data pads DPAD_G.

[0057] The timing controller TC can control the gate driver GDV and the data driver DDV. The timing controller TC can receive input image data (e.g., RGB data) and external signals from an external device (e.g., a graphics processor, a set-top box, etc.), generate control signals (e.g., gate driver control signals, emission driver control signals, and data driver control signals) based on the external signals, and generate image data by converting the input image data. The external signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a reference clock signal, etc. For example, the timing controller TC can convert the input image data into image data having a format that matches the pixel arrangement in the display panel DP. The timing controller TC can be mounted on the panel drive circuit PDC.

[0058] exist Figure 1 In FIG. 5 , the data driver DDV and the timing controller TC are shown as being implemented as separate integrated circuits, but the embodiments of the present disclosure are not limited thereto. For example, the data driver DDV and the timing controller TC may be implemented as one integrated circuit.

[0059] Figure 2 It shows Figure 1 Schematic diagram of the timing controller.

[0060] Reference Figure 2 , the timing controller TC may include a control signal generator CSG (ie, a control signal generator circuit), an output pad unit TOP, and a transmission line TL.

[0061] The control signal generator CSG can receive input image data (e.g., RGB data) and external signals from an external device (e.g., a graphics processor, a set-top box, etc.), generate control signals (e.g., gate driver control signals, emission driver control signals, and data driver control signals) based on the external signals, and generate image data by converting the input image data. The external signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a reference clock signal, etc. For example, the timing controller TC can convert the input image data into image data having a format that matches the pixel arrangement in the display panel DP.

[0062] The control signal generator CSG may transmit the generated control signals (eg, gate driver control signals and emission driver control signals) to the output pad unit TOP through the transmission line TL.

[0063] The output pad unit TOP may be arranged to be spaced apart from the control signal generator CSG in the second direction DR2 .

[0064] The output pad unit TOP may include a plurality of pads having the same size and shape.

[0065] The pads of the output pad unit TOP may be configured to transmit control signals (eg, gate driver control signals and emission driver control signals) generated from the control signal generator CSG to the gate pad GPAD_G. Figures 4 to 8 Describes the settings of the pads of the output pad unit TOP, etc.

[0066] The image data and the data driver control signal generated in the control signal generator CSG may be transmitted to the data driver DDV through separate pads (not shown).

[0067] Figure 3 It is shown that the Figure 1 Schematic circuit diagram of an embodiment of one of the pixels PXL in the display device DD. Figure 1 The pixels PXL shown may be substantially the same or similar to each other. For ease of description, a pixel PXLij located in the i-th (i is an integer greater than or equal to 1 and less than or equal to n) pixel row and the j-th (j is an integer greater than or equal to 1 and less than or equal to m) pixel column is described.

[0068] Reference Figure 1 and Figure 3 , the pixel PXLij may include a plurality of transistors, capacitors, and light emitting elements. For example, the pixel PXLij may include a first transistor M1 and a second transistor M2, a storage capacitor Cst, and a light emitting element LD.

[0069] Hereinafter, a case is described in which the transistors M1 and M2 are configured as N-type transistors (e.g., N-type metal oxide semiconductor (NMOS) transistors), but those skilled in the art may configure the first transistor M1 and the second transistor M2 as P-type transistors (e.g., P-type metal oxide semiconductor (PMOS) transistors) or a combination of N-type transistors and P-type transistors.

[0070] The first transistor M1 may have a gate electrode connected to the first node N1 , a first electrode connected to the second node N2 , and a second electrode connected to the first power line ELVDDL to which the first power voltage ELVDD is applied.

[0071] The second transistor M2 may have a gate electrode connected to the i-th gate line Si, a first electrode connected to the j-th data line Dj, and a second electrode connected to the first node N1. The second transistor M2 may be referred to as a switching transistor, etc.

[0072] The storage capacitor Cst may have a first electrode connected to the first node N1 and a second electrode connected to the second node N2 .

[0073] The light emitting element LD may have an anode connected to the second node N2 and a cathode connected to the second power line ELVSS, to which the second power voltage ELVSS is applied. The light emitting element LD may be a light emitting diode. For example, the light emitting element LD may be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0074] In addition, despite the Figure 3 Only one light emitting element LD is shown in FIG. 1 , but the light emitting element LD may be configured by a plurality of ultra-small light emitting elements. For example, a plurality of ultra-small light emitting elements may be connected in series, in parallel, or in series and in parallel.

[0075] Figure 4 It shows Figure 1 FIG2 is a schematic diagram of an output pad unit TOP of FIG2 . The output pad unit TOP may include a plurality of output pads arranged in a plurality of rows and a plurality of columns. Each of the plurality of rows may extend in a first direction DR1, and the plurality of rows may be spaced apart from each other in a second direction DR2. Each of the plurality of columns may extend in a second direction DR2, and the plurality of columns may be spaced apart from each other in the first direction DR1. The plurality of output pads may be grouped into a plurality of sub-pad groups arranged in a plurality of rows and a plurality of columns. The plurality of sub-pad groups may output different control signals, and each of the plurality of sub-pad groups may be used to output the same control signal.

[0076] refer to Figure 4 , the output pad unit TOP may include a plurality of sub-pad groups. For example, the output pad unit TOP may include a first sub-pad group PAD1 to an eighteenth sub-pad group PAD18. However, the embodiments of the present disclosure are not limited thereto. For example, the output pad unit TOP may include 18 or more sub-pad groups. However, hereinafter, for ease of description, an output pad unit TOP including 18 sub-pad groups will be described.

[0077] Each sub-pad group may include a plurality of pads (i.e., output pads). For example, at least one of the sub-pad groups may include P pads (P is an integer greater than or equal to 2). For example, the first sub-pad group PAD1 may include pads PAD1a to PAD1c.

[0078] The second sub pad group PAD2 may include 2a-th to 2c-th pads PAD2a to PAD2c.

[0079] The third sub-pad group PAD3 may include 3a-th to 3c-th pads PAD3a to PAD3c.

[0080] The fourth sub-pad group PAD4 may include 4a-th to 4c-th pads PAD4a to PAD4c.

[0081] The fifth sub-pad group PAD5 may include 5a-th to 5c-th pads PAD5a to PAD5c.

[0082] The sixth sub-pad group PAD6 may include 6a-th to 6c-th pads PAD6a to PAD6c.

[0083] The seventh sub-pad group PAD7 may include 7a-th to 7c-th pads PAD7a to PAD7c.

[0084] The eighth sub-pad group PAD8 may include 8a-th to 8c-th pads PAD8a to PAD8c.

[0085] The ninth sub-pad group PAD9 may include 9a-th to 9c-th pads PAD9a to PAD9c.

[0086] The tenth sub-pad group PAD10 may include a 10a-th pad PAD10a to a 10c-th pad PAD10c. The eleventh sub-pad group PAD11 may include a 11a-th pad PAD11a to a 11c-th pad PAD11c. The twelfth sub-pad group PAD12 may include a 12a-th pad PAD12a to a 12c-th pad PAD12c. The thirteenth sub-pad group PAD13 may include a 13a-th pad PAD13a to a 13c-th pad PAD13c. The fourteenth sub-pad group PAD14 may include a 14a-th pad PAD14a to a 14c-th pad PAD14c. The fifteenth sub-pad group PAD15 may include a 15a-th pad PAD15a to a 15c-th pad PAD15c. The sixteenth sub-pad group PAD16 may include a 16a-th pad PAD16a to a 16c-th pad PAD16c. The seventeenth sub-pad group PAD17 may include 17a-th to 17c-th pads PAD17a, and the eighteenth sub-pad group PAD18 may include 18a-th to 18c-th pads PAD18a, PAD18c.

[0087] The pads included in each of the first to eighteenth sub-pad groups PAD1 to PAD18 may be spaced apart from each other in the first direction DR1 and arranged side by side (or adjacent to each other). For example, in the first sub-pad group PAD1, the 1a-th pad PAD1a may be arranged adjacent to the 1b-th pad PAD1b in a direction opposite to the first direction DR1, and the 1c-th pad PAD1c may be arranged adjacent to the 1b-th pad PAD1b in the first direction DR1. In an embodiment, the first sub-pad group PAD1 may be composed of three pads (such as the 1a-th pad PAD1a, the 1b-th pad PAD1b, and the 1c-th pad PAD1c) arranged side by side in the first direction DR1. The 1b-th pad PAD1b may be arranged in the space between the 1a-th pad PAD1a and the 1c-th pad PAD1c. For example, in the second sub-pad group PAD2, the 2a-th pad PAD2a may be disposed adjacent to the 2b-th pad PAD2b in a direction opposite to the first direction DR1, and the 2c-th pad PAD2c may be disposed adjacent to the 2b-th pad PAD2b in the first direction DR1. In an embodiment, the second sub-pad group PAD2 may be spaced apart from the first sub-pad group PAD1 in the second direction DR2 and may be composed of three pads (such as the 2a-th pad PAD2a, the 2b-th pad PAD2b, and the 2c-th pad PAD2c) arranged side by side in the first direction DR1. The 2b-th pad PAD2b may be disposed in the space between the 2a-th pad PAD2a and the 2c-th pad PAD2c.

[0088] The arrangement form of the pads PAD18a to PAD18c configuring the output pad unit TOP may be as follows.

[0089] The second sub-pad group PAD2 may be arranged adjacent to the first sub-pad group PAD1 in the second direction DR2. The third sub-pad group PAD3 may be arranged adjacent to the second sub-pad group PAD2 in the second direction DR2. The fourth sub-pad group PAD4 may be arranged adjacent to the first sub-pad group PAD1 in the first direction DR1. The fifth sub-pad group PAD5 may be arranged adjacent to the second sub-pad group PAD2 in the first direction DR1. The sixth sub-pad group PAD6 may be arranged adjacent to the third sub-pad group PAD3 in the first direction DR1. The seventh sub-pad group PAD7 may be arranged adjacent to the fourth sub-pad group PAD4 in the first direction DR1. The eighth sub-pad group PAD8 may be arranged adjacent to the fifth sub-pad group PAD5 in the first direction DR1. The ninth sub-pad group PAD9 may be arranged adjacent to the sixth sub-pad group PAD6 in the first direction DR1. The tenth sub-pad group PAD10 may be arranged adjacent to the seventh sub-pad group PAD7 in the first direction DR1. The eleventh sub-pad group PAD11 may be arranged adjacent to the eighth sub-pad group PAD8 in the first direction DR1. The twelfth sub-pad group PAD12 may be arranged adjacent to the ninth sub-pad group PAD9 in the first direction DR1. The thirteenth sub-pad group PAD13 may be arranged adjacent to the tenth sub-pad group PAD10 in the first direction DR1. The fourteenth sub-pad group PAD14 may be arranged adjacent to the eleventh sub-pad group PAD11 in the first direction DR1. The fifteenth sub-pad group PAD15 may be arranged adjacent to the twelfth sub-pad group PAD12 in the first direction DR1. The sixteenth sub-pad group PAD16 may be arranged adjacent to the thirteenth sub-pad group PAD13 in the first direction DR1. The seventeenth sub-pad group PAD17 may be arranged adjacent to the fourteenth sub-pad group PAD14 in the first direction DR1. The eighteenth sub-pad group PAD18 may be arranged adjacent to the fifteenth sub-pad group PAD15 in the first direction DR1. When the first to eighteenth sub pad groups PAD1 to PAD18 are arranged as described above, the pads included in the output pad unit TOP may be arranged in three rows extending in the first direction DR1 and spaced apart from each other in the second direction DR2.

[0090] The first to eighteenth sub-pad groups PAD1 to PAD18 can transmit different control signals (e.g., gate driver control signals) to the gate pads GPAD_G via transmission lines TL. For example, pads PAD1a to PAD1c 1a included in the first sub-pad group PAD1 can transmit a first gate driver control signal among the gate driver control signals to one of the gate pads GPAD_G. In an embodiment, pads PAD1a to PAD1c 1a in the first sub-pad group PAD1 can be connected to each other and can be used to transmit the first gate driver control signal to the first gate pad among the gate pads GPAD_G.

[0091] The 2a-th pads PAD2a through 2c-th pads PAD2c included in the second sub-pad group PAD2 can transmit a second gate driver control signal among the gate driver control signals to one of the gate pads GPAD_G. In an embodiment, the 2a-th pads PAD2a through 2c-th pads PAD2c in the second sub-pad group PAD2 can be connected to each other and can be used to transmit the second gate driver control signal to a second gate pad among the gate pads GPAD_G. In this case, the first gate driver control signal and the second gate driver control signal can be different from each other, and the first gate pad can be different from the second gate pad.

[0092] Figure 5 It shows that according to the embodiment Figure 1 Schematic diagram of the output pad unit TOP.

[0093] Reference Figure 5 , omitted below and reference Figure 4 The descriptions of the first to eighteenth sub-pad groups PAD1 to PAD18 overlap.

[0094] The specific arrangement form of the pads PAD1a to PAD18c constituting the output pad unit TOP may be as follows.

[0095] The second sub-pad group PAD2 may be arranged adjacent to the first sub-pad group PAD1 in the second direction DR2. The third sub-pad group PAD3 may be arranged adjacent to the second sub-pad group PAD2 in the second direction DR2. The fourth sub-pad group PAD4 may be arranged adjacent to the third sub-pad group PAD3 in the second direction DR2. The fifth sub-pad group PAD5 may be arranged adjacent to the fourth sub-pad group PAD4 in the second direction DR2. The sixth sub-pad group PAD6 may be arranged adjacent to the fifth sub-pad group PAD5 in the second direction DR2. The seventh sub-pad group PAD7 may be arranged adjacent to the first sub-pad group PAD1 in the first direction DR1. The eighth sub-pad group PAD8 may be arranged adjacent to the second sub-pad group PAD2 in the first direction DR1. The ninth sub-pad group PAD9 may be arranged adjacent to the third sub-pad group PAD3 in the first direction DR1. The tenth sub-pad group PAD10 may be arranged adjacent to the fourth sub-pad group PAD4 in the first direction DR1. The eleventh sub-pad group PAD11 may be arranged adjacent to the fifth sub-pad group PAD5 in the first direction DR1. The twelfth sub-pad group PAD12 may be arranged adjacent to the sixth sub-pad group PAD6 in the first direction DR1. The thirteenth sub-pad group PAD13 may be arranged adjacent to the seventh sub-pad group PAD7 in the first direction DR1. The fourteenth sub-pad group PAD14 may be arranged adjacent to the eighth sub-pad group PAD8 in the first direction DR1. The fifteenth sub-pad group PAD15 may be arranged adjacent to the ninth sub-pad group PAD9 in the first direction DR1. The sixteenth sub-pad group PAD16 may be arranged adjacent to the tenth sub-pad group PAD10 in the first direction DR1. The seventeenth sub-pad group PAD17 may be arranged adjacent to the eleventh sub-pad group PAD11 in the first direction DR1. The eighteenth sub-pad group PAD18 may be arranged adjacent to the twelfth sub-pad group PAD12 in the first direction DR1.

[0096] However, the embodiments of the present disclosure are not limited thereto. The first to eighteenth sub-pad groups PAD1 to PAD18 may be arranged in the same manner as Figure 4 and Figure 5 The forms shown are arranged differently in the individual rows and columns.

[0097] Figure 6 It shows that according to the embodiment Figure 1 Figure 1. Output pad unit TOP.

[0098] refer to Figure 6 The output pad unit TOP may include a plurality of sub-pad groups and dummy pads. For example, the output pad unit TOP may include the first to thirteenth sub-pad groups PAD1 to PAD13 and the first to fifteenth dummy pads DP1 to DP15. Figure 4The descriptions of the first to thirteenth sub-pad groups PAD1 to PAD13 overlap.

[0099] The pads included in the first to thirteenth sub-pad groups PAD1 to PAD13 may be pads that receive gate driver control signals from the timing controller TC. On the other hand, the dummy pads DP1 to DP15 may be pads that do not receive any signals from the timing controller TC. As used herein, the term "dummy" refers to pads that have the same or similar structure and shape as the pads of each of the first to thirteenth sub-pad groups PAD1 to PAD13 but do not have a substantial function and exist only as a pattern in the output pad unit TOP.

[0100] exist Figure 6 In the embodiment, the first to eighteenth sub-pad groups PAD1 to PAD18 (reference Figure 4 ) in the fourteenth to eighteenth sub-pad groups PAD14 to PAD18 are used as dummy pads, but the present disclosure is not necessarily limited thereto. The number and placement positions of the dummy pads may vary depending on the product.

[0101] Figure 7 yes Figure 6 Magnified view of section X.

[0102] Reference Figure 6 and Figure 7 Each of the pads PAD1a to PAD13c may have a width equal to the first length L1 in the first direction DR1. Furthermore, each of the pads PAD1a to PAD13c may have a width equal to the second length L2 in the second direction DR2. For example, the 10a-th pad PAD10a may have a width equal to the first length L1 in the first direction DR1 and a width equal to the second length L2 in the second direction DR2.

[0103] The pads adjacent to each other in the first direction DR1 may be spaced apart by a third length L3. For example, the 10ath pad PAD10a and the 13ath pad PAD13a may be spaced apart by a third length L3. For example, the 13ath pad PAD13a and the 13bth pad PAD13b may be spaced apart by a third length L3.

[0104] The pads adjacent to each other in the second direction DR2 may be spaced apart by a fourth length L4. For example, the 11c-th pad PAD11c and the 12c-th pad PAD12c may be spaced apart by a fourth length L4. The fourth dummy pad DP4 and the 13a-th pad PAD13a may be spaced apart by a fourth length L4.

[0105] The distance between adjacent pads in the second direction DR2 can be formed to be wider than the distance between adjacent pads in the first direction DR1. In other words, the fourth length L4 can be larger than the third length L3. Therefore, the influence of the electric field caused by the voltage difference between adjacent pads in the second direction DR2 can be smaller than the influence of the electric field caused by the voltage difference between adjacent pads in the first direction DR1.

[0106] The width of each pad in the first direction DR1 can be smaller than the width of each pad in the second direction DR2. In other words, the first length L1 can be smaller than the second length L2. The area facing each other between adjacent pads in the second direction DR2 can be smaller than the area facing each other between adjacent pads in the first direction DR1. Therefore, the influence of the electric field caused by the voltage difference between adjacent pads in the second direction DR2 can be smaller than the influence of the electric field caused by the voltage difference between adjacent pads in the first direction DR1.

[0107] The transmission line TL may include a first portion, a second portion, and a third portion. The first portion of the transmission line TL may be connected to a control signal generator CSG (reference Figure 2 ) and one of the pads included in the sub-pad group. The second portion of the transmission line TL can connect the pads included in the sub-pad group. The third portion of the transmission line TL can be connected between one of the pads included in the sub-pad group and one of the gate pads GPAD_G. For example, the first portion TL13a of the thirteenth transmission line TL13 can connect the control signal generator CSG to the 13a-th pad PAD13a. The second portions TL13b and TL13c of the thirteenth transmission line TL13 can connect the 13a-th pad PAD13a to the 13c-th pad PAD13c. For example, the second portion TL13b can connect the 13a-th pad PAD13a to the 13b-th pad PAD13b, and the second portion TL13c can connect the 13b-th pad PAD13b to the 13c-th pad PAD13c. The third portion TL13d of the thirteenth transmission line TL13 may connect the 13d-th pad PAD13d to one of the gate pads GPAD_G.

[0108] Each sub-pad group can be connected to the gate pad GPAD_G through a different transmission line TL. Figure 7, the tenth sub-pad group PAD10 including the 10c-th pad PAD10c can be connected to the gate pad GPAD_G through the tenth transmission line TL10. The eleventh sub-pad group PAD11 including the 11c-th pad PAD11c can be connected to the gate pad GPAD_G through the eleventh transmission line TL11. The twelfth sub-pad group PAD12 including the 12c-th pad PAD12c can be connected to the gate pad GPAD_G through the twelfth transmission line TL12. The thirteenth sub-pad group PAD13 can be connected to the gate pad GPAD_G through the thirteenth transmission line TL13.

[0109] In addition, each control signal (e.g., gate driver control signal) can be transmitted to the gate pad GPAD_G through a pad included in one of the pad groups. For example, the tenth gate signal can be transmitted to the gate pad GPAD_G through the 10a-th pads PAD10a to PAD10c included in the tenth sub-pad group PAD10. The eleventh gate signal can be transmitted to the gate pad GPAD_G through the 11a-th pads PAD11a to PAD11c included in the eleventh sub-pad group PAD11. The twelfth gate signal can be transmitted to the gate pad GPAD_G through the 12a-th pads PAD12a to PAD12c included in the twelfth sub-pad group PAD12. The thirteenth gate signal can be transmitted to the gate pad GPAD_G through the 13a-th pads PAD13a to PAD13c included in the thirteenth sub-pad group PAD13.

[0110] According to an embodiment, some of the transmission lines TL connected to the adjacent sub-pad groups in the second direction DR2 may be formed in different layers and may overlap with each other in the third direction DR3. For example, the eleventh transmission line TL11 and the twelfth transmission line TL12 may be formed in different layers and may overlap with each other in the third direction DR3.

[0111] Figure 8 It shows Figure 7 FIG. 1 is a diagram of an embodiment of the present invention.

[0112] refer to Figure 7 and Figure 8, voltage differences can be formed between different pads. For example, a first voltage difference V1 can be formed between the 13a-th pad PAD13a and the 10c-th pad PAD10c, which are adjacent to each other in the first direction DR1. A second voltage difference V2 can be formed between the 13a-th pad PAD13a and the 13b-th pad PAD13b, which are adjacent to each other in the first direction DR1. A second voltage difference V2 can be formed between the 13c-th pad PAD13c and the 13b-th pad PAD13b, which are adjacent to each other in the first direction DR1. A third voltage difference V3 can be formed between the first dummy pad DP1 and the 13c-th pad PAD13c, which are adjacent to each other in the first direction DR1. A fourth voltage difference V4 can be formed between the 13a-th pad PAD13a and the fourth dummy pad DP4, which are adjacent to each other in the second direction DR2. A fourth voltage difference V4 can be formed between the 13b-th pad PAD13b and the fifth dummy pad DP5, which are adjacent to each other in the second direction DR2. A fourth voltage difference V4 may be formed between the 13c-th pad PAD13c and the sixth dummy pad DP6 that are adjacent to each other in the second direction DR2.

[0113] Among the first to fourth voltage differences V1 to V4 , the second voltage difference V2 may be smallest in magnitude.

[0114] When the voltage difference between adjacent pads is large, a strong electric field may be generated between them, and thus charge may migrate. Therefore, corrosion of the pads may occur due to the charge transfer. Since corrosion occurring in the pads may cause increased resistance, disconnection, short circuits, joint defects, etc., corrosion may be a cause of reduced reliability of display devices (DD).

[0115] According to an embodiment of the present disclosure, the distance between the pads adjacent in the second direction DR2 can be formed to be wider than the distance between the pads adjacent in the first direction DR1. Therefore, the influence of the electric field caused by the voltage difference between the pads adjacent in the second direction DR2 can be smaller than the influence of the electric field caused by the voltage difference between the pads adjacent in the first direction DR1. For example, the fourth length L4 (refer to the fourth dummy pad DP4) between the 13a pad PAD13a and the fourth dummy pad DP4 is Figure 6 ) may be larger than the third length L3 (reference length L2) between the 13a-th pad PAD13a and the 10c-th pad PAD10c. Figure 6 Therefore, the influence of the electric field between the 13a-th pad PAD13a and the fourth dummy pad DP4 may be smaller than the influence of the electric field between the 13a-th pad PAD13a and the 10c-th pad PAD10c.

[0116] Furthermore, according to an embodiment of the present disclosure, a pad located at the center of the pads included in a sub-pad group may not be affected by an electric field generated by pads adjacent to the pads in the first direction DR1. For example, among the pads included in the thirteenth sub-pad group PAD13, an electric field due to the second voltage difference V2 may occur between the 13b-th pad PAD13b and the 13a-th pad PAD13a. Furthermore, an electric field due to the second voltage difference V2 may occur between the 13b-th pad PAD13b and the 13c-th pad PAD13c. The magnitudes of the electric fields generated between the 13b-th pad PAD13b and each of the pads PAD13a and PAD13c, which are adjacent to each other in the first direction DR1, may be substantially the same, and the directions of the electric fields generated between the 13b-th pad PAD13b and each of the pads PAD13a and PAD13c, which are adjacent to each other in the first direction DR1, may be opposite to each other. Therefore, when the magnitudes and directions of the formed electric fields are considered and summed, the electric field applied to the 13b-th pad PAD13b may be canceled out, thereby being substantially unaffected by the electric field from the pad adjacent in the first direction DR1.

[0117] According to the embodiments of the present disclosure, since the influence of the electric field on the pad is substantially minimized, corrosion occurring in the pad can be reduced. In addition, as the corrosion occurring in the pad is reduced, an increase in resistance in the pad, disconnection, short circuit, bonding defects, etc. can be substantially prevented, and the reliability of the display device can be improved.

[0118] Figure 9 is a block diagram showing an electronic device 1000 according to an embodiment of the present disclosure, and Figure 10 It shows Figure 9 The electronic device 1000 is implemented as an example of a smart phone.

[0119] Reference Figure 9 and Figure 10 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device (I / O device) 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The electronic device 1000 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or with other systems. Figure 10 As shown, the electronic device 1000 can be implemented as a smart phone. However, this is exemplary, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, a video phone, a smart board, a smart watch, a tablet PC, a car navigation device, a computer monitor, a notebook computer, a head-mounted display device, etc.

[0120] The processor 1010 may perform specific calculations or tasks. Depending on the embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. Depending on the embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0121] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM) device), a volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device), etc.

[0122] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0123] The input / output device 1040 may include input devices such as a keyboard, keys, a touch pad touch screen, and a mouse, and output devices such as a speaker and a printer. According to an embodiment, the display device 1060 may be included in the input / output device 1040.

[0124] The power supply 1050 may supply power required for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0125] The display device 1060 can display an image corresponding to visual information of the electronic device 1000. In this case, the display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. The display device 1060 can be connected to other components via a bus or other communication link.

[0126] Although specific embodiments and application examples are described herein, other embodiments and variations can be derived from the above description. Therefore, the spirit of the present disclosure is not limited to these embodiments, but extends to the scope of the claims, various obvious modifications and equivalents.

Claims

1. A timing controller, comprising: a control signal generator configured to generate a plurality of control signals; an output pad unit, comprising a plurality of output pads for outputting the plurality of control signals to the outside of the timing controller; as well as a plurality of transmission lines connecting the output pad unit to the control signal generator, The plurality of output pads are grouped into a plurality of sub-pad groups, and each of the plurality of sub-pad groups includes P output pads. Wherein, P represents the number of the output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, the P output pads are electrically connected to each other, and The P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction crossing the first direction.

2. The timing controller according to claim 1, in, Each of the plurality of output pads included in the output pad unit has a first length in the first direction and a second length in the second direction, and The second length is longer than the first length.

3. The timing controller according to claim 1, in, the plurality of output pads included in the output pad unit are arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of rows extends in the first direction, and the plurality of rows are spaced apart from each other in the second direction, wherein each of the plurality of columns extends in the second direction, and the plurality of columns are spaced apart from each other in the first direction, wherein the output pads in each of the plurality of rows are spaced apart from each other by a third length in the first direction, and The output pads in each of the plurality of columns are spaced apart from each other in the second direction by a fourth length that is longer than the third length.

4. The timing controller according to claim 1, in, The output pad unit further includes a plurality of dummy pads that do not output the control signal to the outside.

5. The timing controller according to claim 1, in, Each of the plurality of sub-pad groups is connected to the control signal generator through a corresponding one of the plurality of transmission lines.

6. The timing controller according to claim 1, in, The plurality of sub-pad groups include a first sub-pad group and a second sub-pad group, The first sub-pad group and the second sub-pad group are adjacent to each other in the second direction. wherein the plurality of transmission lines include a first transmission line connected to the first sub-pad group and a second transmission line connected to the second sub-pad group, and At least a portion of the first transmission line overlaps with the second transmission line in a third direction perpendicular to the first direction and the second direction.

7. The timing controller according to claim 6, in, The first sub-pad group outputs a first control signal among the plurality of control signals to the outside of the timing controller through the first transmission line. The second sub-pad group outputs the second control signal among the plurality of control signals to the outside of the timing controller through the second transmission line, and The second control signal is different from the first control signal.

8. A display device comprising: a plurality of pixels connected to a plurality of gate lines; a gate driver configured to provide a plurality of gate signals to the plurality of pixels through the plurality of gate lines; a plurality of gate pads configured to transmit a plurality of control signals to the gate driver via a plurality of control lines; as well as a timing controller configured to provide the plurality of control signals to the plurality of gate pads, Wherein, the timing controller includes: a control signal generator configured to generate the plurality of control signals; an output pad unit comprising a plurality of output pads for outputting the plurality of control signals to the outside of the timing controller; and a plurality of transmission lines connecting the output pad unit to the control signal generator, The plurality of output pads are grouped into a plurality of sub-pad groups, and each of the plurality of sub-pad groups includes P output pads. Wherein, P represents the number of the output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, the P output pads are electrically connected to each other, and The P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction crossing the first direction.

9. The display device according to claim 8, in, Each of the plurality of output pads included in the output pad unit has a first length in the first direction and a second length in the second direction, and The second length is longer than the first length.

10. The display device according to claim 8, in, the plurality of output pads included in the output pad unit are arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of rows extends in the first direction, and the plurality of rows are spaced apart from each other in the second direction, wherein each of the plurality of columns extends in the second direction, and the plurality of columns are spaced apart from each other in the first direction, wherein the output pads in each of the plurality of rows are spaced apart from each other by a third length in the first direction, and The output pads in each of the plurality of columns are spaced apart from each other in the second direction by a fourth length that is longer than the third length.

11. The display device according to claim 8, in, The output pad unit further includes a plurality of dummy pads that do not output the control signal to the outside.

12. The display device according to claim 8, in, Each of the plurality of sub-pad groups is connected to the control signal generator through a corresponding one of the plurality of transmission lines.

13. The display device according to claim 8, in, The plurality of sub-pad groups include a first sub-pad group and a second sub-pad group, The first sub-pad group and the second sub-pad group are adjacent to each other in the second direction. wherein the plurality of transmission lines include a first transmission line connected to the first sub-pad group and a second transmission line connected to the second sub-pad group, and At least a portion of the first transmission line overlaps with the second transmission line in a third direction perpendicular to the first direction and the second direction.

14. The display device according to claim 13, in, The first sub-pad group outputs a first control signal among the plurality of control signals to the outside of the timing controller through the first transmission line. The second sub-pad group outputs the second control signal among the plurality of control signals to the outside of the timing controller through the second transmission line, and The second control signal is different from the first control signal.

15. A timing controller comprising: a control signal generator configured to generate a plurality of control signals; an output pad unit, comprising a plurality of output pads for outputting the plurality of control signals to the outside of the timing controller, wherein the plurality of output pads are grouped into a plurality of sub-pad groups, the plurality of sub-pad groups are arranged in a plurality of rows and a plurality of columns, and each of the plurality of sub-pad groups includes P output pads, and wherein P represents the number of the output pads in each of the plurality of sub-pad groups and is an integer greater than or equal to 2, and the P output pads are electrically connected to each other; and a plurality of transmission lines, each of the plurality of transmission lines connecting a corresponding one of the plurality of sub-pad groups to the control signal generator, wherein the P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction crossing the first direction, wherein each of the plurality of rows extends in the first direction, and the plurality of rows are spaced apart from each other in the second direction, and Each of the plurality of columns extends in the second direction, and the plurality of columns are spaced apart from each other in the first direction.

16. The timing controller according to claim 15, in, The P is 3.

17. The timing controller according to claim 16, in, Each of the plurality of sub-pad groups consists of a first output pad, a second output pad, and a third output pad, the first output pad, the second output pad, and the third output pad being spaced apart from each other in the first direction and connected to each other, and Wherein, the second output pad is arranged between the first output pad and the third output pad.

18. The timing controller according to claim 17, in, Each of the multiple transmission lines includes a first portion, two second portions, and a third portion, wherein the first portion is connected to the first output pad of a corresponding group of the multiple sub-pad groups, the two second portions respectively connect the first output pad to the second output pad and connect the third output pad to the second output pad, and the third portion is electrically connected to the gate pad of the display panel.

19. The timing controller according to claim 15, in, Each of the plurality of output pads included in the output pad unit has a first length in the first direction and a second length in the second direction, and The second length is longer than the first length.

20. The timing controller according to claim 19, in, The output pads in each of the plurality of rows are spaced apart from each other by a third length in the first direction, and The output pads in each of the plurality of columns are spaced apart from each other in the second direction by a fourth length that is longer than the third length.

Images