Memory device detecting failure of through silicon via

Abstract

The invention relates to a memory device detecting a fault of a through-silicon via. A memory device includes a base die and a plurality of core dies stacked over the base die. The base die includes: a first base scan control circuit connected to a first node connected to a first via included in the first column; and a second base scan control circuit connected to a second node connected to a second via included in the second column. The first base scan control circuit sets the first node to a floating state when the first column is selected in a test mode, and drives the first node when the second column is selected during the test mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0036097, filed on March 14, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory device, including but not limited to a memory device for detecting failure of a through-silicon via (TSV). Background Art

[0004] Recently, stacked memory systems such as high-bandwidth memory (HBM) have been used in a wide range of applications due to their excellent bandwidth and energy efficiency. Unlike existing memory systems that use a parallel data bus, a stacked memory system includes a stacked memory device consisting of a base chip and multiple memory chips interconnected by through-silicon vias (TSVs, also known as "vias"). When the base chip receives data output from the memory chip during a read operation and transmits the data to a controller, the base chip generates a data strobe signal generated based on a clock signal and transmits the data strobe signal to the memory chip, so that the data can be adjusted to be output from the memory chip based on the data strobe signal. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a memory device may include a base die and a plurality of core dies stacked on the base die. The base die may include: a first base scan control circuit connected to a first node connected to a first via included in a first column; and a second base scan control circuit connected to a second node connected to a second via included in a second column. When the first column is selected during a test mode, the first base scan control circuit sets the first node to a floating state, and when the second column is selected during the test mode, the first base scan control circuit drives the first node.

[0006] According to one embodiment of the present disclosure, a memory device may include a base die and a plurality of core dies stacked on the base die. The plurality of core dies may include a first core die and a second core die. In the present disclosure, the first core die is farthest from the base die among the plurality of core dies, and the first core die may be configured to drive a first plurality of nodes during a first test mode, and to set the first plurality of nodes to a floating state during a second test mode, wherein each of the first plurality of vias is connected to a different node in the first plurality of nodes. The second core die may be configured to set a second plurality of nodes to a floating state during one of the first test mode and the second test mode, wherein each of the second plurality of vias is connected to a different node in the second plurality of nodes.

[0007] According to one embodiment of the present disclosure, a memory device may include a base die, a first core die stacked on the base die, and a second core die stacked on the first core die. In the present disclosure, the base die may include: a first base scan control circuit connected to a first node connected to a first via included in a first column; and a second base scan control circuit connected to a second node connected to a second via included in a second column. In the present disclosure, the first base scan control circuit may set the first node to a floating state during a first test mode, set the first node to a floating state when the first column is selected during a second test mode, and drive the first node when the second column is selected during the second test mode.

[0008] According to one embodiment of the present disclosure, a memory device may include a base die, a first die stacked on the base die and including a first plurality of nodes, and a second die stacked on the first die and including a second plurality of nodes, the second plurality of nodes including a first node and a second node. The first plurality of vias may be connected in a first column, wherein the first plurality of vias includes a first via within the base die, a second via within the first die, and a third via within the second die connected to the first node. The second plurality of vias may be connected in a second column, wherein the second plurality of vias includes a fourth via within the base die, a fifth via within the first die, and a sixth via within the second die connected to the second node. The second die may be configured to drive the first node during a first test mode, set the first node to a floating state when the first column is selected during a second test mode, and drive the first node when the second column is selected during the second test mode. The first die may be configured to set the first plurality of nodes to a floating state during one of the first test mode and the second test mode. The base die can be configured to select a first column and output a first current flowing through the first column as a scan current, and select a second column and output a second current flowing through the second column as a scan current, wherein the scan current identifies any via failures in the first and second pluralities of vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A configuration of a memory device according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A basic scan control circuit included in a basic die according to an embodiment of the present disclosure is shown.

[0011] Figure 3 A scan-out circuit included in a base die according to an embodiment of the present disclosure is shown.

[0012] Figure 4 A core scan control circuit according to an embodiment of the present disclosure is shown.

[0013] Figure 5 and Figure 6 A core scan control circuit during a first test mode according to an embodiment of the present disclosure is shown.

[0014] Figure 7 A basic scan control circuit during a first test mode according to an embodiment of the present disclosure is shown.

[0015] Figure 8 A scan output circuit during a first test mode according to an embodiment of the present disclosure is shown.

[0016] Figure 9 A table illustrating identification of whether a fault occurs according to a scan current during a first test mode according to an embodiment of the present disclosure.

[0017] Figure 10 A configuration of a memory device when a failure does not occur in a via during a first test mode according to an embodiment of the present disclosure is shown.

[0018] Figure 11 A configuration of a memory device when an open circuit occurs in a via during a first test mode according to an embodiment of the present disclosure is shown.

[0019] Figure 12 A configuration of a memory device when a short circuit occurs in a via during a first test mode according to an embodiment of the present disclosure is shown.

[0020] Figure 13 and Figure 14 A core scan circuit during a second test mode according to an embodiment of the present disclosure is shown.

[0021] Figure 15 and Figure 16 A basic scan control circuit during a second test mode according to an embodiment of the present disclosure is shown.

[0022] Figure 17 A scan output circuit during a second test mode according to an embodiment of the present disclosure is shown.

[0023] Figure 18 A table showing whether a failure occurs according to a scan current when during a second test mode according to an embodiment of the present disclosure is shown.

[0024] Figure 19 A configuration of a memory device when a fail does not occur in a via during a second test mode according to an embodiment of the present disclosure is shown.

[0025] Figure 20A configuration of a memory device when a short circuit occurs in a via during a second test mode according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Terms such as "first," "second," and "third" are used to distinguish between various elements and do not imply the size, order, priority, quantity, or importance of the elements, and these elements are not limited by these terms. Thus, a first element in one embodiment may be called a second element in another embodiment without departing from the teachings of the present disclosure.

[0027] When an element is referred to as being "connected" to another element, these elements may be directly connected or connected to one or more intermediate elements between the elements. When two elements are referred to as being "directly connected", there is no intermediate element between the two elements. When an element is identified as being "above" or "on" another element, these elements may directly contact each other or an intermediate element may be provided between these elements. Terms such as "top", "above", "above", "side", "level", "column", "outermost" and other terms that imply a relative spatial relationship or orientation are only used for ease of description or with reference to the accompanying drawings and do not have other restrictions.

[0028] Logic "high" and logic "low" can be used to describe the logic levels of electrical signals. A signal at a logic high level is different from a signal at a logic low level. For example, when a signal at a first voltage corresponds to a signal at a logic high level, a signal at a second voltage corresponds to a signal at a logic low level. In one embodiment, the voltage level at which the logic high level is located is higher than the voltage level at which the logic low level is located. The logic levels of a signal can be different or opposite depending on the embodiment. For example, a signal at a logic high level in one embodiment can be at a logic low level in another embodiment. Unless otherwise specified in this disclosure, an activated signal is at a logic high level, and a deactivated signal is at a logic low level.

[0029] Various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The described embodiments are only for illustrative purposes and do not limit the scope of the present disclosure.

[0030] Figure 1 FIG. 1 shows a configuration of a memory device 10 according to an embodiment of the present disclosure. Figure 1 As shown, the memory device 10 includes a base die 100 , a first core die 110 , a second core die 120 , and a third core die 130 .

[0031] The base die 100 includes vias 200 - 1 , 200 - 2 , and 200 - 3 , base scan control circuits (B-SC CTR) 201 - 1 , 201 - 2 , and 201 - 3 , a scan output circuit (SC OUT) 203 , and a test pad 205 .

[0032] Via 200-1 is arranged between solder ball 141-1 and node nd201, and is electrically connected to solder ball 141-1 and node nd201. Via 200-1 is included in the first column. A column may include, for example, one or more vias, one or more nodes, and one or more solder balls connected in series or electrically connected. The columns are not necessarily arranged vertically. Via 200-2 is arranged between solder ball 141-2 and node nd202, and is electrically connected to solder ball 141-2 and node nd202. Via 200-2 is included in the second column. Via 200-3 is arranged between solder ball 141-3 and node nd203, and is electrically connected to solder ball 141-3 and node nd203. Via 200-3 is included in the third column.

[0033] The basic scanning control circuit 201-1 is connected to the node nd201. The basic scanning control circuit 201-1 is based on the mode signal MD and the first column selection signal CSEL. <1> The node nd201 is driven or current is promoted to flow through the node nd201. The mode signal MD includes information such as whether to enter the first test mode or the second test mode. The first column selection signal CSEL <1> is activated to select the first column. The basic scan control circuit 201-1 is included in the first column. The basic scan control circuit 201-1 drives the node nd201 to a power supply voltage (such as Figure 2 During the down scan operation, current flows through node nd201. The basic scan control circuit 201-1 sets node nd201 to a floating state during the first test mode. During the second test mode, the basic scan control circuit 201-1 drives node nd201 at the power supply voltage when the first column is not selected, and sets node nd201 to a floating state when the first column is selected.

[0034] The basic scanning control circuit 201-2 is connected to the node nd202. The basic scanning control circuit 201-2 is based on the mode signal MD and the second column selection signal CSEL. <2> Drives the node nd202 or promotes current to flow through the node nd202. The second column selection signal CSEL <2> The first test mode is activated to select the second column. The basic scan control circuit 201-2 is included in the second column. The basic scan control circuit 201-2 drives the node nd202 to the power supply voltage during the up scan operation, while current flows through the node nd202 during the down scan operation. The basic scan control circuit 201-2 sets the node nd202 to a floating state during the first test mode. During the second test mode, the basic scan control circuit 201-2 drives the node nd202 to the power supply voltage when the second column is not selected, and sets the node nd202 to a floating state when the second column is selected.

[0035] The basic scanning control circuit 201-3 is connected to the node nd203. The basic scanning control circuit 201-3 is based on the mode signal MD and the third column selection signal CSEL. <3> The third column selection signal CSEL drives the node nd203 or promotes the current to flow through the node nd203. <3> The first test mode is activated to select the third column. The basic scan control circuit 201-3 is included in the third column. The basic scan control circuit 201-3 drives the node nd203 to the power supply voltage during the up scan operation, while a current flows through the node nd203 during the down scan operation. The basic scan control circuit 201-3 sets the node nd203 to a floating state during the first test mode. During the second test mode, the basic scan control circuit 201-3 drives the node nd203 to the power supply voltage when the third column is not selected, and sets the node nd203 to a floating state when the third column is selected.

[0036] The scan output circuit 203 is connected to the nodes nd201, nd202 and nd203, and outputs the current of one of the nodes nd201, nd202 and nd203 as the scan current I-SC at the node nd204 through the test pad 205 based on the mode signal MD and the column selection signal CSEL. The column selection signal CSEL includes a first column selection signal CSEL <1> , the second column selection signal CSEL <2> and the third column select signal CSEL <3> When the first column is selected during the first test mode or the second test mode, scan output circuit 203 outputs the current at node nd201 as scan current I-SC through test pad 205. When the second column is selected during the first test mode or the second test mode, scan output circuit 203 outputs the current at node nd202 as scan current I-SC through test pad 205. When the third column is selected during the first test mode or the second test mode, scan output circuit 203 outputs the current at node nd203 as scan current I-SC through test pad 205.

[0037] The first core die 110 is connected to solder balls 141-1, 141-2, and 141-3 and stacked on the base die 100. The first core die 110 includes vias 210-1, 210-2, and 210-3 and core scan control circuits (C-SC CTR) 211-1, 211-2, and 211-3.

[0038] Via 210-1 is provided between solder ball 142-1 and node nd211 and is electrically connected to solder ball 142-1 and node nd211. Via 210-1 is included in the first column. Via 210-2 is provided between solder ball 142-2 and node nd212 and is electrically connected to solder ball 142-2 and node nd212. Via 210-2 is included in the second column. Via 210-3 is provided between solder ball 142-3 and node nd213 and is electrically connected to solder ball 142-3 and node nd213. Via 210-3 is included in the third column.

[0039] The core scan control circuit 211-1 is connected to the node nd211. The core scan control circuit 211-1 sets the node nd211 to a floating state according to the mode signal MD. The core scan control circuit 211-1 is included in the first column. The core scan control circuit 211-1 sets the node nd211 to a floating state during the up scan operation. The core scan control circuit 211-1 sets the node nd211 to a floating state during the down scan operation. The core scan control circuit 211-1 sets the node nd211 to a floating state during the first test mode. The core scan control circuit 211-1 sets the node nd211 to a floating state during the second test mode.

[0040] The core scan control circuit 211-2 is connected to the node nd212. The core scan control circuit 211-2 sets the node nd212 to a floating state based on the mode signal MD. The core scan control circuit 211-2 is included in the second column. The core scan control circuit 211-2 sets the node nd212 to a floating state during the up scan operation. The core scan control circuit 211-2 sets the node nd212 to a floating state during the down scan operation. The core scan control circuit 211-2 sets the node nd212 to a floating state during the first test mode. The core scan control circuit 211-2 sets the node nd212 to a floating state during the second test mode.

[0041] The core scan control circuit 211-3 is connected to the node nd213. The core scan control circuit 211-3 sets the node nd213 to a floating state based on the mode signal MD. The core scan control circuit 211-3 is included in the third column. The core scan control circuit 211-3 sets the node nd213 to a floating state during the up scan operation. The core scan control circuit 211-3 sets the node nd213 to a floating state during the down scan operation. The core scan control circuit 211-3 sets the node nd213 to a floating state during the first test mode. The core scan control circuit 211-3 sets the node nd213 to a floating state during the second test mode.

[0042] The second core die 120 is connected to the solder balls 142-1, 142-2, and 142-3 and is stacked on the first core die 110. The second core die 120 includes vias 220-1, 220-2, and 220-3 and core scan control circuits 221-1, 221-2, and 221-3.

[0043] Via 220-1 is provided between solder ball 143-1 and node nd221 and is electrically connected to solder ball 143-1 and node nd221. Via 220-1 is included in the first column. Via 220-2 is provided between solder ball 143-2 and node nd222 and is electrically connected to solder ball 143-2 and node nd222. Via 220-2 is included in the second column. Via 220-3 is provided between solder ball 143-3 and node nd223 and is electrically connected to solder ball 143-3 and node nd223. Via 220-3 is included in the third column.

[0044] The core scan control circuit 221-1 is connected to the node nd221. The core scan control circuit 221-1 sets the node nd221 to a floating state according to the mode signal MD. The core scan control circuit 221-1 is included in the first column. The core scan control circuit 221-1 sets the node nd221 to a floating state during the up scan operation. The core scan control circuit 221-1 sets the node nd221 to a floating state during the down scan operation. The core scan control circuit 221-1 sets the node nd221 to a floating state during the first test mode. The core scan control circuit 221-1 sets the node nd221 to a floating state during the second test mode.

[0045] The core scan control circuit 221-2 is connected to the node nd222. The core scan control circuit 221-2 sets the node nd222 to a floating state based on the mode signal MD. The core scan control circuit 221-2 is included in the second column. The core scan control circuit 221-2 sets the node nd222 to a floating state during the up scan operation. The core scan control circuit 221-2 sets the node nd222 to a floating state during the down scan operation. The core scan control circuit 221-2 sets the node nd222 to a floating state during the first test mode. The core scan control circuit 221-2 sets the node nd222 to a floating state during the second test mode.

[0046] The core scan control circuit 221-3 is connected to the node nd223. The core scan control circuit 221-3 sets the node nd223 to a floating state based on the mode signal MD. The core scan control circuit 221-3 is connected to the third column. The core scan control circuit 221-3 sets the node nd223 to a floating state during the up scan operation. The core scan control circuit 221-3 sets the node nd223 to a floating state during the down scan operation. The core scan control circuit 221-3 sets the node nd223 to a floating state during the first test mode. The core scan control circuit 221-3 sets the node nd223 to a floating state during the second test mode.

[0047] The third core die 130 is connected to the solder balls 143-1, 143-2, and 143-3 and is stacked on the second core die 120. The third core die 130 includes vias 230-1, 230-2, and 230-3 and core scan control circuits 231-1, 231-2, and 231-3.

[0048] Via 230-1 is electrically connected to node nd231. Via 230-1 is included in the first column. Via 230-2 is electrically connected to node nd232. Via 230-2 is included in the second column. Via 230-3 is electrically connected to node nd233. Via 230-3 is included in the third column.

[0049] The core scan control circuit 231-1 is connected to the node nd231. The core scan control circuit 231-1 drives the node nd231 or promotes current flow through the node nd231 based on the mode signal MD. The core scan control circuit 231-1 promotes current flow through the node nd231 during an up scan operation. The core scan control circuit 231-1 drives the node nd231 at the power supply voltage during a down scan operation. The core scan control circuit 231-1 drives the node nd231 at the power supply voltage during the first test mode. The core scan control circuit 231-1 promotes current flow through the node nd231 during the second test mode.

[0050] The core scan control circuit 231-2 is connected to the node nd232. The core scan control circuit 231-2 drives the node nd232 or promotes current flow through the node nd232 based on the mode signal MD. The core scan control circuit 231-2 promotes current flow through the node nd232 during an up scan operation. The core scan control circuit 231-2 drives the node nd232 at the power supply voltage during a down scan operation. The core scan control circuit 231-2 drives the node nd232 at the power supply voltage during the first test mode. The core scan control circuit 231-2 promotes current flow through the node nd232 during the second test mode.

[0051] The core scan control circuit 231-3 is connected to a node nd233. The core scan control circuit 231-3 drives the node nd233 or facilitates current flow through the node nd233 based on the mode signal MD. The core scan control circuit 231-3 facilitates current flow through the node nd233 during an up scan operation. The core scan control circuit 231-3 drives the node nd233 at a power supply voltage during a down scan operation. The core scan control circuit 231-3 drives the node nd233 at a power supply voltage during a first test mode. The core scan control circuit 231-3 facilitates current flow through the node nd233 during a second test mode.

[0052] For the convenience of explanation, Figure 1The memory device 10 shown in FIG is described by taking as an example three dies (e.g., a first core die 110, a second core die 120, and a third core die 130) stacked on a base die 100. Depending on the embodiment, the memory device 10 can be implemented by stacking four core dies, eight core dies, twelve core dies, or another number of core dies on the base die 100.

[0053] Figure 2 For example, Figure 1 The basic die shown includes a basic scan control circuit 201-1.

[0054] like Figure 2 As shown, the basic scan control circuit 201-1 includes an OR device 301, a PMOS transistor 302, NMOS transistors 303-1 and 303-2, inverters 307-1, 307-2, 307-3 and 307-4, and a transmission gate 305. The OR device 301 receives the up scan signal UPSCANB and the first column select signal CSEL. <1> An OR operation is performed to generate a base pull-up signal BPU1. Up scan signal UPSCANB is activated during an up scan operation and the second test mode, and deactivated during a down scan operation and the first test mode. OR device 301 generates an activated base pull-up signal BPU1 when an up scan operation is performed without selecting the first column. When base pull-up signal BPU1 is activated, PMOS transistor 302 drives node nd200 at power supply voltage VDD. NMOS transistor 303-1 is turned on based on down scan signal DNSCAN, while NMOS transistor 303-2 is turned on based on bias voltage NBIAS. Down scan signal DNSCAN is activated during a down scan operation, and bias voltage NBIAS is at a voltage level that controls the current flow rate at node nd200. Inverter 307-1 inverts and buffers scan signal SCAN. Scan signal SCAN is activated during an up scan operation, a down scan operation, the first test mode, and the second test mode. The transmission gate 305 transmits the signal at the node nd200 to the node nd201 when the scan signal SCAN is activated. The inverters 307-2, 307-3, and 307-4 latch the voltage of the node nd201 when the scan signal SCAN is deactivated.

[0055] The basic scan control circuit 201-1 receives an up scan signal UPSCANB activated during an up scan operation and a first column select signal CSEL deactivated during an up scan operation. <1> , generating an activated base pull-up signal BPU1. The activated base pull-up signal BPU1 turns on the PMOS transistor 302, driving the node nd200 at the power supply voltage VDD. The voltage of node nd200, driven at the power supply voltage VDD, is output to node nd201 via the turned-on transmission gate 305. In the basic scan control circuit 201-1, the NMOS transistor 303-1 is turned on by the down scan signal DNSCAN, activated during the down scan operation, causing current to flow through node nd200. The voltage of node nd200, from which the current flows, is output to node nd201 via the turned-on transmission gate 305. The basic scan control circuit 201-1 sets node nd200 to a floating state using the up scan signal UPSCANB and the down scan signal DNSCAN, both of which were deactivated during the first test mode. The floating voltage of node nd200 is then output to node nd201 via the turned-on transmission gate 305. During the second test mode, the basic scan control circuit 201-1 receives the first column selection signal CSEL activated to select the first column. <1> , and the activated up scan signal UPSCANB and the deactivated down scan signal DNSCAN are received to generate a deactivated base pull-up signal BPU1. The PMOS transistor 302 is turned off by the deactivated base pull-up signal BPU1, and the node nd200 is in a floating state. The voltage of the floating node nd200 is output to the node nd201 through the turned-on transmission gate 305. During the second test mode, the base scan control circuit 201-1 receives the deactivated first column select signal CSEL when the first column is not selected. <1> At the same time, the activated up scan signal UPSCANB and the deactivated down scan signal DNSCAN are received, generating an activated base pull-up signal BPU1. The activated base pull-up signal BPU1 turns on PMOS transistor 302, driving node nd200 at power supply voltage VDD. The voltage at node nd200, driven by power supply voltage VDD, is output to node nd201 via the turned-on transmission gate 305.

[0056] Figure 3 For example, Figure 1 The scan output circuit 203 is included in the base die shown in FIG.

[0057] like Figure 3 As shown, the scan output circuit 203 includes an OR device 311, inverters 313-1 to 313-6, and transmission gates 315-1 to 315-3.

[0058] The OR device 311 is based on the first mode signal MD <1> and the second mode signal MD <2> Generates a synthetic mode signal MD-S. The first mode signal MD <1> is activated during the first test mode, while the second mode signal MD <2> The device 311 is activated during the second test mode. <1> and the second mode signal MD <2> The OR device 311 generates the synthetic mode signal MD-S which is activated when the first test mode or the second test mode is executed.

[0059] When the first test mode or the second test mode is executed, the transmission gate 315 - 1 is selected in the first column and the first column selection signal CSEL is <1> When activated, it is turned on and the current at the output node nd201 is used as the scan current I-SC.

[0060] When the first test mode or the second test mode is executed, the transmission gate 315 - 2 is selected in the second column and the second column selection signal CSEL is <2> When activated, it is turned on, and the current at the output node nd202 is used as the scan current I-SC.

[0061] When the first test mode or the second test mode is executed, the transmission gate 315 - 3 is selected in the third column and the third column selection signal CSEL <3> When activated, it is turned on and the current at the output node nd203 is used as the scan current I-SC.

[0062] Figure 4 For example, Figure 3 The core scan control circuit 211 - 1 is included in the first core die shown in FIG.

[0063] like Figure 4 As shown, the core scan control circuit 211-1 includes a selector 321-1, exclusive OR (NOR) devices 323-1 and 324-1, an OR device 325-1, a PMOS transistor 327-1, and NMOS transistors 328-1 and 329-1. The selector 321-1 outputs a first test mode signal MD during the first test mode. <1> , and outputs a signal at a logic low level in one of an up scan operation, a down scan operation, and a second test mode. The XOR device 323-1 receives the down scan signal DNSCAN and the output signal from the selector 321-1 to perform an XOR operation. The XOR device 324-1 receives the top core signal TOPB and the up scan signal UPSCANB and performs an XOR operation to generate a core pull-down signal CPD11. The top core signal TOPB is located in the top layer or outermost layer (e.g., the top core signal is located in the top layer or outermost layer) of the memory device 10 by the core scan control circuit. Figure 1In the example of the core die 130, which is farthest from the base die 100, it is activated. Since the core scan control circuit 211-1 is not located at the top or outermost layer of the memory device 10, the top core signal TOPB is deactivated in the core scan control circuit 211-1. The OR device 325-1 receives the output signal from the XOR device 323-1 and the top core signal TOPB, and performs an OR operation to generate the core pull-up signal CPU11. The PMOS transistor 327-1 is turned on based on the core pull-up signal CPU11 to drive the node nd211 to the power supply voltage VDD. The NMOS transistor 328-1 is turned on based on the core pull-down signal CPD11. The NMOS transistor 329-1 is turned on based on the bias voltage NBIAS.

[0064] The core scan control circuit 211-1 sets the node nd211 to a floating state based on the up scan signal UPSCANB activated when the up scan operation is performed and the top core signal TOPB deactivated when the up scan operation is performed. The core scan control circuit 211-1 sets the node nd211 to a floating state based on the down scan signal DNSCAN activated when the down scan operation is performed. The core scan control circuit 211-1 sets the node nd211 to a floating state during the first test mode. The core scan control circuit 211-1 sets the node nd211 to a floating state during the second test mode.

[0065] Figure 5 and Figure 6 During the first test mode, for example Figure 1 The core die shown in FIG. 1 includes core scan control circuits 211 - 1 (or 221 - 1 ) and 231 - 1 .

[0066] like Figure 5As shown in the core scan control circuit 211-1, during the first test mode, when the first mode signal MD <1> is activated at a logic high level 'H', the second mode signal MD <2> When the core pull-up signal CPU11 is deactivated at a logic high level 'H', the up scan signal UPSCANB is deactivated at a logic high level 'H', the down scan signal DNSCAN is deactivated at a logic low level 'L', and the top core signal TOPB is deactivated at a logic high level 'H', the PMOS transistor 327-1 and the NMOS transistor 328-1 are both turned off by the core pull-up signal CPU11 deactivated at a logic high level 'H' and the core pull-down signal CPD11 deactivated at a logic low level 'L'. Therefore, the core scan control circuit 211-1 included in the core die 110 that is not the top core sets the node nd211 to a floating state. The core scan control circuit 221-1 may be implemented by a circuit similar to the core scan control circuit 211-1 and may operate in a similar manner such that the core scan control circuit 221-1 sets the node nd221 (not shown, but corresponding to Figure 4 nd211) is set to floating state.

[0067] Figure 6 The core scanning control circuit 231-1 is shown. Figure 6 As shown, the core scan control circuit 231-1 includes a selector 321-3, XOR devices 323-3 and 324-3, an OR device 325-3, a PMOS transistor 327-3, and NMOS transistors 328-3 and 329-3. Figure 4 The core scan control circuit 211 - 1 shown in FIG is implemented in a similar manner.

[0068] like Figure 6 As shown, during the first test mode, when the first mode signal MD <1> is activated at a logic high level 'H', the second mode signal MD <2> When the core pull-up signal CPU31 is activated at a logic low 'L' and the core pull-down signal CPD31 is deactivated at a logic low 'L', the PMOS transistor 327-3 is turned on and the NMOS transistor 328-3 is turned off. Therefore, the core scan control circuit 231-1 included in the core die 130 as the top core drives the node nd231 at the power supply voltage VDD.

[0069] Figure 7 shows, for example, during the first test mode Figure 2The basic scanning control circuit 201-1 is shown.

[0070] like Figure 7 As shown, during the first test mode, when the up scan signal UPSCANB is deactivated at a logic high level 'H' and the down scan signal DNSCAN is deactivated at a logic low level 'L', both the PMOS transistor 302 and the NMOS transistor 303-1 are turned off. Therefore, the basic scan control circuit 201-1 sets both the node nd200 and the node nd201 to a floating state.

[0071] Figure 8 shows, for example, during the first test mode Figure 3 The scan output circuit 203 shown in FIG.

[0072] like Figure 8 As shown, during the first test mode, the first mode signal MD <1> is activated at a logic high level 'H' and the second mode signal MD <2> is deactivated at a logic low level 'L', so that the synthesized mode signal MD_S is activated at a logic high level 'H'. When the first column select signal CSEL <1> is activated at a logic high level 'H' and the second column select signal CSEL <2> and the third column select signal CSEL <3> When both are deactivated at a logic low level 'L', the scan output circuit 203 outputs the current at the node nd201 as the scan current I-SC.

[0073] Figure 9 A table showing whether a fault occurs according to a scanning current during the first test mode is shown. Figure 10 The configuration of the memory device 10 is shown when no failure occurs in the via during the first test mode. Figure 11 The configuration of the memory device 10 is shown when an open failure occurs in a via during the first test mode. Figure 12 FIG. 1 shows the configuration of the memory device 10 when a short circuit failure occurs in a via during the first test mode. Figures 9 to 12 , describes an operation of identifying whether a fault has occurred according to the scan current I-SC during the first test mode.

[0074] like Figures 9 to 12As shown, during the first test mode, in the core die 130, all PMOS transistors connected to the nodes nd231, nd232, and nd233 connected to the vias 230-1, 230-2, and 230-3, respectively, are turned on, and the nodes nd231, nd232, and nd233 are driven at the power supply voltage. During the first test mode, in the core dies 120 and 110, all PMOS transistors connected to the nodes nd221, nd222, nd223, nd211, nd212, and nd213 connected to the vias 220-1, 220-2, 220-3, 210-1, 210-2, and 210-3, respectively, are turned off. During the first test mode, in base die 100 , all PMOS transistors connected to nodes nd201 , nd202 , and nd203 respectively connected to vias 200 - 1 , 200 - 2 , and 200 - 3 are turned off, and the first column is selected so that only the transmission gate connected to node nd201 is turned on.

[0075] like Figure 9 and Figure 10 As shown in FIG, when no open circuit or short circuit occurs in the through holes 230-1, 230-2, 230-3, 220-1, 220-2, 220-3, 210-1, 210-2, 210-3, 200-1, 200-2 and 200-3, the scan current I-SC is the target current IREF at the node nd201, which is connected to the node nd231 driven by the power supply voltage VDD via the through holes 220-1, 210-1 and 200-1.

[0076] like Figure 9 and Figure 11 As shown, when an open circuit occurs in the via 210-1, since the via 210-1 is open and the current from the node nd231 is not normally or completely transmitted to the node nd201, the scan current I-SC is less than the target current IREF at the node nd231 driven with the power supply voltage VDD and the node nd201 connected via the vias 220-1, 210-1 and 200-1.

[0077] like Figure 9 and Figure 12 As shown, when a short circuit occurs between vias 210-1 and 210-2, the current flowing through node nd231, which is driven by power supply voltage VDD, flows through node nd201, which is connected via vias 220-1, 210-1, and 200-1. Furthermore, the current flowing through node nd232, which is driven by power supply voltage VDD, also flows through node nd201 via vias 220-2 and 210-2. Therefore, the scan current I-SC at node nd204 is greater than the target current IREF.

[0078] Figure 13 and Figure 14 The core scan circuits 211 - 1 (or 221 - 1 ) and 231 - 1 during the second test mode are shown.

[0079] like Figure 13 As shown, during the second test mode, when the first mode signal MD <1> is deactivated at a logic low level 'L', the second mode signal MD <2> When the up scan signal UPSCANB is activated at a logic high level 'H', the down scan signal DNSCAN is deactivated at a logic low level 'L', and the top core signal TOPB is deactivated at a logic high level 'H', the PMOS transistor 327-1 and the NMOS transistor 328-1 are both turned off by the core pull-up signal CPU11 being deactivated at a logic high level 'H' and the core pull-down signal CPD11 being deactivated at a logic low level 'L'. Therefore, the core scan control circuit 211-1 included in the non-top core core die 110 sets the node nd211 to a floating state. The core scan control circuit 221-1 can be implemented by a circuit similar to the core scan control circuit 211-1 and operates in a similar manner, so that the core scan control circuit 221-1 sets the node nd221 to a floating state.

[0080] like Figure 14 As shown, during the second test mode, when the first mode signal MD <1> is deactivated at a logic low level 'L', the second mode signal MD <2> When the up scan signal UPSCANB is activated at a logic high level 'H', the down scan signal DNSCAN is deactivated at a logic low level 'L', and the top core signal TOPB is activated at a logic low level 'L', the core pull-up signal CPU31 is deactivated at a logic high level 'H' and the core pull-down signal CPD31 is activated at a logic high level 'H', the PMOS transistor 327-3 is turned off, while the NMOS transistor 328-3 is turned on. Therefore, the core scan control circuit 231-1 included in the core die 130 as the top core promotes current flow through the node nd231.

[0081] Figure 15 and Figure 16 During the second test mode, for example Figure 1 The basic bare die shown in FIG includes basic scan control circuits 201 - 1 and 201 - 2 .

[0082] like Figure 15As shown, during the second test mode, when the up scan signal UPSCANB is activated at a logic low level 'L', the down scan signal DNSCAN is deactivated at a logic low level 'L' and the first column select signal CSEL <1> When activated at a logic high level 'H', both the PMOS transistor 302 and the NMOS transistor 303-1 are turned off. Thus, the basic scanning control circuit 201-1 sets each of the node nd200 and the node nd201 to a floating state.

[0083] like Figure 16 As shown, during the second test mode, when the up scan signal UPSCANB is activated at a logic low level 'L', the down scan signal DNSCAN is deactivated at a logic low level 'L' and the second column select signal CSEL <2> When deactivated at a logic low level 'L', the PMOS transistor 302 is turned on. Therefore, the basic scanning control circuit 201-2 drives the node nd202 with the power supply voltage VDD.

[0084] Figure 17 During the second test mode, for example Figure 3 The scan output circuit 203 shown in FIG.

[0085] like Figure 17 As shown, during the second test mode, the first mode signal MD <1> is deactivated at a logic low level 'L' and the second mode signal MD <2> is activated at a logic high level 'H', so that the synthesized mode signal MD-S is activated at a logic high level 'H'. When the first column select signal CSEL <1> is activated at a logic high level 'H' and the second column select signal CSEL <2> and the third column select signal CSEL <3> When both are deactivated at a logic low level 'L', the scan output circuit 203 outputs the current at the node nd201 as the scan current I-SC.

[0086] Figure 18 A table showing whether a failure occurs according to the scan current I-SC during the second test mode is shown. Figure 19 The configuration of the memory device when no failure occurs in the via during the second test mode is shown. Figure 20 FIG. 1 shows a configuration of a memory device when a short circuit occurs in a via during a second test mode. Figures 18 to 20 , describes an operation of identifying whether a fault has occurred according to the scan current I-SC during the second test mode.

[0087] like Figures 18 to 20As shown, during the second test mode, in the core dies 130, 120, and 110, all PMOS transistors connected to the nodes nd231, nd232, nd233, nd221, nd222, nd223, nd211, nd212, and nd213, which are respectively connected to the vias 230-1, 230-2, 230-3, 220-1, 220-2, 220-3, 210-1, 210-2, and 210-3, are turned off. During the second test mode, in the base die 100, the PMOS transistor connected to the node nd201 connected to the via 200-1 is turned off, all PMOS transistors connected to the nodes nd202 and nd203, which are respectively connected to the vias 200-2 and 200-3, are turned on, and the first column is selected so that only the transmission gate connected to the node nd201 is turned on.

[0088] like Figure 18 and Figure 19 As shown, when no open circuit or short circuit occurs in the through holes 230-1, 230-2, 230-3, 220-1, 220-2, 220-3, 210-1, 210-2, 210-3, 200-1, 200-2 and 200-3, the scan current I-SC at the node nd204 is 0A according to the current at the node nd201 connected to the nodes nd231, nd221 and nd211 in the floating state through the through holes 220-1, 210-1 and 200-1.

[0089] like Figure 18 and Figure 20 As shown, when a short circuit occurs between vias 210-1 and 210-2, the current flowing through node nd202 driven by power supply voltage VDD also flows through node nd201 connected by vias 200-2, 210-2, 210-1, and 200-1. Therefore, the scan current I-SC at node nd204 is greater than 0A.

[0090] Although detailed embodiments of the present disclosure are described in this disclosure, it will be understood by those skilled in the art that various modifications, additions, and substitutions may be made without departing from the scope, concept, and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but rather from an illustrative perspective. Therefore, the scope of the present disclosure should not be limited to the aforementioned embodiments. All variations within the meaning and scope of the equivalents of the claims are intended to be included within their scope.

Claims

1. A memory device comprising: Basic die; as well as a plurality of core dies stacked on the base die; Wherein, the basic bare chip includes: a first basic scan control circuit connected to a first node connected to a first via included in a first column; and a second basic scan control circuit connected to a second node connected to a second via included in the second column; and Wherein, the first basic scanning control circuit: When the first column is selected during a test mode, setting the first node to a floating state; and When the second column is selected during the test mode, the first node is driven.

2. The memory device according to claim 1, wherein The second basic scanning control circuit: driving the second node when the first column is selected during the test mode; as well as When the second column is selected during the test mode, the second node is set to a floating state.

3. The memory device according to claim 1, wherein Each core die of the plurality of core dies comprises: a first core scan control circuit connected to a third node connected to a third via included in the first column; and A second core scan control circuit is connected to a fourth node connected to a fourth via included in the second column.

4. The memory device according to claim 3, in, The first via is electrically connected to the third via; and Wherein, the second through hole is electrically connected to the fourth through hole.

5. The memory device according to claim 3, wherein The first core scan control circuit sets the third node to a floating state during the test mode. The memory device according to claim 3 , wherein: The second core scan control circuit sets the fourth node to a floating state during the test mode.

7. The memory device according to claim 1 , further comprising a scan output circuit, wherein: outputting a current of the first node as a scan current when the first column is selected during the test mode; and When the second column is selected during the test mode, the current of the second node is output as the scan current.

8. A memory device comprising: Basic die; as well as a plurality of core dies stacked on the base die, wherein the plurality of core dies include a first core die and a second core die; wherein the first core die is farthest from the base die among the plurality of core dies, the first core die: driving a first plurality of nodes during a first test mode; and setting the first plurality of nodes to a floating state during a second test mode, wherein each of the first plurality of vias is connected to a different node among the first plurality of nodes; and The second core die sets a second plurality of nodes to a floating state during one of the first test mode and the second test mode, wherein each of the second plurality of vias is connected to a different node in the second plurality of nodes.

9. The memory device according to claim 8, wherein The base die places a third plurality of nodes in a floating state, wherein each of the third plurality of vias is connected to a different node of the third plurality of nodes.

10. The memory device according to claim 9, wherein The base die: driving nodes of the third plurality of nodes connected to a plurality of unselected columns during the second test mode; as well as During the second test mode, nodes of the third plurality of nodes connected to the selected column are set to a floating state.

11. The memory device of claim 9 , further comprising a scan output circuit that outputs a current of a node connected to the first column among the third plurality of nodes as a scan current when the first column is selected during one of the first test mode and the second test mode.

12. The memory device of claim 8, further comprising a third core die disposed between the first core die and the base die, wherein The third core die sets a fourth plurality of nodes to a floating state during one of the first test mode and the second test mode, wherein each of a fourth plurality of vias is connected to a different node of the fourth plurality of nodes.

13. A memory device comprising: Basic die; a first core die stacked on top of the base die; as well as a second core die stacked on top of the first core die; Wherein, the basic bare chip includes: a first basic scan control circuit connected to a first node connected to a first via included in a first column; and a second basic scan control circuit connected to a second node connected to a second via included in the second column, and Wherein, the first basic scanning control circuit: setting the first node to a floating state during a first test mode; and When the first column is selected during the second test mode, the first node is set to a floating state, and when the second column is selected during the second test mode, the first node is driven.

14. The memory device according to claim 13, wherein: The first basic scanning control circuit: driving the first node based on a pull-up signal activated according to an up scan signal and a column select signal; as well as The current is promoted to flow through the first node based on the downlink scan signal.

15. The memory device according to claim 13, wherein: The second basic scanning control circuit: setting the second node to a floating state during the first test mode; driving the second node when the first column is selected during the second test mode; as well as When the second column is selected during the second test mode, the second node is set to a floating state.

16. The memory device according to claim 13, in, The first core die comprises: a first core scan control circuit connected to a third node connected to a third via included in the first column; and a second core scan control circuit connected to a fourth node connected to a fourth via included in the second column; and The first core scan control circuit sets the third node to a floating state during one of the first test mode and the second test mode.

17. The memory device according to claim 16, wherein: The first core scanning control circuit: driving the third node based on a core pull-up signal activated according to a mode signal, a down scan signal, and a top signal; as well as Current is facilitated to flow through the third node based on a core pull-down signal activated according to the up scan signal and the top signal.

18. The memory device according to claim 16, wherein: The second core scan control circuit sets the fourth node to a floating state during one of the first test mode and the second test mode.

19. The memory device according to claim 16, in, The second core die comprises: a third core scan control circuit connected to a fifth node connected to a fifth via included in the first column; and a fourth core scan control circuit connected to a sixth node connected to a sixth via included in the second column; and Wherein, the third core scanning control circuit: driving the fifth node during the first test mode; When the first column is selected during the second test mode, setting the fifth node to a floating state; and When the second column is selected during the second test mode, the fifth node is driven.

20. The memory device according to claim 19, in, The first through-hole, the third through-hole, and the fifth through-hole are electrically connected to each other; and The second through hole, the fourth through hole and the sixth through hole are electrically connected to each other.

21. The memory device of claim 19, wherein: The third core scanning control circuit: driving the fifth node based on a core pull-up signal activated according to a mode signal, a down scan signal, and a top signal; as well as Current is facilitated to flow through the fifth node based on the core pull-down signal activated according to the up scan signal and the top signal.

22. The memory device of claim 19, wherein: The fourth core scanning control circuit: driving the sixth node during the first test mode; driving the sixth node when the first column is selected during the second test mode; as well as When the second column is selected during the second test mode, the sixth node is set to a floating state.

23. The memory device according to claim 13, further comprising a scan output circuit, wherein: outputting a current of the first node as a scan current when the first column is selected during one of the first test mode and the second test mode; and When the second column is selected during one of the first test mode and the second test mode, a current of the second node is output as the scan current.

24. A memory device comprising: Basic die; a first die stacked on the base die and comprising a first plurality of nodes; a second die stacked above the first die and comprising a second plurality of nodes including a first node and a second node; a first plurality of vias connected in a first column, wherein the first plurality of vias includes a first via within the base die, a second via within the first die, and a third via within the second die connected to the first node; and a second plurality of vias connected in a second column, wherein the second plurality of vias includes a fourth via in the base die, a fifth via in the first die, and a sixth via in the second die connected to the second node; wherein the second die: drives the first node during a first test mode; sets the first node to a floating state when the first column is selected during a second test mode; and drives the first node when the second column is selected during the second test mode; wherein the first die sets the first plurality of nodes to a floating state during one of the first test mode and the second test mode; and The base die: selects the first column and outputs a first current flowing through the first column as a scanning current; and selects the second column and outputs a second current flowing through the second column as the scanning current, wherein the scanning current identifies any via failure in the first plurality of vias and the second plurality of vias.

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