Multilayer ceramic capacitor

Abstract

Provided is a highly reliable multilayer ceramic capacitor in which the occurrence of electrostrictive cracks is suppressed, the multilayer ceramic capacitor being provided with a laminate in which a plurality of inner dielectric layers and a plurality of inner electrode layers are laminated, and an outer electrode, the inner dielectric layers including: a central region in which the inner dielectric layers are laminated in a longitudinal direction and a lamination direction when viewed in a cross section parallel to the longitudinal direction and the lamination direction; a central portion disposed in the longitudinal direction; and an end region disposed at an end in the longitudinal direction, the center region including: a rectangular first region having a dimension in the longitudinal direction of Td / 2 and a dimension in the lamination direction of Td, where Td is the thickness of the inner dielectric layer in the lamination direction; and a rectangular second region which is adjacent to the first region and has a dimension in the longitudinal direction of Td / 2 and a dimension in the stacking direction of Td, the porosity of the first region being higher than that of the other regions, and the difference between the porosity in the first region and the porosity in the second region being 1%-5%.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, a multilayer ceramic capacitor includes a laminate having dielectric layers and internal electrode layers alternately laminated thereon, with dielectric layers laminated on the upper and lower surfaces thereof, and a pair of external electrodes formed on both end surfaces of the laminate.

[0003] Furthermore, multilayer ceramic capacitors are generally manufactured by alternately laminating ceramic green sheets containing dielectric ceramics such as barium titanate and unfired internal electrode layers to form green sheets, firing the green sheets, and then forming external electrodes on the end faces of the resulting stack.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2001-237137

[0007] However, during the laminate manufacturing process, firing the green sheets causes the dielectric ceramic to shrink, creating voids within the dielectric layer. Furthermore, barium titanate is a high-dielectric-constant ceramic, so when voltage is applied, stress is easily applied to the voids due to electrostriction. If the voids are concentrated in specific areas within the dielectric layer, electrostrictive cracks can form in those areas, degrading the insulation resistance of the dielectric layer and reducing the reliability of the laminated ceramic capacitor. Summary of the Invention

[0008] Problems to be solved by the invention

[0009] An object of the present invention is to provide a highly reliable multilayer ceramic capacitor that suppresses the occurrence of electrostrictive cracks.

[0010] Technical solutions to solve problems

[0011] The inventors of the present invention have discovered that the occurrence rate of electrostrictive cracks can be reduced by controlling the distribution of voids in the dielectric layer, and have ultimately completed the present invention.

[0012] That is, the present invention is a multilayer ceramic capacitor comprising:

[0013] A laminate comprising an inner layer portion and an outer layer portion, the inner layer portion comprising a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, the outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having a first principal surface and a second principal surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and

[0014] a pair of external electrodes, arranged at both ends of the stack in the longitudinal direction so as to cover at least the first end face and the second end face, respectively, and connected to the internal electrode layer;

[0015] When observing a cross section parallel to the longitudinal direction and the stacking direction,

[0016] The inner dielectric layer comprises:

[0017] a central region, arranged in the central portion in the longitudinal direction; and

[0018] The end region is arranged at the end in the longitudinal direction,

[0019] If the thickness of the inner dielectric layer in the stacking direction is Td, the central region includes:

[0020] The first region of the rectangular shape has a length dimension of Td / 2 and a stacking dimension of Td; and

[0021] The second rectangular region is adjacent to the first region, and has a lengthwise dimension of Td / 2 and a stacking dimension of Td.

[0022] The porosity of the first region is higher than that of other regions.

[0023] A difference between the porosity in the first region and the porosity in the second region is 1% or more and 5% or less.

[0024] Effects of the Invention

[0025] According to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor in which the distribution of voids in a dielectric layer is controlled to suppress the occurrence of electrostrictive cracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a perspective view showing a multilayer ceramic capacitor.

[0027] Figure 2 yes Figure 1This is a cross-sectional view taken along line II-II (LT cross-section) of the multilayer ceramic capacitor shown.

[0028] Figure 3 yes Figure 1 The following is a cross-sectional view (WT cross-sectional view) of the multilayer ceramic capacitor taken along line III-III.

[0029] Figure 4 It shows Figure 1 Schematic diagram of the structure of the inner layer portion of the multilayer ceramic capacitor shown.

[0030] Figure 5 Schematic diagram showing the distribution of voids in the dielectric layer.

[0031] Description of Reference Numerals

[0032] 1: Multilayer ceramic capacitor;

[0033] 10: laminate;

[0034] 20: dielectric layer;

[0035] 30: internal electrode layer;

[0036] 31: first internal electrode layer;

[0037] 311: first counter electrode portion;

[0038] 312: first lead electrode portion;

[0039] 32: second internal electrode layer;

[0040] 321: second counter electrode portion;

[0041] 322: second lead electrode portion;

[0042] 40: external electrode;

[0043] 41: 1st external electrode;

[0044] 415: first base electrode layer;

[0045] 416: 1st plating layer;

[0046] 42: second external electrode;

[0047] 425: second base electrode layer;

[0048] 426: second plating layer;

[0049] 100: inner layer;

[0050] 200: outer layer;

[0051] 201: 1st outer layer;

[0052] 202: 2nd outer layer;

[0053] P: gap;

[0054] L30: electrode opposing portion;

[0055] LG1: 1st end gap;

[0056] LG2: 2nd end gap;

[0057] W30: electrode opposing part;

[0058] WG1: first lateral gap;

[0059] WG2: second lateral gap;

[0060] L: length direction;

[0061] T: stacking direction;

[0062] W: width direction;

[0063] LS1: 1st end face;

[0064] LS2: 2nd end face;

[0065] TS1: 1st main surface;

[0066] TS2: 2nd main surface;

[0067] WS1: side 1;

[0068] WS2: Side 2. DETAILED DESCRIPTION

[0069] The following describes embodiments of the multilayer ceramic capacitor of the present invention, but the present invention is not limited thereto. Furthermore, the drawings are sometimes simplified for purposes of illustrating the invention, and the depicted components or the dimensional ratios between components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings or depicted with the number of components omitted.

[0070] (Multilayer Ceramic Capacitors)

[0071] Figure 1 is a perspective view showing a laminated ceramic capacitor, Figure 2 yes Figure 1 The II-II line cross-sectional view of the multilayer ceramic capacitor shown in FIG. Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor taken along line III-III. FIG. Figure 4 It shows Figure 1 Schematic diagram of the structure of the inner layer portion of the multilayer ceramic capacitor shown. Figures 1 to 4 The illustrated multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 . The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0072] exist Figures 1 to 3 In FIG, an XYZ orthogonal coordinate system is shown. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10. Thus, Figure 2 The section shown is also called the LT section. Figure 3 The cross section shown is also referred to as the WT cross section.

[0073] In addition, the longitudinal direction L, the width direction W, and the stacking direction T do not necessarily need to be orthogonal to each other, and may be intersecting with each other.

[0074] Regarding the dimensions of the multilayer ceramic capacitor, preferably, the dimension in the longitudinal direction L is greater than or equal to 0.2 mm and less than or equal to 10 mm, the dimension in the width direction W is greater than or equal to 0.1 mm and less than or equal to 10 mm, and the dimension in the stacking direction T is greater than or equal to 0.1 mm and less than or equal to 10 mm.

[0075] (Laminated body)

[0076] The stacked body 10 is substantially in the shape of a rectangular parallelepiped and has a first main surface TS1 and a second main surface TS2 that are opposite to each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that are opposite to each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that are opposite to each other in the length direction L. Furthermore, the surface of each surface may be provided with projections and depressions or may be roughened.

[0077] It is preferable to round the corners and ridges of the laminate 10. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0078] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in a stacking direction T. Furthermore, the laminate 10 includes an inner layer portion 100 in the stacking direction T and a first outer layer portion 201 and a second outer layer portion 202 disposed so as to sandwich the inner layer portion 100 .

[0079] Because the functions required of the inner portion 100 and the outer portion 200 differ, the components of the inner dielectric layer 20i constituting the inner portion 100 and the outer dielectric layer 20o constituting the outer portion 200 may differ. For example, the inner dielectric layer 20i is required to have a high dielectric constant, while the outer dielectric layer 20o is required to have high moisture resistance, weather resistance, and strength.

[0080] Therefore, the dielectric layer constituting the inner layer portion 100 is referred to as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 is referred to as the outer dielectric layer 20o. However, when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they are collectively referred to as the dielectric layer 20 in the description.

[0081] (Inner layer)

[0082] Figure 4 The structure of the inner portion 100 is schematically shown. The inner portion 100 includes multiple inner dielectric layers 20i and multiple internal electrode layers 30. In the inner portion 100, the multiple internal electrode layers 30 are arranged opposite each other with the inner dielectric layers 20i interposed therebetween. The inner portion 100 generates electrostatic capacitance and essentially functions as a capacitor.

[0083] As the material of dielectric layer 20, for example, dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component can be used. In addition, as the material of dielectric layer 20, Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds can be added as auxiliary components.

[0084] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably 0.2 μm or more and 15 μm or less, for example. By reducing the thickness of the inner dielectric layer 20i, the electrostatic capacitance can be increased.

[0085] (Outer layer)

[0086] The first outer layer portion 201 is arranged on the first principal surface TS1 side of the stacked body 10, and the second outer layer portion 202 is arranged on the second principal surface TS2 side of the stacked body 10. More specifically, the first outer layer portion 201 is arranged between the first principal surface TS1 and the internal electrode layer 30 closest to the first principal surface TS1 among the multiple internal electrode layers 30, and the second outer layer portion 202 is arranged between the second principal surface TS2 and the internal electrode layer 30 closest to the second principal surface TS2 among the multiple internal electrode layers 30. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0087] The outer layer portion 200 is formed of an insulating material. The first outer layer portion 201 and the second outer layer portion 202 can each be composed of multiple outer dielectric layers 20o, but can also be composed of a single outer dielectric layer 20o. Furthermore, the outer dielectric layer 20o can be composed of the same dielectric material as the inner dielectric layer 20i, but can also contain a different component from the inner dielectric layer 20i depending on the required function.

[0088] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10.

[0089] The first internal electrode layer 31 includes a first counter electrode portion 311 and a first lead-out electrode portion 312 , and the second internal electrode layer 32 includes a second counter electrode portion 321 and a second lead-out electrode portion 322 .

[0090] The first opposing electrode portion 311 and the second opposing electrode portion 321 oppose each other in the stacking direction T of the stacked body 10, with the inner dielectric layer 20i interposed therebetween. The shapes of the first opposing electrode portion 311 and the second opposing electrode portion 321 are not particularly limited; for example, they may be substantially rectangular. The first opposing electrode portion 311 and the second opposing electrode portion 321 generate electrostatic capacitance and essentially function as capacitors.

[0091] The first lead-out electrode portion 312 extends from the first opposing electrode portion 311 toward the first end surface LS1 of the stack 10 and is exposed at the first end surface LS1. The second lead-out electrode portion 322 extends from the second opposing electrode portion 321 toward the second end surface LS2 of the stack 10 and is exposed at the second end surface LS2. The lengths of the first opposing electrode portion 311 and the first lead-out electrode portion 312 in the width direction W may be the same, but may also be different. In addition, their lengths in the width direction W may also gradually change toward the first end surface LS1 where they are exposed. The lengths of the second opposing electrode portion 321 and the second lead-out electrode portion 322 in the width direction W may be the same, but may also be different. In addition, their lengths in the width direction W may also gradually change toward the second end surface LS2 where they are exposed.

[0092] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, with a gap provided between the first internal electrode layer 31 and the second end surface LS2 of the stacked body 10 (i.e., the second external electrode 42). Furthermore, the second internal electrode layer 32 is connected to the second external electrode 42, with a gap provided between the second internal electrode layer 32 and the first end surface LS1 of the stacked body 10 (i.e., the first external electrode 41).

[0093] The first and second internal electrode layers 31 and 32 contain metallic Ni as a main component. Furthermore, the first and second internal electrode layers 31 and 32 may contain, as a main component, at least one metal selected from, for example, Cu, Ag, Pd, Sn, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy, or may contain other components in addition to the main component. Furthermore, the first and second internal electrode layers 31 and 32 may contain, as a main component, particles of a dielectric having the same composition as the ceramic contained in the inner dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0094] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.2 μm to 2.0 μm, and more preferably 0.3 μm to 0.35 μm. The number of first internal electrode layers 31 and second internal electrode layers 32 is not particularly limited.

[0095] Furthermore, as a method for measuring the thickness of the inner dielectric layer 20i and the internal electrode layer 30, for example, a method of observing the LT cross-section near the center in the width direction of the laminate exposed by polishing using a scanning electron microscope can be used. Furthermore, each value may be the average of values ​​measured at multiple locations in the longitudinal direction, or further, the average of values ​​measured at multiple locations in the lamination direction.

[0096] like Figure 3 As shown, the stack 10 has an electrode-facing portion W30 in which the internal electrode layers 30 face each other in the width direction W, and a first side gap WG1 and a second side gap WG2 arranged to sandwich the electrode-facing portion W30. The first side gap WG1 is located between the electrode-facing portion W30 and the first side surface WS1, and the second side gap WG2 is located between the electrode-facing portion W30 and the second side surface WS2. More specifically, the first side gap WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap WG1 and the second side gap WG2 do not include the internal electrode layers 30, but only the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also referred to as W-gaps.

[0097] like Figure 2As shown, the laminate 10 has, in the longitudinal direction L, an electrode opposing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 oppose each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode opposing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode opposing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the internal dielectric layer 20i. The second end gap LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the internal dielectric layer 20i. The first end gap LG1 functions as an extraction electrode portion of the first internal electrode layer 31 extending to the first end surface LS1, while the second end gap LG2 functions as an extraction electrode portion of the second internal electrode layer 32 extending to the second end surface LS2. The first end gap LG1 and the second end gap LG2 are also referred to as L-gaps.

[0098] Furthermore, the first opposing electrode portion 311 of the first internal electrode layer 31 and the second opposing electrode portion 321 of the second internal electrode layer 32 are located in the electrode opposing portion L30. Furthermore, the first lead electrode portion 312 of the first internal electrode layer 31 is located in the first end gap LG1, and the second lead electrode portion 322 of the second internal electrode layer 32 is located in the second end gap LG2.

[0099] The thickness of the laminate 10 can be measured, for example, by observing a LT cross-section of the laminate near the center in the width direction, or a WT cross-section of the laminate near the center in the longitudinal direction, exposed by polishing, using a scanning electron microscope. Alternatively, each value may be an average of values ​​measured at multiple locations in the longitudinal or width directions.

[0100] Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing the LT cross-section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope can be cited. In addition, each value can be set as the average value of the measured values ​​at multiple locations in the lamination direction.

[0101] Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing a WT cross-section near the longitudinal center of the laminate exposed by polishing with a scanning electron microscope can be cited. In addition, each value can also be set as the average value of the measured values ​​at multiple locations in the lamination direction.

[0102] (External electrode)

[0103] The external electrode 40 includes a first external electrode 41 and a second external electrode 42 .

[0104] The first external electrode 41 is disposed on the first end surface LS1 of the stacked body 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0105] The second external electrode 42 is arranged on the second end surface LS2 of the stacked body 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. In addition, the second external electrode 42 may extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0106] The first external electrode 41 includes a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 includes a second base electrode layer 425 and a second plating layer 426. Alternatively, the first external electrode 41 may be composed solely of the first plating layer 416, and the second external electrode 42 may be composed solely of the second plating layer 426.

[0107] The first base electrode layer 415 and the second base electrode layer 425 may also be sintered layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Specifically, borosilicate glass can be used. The metal may contain Cu as a main component. Furthermore, the metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component, or may contain other components other than these main components.

[0108] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by dipping and then firing. Alternatively, the fired layer can be fired after the internal electrode layer or simultaneously with the internal electrode layer. Furthermore, the fired layer can consist of multiple layers.

[0109] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-mentioned fired layer or directly on the laminate without forming a fired layer.

[0110] The resin layer is formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate and then firing it. This layer can be fired after the internal electrode layer or simultaneously. Furthermore, the resin layer can be composed of multiple layers.

[0111] The thickness of each of the first foundation electrode layer 415 and the second foundation electrode layer 425 , which are fired layers or resin layers, is not particularly limited and may be 2 μm or more and 220 μm or less.

[0112] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0113] The first plating layer 416 covers at least a portion of the first underlying electrode layer 415, and the second plating layer 426 covers at least a portion of the second underlying electrode layer 425. The first plating layer 416 and the second plating layer 426 include, for example, at least one selected from a metal such as Cu, Ni, Ag, Pd, or Au, or an alloy such as an Ag-Pd alloy.

[0114] The first plating layer 416 and the second plating layer 426 can also be formed by multiple layers. Preferably, they are a two-layer structure of a Ni plating layer and a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being corroded by the solder when installing the ceramic electronic component, and the Sn plating layer can improve the wettability of the solder when installing the ceramic electronic component, making installation easier. The first plating layer 416 and the second plating layer 426 can also be stacked respectively with a Cu plating layer, a Ni plating layer, and a Sn plating layer to form a three-layer structure. The outermost layer can also be set as an Au plating layer.

[0115] The thickness of each of the first plating layer 416 and the second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0116] (Porosity)

[0117] In the multilayer ceramic capacitor 1 according to the present invention, when observing a cross section LT parallel to the longitudinal direction L and the stacking direction T, the inner dielectric layer 20i includes a central region located in the center portion in the longitudinal direction L and end regions located at the ends in the longitudinal direction L. Here, the central region refers to a region located in the center when the electrode-opposing portion L30 is divided into three equal parts in the longitudinal direction L. Furthermore, the end regions refer to regions excluding the central region when the electrode-opposing portion L30 is divided into three equal parts in the longitudinal direction L.

[0118] Furthermore, if the thickness of the inner dielectric layer 20i in the stacking direction T is Td, then in the central region of the inner dielectric layer 20i, as shown in FIG. Figure 5 As shown, it comprises: a rectangular region A1 (equivalent to the "first region" of the present invention), the dimension in the longitudinal direction L is set to Td / 2, and the dimension in the stacking direction is set to Td; and a rectangular region A2 (equivalent to the "second region" of the present invention), adjacent to the region A1, the dimension in the longitudinal direction is set to Td / 2, and the dimension in the stacking direction T is set to Td, the porosity of the region A1 is higher than that of other regions, and the difference between the porosity P1 in the region A1 and the porosity P2 in the region A2 is set to be greater than 1% and less than 5%.

[0119] Within the inner dielectric layer 20i, areas with a high concentration of voids P have lower strength than other areas. Therefore, if many voids P exist in areas where electrostrictive stress concentrates, cracks are more likely to form starting from these voids. In particular, if the distribution of voids results in areas with large variations in density within the inner dielectric layer 20i, stress will concentrate in the areas with the high concentration of voids.

[0120] In the multilayer ceramic capacitor according to the present invention, Figure 5 As shown, in the central region of the inner dielectric layer 20i, there is a rectangular region A1 having a dimension in the longitudinal direction L of Td / 2 and a dimension in the stacking direction of Td; and a rectangular region A2 adjacent to the region A1 having a dimension in the longitudinal direction of Td / 2 and a dimension in the stacking direction of Td. The difference between the porosity P1 in the region A1 and the porosity P2 in the region A2 is set to be greater than 1% and less than 5%. This can reduce the difference in the density of the voids and reduce the occurrence of electrostrictive cracks.

[0121] The difference between the porosity P1 and the porosity P2 is set to 1% or more and 5% or less. If it is less than 1%, it is not suitable for mass production due to manufacturing conditions. If it exceeds 5%, the effect of suppressing the occurrence of electrostrictive cracks decreases.

[0122] like Figure 2As shown, when the height of the stacked body 10 in the stacking direction T is Ts, the region A1 and the region A2 preferably exist within a range of a height of Ts / 10 located at the center in the stacking direction T of the stacked body 10 .

[0123] Electrostrictive stress in a multilayer ceramic capacitor tends to concentrate at the center of the laminate 10 in the stacking direction T. Therefore, reducing the density differences caused by voids in the inner dielectric layer 20i, which exists within a range of height Ts / 10 at the center of the laminate 10 in the stacking direction T, is effective in reducing the occurrence of electrostrictive cracks.

[0124] Therefore, in the inner dielectric layer 20i that is located in the center of the stacking direction T of the stacked body 10 and has a height range of Ts / 10, by setting the difference between the porosity P1 of the region A1 and the porosity P2 of the region A2 to 1% or more and 5% or less, the occurrence of electrostrictive cracks can be more effectively reduced.

[0125] (Determination of void ratio)

[0126] The porosity can be measured by observing the LT cross section at the center in the width direction W of the laminate 10 exposed by polishing using a scanning electron microscope (SEM).

[0127] The captured SEM image is binarized to identify voids P. The porosity is then calculated using the following formula (1) based on the area of ​​the target region in the SEM image and the area of ​​voids P within the target region. For example, the observation range is set to 10 μm × 10 μm, and the target region within this range is analyzed to calculate the porosity.

[0128] Void ratio (%) = (area of ​​voids / area of ​​target area) × 100 … (1)

[0129] (Manufacturing of Multilayer Ceramic Capacitors)

[0130] Next, an example of a method for manufacturing a multilayer ceramic capacitor will be described.

[0131] First, ceramic green sheets for forming dielectric layers and conductive paste for internal electrodes are prepared. The conductive paste for internal electrodes contains a binder and a solvent, and known organic binders and organic solvents can be used. The conductive paste for internal electrodes forms the internal electrodes 53.

[0132] Next, a conductive paste for internal electrodes is printed in a predetermined pattern on the ceramic green sheet by, for example, screen printing or gravure printing, thereby forming an internal electrode pattern.

[0133] Next, a predetermined number of outer layer ceramic green sheets, without internal electrode patterns, are stacked. Ceramic green sheets with internal electrodes are sequentially stacked on top of these sheets, and a predetermined number of outer layer ceramic green sheets are stacked on top of these sheets to produce a laminate. The ceramic green sheets form the dielectric layer 20 that constitutes the laminated ceramic capacitor 1.

[0134] The resulting laminated sheet is pressed in the stacking direction by isostatic pressing or other means to produce a laminated block. The laminated block is then cut into predetermined dimensions to produce laminated chips. The corners and edges of the laminated chips can also be rounded by barrel grinding or other means.

[0135] The stacked small pieces are then fired to produce the stacked body 10. The firing temperature at this time depends on the materials of the dielectric and the internal electrodes, but is preferably 900°C or higher and 1300°C or lower.

[0136] The stacked sheets are fired while pressure is applied sequentially from the center toward both ends. The distribution of voids in the dielectric layer is controlled by adjusting the pressure applied to the stacked sheets, the speed of movement of the pressure-applying area, the firing temperature, and the firing time.

[0137] Next, the first end surface LS1 of the laminate 10 is dipped into a conductive paste serving as the electrode material for the base electrode layer using a dipping method, thereby applying the conductive paste for the first base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the laminate 10 is dipped into a conductive paste serving as the electrode material for the base electrode layer using a dipping method, thereby applying the conductive paste for the second base electrode layer 425 to the second end surface LS2. These conductive pastes are then fired to form the first and second base electrode layers 415, 425 as fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0138] In addition, as described above, the first base electrode layer 415 and the second base electrode layer 425 as resin layers can be formed by applying a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it, or the first base electrode layer 415 and the second base electrode layer 425 as thin films can be formed by a thin film forming method such as sputtering or evaporation.

[0139] Then, a first plating layer 416 is formed on the surface of the first foundation electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second foundation electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 is obtained.

[0140] [Example]

[0141] Electrostriction test (crack detection and evaluation)

[0142] Electrostrictive tests were performed on multilayer ceramic capacitors.

[0143] Following the aforementioned manufacturing method, samples were produced batch by batch, with varying void distributions achieved by adjusting manufacturing conditions. These samples served as samples for each experimental level. Samples within each batch were manufactured using the same design and manufacturing conditions. For each experimental level (five different chip sizes x four levels), 20 samples for void ratio measurement and 100 samples for electrostriction testing were prepared from the same batch. The void ratio was evaluated using the average value of the measurement results.

[0144] An electrostrictive test of the multilayer ceramic capacitor was conducted using a breakdown voltage measuring device (BDV device) with the voltage increased to DC 150 V at a voltage increase rate of 100 V / sec.

[0145] The samples were evaluated by observing the presence of cracks using an ultrasonic flaw detector.

[0146] Specifically, first, the sample multilayer ceramic capacitor was arranged so that the main surface thereof became the upper surface.

[0147] Next, ultrasonic waves were irradiated and scanned on the top surfaces of the arrayed multilayer ceramic capacitors using an ultrasonic probe. The reflected waves of the ultrasonic waves were observed, and the presence of cracks was confirmed by detecting the reflected waves that returned faster than the bottom wave.

[0148] Here, samples in which cracks were confirmed were counted as electrostrictive defects, and the crack generation rate was calculated using the number of samples from the same batch (n=100) as the denominator.

[0149] As the evaluation criteria, a crack generation rate of 10% or less was rated as 0 (pass), and a crack generation rate exceeding 10% was rated as x (fail). The results are shown in Table 1.

[0150] [Table 1]

[0151]

[0152] As shown in Table 1, it was confirmed that a good result was obtained when the difference between the porosity P1 in the region A1 and the porosity P2 in the region A2 was 1% or more and 5% or less.

[0153] As mentioned above, although embodiment of this invention was described, this invention is not limited to embodiment, It can implement in various forms within the range which does not deviate from the summary of this invention.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising an inner layer portion and an outer layer portion, the inner layer portion comprising a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, the outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having a first principal surface and a second principal surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes, arranged at both ends of the stack in the longitudinal direction so as to cover at least the first end face and the second end face, respectively, and connected to the internal electrode layer; When observing a cross section parallel to the longitudinal direction and the stacking direction, The inner dielectric layer comprises: a central region, arranged in the central portion in the longitudinal direction; and The end region is arranged at the end in the longitudinal direction, If the thickness of the inner dielectric layer in the stacking direction is Td, the central region includes: The first region of the rectangular shape has a length dimension of Td / 2 and a stacking dimension of Td; and The second rectangular region is adjacent to the first region, and has a lengthwise dimension of Td / 2 and a stacking dimension of Td. The porosity of the first region is higher than that of other regions. A difference between the porosity in the first region and the porosity in the second region is 1% or more and 5% or less.

2. The multilayer ceramic capacitor according to claim 1, wherein When the height of the stacked body in the stacking direction is Ts, The first region and the second region exist in a range located at the center in the stacking direction of the stacked body and having a height of Ts / 10.

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