Multilayer ceramic capacitor

Abstract

The base portion includes: a first outer layer portion (X1) positioned closer to the first main surface side than an internal electrode layer closest to the first main surface side in the stacking direction among the plurality of internal electrode layers; and a second outer layer section that is positioned closer to the second main surface side than an internal electrode layer that is closest to the second main surface side in the stacking direction among the plurality of internal electrode layers. The first outer layer portion (X1) and the second outer layer portion each include an outermost layer portion (Xa) disposed on the outermost side and an inner layer portion (Xb) located on the inner side of the outermost layer portion (Xa). The maximum height (Ha) of the irregularities on the outer surface of the outermost layer section (Xa) is smaller than the maximum height (Hb) of the irregularities on the outer surface of the inner outer layer section (Xb).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a multilayer ceramic capacitor. BACKGROUND

[0002] As a prior art document disclosing a structure of a multilayer ceramic capacitor, there is Japanese Patent Application Publication No. 2021-2645 (Patent Document 1). The multilayer ceramic capacitor described in Patent Document 1 includes a ceramic main body, a plurality of internal electrodes, and a side edge portion. The side edge portion is divided into a first region adjacent to an outer side surface and a second region adjacent to the internal electrodes. The second region includes dielectric grains having a larger size than dielectric grains included in the first region.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-2645 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In a case where a dielectric particle is sintered to form an outer surface of a ceramic main body, a large number of fine irregularities exist on the outer surface. In a case where an impact is applied to the fine irregularities, a crack is generated on the outer surface, and the moisture resistance of the multilayer ceramic capacitor is reduced.

[0008] The present disclosure was completed in view of the above-described problems, and aims to provide a multilayer ceramic capacitor capable of suppressing a reduction in moisture resistance.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] A multilayer ceramic capacitor according to the present disclosure includes a base portion and an external electrode. The base portion includes a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and has a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction. The external electrode is provided on each of the first end surface and the second end surface, and is electrically connected to the plurality of internal electrode layers. The base portion includes a first outer layer portion located on a position closer to the first main surface than an internal electrode layer located closest to the first main surface among the plurality of internal electrode layers, and a second outer layer portion located on a position closer to the second main surface than an internal electrode layer located closest to the second main surface among the plurality of internal electrode layers. Each of the first outer layer portion and the second outer layer portion includes an outermost layer portion disposed on an outermost side and an inner side outer layer portion located on an inner side of the outermost layer portion. A maximum height of irregularities of an outer surface of the outermost layer portion is smaller than a maximum height of irregularities of an outer surface of the inner side outer layer portion.

[0011] The effects of the invention

[0012] According to this disclosure, it is possible to suppress the reduction of moisture resistance in multilayer ceramic capacitors. Attached Figure Description

[0013] Figure 1 This is a perspective view schematically showing the appearance of a stacked ceramic capacitor according to an embodiment.

[0014] Figure 2 This is a perspective view schematically showing the substrate portion of a multilayer ceramic capacitor according to an embodiment.

[0015] Figure 3 Observe from the direction of the arrow on line III-III Figure 1 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0016] Figure 4 Observe from the direction of the arrow on line IV-IV Figure 1 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0017] Figure 5 Observe from the direction of the arrow on the VV line Figure 3 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0018] Figure 6 Observe from the direction of the arrow on line VI-VI Figure 3 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0019] Figure 7 This is a schematic cross-sectional view illustrating the details of the side edge portion of the multilayer ceramic capacitor used to explain the embodiment.

[0020] Figure 8 This is a schematic cross-sectional view illustrating the details of the outer layer of the multilayer ceramic capacitor used to explain the embodiments.

[0021] Figure 9 This is a schematic cross-sectional view illustrating the details of the end edges and external electrodes of the multilayer ceramic capacitor used to explain the embodiments.

[0022] Figure 10 This is a schematic cross-sectional view showing the detailed structure of the external electrodes of the multilayer ceramic capacitor according to the embodiment.

[0023] Figure 11 This is a schematic cross-sectional view used to illustrate the offset in the width direction of the protruding portion of the internal electrode layer in the multilayer ceramic capacitor of the embodiment.

[0024] Figure 12is a flowchart showing a manufacturing method of a multilayer ceramic capacitor of an embodiment.

[0025] Figure 13 is a schematic cross-sectional view for explaining details of an end edge portion and an external electrode of a multilayer ceramic capacitor of a modification.

[0026] Figure 14 is a flowchart showing a manufacturing method of a multilayer ceramic capacitor of a modification. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be explained in detail with reference to the drawings. Further, in the embodiments shown below, the same reference numerals are affixed to the same or common portions in the drawings, and the explanation thereof will not be repeated. Further, in the drawings, L represents a length direction of a base portion described later, W represents a width direction of the base portion, and T represents a stacking direction of the base portion.

[0028] Figure 1 is a perspective view schematically showing an external appearance of a multilayer ceramic capacitor of an embodiment. Figure 2 is a perspective view schematically showing a base portion of a multilayer ceramic capacitor of an embodiment. Figure 3 is a schematic cross-sectional view obtained by observing the multilayer ceramic capacitor shown in Figure 1 from the arrow direction of the III-III line. Figure 4 is a schematic cross-sectional view obtained by observing the multilayer ceramic capacitor shown in Figure 1 from the arrow direction of the IV-IV line. Figure 5 is a schematic cross-sectional view obtained by observing the multilayer ceramic capacitor shown in Figure 3 from the arrow direction of the V-V line. Figure 6 is a schematic cross-sectional view obtained by observing the multilayer ceramic capacitor shown in Figure 3 from the arrow direction of the VI-VI line.

[0029] As shown in Figures 1 to 6 , a multilayer ceramic capacitor 100 of an embodiment includes a base portion 110 and an external electrode. The multilayer ceramic capacitor 100 includes a first external electrode 120 and a second external electrode 130 as the external electrode.

[0030] As shown in Figure 1 , the base portion 110 has a substantially rectangular parallelepiped shape. The base portion 110 has a first main face 111 and a second main face 112 opposed in the stacking direction T, a first side face 113 and a second side face 114 opposed in the width direction W orthogonal to the stacking direction T, and a first end face 115 and a second end face 116 opposed in the length direction L orthogonal to the stacking direction T and the width direction W.

[0031] It is preferable that the base portion 110 has a rounded corner at a corner portion and a rounded edge at an edge portion. Here, the corner portion is a portion where three faces of the base portion 110 meet, and the edge portion is a portion where two faces of the base portion 110 meet.

[0032] As shown in Figure 1 and Figures 3 to 6 , the first external electrode 120 is provided to the first end surface 115. Specifically, the first external electrode 120 is formed on the entirety of the first end surface 115, and is formed in such a manner as to wrap from the first end surface 115 to the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. As shown in Figure 5 and Figure 6 , the first external electrode 120 includes an extension portion 120E that extends from the first end surface 115 toward the first side surface 113 and the second side surface 114, respectively.

[0033] As shown in Figure 1 and Figures 3 to 6 , the second external electrode 130 is provided to the second end surface 116. Specifically, the second external electrode 130 is formed on the entirety of the second end surface 116, and is formed in such a manner as to wrap from the second end surface 116 to the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. As shown in Figure 5 and Figure 6 , the second external electrode 130 includes an extension portion 130E that extends from the second end surface 116 toward the first side surface 113 and the second side surface 114, respectively.

[0034] Further, the detailed structure of the first external electrode 120 and the second external electrode 130 will be described later.

[0035] As shown in Figures 2 to 6 , the base portion 110 includes the laminate 101 and a cladding layer 160. The cladding layer 160 contains Si and K.

[0036] The laminate 101 has a pair of main surfaces 101a, 101b opposite in the stacking direction T, a pair of side surfaces 101c, 101d opposite in the width direction, and a pair of end surfaces 101e, 101f opposite in the length direction. The pair of main surfaces 101a, 101b, the pair of side surfaces 101c, 101d, and the pair of end surfaces 101e, 101f are covered with the cladding layer 160. The cladding layer 160 is located at the first side surface 113, the second side surface 114, the first main surface 111, and the second main surface 112. At the first end surface 115 and the second end surface 116, the plurality of dielectric layers 140 are covered with the cladding layer 160.

[0037] As shown in Figures 2 to 4 , the laminate 101 has a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 alternately stacked along the stacking direction T.

[0038] The plurality of internal electrode layers 150 include a plurality of first internal electrode layers 151 and a plurality of second internal electrode layers 152. The plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 are alternately stacked in the stacking direction T.

[0039] The plurality of first internal electrode layers 151 are led out to the end surface 101e. The plurality of first internal electrode layers 151 are electrically connected to the first external electrode 120. The plurality of second internal electrode layers 152 are led out to the end surface 101f. The plurality of second internal electrode layers 152 are electrically connected to the second external electrode 130. Both end portions of the plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 in the width direction W are exposed to the side surfaces 101c, 101d.

[0040] In addition, in the Figures 2 to 4 , an example in which the first internal electrode layer 151 and the second internal electrode layer 152 each are provided with seven pieces is shown, but the number of pieces of the first internal electrode layer 151 and the second internal electrode layer 152 each is not limited to seven pieces. The number of pieces of the plurality of internal electrode layers 150 is preferably one piece or more and 1000 pieces or more. The thickness of the internal electrode layer 150 is preferably 0.3 μm or more and 0.8 μm or less.

[0041] As shown in Figure 5 , the first internal electrode layer 151 includes a first opposing portion 151C and a first lead-out portion 151X. The first opposing portion 151C opposes the second internal electrode layer 152 adjacent in the stacking direction T. The first lead-out portion 151X connects the first opposing portion 151C and the first external electrode 120. The first lead-out portion 151X is led out to the first end surface 115 side. The first opposing portion 151C and the first lead-out portion 151X are integrally configured.

[0042] The first internal electrode layer 151 has a first narrow-width portion 151N in which the width in the width direction W is narrower than the central portion in the length direction L on the side opposite to the side connected to the first external electrode 120 in the length direction L. In the width direction W, the width W2 of the first narrow-width portion 151N is smaller than the width Wl of the first opposing portion 151C.

[0043] As shown in Figure 5 , a region in which the internal electrode layers 150 adjacent to each other in the base portion 110 on the second end surface 116 side do not overlap in the stacking direction T, that is, a region from the end portion on the second end surface 116 side of the region in which the internal electrode layers 150 adjacent to each other overlap in the stacking direction T to the second end surface 116 is set as Lgap.

[0044] Alternatively, the first narrow portion 151N may not need to be formed, and the width of the portion where the first narrow portion 151N is formed may also be W1. In this case, it is preferable that the length of the protrusion 120E of the first external electrode 120 in the longitudinal direction L is shorter than the length of Lgap along the longitudinal direction L, or that the protrusion 120E is not formed.

[0045] like Figure 6 As shown, the second internal electrode layer 152 includes a second opposing portion 152C and a second lead-out portion 152X. The second opposing portion 152C opposes the first internal electrode layer 151 adjacent in the stacking direction T. The second lead-out portion 152X connects the second opposing portion 152C and the second external electrode 130. The second lead-out portion 152X extends towards the second end face 116. The second opposing portion 152C and the second lead-out portion 152X are integrally formed.

[0046] The second inner electrode layer 152 has a second narrow portion 152N on the side opposite to the side connected to the second outer electrode 130 in the length direction L, and the width in the width direction W is narrower than the central portion in the length direction L. In the width direction W, the width W4 of the second narrow portion 152N is smaller than the width W3 of the second opposing portion 152C.

[0047] like Figure 6 As shown, the region in the substrate portion 110 on the first end face 115 side where the adjacent internal electrode layers 150 do not overlap in the stacking direction T, that is, the region from the end of the region where the adjacent internal electrode layers 150 overlap in the stacking direction T to the first end face 115, is defined as Lgap.

[0048] Alternatively, the second narrow portion 152N may not need to be formed, and the width of the portion where the second narrow portion 152N is formed may also be W3. In this case, it is preferable that the length of the protrusion 130E of the second external electrode 130 in the longitudinal direction L is shorter than the length of Lgap along the longitudinal direction L, or that the protrusion 130E is not formed.

[0049] The first internal electrode layer 151 and the second internal electrode layer 152 each comprise a metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy comprising that metal. In this embodiment, the first internal electrode layer 151 and the second internal electrode layer 152 each comprise Ni as the main component. Alternatively, the first internal electrode layer 151 and the second internal electrode layer 152 may also comprise dielectric particles of the same composition as the ceramic contained in the dielectric layer 140. Furthermore, the first internal electrode layer 151 and the second internal electrode layer 152 may each comprise Sn at the interface between themselves and the dielectric layer 140.

[0050] The plurality of dielectric layers 140 includes an outer dielectric layer located between the inner electrode layer 150 on the side closest to the first main surface 111 in the stacking direction T and the inner electrode layer 150 on the side closest to the second main surface 112 in the stacking direction T, and an inner dielectric layer located between adjacent inner electrode layers 150 in the stacking direction T. The number of dielectric layers 140 is preferably 100 or more and 1000 or less. The thickness of the dielectric layer 140 is preferably 0.4 μm or more and 0.8 μm or less.

[0051] Each of the multiple dielectric layers 140 can use a dielectric ceramic as the ceramic material, for example, containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, materials formed by adding by-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components can also be used.

[0052] like Figure 3 and Figure 4 As shown, the substrate portion 110 is divided into an inner layer portion C, a first outer layer portion X1 and a second outer layer portion X2, a first side edge portion S1 and a second side edge portion S2, a first end edge portion E1 and a second end edge portion E2. The inner layer portion C has electrostatic capacitance by being stacked in the lamination direction T through the first opposing portion 151C of the first internal electrode layer 151 (described later) and the second opposing portion 152C of the second internal electrode layer 152 (described later).

[0053] The first outer layer X1 and the second outer layer X2 sandwich the inner layer C in the stacking direction T. The first outer layer X1 is located outside the inner layer C in the stacking direction T, on the side of the first main surface 111. That is, the first outer layer X1 is located closer to the first main surface 111 than the inner electrode layer 150 located closest to the first main surface 111 in the stacking direction T. The second outer layer X2 is located outside the inner layer C in the stacking direction T, on the side of the second main surface 112. That is, the second outer layer X2 is located closer to the second main surface 112 than the inner electrode layer 150 located closest to the second main surface 112 in the stacking direction T.

[0054] The first outer layer X1 and the second outer layer X2 extend in the length direction L and the width direction W respectively, in a manner that includes the ridge portion of the base portion 110. The thickness of each of the first outer layer X1 and the second outer layer X2 is preferably 10 μm or more and 30 μm or less.

[0055] Both the first outer layer X1 and the second outer layer X2 include an outermost outer layer disposed on the outermost side and an inner outer layer disposed inside the outermost outer layer. The outermost outer layer is composed of a covering layer 160. The inner outer layer is composed of an outer dielectric layer.

[0056] like Figure 3As shown, the first end edge portion E1 and the second end edge portion E2 sandwich the inner layer portion C in the length direction L. The first end edge portion E1 is located outside the inner layer portion C in the length direction L, on the first end surface 115 side. The second end edge portion E2 is located outside the inner layer portion C in the length direction L, on the second end surface 116 side.

[0057] As shown, the side edge portion is located between the first side surface 113 and the plurality of internal electrode layers 150 and between the second side surface 114 and the plurality of internal electrode layers 150 in the width direction W in the base portion 110. The side edge portion is constituted by the covering layer 160. The covering layer 160 covers both end portions of the plurality of internal electrode layers 150 in the width direction W. Figures 4 to 6

[0058] Specifically, the first side edge portion S1 is provided to the side surface 101c of the above-described stacked body. The first side edge portion S1 is provided in a manner of covering the entirety of the side surface 101c. The first side edge portion S1 is present in the above-described base portion 110 in a range from one end portion of the internal electrode layers 150 on one side in the width direction W to the first side surface 113. That is, the covering layer 160 is formed on one end portion in the width direction W of the central portion in the length direction L of each of the plurality of internal electrode layers 150.

[0059] The second side edge portion S2 is provided to the side surface 101d of the above-described stacked body. The second side edge portion S2 is provided in a manner of covering the entirety of the side surface 101d. The second side edge portion S2 is present in the above-described base portion 110 in a range from the other end portion of the internal electrode layers 150 on the other side in the width direction W to the second side surface 114. That is, the covering layer 160 is formed on the other end portion in the width direction W of the central portion in the length direction L of each of the plurality of internal electrode layers 150.

[0060] The stacked ceramic capacitor 100 including the base portion 110, the first external electrode 120, and the second external electrode 130 is not particularly limited in specification, but for example, the following ranges can be adopted.

[0061] As shown, the size (length dimension L0) of the length direction L of the stacked ceramic capacitor 100 is, for example, 0.1 mm or more and 3.2 mm or less. The size (thickness dimension T0) of the stacking direction T of the stacked ceramic capacitor 100 is 0.05 mm or more and 1.6 mm or less. As shown, Figure 3 Figure 4 As shown, the size (width dimension W0) of the width direction W of the stacked ceramic capacitor 100 is, for example, 0.05 mm or more and 1.6 mm or less.

[0062] ​​The multilayer ceramic capacitor 100 has, for example, a size of 0.1 mm in length dimension L0, 0.05 mm in width dimension W0, and 0.05 mm in thickness dimension T0, or a size of 0.6 mm in length dimension L0, 0.3 mm in width dimension W0, and 0.3 mm in thickness dimension T0, or a size of 1.0 mm in length dimension L0, 0.5 mm in width dimension W0, and 0.5 mm in thickness dimension T0, or a size of 1.6 mm in length dimension L0, 0.8 mm in width dimension W0, and 0.8 mm in thickness dimension T0, or a size of 3.2 mm in length dimension L0, 1.6 mm in width dimension W0, and 1.6 mm in thickness dimension T0. Further, the above sizes take into account tolerances.

[0063] Figure 7 is a schematic cross-sectional view for explaining details of the side edge portion of the multilayer ceramic capacitor of the embodiment. In Figure 7 , a cross section parallel to the stacking direction T and the width direction W on the side of the second side surface 114 of the base portion 110 is shown. In the following description, the side of the second side edge portion S2 is described, but the same applies to the side of the first side edge portion S1.

[0064] As shown in Figure 7 , the second side edge portion S2 is composed of a cladding layer 160 containing Si and K. The composition of the cladding layer 160 can be confirmed by EDX (Energy dispersive X-ray spectroscopy). The cladding layer 160 is amorphous, which can be confirmed by Raman spectroscopy. In addition, it can also be confirmed that the cladding layer 160 is amorphous from the fact that a specific crystal pattern cannot be detected by X-ray diffraction using the cladding layer 160.

[0065] The second side edge portion S2 protrudes in a manner to contact the end portions in the width direction W of the plurality of internal electrode layers 150. Thereby, the partial portion 161 of the cladding layer 160 covering the portions of both end portions in the width direction W of the plurality of internal electrode layers 150 is sandwiched between the adjacent ones of the plurality of dielectric layers 140 in the stacking direction T. The reason for this shape is that the shrinkage rate of the internal electrode layer 150 is larger than that of the dielectric layer 140 at the time of firing. By this shape of the side edge portion, the fixing force of the side edge portion to the side surfaces 101c, 101d of the multilayer body 101 can be increased. Further, peeling of the side edge portion can be suppressed.

[0066] The minimum thickness TS of the covering layer 160 on the end portion in the width direction W of the plurality of internal electrode layers 150 is 0.01 μm or more and 10 μm or less. From the viewpoint of moisture resistance, the minimum thickness TS is more preferably 0.1 μm or more, and further preferably 0.3 μm or more. The shortest distance TP between the plurality of internal electrode layers 150 and the first side surface S1 and the shortest distance TP between the plurality of internal electrode layers 150 and the second side surface S2 is 0.01 μm or more and 10 μm or less. From the viewpoint of moisture resistance, the shortest distance TP is more preferably 0.1 μm or more, and further preferably 0.3 μm or more. Note that the numerical range of the minimum thickness TS and the shortest distance TP is not limited to the above range.

[0067] Using Figure 7 The above-described relationship of the shape and thickness can be confirmed by polishing the base portion 110 from the first external electrode 120 side to the central portion in the length direction L, and observing a cross section of the base portion 110 parallel to the stacking direction T and the width direction W using an electron microscope or the like. The thinnest thickness of the covering layer 160 measured in an image obtained by photographing the first internal electrode layer 151 or the second internal electrode layer 152 at the central portion in the stacking direction T of the cross section into a range of about 10 pieces of the field of view using an SEM (Scanning Electron Microscope) is set as the minimum thickness TS. Similarly, in the image, the shortest distance measured between the internal electrode layer 150 and the first side surface S1 or the second side surface S2 is set as the shortest distance TP.

[0068] Figure 8 is a schematic cross-sectional view for explaining a detailed configuration of the outer layer portion of the layered ceramic capacitor of the embodiment. In Figure 8 , a cross section of the base portion 110 parallel to the stacking direction T and the width direction W on the first outer layer portion X1 side is shown. In the following description, the first outer layer portion X1 side is described, but the same applies to the second outer layer portion X2 side.

[0069] As Figure 8 shown, the first outer layer portion X1 includes an outermost layer portion Xa disposed at the outermost side and an inner side outer layer portion Xb located inside the outermost layer portion Xa. The outermost layer portion Xa is composed of the covering layer 160. The inner side outer layer portion Xb is composed of the outer layer dielectric layer 140.

[0070] The outer surface of the inner outer layer Xb has fine irregularities caused by the dielectric grains of the outer dielectric layer 140. The cladding layer 160 is amorphous and covers the inner outer layer Xb in a way that fills the irregularities on its outer surface, so there are almost no irregularities on the outer surface of the outermost layer Xa. Therefore, the maximum height Ha of the irregularities on the outer surface of the outermost layer Xa is smaller than the maximum height Hb of the irregularities on the outer surface of the inner outer layer Xb. As a result, the impact resistance of the outermost layer Xa can be improved, and the reduction in the moisture resistance of the multilayer ceramic capacitor 100 can be suppressed.

[0071] The minimum thickness TM of the covering layer 160 in the stacking direction T of each of the first outer layer X1 and the second outer layer X2 is 0.01 μm or more and 0.5 μm or less. Furthermore, the value range of the minimum thickness TM is not limited to the above range.

[0072] use Figure 8 The relationship between the shape and thickness described above can be confirmed by grinding the substrate 110 from the side of the first external electrode 120 to the center of the length direction L, and observing a cross-section of the substrate 110 parallel to the stacking direction T and the width direction W using an electron microscope or the like. The thinnest thickness TM of the coating layer 160 in the stacking direction T, measured in an image obtained by taking a picture using a SEM (Scanning Electron Microscope) at the end of the stacking direction T of this cross-section where the first outer layer X1 or the second outer layer X2 enters the field of view, is defined as the minimum thickness TM.

[0073] Figure 9 This is a schematic cross-sectional view illustrating the detailed features of the end edges and external electrodes of the multilayer ceramic capacitor used to explain the embodiments. Figure 9 The diagram shows a cross-section of the second end edge E2 side of the substrate portion 110, parallel to the lamination direction T and the length direction L. In the following description, the second end edge E2 side will be described, but the same applies to the first end edge E1 side.

[0074] like Figure 9As shown, the external electrode includes a Cu layer 10, which contains Cu component 11 as the main component and glass component 12. The composition of the Cu layer 10 can be confirmed by EDX. A cladding layer 160 is disposed on the second end face 116, and a portion 13 of the Cu layer 10 penetrates the cladding layer 160 and is electrically connected to the second internal electrode layer 152. The cladding layer 160 is located between the plurality of dielectric layers 140 and the external electrode. Specifically, the cladding layer 160 is located between the plurality of dielectric layers 140 and the Cu layer 10. The thickness of the Cu layer 10 is 30 μm or more and 100 μm or less at the center of the stacking direction T and the width direction W. In addition, the numerical range of the thickness of the Cu layer 10 is not limited to the above range. The Cu layer 10 may also be a resin layer containing Cu component and glass component. In this case, a base metal layer is formed between the resin layer and the cladding layer 160.

[0075] Figure 7 The minimum thickness TS of the cladding layer 160 located at the ends of the plurality of internal electrode layers 150 in the width direction W is shown to be... Figure 9 The minimum thickness TE of the cladding layer 160 located between the plurality of dielectric layers 140 and the Cu layer 10 serving as an external electrode is shown.

[0076] use Figure 9 The relationship between the shape and thickness described above can be confirmed by grinding the substrate 110 from the first side 113 to the center of the width direction W, and observing a cross-section of the substrate 110 parallel to the stacking direction T and the length direction L using an electron microscope or the like. The thinnest thickness TE of the coating layer 160, measured in an image obtained by SEM at the center of the stacking direction T and the end of the length direction L of this cross-section, where the first internal electrode layer 151 or the second internal electrode layer 152 enters the field of view in about 10 images, is defined as the minimum thickness TE.

[0077] Become like Figure 9 The reason for the shape shown is that, because the cladding layer 160 contains K, the melting point of the Si contained in the cladding layer 160 is lowered to below the firing temperature of the Cu layer 10. Therefore, during the firing of the Cu layer 10, the cladding layer 160 melts, and the shrinkage force of the Cu layer 10 acts on the molten cladding layer 160, with a portion 13 of the Cu layer 10 penetrating the cladding layer 160 and connecting to the second inner electrode layer 152.

[0078] The K contained in the clad layer 160 flows and diffuses into the glass component 12 in the Cu layer 10. That is, the glass component 12 contains K. The closer to the 2nd end surface 116, the higher the concentration of K contained in the glass component 12. In addition, part of Si contained in the clad layer 160 enters the Cu layer 10 to combine with the glass component 12 in the Cu layer 10. Cu diffuses from the Cu layer 10 into Ni of the internal electrode layer 150. Thus, the fixing force of the Cu layer 10 to the internal electrode layer 150 increases. Further, peeling of the 1st external electrode 120 and the 2nd external electrode 130 can be suppressed.

[0079] Figure 7 The Si concentration of the clad layer 160 shown on the end portion in the width direction W of the plurality of internal electrode layers 150 is higher than that of the clad layer 160 shown on the end portion in the width direction W of the plurality of internal electrode layers 150. Figure 9 The Si concentration of the clad layer 160 shown between the plurality of dielectric layers 140 and the external electrode is high.

[0080] Figure 7 The K concentration of the clad layer 160 shown on the end portion in the width direction W of the plurality of internal electrode layers 150 is higher than that of the clad layer 160 shown on the end portion in the width direction W of the plurality of internal electrode layers 150. Figure 9 The K concentration of the clad layer 160 shown between the plurality of dielectric layers 140 and the external electrode is high.

[0081] The concentration distribution of Si and K can also be observed from a captured image of TEM (Transmission Electron Microscope) or EDX. For example, in an image obtained by capturing the 1st internal electrode layer 151 or the 2nd internal electrode layer 152 with TEM to enter a range of about one field of view, the concentration gradient of Si and K is measured with TEM as a mole ratio of 100 mol with respect to Ti contained in the dielectric layer 140.

[0082] With the above-described structure of the clad layer 160 and the external electrode, it is possible to ensure moisture resistance with a thinner side edge portion, and it is possible to ensure electrical connection of the internal electrode layer 150 to the external electrode without removing the clad layer 160 at the 1st end surface 115 and the 2nd end surface 116 by sandblasting or the like. Further, it is possible to expand the allocable area of the internal electrode layer 150, and make the multilayer ceramic capacitor 100 small and large-capacitance.

[0083] Figure 10 is a schematic cross-sectional view showing a detailed structure of an external electrode of a multilayer ceramic capacitor of an embodiment. In Figure 10 In the 2nd external electrode 130 side of the base portion 110, a cross section parallel to the stacking direction T and the length direction L is shown. In the following description, the 2nd external electrode 130 side is described, but the same applies to the 1st external electrode 120 side.

[0084] AsFigure 10 As shown, the first external electrode 120 and the second external electrode 130 include a Cu layer 10 disposed on the substrate portion 110, a Ni plating layer 20 disposed on the Cu layer 10, and a Sn plating layer 30 disposed on the Ni plating layer 20.

[0085] Furthermore, the material constituting the coating can also be a metal or an alloy containing the metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au. The combined thickness of the Ni coating 20 and the Sn coating 30 is, for example, 3 μm or more and 20 μm or less.

[0086] In this embodiment, such as Figure 6 As shown, when viewed in the width direction W, the protrusion 120E overlaps only with a narrow portion 152N of the second internal electrode layer 152, which is not electrically connected to the first external electrode 120 containing the protrusion 120E, among the plurality of internal electrode layers 150. Figure 5 and Figure 10 As shown, when viewed in the width direction W, the protrusion 130E overlaps only with the narrow portion 151N of the first internal electrode layer 151, which is not electrically connected to the second external electrode 130 containing the protrusion 130E, among the plurality of internal electrode layers 150.

[0087] Therefore, it is possible to suppress the situation where the protrusion 120E is electrically connected to the end of the second inner electrode layer 152 in the width direction W and short-circuit occurs. Similarly, it is possible to suppress the situation where the protrusion 130E is electrically connected to the end of the first inner electrode layer 151 in the width direction W and short-circuit occurs.

[0088] Figure 11 This is a schematic cross-sectional view illustrating the offset in the width direction of the protruding portion of the internal electrode layer in the multilayer ceramic capacitor used to explain the embodiment. Additionally, in Figure 11 The diagram is provided for illustrative purposes to show the offset of the protruding part; the position of the protruding part is not limited to [specific location]. Figure 11 As shown in the diagram.

[0089] like Figure 11 As shown, the offset D1 in the width direction W between the protrusion 130E located on the first side 113 and the protrusion 130E located on the second side 114 is 3 μm or more. The same offset is also present in the protrusions 120E. Thus, the ends of the protrusions 120E and 130E in the width direction W are not aligned in the stacking direction T, but are offset in the width direction W.

[0090] On the other hand, such as Figure 4As shown, in a cross section of the base portion 110 at the central portion in the length direction L of the base portion 110, parallel to the stacking direction T and the width direction W, the width direction W offset amount of the internal electrode layers 150 adjacent to each other in the stacking direction T is less than 3 μm.

[0091] That is, the position offset amount in the width direction W of the first narrow portion 151N and the second narrow portion 152N is greater than the position offset amount in the width direction W of the central portion of the length direction L of the plurality of internal electrode layers 150.

[0092] Therefore, it is preferable that the width of the first narrow portion 151N and the second narrow portion 152N be greater than the assumed maximum position offset amount in the width direction W of the first narrow portion 151N and the second narrow portion 152N, and be narrower than the width of the central portion of the length direction L of the plurality of internal electrode layers 150. Thereby, it is possible to stably suppress the case where the extension portion 120E is electrically connected to the end portion in the width direction W of the second internal electrode layer 152 and short-circuits. Also, it is possible to stably suppress the case where the extension portion 130E is electrically connected to the end portion in the width direction W of the first internal electrode layer 151 and short-circuits.

[0093] Hereinafter, the manufacturing method of the multilayer ceramic capacitor 100 of the present embodiment will be described. Figure 12 is a flowchart showing the manufacturing method of the multilayer ceramic capacitor of the present embodiment.

[0094] As shown in Figure 12 , a ceramic dielectric slurry is prepared (step S1). Specifically, a ceramic dielectric powder, an additive powder, a binder resin, a dissolving solution, and the like are mixed and dispersed, whereby the ceramic dielectric slurry is prepared. The ceramic dielectric powder is, for example, a dielectric particle of a perovskite structure such as BaTiO3, CaTiO3, SrTiO3, CaZrO3, or CaHfO3. The additive powder is composed of, for example, at least any one of a Si compound, a Mg compound, a Mn compound, a Fe compound, a Cr compound, a Ni compound, and a Co compound. As the binder resin, a polyurethane resin, a urea resin, a melamine resin, an epoxy resin, a vinyl acetate resin, an acrylic resin, or a water-based polymer such as polyvinyl alcohol (PVA) or polyvinyl butyral (PVB), or the like can be used. They can be used alone or in a mixture of two or more. The ceramic dielectric slurry can be either of a solvent system and a water system. In the case where the ceramic dielectric slurry is a water-based paint, the ceramic dielectric slurry is prepared by mixing a water-soluble binder and a dispersant, or the like, with a dielectric raw material dissolved in water.

[0095] Next, a ceramic dielectric sheet is formed (step S2). Specifically, a ceramic dielectric paste is formed into a sheet shape on a support film and dried by using an extrusion coater, a gravure coater, or a microgravure coater, and the like, thereby forming a ceramic dielectric sheet. From the viewpoint of miniaturization and high capacitance of the multilayer ceramic capacitor, the thickness of the ceramic dielectric sheet is preferably 0.4 μm or more and 0.8 μm or less.

[0096] Next, a mother sheet is formed (step S3). Specifically, a mother sheet in which a predetermined internal electrode pattern is provided on a ceramic dielectric sheet is formed by applying a conductive paste to the ceramic dielectric sheet in a predetermined pattern. The conductive paste contains a Ni powder, a solvent, a dispersant, a binder, and the like, and is prepared in a manner that the viscosity is constant. As the binder, polyvinyl butyral (PVB) or polyvinyl alcohol (PVA), or the like is used. As the application method of the conductive paste, a screen printing method, an inkjet method, a gravure printing method, or the like can be used. From the viewpoint of miniaturization and high capacitance of the multilayer ceramic capacitor, the thickness of the internal electrode pattern is preferably 0.3 μm or more and 0.8 μm or less. In addition, as the mother sheet, in addition to the mother sheet having the internal electrode pattern, a ceramic dielectric sheet that has not undergone the above step S3 is prepared.

[0097] Next, a plurality of mother sheets are laminated (step S4). Specifically, a mother sheet composed only of a ceramic dielectric sheet in which no internal electrode pattern is formed is laminated in a predetermined number of sheets in a manner that the thickness becomes 10 μm or more and 30 μm or less, for example. On top of this, a mother sheet having an internal electrode pattern is laminated in a predetermined number of sheets. The number of laminated sheets of the mother sheet having an internal electrode pattern is one or more and 1000 or less, for example. Further, on top of this, a mother sheet composed only of a ceramic dielectric sheet in which no internal electrode pattern is formed is laminated in a predetermined number of sheets in a manner that the thickness becomes 10 μm or more and 30 μm or less, for example. Thus, a mother sheet group is constituted.

[0098] Next, a dielectric block is formed by pressing the mother sheet group (step S5). Specifically, the mother sheet group is pressed in the lamination direction by isostatic pressing or rigid body pressing, and is pressed and joined, thereby forming a dielectric block. At this time, the ceramic dielectric sheets are pressed at a predetermined temperature, and are caused to adhere to each other. In addition, by disposing a certain thickness of ceramic dielectric sheets on the outermost layer in the lamination direction and pressing, the dielectric sheets on which the internal electrode patterns are formed can be protected.

[0099] Next, the dielectric block is cut to form a chip (step S6). Specifically, the dielectric block is cut in a matrix shape by shearing, dicing, or laser cutting, and is singulated into a plurality of chips. At the time of cutting the dielectric block, the dielectric block can also be cut in a state in which the dielectric block is heated and softened.

[0100] Next, the chip is fired (step S7). Specifically, the chip is heated, thereby firing the dielectric material and the conductive material contained in the chip, to form the laminate 101. The firing temperature is appropriately set in correspondence with the dielectric material and the conductive material.

[0101] Next, the chip after the firing is coated with the coating layer 160 (step S8). Specifically, the laminate 101 after the firing is dipped in a solution containing Si and K, and then dried. The above solution is, for example, water glass containing K.

[0102] Next, the chip is coated with the paste to be the Cu layer 10 (step S9). Specifically, the paste containing Cu particles and containing a glass component is coated on the first end surface 115 and the second end surface 116 of the base portion 110 after the drying, and then dried.

[0103] Next, the chip coated with the paste to be the Cu layer 10 is fired (step S10). Specifically, the base portion 110 coated with the paste to be the Cu layer 10 is fired at a temperature of 600°C or higher and 800°C or lower. Thereby, the metal component contained in the paste to be the Cu layer 10 is sintered, and the coating layer 160 is melted, the first internal electrode layer 151 and the Cu layer 10 are electrically connected at the first end surface 115, and the second internal electrode layer 152 and the Cu layer 10 are electrically connected at the second end surface 116.

[0104] Next, the external electrodes are formed (step S11). The Ni plating layer 20 and the Sn plating layer 30 are formed by sequentially performing plating of Ni and plating of Sn on the Cu layer 10, thereby forming the first external electrode 120 and the second external electrode 130.

[0105] By going through the above series of steps, the laminate ceramic capacitor 100 of the embodiment can be manufactured.

[0106] Hereinafter, the laminate ceramic capacitor of the modification of the embodiment will be described. Further, the laminate ceramic capacitor of the modification is different from the laminate ceramic capacitor 100 of the embodiment in that the base electrode layer containing Ni as a main component is formed on the first end surface 115 and the second end surface 116 of the base portion 110, and mainly this point, and thus the description will not be repeated for the same structure as the laminate ceramic capacitor 100 of the embodiment.

[0107] Figure 13 is a schematic cross-sectional view for illustrating the details of the end edge portion and the external electrode of the laminate ceramic capacitor of the modification. In Figure 13 , a cross section parallel to the stacking direction T and the length direction L on the second end edge portion E2 side of the base portion 110 is shown. In the following description, the second end edge portion E2 side is described, but the same applies to the first end edge portion El side.

[0108] AsFigure 13 As shown, the external electrode includes the base electrode layer 40 containing Ni as a main component and the Cu layer 10 containing the Cu component 11 as a main component and containing the glass component 12. Also, the base electrode layer 40 can further include dielectric particles of the same composition group as the ceramic included in the dielectric layer 140.

[0109] The base electrode layer 40 is formed on the 2nd end surface 116, the cladding layer 160 is formed on the base electrode layer 40, and the Cu layer 10 is formed on the cladding layer 160. The base electrode layer 40 is covered with the Cu layer 10.

[0110] Figure 7 The minimum thickness TS of the cladding layer 160 shown on the end portions in the width direction W of the plurality of internal electrode layers 150 is thinner than the minimum thickness T of the cladding layer 160 shown between the base electrode layer 40 and the Cu layer 10. Figure 13 The minimum thickness TF of the cladding layer 160 shown between the base electrode layer 40 and the Cu layer 10 is thicker than the minimum thickness T of the cladding layer 160 shown on the end portions in the width direction W of the plurality of internal electrode layers 150.

[0111] As shown, the Cu layer 10 is partially 13 electrically connected to the base electrode layer 40 through the cladding layer 160. The Cu layer 10 is electrically connected to the 2nd internal electrode layer 152 via the base electrode layer 40. Figure 13

[0112] In the present modified example, the base electrode layer 40 is formed so as to wrap around from the 2nd end surface 116 to the 1st main surface 111, the 2nd main surface 112, the 1st side surface 113, and the 2nd side surface 114. Also, the base electrode layer 40 is formed so as to wrap around from the 1st end surface 115 to the 1st main surface 111, the 2nd main surface 112, the 1st side surface 113, and the 2nd side surface 114.

[0113] In the multilayer ceramic capacitor of the modified example, the Cu layer 10 and the 2nd internal electrode layer 152 are electrically connected via the base electrode layer 40 covering the entirety of the 2nd end surface 116, and thus the 2nd internal electrode layer 152 and the 2nd external electrode 130 can be stably electrically connected. Also, the Cu layer 10 and the 1st internal electrode layer 151 are electrically connected via the base electrode layer 40 covering the entirety of the 1st end surface 115, and thus the 1st internal electrode layer 151 and the 1st external electrode 120 can be stably electrically connected.

[0114] The K included in the cladding layer 160 flows and diffuses into the glass component 12 in the Cu layer 10. Part of the Si included in the cladding layer 160 enters into the Cu layer 10 to combine with the glass component 12 in the Cu layer 10. Cu diffuses from the Cu layer 10 into the Ni of the base electrode layer 40. Thereby, the fixing force of the Cu layer 10 to the base electrode layer 40 increases. Further, peeling of the 1st external electrode 120 and the 2nd external electrode 130 can be suppressed.

[0115] ​Next, a manufacturing method of the multilayer ceramic capacitor of the modification example will be described. Figure 14 is a flowchart showing the manufacturing method of the multilayer ceramic capacitor of the modification example.

[0116] As shown in Figure 14 , the manufacturing method of the multilayer ceramic capacitor of the modification example is the same as the processes S1 to S6 of the manufacturing method of the multilayer ceramic capacitor 100.

[0117] After the process S6, the chip is coated with a paste that becomes the base electrode layer (process S17). Specifically, the paste containing Ni particles is applied to and dried on the end surface 101e and the end surface 101f of the laminate 101, respectively.

[0118] Next, the chip coated with the paste that becomes the base electrode layer 40 is fired (process S18). Specifically, the chip is heated, whereby the paste containing Ni particles is fired together with the dielectric material and the conductive material contained in the chip, thereby forming the laminate 101 and the base electrode layer 40.

[0119] Next, the chip on which the base electrode layer 40 is formed is formed with a coating layer 160 (process S19). Specifically, the laminate 101 on which the base electrode layer 40 is formed is dipped in a solution containing Si and K, and then dried. The above solution is, for example, a water glass containing K.

[0120] Next, the chip is coated with a paste that becomes the Cu layer 10 (process S20). Specifically, the paste containing Cu particles and containing a glass component is applied so as to cover the base electrode layer 40 of each of the first end surface 115 and the second end surface 116 through the coating layer 160, and then dried.

[0121] Next, the chip coated with the paste that becomes the Cu layer 10 is fired (process S21). Specifically, the chip coated with the paste that becomes the Cu layer 10 is fired at a temperature of 600°C or higher and 800°C or lower. Thereby, the metal component contained in the paste that becomes the Cu layer 10 is sintered, and the coating layer 160 is melted, and the base electrode layer 40 is electrically connected to the Cu layer 10.

[0122] Next, an external electrode is formed (process S22). The Ni plating layer 20 and the Sn plating layer 30 are formed by sequentially performing plating of Ni and plating of Sn on the Cu layer 10, thereby forming the first external electrode 120 and the second external electrode 130.

[0123] By going through the above series of processes, the multilayer ceramic capacitor of the modification example can be manufactured.

[0124] In the description of the above embodiment, structures that can be combined can be combined with each other.

[0125] It should be considered that the embodiments disclosed herein are illustrative and not restrictive in all aspects. The scope of the present application is indicated by the claims and not by the above description, and it is intended to include all modifications within the meaning and range equivalent to the claims.

[0126] BRIEF DESCRIPTION OF DRAWINGS

[0127] 10 Cu layer; 11 Cu component; 12 glass component; 20 Ni plating layer; 30 Sn plating layer; 40 base electrode layer; 100 laminated ceramic capacitor; 101 laminate; 101a, 101b main surface; 101c, 101d side surface; 101e, 101f end surface; 110 base portion; 111 first main surface; 112 second main surface; 113 S1 first side surface; 114 S2 second side surface; 115 first end surface; 116 second end surface; 120 first external electrode; 120E, 130E extension portion; 130 second external electrode; 140 dielectric layer; 150 internal electrode layer; 151 first internal electrode layer; 151C first opposing portion; 151N, 152N narrow portion; 151X first lead-out portion; 152 second internal electrode layer; 152C second opposing portion; 152X second lead-out portion; 160 covering layer; C inner layer portion; E1 first end edge portion; E2 second end edge portion; S1 first side edge portion; S2 second side edge portion; X1 first outer layer portion; X2 second outer layer portion; Xa outermost layer portion; Xb inner outer layer portion.

Claims

1. A multilayer ceramic capacitor, wherein the multilayer ceramic capacitor comprises: a base portion including a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; and external electrodes provided on the first end surface and the second end surface, respectively, and electrically connected to the plurality of internal electrode layers, the base portion includes: a first outer layer portion located on a position closer to the first main surface than an internal electrode layer located closest to the first main surface among the plurality of internal electrode layers in the stacking direction; and a second outer layer portion located on a position closer to the second main surface than an internal electrode layer located closest to the second main surface among the plurality of internal electrode layers in the stacking direction, the first outer layer portion and the second outer layer portion each include an outermost layer portion disposed on an outermost side and an inner side outer layer portion located on an inner side of the outermost layer portion, a maximum height of a concave-convex of an outer surface of the outermost layer portion is smaller than a maximum height of a concave-convex of an outer surface of the inner side outer layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein the outermost layer portion is composed of a cladding layer containing Si and K.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the inner side outer layer portion is composed of a part of the plurality of dielectric layers.

4. The multilayer ceramic capacitor according to claim 2, wherein the cladding layer covers both end portions of the plurality of internal electrode layers in the width direction.

5. The multilayer ceramic capacitor according to claim 4, wherein a part of the cladding layer covering both end portions of the plurality of internal electrode layers in the width direction is sandwiched between adjacent dielectric layers in the stacking direction among the plurality of dielectric layers.

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