Method for forming semiconductor device

Abstract

A method of forming a semiconductor device includes forming a plurality of first patterns extending in a first direction in a first hard mask layer on a substrate, each first pattern including a first central section and two first end sections; forming a plurality of second patterns extending in a second direction different from the first direction in the second hard mask layer on the substrate, wherein each second pattern comprises a second central section and two second end sections; forming a hole pattern in a third hard mask layer by using the first pattern and the second pattern, wherein the third hard mask layer is positioned above the substrate and below the first and second hard mask layers; forming a photoresist layer to cover a second central section of the second pattern; and removing a first end section of the first pattern and a second end section of the second pattern. According to the method, the accuracy requirement of the position where the edge of the photoresist layer is located is low, and the gap filling material cannot be filled into the hole, so that the shape of the hole can be maintained, and the yield of the capacitor hole can be improved.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device. Background Art

[0002] The yield of capacitor holes in semiconductor devices is determined by the quality of the hole pattern that serves as a mask. However, in conventional practices, a mask is formed to surround the periphery of the hole pattern, and the holes of the hole pattern are exposed. In other words, the edge of such a mask is directly adjacent to the hole. As a result, the accuracy of the edge position is required to be high and it is easy to result in poor hole quality. The subsequent stack alignment and overlay measurement is achieved using a matrix mask, and this matrix mask is defined by the aforementioned mask and capacitor holes. Therefore, poor edge quality leads to poor alignment and overlay measurement signals. The stack in subsequent processes will suffer the consequences of poor alignment and overlay.

[0003] In view of this, how to provide a method that can provide high-quality hole patterns is still a goal of research and development in this field. Summary of the Invention

[0004] A technical aspect of the present invention is a method for forming a semiconductor device.

[0005] In one embodiment of the present invention, a method for forming a semiconductor device includes forming a plurality of first patterns extending in a first direction in a first hard mask layer on a substrate, wherein each of the first patterns includes a first central section and two first end sections; forming a plurality of second patterns extending in a second direction different from the first direction in the first hard mask layer on the substrate, wherein each of the second patterns includes a second central section and two second end sections; forming a hole pattern in a third hard mask layer by using the first pattern and the second pattern, wherein the third hard mask layer is located above the substrate and below the first hard mask layer and the second hard mask layer; forming a photoresist layer to cover the second central section of the second pattern; and removing the first end section of the first pattern and the second end section of the second pattern.

[0006] In one embodiment of the present invention, forming the first pattern further includes forming a plurality of first dummy patterns on the first hard mask layer; forming a plurality of first spacer layers respectively surrounding the first dummy patterns; removing the first dummy patterns; and etching the first hard mask layer using the first spacer layers to form the first pattern.

[0007] In one embodiment of the present invention, forming the first pattern further includes forming a plurality of second dummy patterns on the second hard mask layer; forming a plurality of second spacer layers respectively surrounding the second dummy patterns; removing the second dummy patterns; and etching the second hard mask layer using the second spacer layers to form the second pattern.

[0008] In one embodiment of the present invention, forming the photoresist layer to cover the second central section of the second pattern further includes forming the photoresist layer such that the first end section of the first pattern and the second end section of the second pattern are exposed from the photoresist layer.

[0009] In one embodiment of the present invention, forming the photoresist layer to cover the second central section of the second pattern further includes forming the photoresist layer such that a first distance exists between a first edge of the photoresist layer along the first direction and one of the first patterns closest to the first edge, and the first distance is in a range of 0 to 50 nanometers.

[0010] In one embodiment of the present invention, forming the photoresist layer to cover the second central section of the second pattern further includes forming the photoresist layer such that a second distance exists between a second edge of the photoresist layer along the second direction and one of the second patterns closest to the second edge, and the second distance is in a range of 0 to 50 nanometers.

[0011] In one embodiment of the present invention, forming a hole pattern in the third hard mask layer by using the first pattern and the second pattern further includes making a size of a plurality of holes in the hole pattern range from 20×20 nm square to 50×50 nm square.

[0012] In one embodiment of the present invention, the method for forming a display device further includes filling a gap-filling material around the hole pattern, wherein the gap-filling material is not filled in the plurality of holes of the hole pattern.

[0013] In one embodiment of the present invention, the method for forming a display device further includes using a gap filling material as a low-fluidity material.

[0014] In one embodiment of the present invention, the method for forming a display device further includes etching the gap filling material to expose the upper surface of the hole pattern.

[0015] In one embodiment of the present invention, the method for forming a semiconductor device further includes etching a substrate using the hole pattern to form a plurality of capacitor vias.

[0016] A technical aspect of the present invention is a method for forming a semiconductor device.

[0017] In one embodiment of the present invention, a method for forming a semiconductor device includes forming a hole pattern in a first hard mask layer on a substrate, wherein the hole pattern includes a central segment and a plurality of end segments surrounding the central segment; forming a photoresist layer to cover the central segment of the hole pattern; removing the end segments of the hole pattern; and etching the substrate using the hole pattern to form a plurality of capacitor vias.

[0018] In one embodiment of the present invention, forming the hole pattern in the first hard mask layer further includes making the sizes of the holes in the hole pattern range from 20×20 nanometers square to 50×50 nanometers square.

[0019] In one embodiment of the present invention, the method for forming a semiconductor device further includes filling a gap-filling material around the hole pattern, wherein the gap-filling material is not filled in the hole.

[0020] In one embodiment of the present invention, forming the hole pattern in the first hard mask layer further includes etching the gap filling material to expose the upper surface of the hole pattern.

[0021] In one embodiment of the present invention, forming the hole pattern in the first hard mask layer further includes forming a plurality of first patterns extending in a first direction in the second hard mask layer on the substrate, wherein each of the first patterns includes a first central segment and two first end segments.

[0022] In one embodiment of the present invention, forming the photoresist layer to cover the central section of the hole pattern further includes forming the photoresist layer such that a first distance exists between a first edge of the photoresist layer along the first direction and one of the first patterns closest to the first edge, and the first distance is in a range of 0 to 50 nanometers.

[0023] In one embodiment of the present invention, forming the hole pattern in the first hard mask layer further includes forming a plurality of second patterns extending in a second direction different from the first direction in a third hard mask layer on the substrate, wherein each of the second patterns includes a second central segment and two second end segments.

[0024] In one embodiment of the present invention, the first central section and the second central section define the central section of the hole pattern.

[0025] In one embodiment of the present invention, forming the photoresist layer to cover the central section of the hole pattern further includes forming the photoresist layer such that a second distance exists between a second edge of the photoresist layer along the second direction and one of the second patterns closest to the second edge, and the second distance is in a range of 0 to 50 nanometers.

[0026] In the above-mentioned embodiment, the method of the present invention can relax the accuracy requirements for the edge of the photoresist layer by using a photoresist layer to cover the first central section of the first pattern and the second central section of the second pattern. Furthermore, since the gap-filling material cannot fill the hole, it helps maintain the shape of the hole. This improves the yield of the capacitor hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0028] Figure 2A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0029] Figure 2B for Figure 2A Cross-sectional view along line segment 2B-2B.

[0030] Figure 3A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0031] Figure 3B for Figure 3A Cross-sectional view along line segment 3B-3B.

[0032] Figure 4A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0033] Figure 4B for Figure 4A Cross-sectional view along line segment 4B-4B.

[0034] Figure 5A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0035] Figure 5B for Figure 5A Cross-sectional view along line segment 5B-5B.

[0036] Figure 6A and Figure 6B Schematic diagrams of first patterns and second patterns according to different embodiments of the present invention.

[0037] Figure 7A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0038] Figure 7B for Figure 7A Cross-sectional view along line segment 7B-7B.

[0039] Figure 8A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0040] Figure 8B for Figure 8A Cross-sectional view along line 8B-8B.

[0041] Figure 9 FIG. 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0042] Figure 10AFIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0043] Figure 10B for Figure 10A Cross-sectional view along line segment 10B-10B.

[0044] Figure 11 FIG. 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0045] Figure 12 FIG. 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following drawings illustrate various embodiments of the present invention. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details should not be construed as limiting the present invention. In other words, in some embodiments of the present invention, these practical details are optional. Furthermore, to simplify the drawings, some conventional structures and components are depicted in simplified schematic form. For clarity, the thicknesses of layers and regions in the drawings may be exaggerated, and identical reference numerals represent identical components throughout the drawings.

[0047] Figure 1 FIG. 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0048] Figure 2A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention.

[0049] Figure 2B for Figure 2A Cross-sectional view along line segment 2B-2B. Figure 3A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 3B for Figure 3A Cross-sectional view along line segment 3B-3B.

[0050] The method for forming a semiconductor device begins by forming a plurality of first patterns 136 ( Figure 3B ) in the first hard mask layer 120 on the substrate 110. The first hard mask layer 120 is disposed on the third hard mask layer 140, and the third hard mask layer 140 is disposed on the substrate 110. The substrate 110 includes a plurality of layers, such as a lower silicon nitride layer, a borophospho-silicate glass (BPSG) layer, an oxide layer, and an upper silicon nitride layer. For example, the steps of forming the first pattern 136 are shown in FIG. Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B In this embodiment, the step of forming the first pattern 136 is a self-aligned double patterning (SADP) method. In other embodiments, the step of forming the first pattern 136 is a litho-etch-litho-etch (LELE) method, a litho-freeze-litho-etch (LFLE) method, or other suitable methods.

[0051] like Figure 1 As shown, a plurality of first dummy patterns 132 are formed on the first hard mask layer 120. Figure 2A and Figure 2B As shown, a plurality of first spacer layers 134 are formed to surround the first dummy patterns 132. Specifically, the material of the first spacer layers 134 is first deposited to cover the first dummy patterns 132 and the first hard mask layer 120, and then a portion of the material located above the first hard mask layer 120 and on the upper surface of the first dummy patterns 132 is removed. Figure 2A As shown, each of the first spacers 134 has a rectangular shape surrounding the first dummy pattern 132 , and the first dummy pattern 132 is exposed.

[0052] like Figure 3A and Figure 3B As shown, the first dummy pattern 132 is removed, and the first hard mask layer 120 is etched using the first spacer layer 134 as a mask to form first patterns 136. Each first pattern 136 includes a first central section 1362 and two first end sections 1364 and 1366. The first central section 1362 corresponds to the section that will be used to form capacitor holes in a subsequent process. The first end sections 1364 and 1366 correspond to the sections that will be removed in a subsequent process.

[0053] Figure 4A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 4B for Figure 4A Cross-sectional view along line segment 4B-4B. Figure 5A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 5B for Figure 5A Cross-sectional view along line segment 5B-5B.

[0054] The method for forming the semiconductor device continues with the step of forming a plurality of second patterns 176 extending in a second direction D2 different from the first direction D1. Figure 4A As shown, the first spacer layer 134 and the first pattern 136 are covered by the dielectric layer 150, and the second hard mask layer 160 is disposed above the dielectric layer 150. The second dummy pattern 172 is formed on the second hard mask layer 160. The second spacer layer 174 is formed to surround the second dummy pattern 172. The process of forming the second dummy pattern 172 and the second spacer layer 174 is substantially the same as that of Figure 1 and Figure 2B The process of forming the first dummy pattern 132 and the first spacer layer 134 is the same.

[0055] like Figure 5A and Figure 5B As shown, the second dummy pattern 172 is removed, and the second hard mask layer 160 is etched using the second spacer layer 174 as a mask to form second patterns 176. Each second pattern 176 includes a second central segment 1762 and two second end segments 1764 and 1766. The second central segment 1762 corresponds to the segment that will be used to form capacitor holes in a subsequent process. The second end segments 1764 and 1766 correspond to the segments that will be removed in a subsequent process.

[0056] Figure 6A and Figure 6B Schematic diagram of the first pattern 136a and the second pattern 176a according to different embodiments of the present invention. Figure 6A As shown, the first pattern 136a and the second pattern 176a extend in a third direction D3 and a fourth direction D4 that are different from the first direction D1 and the second direction D2. Figure 6B As shown, the first pattern 136b and the second pattern 176b extend in a fifth direction D5 and a sixth direction D6 that are different from the first direction D1 and the second direction D2. The angle difference between the fifth direction D5 and the sixth direction D6 may be different from 90 degrees.

[0057] Figure 7A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 7B for Figure 7A Cross-sectional view along line 7B-7B. The method of forming the semiconductor device continues by forming a hole pattern 142 in the third hard mask layer 140 using the first pattern 136 and the second pattern 176 as masks. The third hard mask layer 140 is etched to transform the first pattern 136 and the second pattern 176 to form the hole pattern 142. Therefore, the first central section 1362 ( Figure 3A ) spans the second central section 1762 of the second pattern 176 ( Figure 5A) and form a plurality of holes 144. In other words, the first central section 1362 ( Figure 3A ) spans the second central section 1762 of the second pattern 176 to define the central section of the hole pattern 142. The size of the holes 144 of the hole pattern 142 ranges from 20×20 nanometers square to 50×50 nanometers square.

[0058] Figure 8A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 8B for Figure 8A Cross-sectional view along line 8B-8B. The method for forming the semiconductor device continues with the step of forming a photoresist layer 180 to cover the first central section 1362 of the first pattern 136 and the second central section 1762 of the second pattern 176. In other words, the plurality of holes 144 of the hole pattern 142 are covered by the photoresist layer 180. The first end sections 1364 and 1366 of the first pattern 136 and the second end sections 1764 and 1766 of the second pattern 176 are exposed from the photoresist layer 180.

[0059] Reference Figure 8A A first distance L1 is defined between a first edge 182 of the photoresist layer 180 along the first direction D1 and the portion of the first pattern 136 closest to the first edge 182, and the first distance L1 is within a range of 0 to 50 nanometers. Similarly, a second distance L2 is defined between a second edge 184 of the photoresist layer 180 along the second direction D2 and the portion of the second pattern 176 closest to the second edge 184, and the second distance L2 is within a range of 0 to 50 nanometers.

[0060] Through these methods, the first distance L1 does not affect the shape of the hole 144. In other words, the accuracy requirements for the position of the edge of the photoresist layer 180 are relatively loose. In conventional methods, the photoresist layer is formed to cover the edge area of ​​the hole pattern 142. In other words, the photoresist layer covers the first end sections 1364 and 1366 of the first pattern 136 and the second end sections 1764 and 1766 of the second pattern 176, and the edge of the photoresist layer is directly adjacent to the hole 144. As a result, the accuracy requirements for the position of the edge of the photoresist layer are relatively high. Otherwise, the shape of the hole 144 will be affected.

[0061] Figure 9 FIG1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 8A and Figure 9The method of forming the semiconductor device continues with the step of removing the first end sections 1364, 1366 of the first pattern 136 and the second end sections 1764, 1766 of the second pattern 176. After removing the second end sections 1764, 1766 of the second pattern 176, the photoresist layer 180 is removed to expose the first central section 1362 of the first pattern 136 and the second central section 1762 of the second pattern 176.

[0062] Figure 10A FIG. 1 is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 10B for Figure 10A The method of forming the semiconductor device continues with filling the gap filling material 190 around the hole pattern 142, wherein the gap filling material 190 is not filled into the hole 144. Figure 10B Since the gap filling material 190 has lower resin fluidity, higher molecular weight, higher etching resistance, higher flatness, and contains more reactive resin, the gap filling material 190 may not be filled into the holes 144 of the hole pattern 142 .

[0063] Figure 11 FIG2 is a cross-sectional view illustrating an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present invention. The method continues by polishing or etching back gapfill material 190 until the upper surface of hole pattern 142 is exposed to confirm that no gapfill material 190 remains in hole 144. Since gapfill material 190 cannot fill hole 144, the shape of hole 144 is maintained.

[0064] Figure 12 FIG. 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present invention. The method for forming a semiconductor device continues with a step of etching the substrate 110 using the hole pattern 142 to form a capacitor hole 112 .

[0065] In summary, the method of the present invention can relax the precision requirements for the edge of the photoresist layer by using a photoresist layer to cover the first central section of the first pattern and the second central section of the second pattern. Furthermore, since the gap-filling material cannot fill the holes, it helps maintain the hole shape. This improves the yield of capacitor holes.

[0066] Although the present invention has been disclosed above in terms of embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0067]

Explanation of symbols

[0068] 110:Substrate

[0069] 112: Capacitor hole

[0070] 120: First hard mask layer

[0071] 132: First dummy pattern

[0072] 134: first spacer layer

[0073] 136,136a,136b: First pattern

[0074] 1362: First central section

[0075] 1364, 1366: first terminal segment

[0076] 140: Third hard mask layer

[0077] 142:Hole pattern

[0078] 144: Hole

[0079] 150: dielectric layer

[0080] 160: Second hard mask layer

[0081] 172: Second virtual pattern

[0082] 174: Second spacer layer

[0083] 176, 176a, 176b: Second pattern

[0084] 1762: Second Central Section

[0085] 1764, 1766: Second terminal segment

[0086] 180: Photoresist layer

[0087] 182: First Edge

[0088] 184: Second Edge

[0089] 190: Gap filling material

[0090] D1: First direction

[0091] D2: Second direction

[0092] D3: Third direction

[0093] D4: The fourth direction

[0094] D5: The fifth direction

[0095] D6: Sixth Direction

[0096] L1: First distance

[0097] L2: Second distance

[0098] 2B-2B,3B-3B,4B-4B,5B-5B,7B-7B,8B-8B,10B-10B: line segments.

Claims

1. A method for forming a semiconductor device, characterized in that: Include: forming a plurality of first patterns extending in a first direction in a first hard mask layer on a substrate, wherein each of the plurality of first patterns comprises a first central segment and two first end segments; forming a plurality of second patterns extending in a second direction different from the first direction in a second hard mask layer on the substrate, wherein each of the plurality of second patterns includes a second central segment and two second end segments; forming a hole pattern in a third hard mask layer by using the plurality of first patterns and the plurality of second patterns, wherein the third hard mask layer is located above the substrate and below the first hard mask layer and the second hard mask layer; forming a photoresist layer to cover the plurality of second central sections of the plurality of second patterns; as well as The first end sections of the first patterns and the two second end sections of the second patterns are removed.

2. The method for forming a semiconductor device according to claim 1, wherein: The forming of the plurality of first patterns further comprises: forming a plurality of first dummy patterns on the first hard mask layer; forming a plurality of first spacer layers respectively surrounding the plurality of first dummy patterns; removing the plurality of first dummy patterns; as well as The first hard mask layer is etched using the plurality of first spacer layers to form the plurality of first patterns.

3. The method for forming a semiconductor device according to claim 2, wherein: The forming of the plurality of first patterns further comprises: forming a plurality of second dummy patterns on the second hard mask layer; forming a plurality of second spacer layers respectively surrounding the plurality of second dummy patterns; removing the plurality of second dummy patterns; as well as The second hard mask layer is etched using the plurality of second spacer layers to form the plurality of second patterns.

4. The method for forming a semiconductor device according to claim 1, wherein: The photoresist layer is formed to cover the second central sections of the second patterns, further comprising: The photoresist layer is formed so that the first end segments of the first patterns and the two second end segments of the second patterns are exposed from the photoresist layer.

5. The method for forming a semiconductor device according to claim 1, wherein: The photoresist layer is formed to cover the second central sections of the second patterns, further comprising: The photoresist layer is formed such that a first distance exists between a first edge of the photoresist layer along the first direction and one of the first patterns closest to the first edge, and the first distance is in a range of 0 to 50 nanometers.

6. The method for forming a semiconductor device according to claim 1, wherein: The photoresist layer is formed to cover the second central sections of the second patterns, further comprising: The photoresist layer is formed such that a second distance exists between a second edge of the photoresist layer along the second direction and one of the second patterns closest to the second edge, and the second distance is in a range of 0 to 50 nanometers.

7. The method for forming a semiconductor device according to claim 1, wherein: The forming of the hole pattern in the third hard mask layer by using the plurality of first patterns and the plurality of second patterns further comprises: The size of the plurality of holes of the hole pattern is in a range from 20×20 nanometers square to 50×50 nanometers square.

8. The method for forming a semiconductor device according to claim 1, wherein: Also includes: A gap filling material is filled around the hole pattern, wherein the gap filling material is not filled in the holes of the hole pattern.

9. The method for forming a semiconductor device according to claim 8, wherein: The gap filling material is a low-flow material.

10. The method for forming a semiconductor device according to claim 8, wherein: Also includes: The gap-fill material is etched to expose an upper surface of the hole pattern.

11. The method for forming a semiconductor device according to claim 10, wherein: Also includes: A plurality of capacitor vias are formed by etching the substrate using the hole pattern.

12. A method for forming a semiconductor device, characterized in that: Include: forming a hole pattern in the first hard mask layer on the substrate, wherein the hole pattern comprises a central segment and a plurality of end segments surrounding the central segment; forming a photoresist layer to cover the central section of the hole pattern; removing the end sections of the hole pattern; as well as A plurality of capacitor vias are formed by etching the substrate using the hole pattern.

13. The method for forming a semiconductor device according to claim 12, wherein: The step of forming the hole pattern in the first hard mask layer further comprises: The size of the plurality of holes in the hole pattern is in a range from 20×20 nanometers square to 50×50 nanometers square.

14. The method for forming a semiconductor device according to claim 13, wherein: Also includes: A gap filling material is filled around the hole pattern, wherein the gap filling material is not filled in the plurality of holes.

15. The method for forming a semiconductor device according to claim 14, wherein: The step of forming the hole pattern in the first hard mask layer further comprises: The gap-fill material is etched to expose an upper surface of the hole pattern.

16. The method for forming a semiconductor device according to claim 12, wherein: The step of forming the hole pattern in the first hard mask layer further comprises: A plurality of first patterns extending in a first direction are formed in the second hard mask layer on the substrate, wherein each of the plurality of first patterns includes a first central segment and two first end segments.

17. The method for forming a semiconductor device according to claim 16, wherein: The step of forming the photoresist layer to cover the central section of the hole pattern further comprises: The photoresist layer is formed such that a first distance exists between a first edge of the photoresist layer along the first direction and one of the first patterns closest to the first edge, and the first distance is in a range of 0 to 50 nanometers.

18. The method for forming a semiconductor device according to claim 17, wherein: The step of forming the hole pattern in the first hard mask layer further comprises: A plurality of second patterns extending in a second direction different from the first direction are formed in a third hard mask layer on the substrate, wherein each of the plurality of second patterns includes a second central segment and two second end segments.

19. The method for forming a semiconductor device according to claim 18, wherein: The first central section and the second central section define the central section of the hole pattern.

20. The method for forming a semiconductor device according to claim 18, wherein: The step of forming the photoresist layer to cover the central section of the hole pattern further comprises: The photoresist layer is formed such that a second distance exists between a second edge of the photoresist layer along the second direction and one of the second patterns closest to the second edge, and the second distance is in a range of 0 to 50 nanometers.

Images