Power chip packaging structure and manufacturing method thereof

Abstract

The invention discloses a power chip packaging structure and a manufacturing method thereof. The power chip packaging structure comprises a carrier plate, a self-correcting layer, a conductive paste and a power chip. The carrier plate comprises a ceramic plate and an inner metal layer formed on the ceramic plate, and the inner metal layer is provided with a connecting pad. The self-correcting layer is formed on the inner metal layer, and the self-correcting layer and the connecting pad jointly form a groove. The self-correcting layer comprises a colloid and a plurality of elastomers wrapped in the colloid. And the conductive paste is filled in the groove. The power chip includes a chip body disposed on the self-correcting layer and a bonding pad formed on the chip body. The bonding pad is connected to the conductive paste, so that the power chip is electrically coupled to the carrier plate. Therefore, in the production process, the power chip can be continuously supported by the plurality of first elastic bodies to be maintained at a default position, and further inclination is avoided.

Description

Technical Field

[0001] The present application relates to a packaging structure, and in particular to a power chip packaging structure and a manufacturing method thereof. Background Art

[0002] When conventional power chip packaging structures utilize a wire-less architecture, the power chip within the existing power chip packaging structure is prone to tilting, resulting in poor reliability. The inventors, believing these deficiencies can be improved, have conducted extensive research and applied scientific principles to develop a design that effectively mitigates these deficiencies. Summary of the Invention

[0003] The present application provides a power chip packaging structure and a manufacturing method thereof, which can effectively improve the defects that may occur in the existing power chip packaging structure.

[0004] The present application discloses a method for manufacturing a power chip package structure, which includes: a pre-processing step of providing a first carrier plate, comprising a first ceramic plate and a first inner metal layer formed on the inner surface of the first ceramic plate; wherein the first inner metal layer has at least one first connection pad; a forming step of forming a first self-aligning layer on the first inner metal layer, wherein the first self-aligning layer has at least one first groove exposing at least one first connection pad; wherein the first self-aligning layer comprises a first colloid in a semi-cured state and a plurality of first elastomers coated in the first colloid; and a filling step of forming a first self-aligning layer in at least one first groove. At least one first conductive paste is filled in the groove; a chip placement step is performed: a power chip is placed on the first self-correcting layer and the at least one first conductive paste using a fixture, so that at least one first bonding pad of the power chip is connected to the at least one first conductive paste, and at least one first elastomer is deformed by the pressure of the power chip; a self-correction step is performed: the fixture is removed to restore the at least one first elastomer that has been deformed by the pressure to its original shape, and the power chip is pushed to a default position; and a curing step is performed: the first conductive paste is sintered and the first colloid is cured to fix the power chip to the first conductive paste and the first self-correcting layer.

[0005] Optionally, the number of the at least one first connection pad, the number of the at least one first groove, the number of the at least one first bonding pad, and the number of the at least one first conductive paste are each two.

[0006] Optionally, in the preceding step, the first inner metal layer is formed with at least one gap surrounding the at least one first connection pad; and in the forming step, the first colloid fills the at least one gap.

[0007] Optionally, in the self-calibration step, the first colloid is heated in the crystal placement step, so that its fluidity is higher than that of the first colloid in the forming step.

[0008] Optionally, each first elastic body is an elastic ball made of a polymer material, and at least one first conductive paste is further defined as a silver paste.

[0009] Optionally, top edges of the plurality of elastic balls are substantially flush with the top surface of the first colloid and abut against the power chip.

[0010] Optionally, the first carrier is a direct copper clad ceramic substrate and includes a first outer metal layer, and the first inner metal layer and the first outer metal layer are sintered and fixed to an inner plate surface and an outer plate surface of the first ceramic plate respectively.

[0011] The present application also discloses a power chip packaging structure, which includes: a first carrier, including a first ceramic plate and a first inner metal layer formed on the inner plate surface of the first ceramic plate; wherein the first inner metal layer has at least one first connection pad; a first self-correcting layer, formed on the first inner metal layer, and the first self-correcting layer and the at least one first connection pad together form at least one first groove; wherein the first self-correcting layer includes a first colloid and a plurality of first elastomers coated in the first colloid; at least one first conductive paste is filled in the at least one first groove; and a power chip, including: a chip body, disposed on the first self-correcting layer; and at least one first bonding pad, formed on the first surface of the chip body; wherein the at least one first bonding pad is connected to the at least one first conductive paste to electrically couple the power chip to the first carrier.

[0012] Optionally, each first elastic body is an elastic ball made of a polymer material, and at least one first conductive paste is further defined as a sintered and solidified silver paste.

[0013] Optionally, top edges of the plurality of elastic balls are substantially aligned with the top surface of the first colloid and abut against the first surface of the power chip.

[0014] Optionally, the number of the at least one first connection pad, the number of the at least one first groove, the number of the at least one first bonding pad, and the number of the at least one first conductive paste are each two; wherein the first inner metal layer has a thermal pad located between the two first connection pads, and the first self-correction layer and the thermal pad together form a receiving groove; the power chip packaging structure includes a thermal paste filled in the receiving groove, the power chip has a heat dissipation pad located between the two first bonding pads, and the heat dissipation pad is connected to the thermal paste.

[0015] Optionally, the power chip packaging structure further includes: a second carrier board, comprising a second ceramic board and a second inner metal layer formed on the inner board surface of the second ceramic board; wherein the second inner metal layer has at least one second connection pad; a second self-correcting layer, formed on the second inner metal layer, and the second self-correcting layer and the at least one second connection pad together form at least one second groove; wherein the second self-correcting layer comprises a second colloid and a plurality of second elastomers coated in the second colloid; and at least one second conductive paste, filled in the at least one second groove; wherein the power chip comprises at least one second bonding pad, which is formed on the second surface of the chip body, and the second self-correcting layer is arranged on the second surface of the chip body; wherein the at least one second bonding pad is connected to the at least one second conductive paste to electrically couple the power chip to the second carrier board.

[0016] Optionally, the power chip package structure further includes a plurality of pins, which are spaced apart and arranged outside the power chip and clamped and fixed between the first carrier and the second carrier; wherein each pin is electrically coupled to the first carrier and the second carrier.

[0017] Optionally, the first surface of the power chip is completely covered by the first self-alignment layer and at least one first conductive paste, and the second surface of the power chip is completely covered by the second self-alignment layer and at least one second conductive paste.

[0018] Optionally, the first carrier and the second carrier are each a direct copper-clad ceramic substrate, and the first carrier includes a first outer metal layer, and the second carrier includes a second outer metal layer; wherein the first inner metal layer and the first outer metal layer are sintered and fixed to the inner plate surface and an outer plate surface of the first ceramic plate, respectively; the second inner metal layer and the second outer metal layer are sintered and fixed to the inner plate surface and an outer plate surface of the second ceramic plate, respectively.

[0019] The present application further discloses a power chip packaging structure, which includes: a first carrier board, including a first ceramic board and a first inner metal layer formed on the inner board surface of the first ceramic board; wherein the first inner metal layer has at least one first connection pad; a first self-correction layer, including a plurality of correction blocks formed on the first inner metal layer; wherein the plurality of correction blocks are arranged at intervals from each other and surround the outside of at least one first connection pad; wherein each correction block includes a first colloid and a plurality of first elastomers coated in the first colloid; at least one first conductive paste formed on at least one first connection pad; and a power chip, including: a chip body, disposed on the first self-correction layer, and a plurality of corners of the chip body are respectively disposed on the plurality of correction blocks; and

[0020] At least one first bonding pad is formed on the first surface of the chip body; wherein the at least one first bonding pad is connected to at least one first conductive paste so as to electrically couple the power chip to the first carrier.

[0021] Optionally, each first elastic body is an elastic ball made of a polymer material, and at least one first conductive paste is further defined as a sintered and solidified silver paste; the top edges of the multiple elastic balls in each correction block are roughly aligned with the top surface of the first colloid and abut against the first surface of the power chip.

[0022] Optionally, top edges of the multiple elastic balls in each calibration block are substantially aligned with the top surface of the first colloid and abut against the first surface of the power chip.

[0023] In summary, the power chip packaging structure and manufacturing method disclosed in the embodiments of the present application configure the first self-correction layer between the first carrier and the power chip, so that during the production process of the power chip packaging structure, the power chip can be continuously supported by multiple first elastic bodies and maintained in a default position, thereby preventing the power chip from tilting relative to the first carrier to maintain better reliability.

[0024] To further understand the features and technical content of this application, please refer to the following detailed description and drawings of this application. However, such description and drawings are only used to illustrate this application and do not limit the scope of protection of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a three-dimensional schematic diagram of the power chip packaging structure of the first embodiment of the present application.

[0026] Figure 2 for Figure 1 Schematic cross-sectional view along section line II-II.

[0027] Figure 3 for Figure 1 Schematic cross-sectional view along line III-III (molded package omitted).

[0028] Figure 4 for Figure 1 Schematic cross-sectional view along line IV-IV (molded package omitted).

[0029] Figure 5 This is a flow chart of a method for manufacturing a power chip packaging structure according to the first embodiment of the present application.

[0030] Figure 6 for Figure 5 Schematic diagram of the pre-steps and forming steps.

[0031] Figure 7 for Figure 5 Schematic diagram of the filling step and the wafer placement step.

[0032] Figure 8 for Figure 5 Schematic diagram of the self-calibration steps.

[0033] Figure 9 This is a schematic cross-sectional view of the power chip packaging structure of the second embodiment of the present application.

[0034] Figure 10 Schematic cross-sectional view of the power chip packaging structure of the third embodiment of the present application (the molded package is omitted). DETAILED DESCRIPTION

[0035] The following is an explanation of the implementation methods of the "power chip packaging structure and its manufacturing method" disclosed in this application through specific specific embodiments. Those skilled in the art can understand the advantages and effects of this application from the content disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without deviating from the concept of this application. In addition, the drawings of this application are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical content of this application in detail, but the disclosed content is not intended to limit the scope of protection of this application.

[0036] It should be understood that although terms such as "first," "second," and "third" may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. In addition, the term "or" as used herein may include any one or more combinations of the associated listed items, as appropriate.

[0037] Example 1

[0038] See also Figures 1 to 8 , which is Example 1 of the present application. This embodiment discloses a power chip package structure 100 and a manufacturing method thereof (S100). To facilitate the description of this embodiment, the following will first introduce the components of the power chip package structure 100 and their connection relationships, and then describe the main implementation steps of the power chip package structure manufacturing method (S100).

[0039] like Figures 1 to 4In this embodiment, the power chip package structure 100 adopts a wire-less architecture, and the power chip package structure 100 includes a first module 1, a second module 2 spaced apart from the first module 1, a power chip 3 clamped and fixed between the first module 1 and the second module 2, and a plurality of pins 4 spaced apart from each other and arranged on the outside of the power chip 3.

[0040] The power chip 3 includes a chip body 33, two first bonding pads 31 formed on one side of the chip body 33, and a second bonding pad 32 formed on the other side of the chip body 33. In this embodiment, the chip body 33 has a first surface 331 and a second surface 332 located on opposite sides. The two first bonding pads 31 are formed on the first surface 331 spaced apart from each other and may be a source pad and a gate pad, while the second bonding pad 32 is formed on the second surface 332 and may be a drain pad, but the present application is not limited thereto.

[0041] It should be noted that the type of the power chip 3 can be adjusted and varied according to actual needs. For example, the power chip 3 can be an insulated gate bipolar transistor (IGBT), a power metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a silicon carbide (SiC) power device, a gallium nitride (GaN) power device, a high electron mobility transistor (HEMT), or a fast recovery diode (FRD). In addition, the number of the power chips 3 can also be adjusted to multiple according to actual needs.

[0042] The first module 1 includes a first carrier 11, a first self-aligning layer 12, and two first conductive pastes 13 formed on the first carrier 11. The first carrier 11 includes a first ceramic plate 111, a first inner metal layer 112 formed on the inner surface of the first ceramic plate 111, and a first outer metal layer 113 formed on the outer surface of the first ceramic plate 111.

[0043] In this embodiment, the first carrier 11 is a direct bonded copper (DBC) ceramic substrate, and the first inner metal layer 112 and the first outer metal layer 113 are sintered and fixed to the inner and outer surfaces of the first ceramic plate 111, respectively. However, the present application is not limited to this. For example, in other embodiments not shown in this application, the first inner metal layer 112 and the first outer metal layer 113 can also be formed on the inner and outer surfaces of the first carrier 11, respectively, using direct plated copper (DPC) technology or active metal brazing (AMB) technology.

[0044] Specifically, the first inner metal layer 112 includes two first connection pads 1121 spaced apart from each other, and a first metal pad 1122 located outside the two first connection pads 1121. Furthermore, the first inner metal layer 112 is formed with a plurality of first gaps G1 surrounding the two first connection pads 1121. In other words, the layout of the remaining portions of the first inner metal layer 112, other than the two first connection pads 1121, can be adjusted based on actual needs.

[0045] The first self-calibrating layer 12 is formed on the first inner metal layer 112, and the first self-calibrating layer 12 and each of the first connection pads 1121 form a first groove S1. The first self-calibrating layer 12 includes a first colloid 121 and a plurality of first elastomers 122 encapsulated within the first colloid 121.

[0046] Specifically, the first colloid 121 is preferably a low-stress resin, and the first colloid 121 fills each of the first gaps G1. Furthermore, each of the first elastic bodies 122 is an elastic ball made of a polymer material. The plurality of elastic balls have an average diameter, and the difference between the diameter of each elastic ball and the average diameter is no greater than 5 microns (μm).

[0047] The two first conductive pastes 13 are respectively filled in the two first grooves S1 , and each of the first conductive pastes 13 is further defined as a sintered and solidified silver paste in this embodiment, but is not limited thereto.

[0048] The power chip 3 is disposed on the first self-calibrating layer 12, and the first surface 331 of the chip body 33 is disposed on and adhered to the first adhesive 121. The two first bonding pads 31 are respectively connected to the two first conductive pastes 13, electrically coupling the power chip 3 to the first carrier 11. The first surface 331 of the power chip 3 is preferably completely covered by the first self-calibrating layer 12 and the two first conductive pastes 13. The top edges of the multiple elastic balls on the first self-calibrating layer 12 are substantially aligned with the top surface of the first adhesive 121 and abut against the first surface 331 of the power chip 3.

[0049] It should be noted that in this embodiment, the number of the first grooves S1, the number of the first connection pads 1121, and the number of the first conductive pastes 13 are each described as two, corresponding to the two first bonding pads 31 of the power chip 3, but the present application is not limited to this. In other words, the number of the first connection pads 1121, the number of the first grooves S1, the number of the first bonding pads 31, and the number of the first conductive pastes 13 can also be adjusted to at least one according to actual needs.

[0050] As described above, in this embodiment, the power chip packaging structure 100 adopts the first self-calibration layer 12 clamped between the first carrier 11 and the power chip 3, so that during the production process of the power chip packaging structure 100, the power chip 3 can be continuously supported by the multiple first elastic bodies 122 and maintained in a default position, thereby preventing the power chip 3 from tilting relative to the first carrier 11, thereby maintaining better reliability.

[0051] The second module 2 includes a second carrier 21, a second self-aligning layer 22, and a second conductive paste 23 formed on the second carrier 21. The second carrier 21 includes a second ceramic plate 211, a second inner metal layer 212 formed on the inner surface of the second ceramic plate 211, and a second outer metal layer 213 formed on the outer surface of the second ceramic plate 211.

[0052] In this embodiment, the second carrier 21 is a direct-bonded copper (DBC) ceramic substrate, and the second inner metal layer 212 and the second outer metal layer 213 are sintered and fixed to the inner and outer surfaces of the second ceramic plate 211, respectively. However, the present application is not limited to this. For example, in other embodiments not shown in this application, the second inner metal layer 212 and the second outer metal layer 213 can also be formed on the inner and outer surfaces of the second carrier 21, respectively, using direct copper plating (DPC) technology or active metal brazing (AMB) technology.

[0053] Specifically, the second inner metal layer 212 includes a second connection pad 2121 and a second metal pad 2122 located outside the two second connection pads 2121. The second inner metal layer 212 also defines a second gap G2 surrounding the second connection pad 2121. In other words, the layout of the second inner metal layer 212, other than the second connection pad 2121, can be adjusted based on actual needs.

[0054] The second self-calibrating layer 22 is formed on the second inner metal layer 212 and forms a second groove S2 with the second connection pad 2121. The second self-calibrating layer 22 includes a second colloid 221 and a plurality of second elastomers 222 encapsulated within the second colloid 221.

[0055] Specifically, the second colloid 221 is preferably a low-stress resin, and the second colloid 221 fills the second gap G2. Furthermore, each of the second elastic bodies 222 is an elastic ball made of a polymer material. The plurality of elastic balls have an average diameter, and the difference between the diameter of each elastic ball and the average diameter is no greater than 5 microns.

[0056] The second conductive paste 23 is filled in the second groove S2 , and the second conductive paste 23 is further defined as a sintered and solidified silver paste in this embodiment, but is not limited thereto.

[0057] The power chip 3 is disposed on the second self-calibrating layer 22, and the second surface 332 of the chip body 33 is disposed on and adhered to the second adhesive 221. The second bonding pads 32 are connected to the second conductive paste 23, electrically coupling the power chip 3 to the second carrier 21. The second surface 332 of the power chip 3 is preferably completely covered by the second self-calibrating layer 22 and the second conductive paste 23. The top edges of the plurality of elastic balls on the second self-calibrating layer 22 are substantially aligned with the top surface of the second adhesive 221 and abut against the second surface 332 of the power chip 3.

[0058] It should be noted that in this embodiment, the number of second grooves S2, the number of second connection pads 2121, and the number of second conductive pastes 23 are each described as one, corresponding to the second bonding pads 32 of the power chip 3, but the present application is not limited to this. In other words, the number of second connection pads 2121, the number of second grooves S2, the number of second bonding pads 32, and the number of second conductive pastes 23 can also be adjusted to more than one based on actual needs.

[0059] As described above, in this embodiment, the power chip packaging structure 100 adopts the second self-calibration layer 22 clamped between the second carrier 21 and the power chip 3, so that during the production process of the power chip packaging structure 100, the power chip 3 can be continuously supported by the multiple second elastic bodies 222 and maintained in the default position, thereby preventing the power chip 3 from tilting relative to the second carrier 21 to maintain better reliability.

[0060] Furthermore, the plurality of pins 4 are clamped and fixed between the first carrier 11 and the second carrier 21, and each pin 4 can be connected and fixed to the first carrier 11 and the second carrier 21 via a conductive material (e.g., conductive paste), thereby electrically coupling each pin 4 to the first carrier 11 and the second carrier 21. Furthermore, in this embodiment, the power chip package structure 100 further includes a molding compound 6, such that the first module 1, the second module 2, and the power chip 3 are embedded within the molding compound 6. A portion of each pin 4 extends through the molding compound 6, and the first outer metal layer 113 and the second outer metal layer 213 are also exposed outside the molding compound 6, thereby improving heat dissipation performance.

[0061] like Figure 2 and Figures 5 to 8 The above is a description of the structure of the power chip package structure 100 in this embodiment. The following is a brief introduction to the power chip package structure manufacturing method S100. The technical content thereof can refer to the above description of the power chip package structure 100. However, the power chip package structure 100 is not limited to being manufactured by implementing the power chip package structure manufacturing method S100.

[0062] Furthermore, to facilitate understanding of this embodiment, the following only describes the manufacturing process between the first module 1 and the power chip 3. The power chip package structure manufacturing method S100 in this embodiment sequentially includes (or implements) a pre-processing step S110, a forming step S120, a filling step S130, a die placement step S140, a self-calibration step S150, and a curing step S160.

[0063] The preceding step S110: Figure 5 and Figure 6As shown, a first carrier 11 is provided, comprising a first ceramic plate 111 and a first inner metal layer 112 formed on the inner surface of the first ceramic plate 111. The first inner metal layer 112 has at least one first connection pad 1121, and the first inner metal layer 112 is formed with at least one first gap G1 surrounding the at least one first connection pad 1121.

[0064] The forming step S120: Figure 5 and Figure 6 As shown, a first self-calibrating layer 12 is formed on the first inner metal layer 112, having at least one first groove S1 exposing at least one first connection pad 1121. The first self-calibrating layer 12 comprises a first colloid 121 in a semi-cured (B-stage) state and a plurality of first elastomers 122 encapsulated within the first colloid 121. Specifically, the first colloid 121 fills at least one first gap G1, and each first elastomer 122 is an elastic ball made of a polymer material.

[0065] It should be noted that the first self-aligning layer 12 can be heated to 120 degrees Celsius in the forming step S120 to perform pre-drying to volatilize at least part of the solvent in the first colloid 121 , but the present invention is not limited thereto.

[0066] The filling step S130: Figure 5 and Figure 7 As shown, at least one first conductive paste 13 is filled into at least one first groove S1. In this embodiment, at least one first conductive paste 13 is further limited to a silver paste. It should be noted that the first conductive paste 13 can be heated to 130 degrees Celsius during the filling step S130 for pre-drying, but the present invention is not limited thereto.

[0067] The wafer placement step S140: Figure 5 and Figure 7 As shown, a jig 200 is used to place a power chip 3 between the first self-calibration layer 12 and at least one first conductive paste 13, such that at least one first bonding pad 31 of the power chip 3 is connected to at least one first conductive paste 13, and at least one first elastic member 122 is deformed by the pressure of the power chip 3. It should be noted that during the die placement step S140 of this embodiment, the power chip 3 may be hot-pressed at a force of 400 grams and a temperature of 170 degrees for at least 3 seconds, but this is not limiting.

[0068] The self-calibration step S150: Figure 5 and Figure 8As shown, the jig 200 is removed, allowing the at least one first elastic body 122 that was compressed and deformed to return to its original shape and push the power chip 3 to a default position. In the self-calibration step S150, the first colloid 121 is heated in the die placement step S140, making its fluidity higher than that of the first colloid 121 in the forming step S120. This facilitates the compression and deformation of the at least one first elastic body 122 to return to its original shape within the first colloid 121.

[0069] The curing step S160: Figure 5 and Figure 2 As shown, the first conductive paste 13 is sintered and the first colloid 121 is cured to fix the power chip 3 to the first conductive paste 13 and the first self-aligning layer 12. The top edges of the plurality of elastic balls are substantially aligned with the top surface of the first colloid 121 and abut against the power chip 3.

[0070] Furthermore, the sintering process of the first conductive paste 13 in this embodiment can be performed at 250 degrees C., and can adopt pressure-less sintering or pressure-assisted sintering at a pressure of 10 MPa according to actual needs, but this application is not limited thereto.

[0071] In addition, the number of the at least one first connection pad 1121, the number of the at least one first groove S1, the number of the at least one first bonding pad 31, and the number of the at least one first conductive paste 13 are each two in this embodiment, but the present application is not limited thereto. Furthermore, the packaging process between the second module 2 and the power chip 3 is similar to steps S110 to S160 described above. After the second module 2 is mounted on the power chip 3, a further packaging step (not shown) is performed to form the molded package 6. The details are not repeated here.

[0072] Example 2

[0073] See also Figure 9 As shown, this is the second embodiment of the present application. Since this embodiment is similar to the above-mentioned first embodiment, the similarities between the two embodiments will not be repeated here. The differences between this embodiment and the above-mentioned first embodiment are roughly described as follows:

[0074] In this embodiment, the first inner metal layer 112 has a thermal pad 1123 located between the two first connection pads 1121. The first self-calibration layer 12 and the thermal pad 1123 jointly form a receiving groove S. Furthermore, the power chip package structure 100 includes a thermal paste 5 filled within the receiving groove S. The power chip 3 has a heat dissipation pad 34 formed on the first surface 331. The heat dissipation pad 34 is located between the two first bonding pads 31 and connected to the thermal paste 5. The thermal paste 5 may also be silver paste, but is not limited thereto.

[0075] Example 3

[0076] See also Figure 10 As shown, this is the third embodiment of the present application. Since this embodiment is similar to the above-mentioned first embodiment, the similarities between the two embodiments will not be repeated here. The differences between this embodiment and the above-mentioned first embodiment are roughly described as follows:

[0077] In this embodiment, the size of the first self-calibration layer 12 can be reduced based on actual needs. Specifically, the first self-calibration layer 12 includes a plurality of calibration blocks 12a formed on the first inner metal layer 112. The calibration blocks 12a are spaced apart and surround two first connection pads 1121. Each first connection pad 1121 has a first conductive paste 13 formed thereon. Each calibration block 12a includes a first colloid 121 and a plurality of first elastomers 122 encapsulated within the first colloid 121. The features of the first colloid 121 and the first elastomers 122 in this embodiment are generally similar to those described in the first embodiment above and are not further elaborated here.

[0078] The chip body 33 is disposed on the first self-calibration layer 12, with multiple corners of the chip body 33 disposed on multiple calibration blocks 12a. Each of the first bonding pads 31 is connected to a first conductive paste 13, electrically coupling the power chip 3 to the first carrier 11. The top edges of the multiple first elastic bodies 122 (e.g., elastic balls) in each calibration block 12a are substantially aligned with the top surface of the first gel 121 and abut against the first surface 331 of the power chip 3, effectively preventing the power chip 3 from tilting relative to the first carrier 11 and maintaining optimal reliability.

[0079] In addition, the size of the second self-calibration layer 22 can also be reduced according to actual needs, which is not detailed in this application.

[0080] Technical effects of the invention

[0081] In summary, the power chip package structure and manufacturing method disclosed in the embodiments of this application employ a first self-aligning layer disposed between the first carrier and the power chip. This allows the power chip to be continuously supported by the first elastic members during the production process, maintaining a default position. This prevents the power chip from tilting relative to the first carrier, thereby maintaining optimal reliability. Furthermore, the size of the first self-aligning layer can be adjusted based on actual needs.

[0082] The contents disclosed above are only preferred feasible embodiments of the present application and do not limit the patent scope of the present application. Therefore, any equivalent technical changes made using the description and drawings of the present application are included in the patent scope of the present application.

Claims

1. A method for manufacturing a power chip packaging structure, characterized in that: The power chip packaging structure manufacturing method comprises: A pre-step: providing a first carrier board, comprising a first ceramic board and a first inner metal layer formed on an inner surface of the first ceramic board; wherein the first inner metal layer has at least one first connection pad; A forming step is performed: forming a first self-aligning layer on the first inner metal layer, the first self-aligning layer having at least one first groove exposing at least one first connection pad; wherein the first self-aligning layer comprises a first colloid in a semi-cured state and a plurality of first elastomers coated within the first colloid; a filling step: filling at least one first conductive paste into at least one of the first grooves; a die placement step of placing a power chip on the first self-aligning layer and at least one of the first conductive pastes using a jig, such that at least one first bonding pad of the power chip is connected to the at least one first conductive paste, and at least one of the first elastic members is deformed by pressure from the power chip; a self-calibration step: removing the jig to restore the at least one first elastic body that has been deformed by compression to its original shape, and pushing and moving the power chip to a default position; and A curing step is to sinter the first conductive paste and cure the first colloid so as to fix the power chip to the first conductive paste and the first self-alignment layer.

2. The method for manufacturing a power chip packaging structure according to claim 1, wherein: The number of at least one first connection pad, the number of at least one first groove, the number of at least one first bonding pad, and the number of at least one first conductive paste are each two.

3. The method for manufacturing a power chip packaging structure according to claim 1, wherein: In the preceding step, the first inner metal layer is formed with at least one gap surrounding at least one of the first connection pads; and in the forming step, the first colloid fills the at least one gap.

4. The method for manufacturing a power chip packaging structure according to claim 1, wherein: In the self-calibration step, the first colloid is heated in the crystal placement step, so that its fluidity is higher than that of the first colloid in the forming step.

5. The method for manufacturing a power chip packaging structure according to claim 1, wherein: Each of the first elastic bodies is an elastic ball made of a polymer material, and at least one of the first conductive pastes is further defined as a silver paste.

6. The method for manufacturing a power chip packaging structure according to claim 5, wherein: The top edges of the plurality of elastic balls are aligned with the top surface of the first colloid and abut against the power chip.

7. The method for manufacturing a power chip packaging structure according to claim 1, wherein: The first carrier is a direct copper-clad ceramic substrate and includes a first outer metal layer, and the first inner metal layer and the first outer metal layer are sintered and fixed to the inner plate surface and an outer plate surface of the first ceramic plate respectively.

8. A power chip packaging structure, characterized in that: The power chip packaging structure includes: A first carrier board comprising a first ceramic board and a first inner metal layer formed on an inner surface of the first ceramic board; wherein the first inner metal layer has at least one first connection pad; a first self-aligning layer formed on the first inner metal layer, wherein the first self-aligning layer and at least one of the first connection pads together form at least one first groove; wherein the first self-aligning layer comprises a first colloid and a plurality of first elastomers coated within the first colloid; At least one first conductive paste is filled in at least one of the first grooves; and A power chip, comprising: a chip body disposed on the first self-calibration layer; and At least one first bonding pad is formed on the first surface of the chip body; wherein at least one first bonding pad is connected to at least one first conductive paste, The power chip is electrically coupled to the first carrier board.

9. The power chip packaging structure according to claim 8, characterized in that: Each of the first elastic bodies is an elastic ball made of a polymer material, and at least one of the first conductive pastes is further defined as a sintered and solidified silver paste.

10. The power chip packaging structure according to claim 9, characterized in that: The top edges of the plurality of elastic balls are aligned with the top surface of the first colloid and abut against the first surface of the power chip.

11. The power chip packaging structure according to claim 8, characterized in that: The number of at least one first connection pad, the number of at least one first groove, the number of at least one first bonding pad, and the number of at least one first conductive paste are each two; wherein the first inner metal layer has a thermal pad located between the two first connection pads, and the first self-correcting layer and the thermal pad jointly form a receiving groove; the power chip packaging structure includes a thermal paste filled in the receiving groove, the power chip has a heat dissipation pad located between the two first bonding pads, and the heat dissipation pad is connected to the thermal paste.

12. The power chip packaging structure according to claim 8, characterized in that: The power chip packaging structure further comprises: a second carrier board comprising a second ceramic board and a second inner metal layer formed on an inner surface of the second ceramic board; wherein the second inner metal layer has at least one second connection pad; a second self-aligning layer formed on the second inner metal layer, wherein the second self-aligning layer and at least one second connection pad together form at least one second groove; wherein the second self-aligning layer comprises a second colloid and a plurality of second elastomers coated in the second colloid; and At least one second conductive paste is filled in at least one of the second grooves; The power chip includes at least one second bonding pad formed on the second surface of the chip body, and the second self-correction layer is disposed on the second surface of the chip body; at least one second bonding pad is connected to at least one second conductive paste to electrically couple the power chip to the second carrier.

13. The power chip packaging structure according to claim 12, characterized in that: The power chip packaging structure further includes a plurality of pins, which are spaced apart and arranged outside the power chip and clamped and fixed between the first carrier and the second carrier; wherein each of the pins is electrically coupled to the first carrier and the second carrier.

14. The power chip packaging structure according to claim 12, wherein: The first surface of the power chip is completely covered by the first self-aligning layer and at least one first conductive paste, and the second surface of the power chip is completely covered by the second self-aligning layer and at least one second conductive paste.

15. The power chip packaging structure according to claim 12, wherein: The first carrier plate and the second carrier plate are each a direct copper-clad ceramic substrate, and the first carrier plate includes a first outer metal layer, and the second carrier plate includes a second outer metal layer; wherein the first inner metal layer and the first outer metal layer are sintered and fixed to the inner plate surface and an outer plate surface of the first ceramic plate, respectively; the second inner metal layer and the second outer metal layer are sintered and fixed to the inner plate surface and an outer plate surface of the second ceramic plate, respectively.

16. A power chip packaging structure, characterized in that: The power chip packaging structure includes: A first carrier board comprising a first ceramic board and a first inner metal layer formed on an inner surface of the first ceramic board; wherein the first inner metal layer has at least one first connection pad; a first self-calibration layer comprising a plurality of calibration blocks formed on the first inner metal layer; wherein the plurality of calibration blocks are spaced apart from each other and surround at least one of the first connection pads; wherein each calibration block comprises a first colloid and a plurality of first elastomers coated within the first colloid; and at least one first conductive paste formed on at least one of the first connection pads; and A power chip, comprising: a chip body disposed on the first self-calibration layer, wherein a plurality of corners of the chip body are respectively disposed on a plurality of the calibration blocks; and At least one first bonding pad is formed on the first surface of the chip body; wherein, at least one first bonding pad is connected to at least one first conductive paste, so that the power chip is electrically coupled to the first carrier.

17. The power chip packaging structure according to claim 16, characterized in that: Each of the first elastomers is an elastic ball made of a polymer material, and at least one of the first conductive pastes is further defined as a sintered and solidified silver paste; the top edges of the multiple elastic balls in each of the calibration blocks are aligned with the top surface of the first colloid and abut against the first surface of the power chip.

18. The power chip packaging structure according to claim 17, characterized in that: The top edges of the plurality of elastic balls in each calibration block are aligned with the top surface of the first colloid and abut against the first surface of the power chip.

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