Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the steps that a semiconductor base body is provided, the semiconductor base body comprises a substrate and a first layer structure on the substrate, and an air gap hole is formed in the first layer structure; a porous filler is formed in the air gap holes, the air gap holes are filled with the porous filler, and the dielectric constant of the porous filler is smaller than that of the first layer structure; and forming a second-layer structure, wherein the second-layer structure covers the first-layer structure and the porous filler. According to the method, the effect of reducing the parasitic capacitance of the air gap hole in the first layer structure can be optimized, so that the parasitic capacitance between the interconnection layers in the same layer in the first layer structure is reduced as much as possible, and the radio frequency performance of the semiconductor device is improved. Meanwhile, the second-layer structure can be not limited to the adoption of the previous low-step coverage chemical vapor deposition process, and the selectivity of the material and the process of the second-layer structure is widened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Radio frequency technology is widely used in various aspects of life, such as semiconductor devices such as RF switches. However, as the frequency of semiconductor devices continues to increase, the parasitic capacitance of semiconductor devices increases, resulting in a sharp decline in the RF performance of semiconductor devices. Summary of the Invention

[0003] The semiconductor device and its preparation method provided in this application are intended to solve the problem that the parasitic capacitance of the semiconductor device is large, resulting in a sharp decline in the radio frequency performance of the semiconductor device.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a method for preparing a semiconductor device, the method comprising: providing a semiconductor substrate; the semiconductor substrate comprises a stacked substrate and a first layer structure, air gaps are formed in the first layer structure; forming a porous filler in the air gaps; the porous filler fills the air gaps, and the dielectric constant of the porous filler is less than the dielectric constant of the first layer structure; forming a second layer structure, the second layer structure covering the first layer structure and the porous filler.

[0005] In one embodiment of the present application, the first layer structure includes a dielectric material layer, a plurality of contact plugs disposed in the dielectric material layer, and a plurality of interconnection layers;

[0006] The air gap holes are formed in the dielectric material layer, and at least a portion of the air gap holes is located between two adjacent interconnection layers; the dielectric constant of the porous filler is smaller than the dielectric constant of the dielectric material layer.

[0007] In one embodiment of the present application, the first layer structure also includes a first etch stop layer; the dielectric material layer includes a first dielectric material layer and a second dielectric material layer; the second dielectric material layer is located on the first dielectric material layer; the first etch stop layer is located between the first dielectric material layer and the second dielectric material layer; the contact plug is arranged in the first dielectric material layer, and the interconnection layer is arranged in the second dielectric material layer and the first etch stop layer; along the stacking direction of the first layer structure, the air gap hole extends at least into the second dielectric material layer.

[0008] In one embodiment of the present application, the step of forming a porous filler in the air gap pores includes:

[0009] Filling the air gap pores with a polymer solution comprising a polymer solute and a solvent;

[0010] spraying deionized water on the surface of the polymer solution to form a porous filler through a phase separation process;

[0011] The deionized water and the solvent are removed.

[0012] In one embodiment of the present application, before the step of forming a porous filler in the air gap pores, the method further includes:

[0013] The groove walls of the air gap holes are subjected to hydrophobic treatment.

[0014] In one embodiment of the present application, the thermal decomposition temperature of the porous filler is greater than 500°C.

[0015] In one embodiment of the present application, the first layer structure further includes a diffusion barrier layer, which is provided on the dielectric material layer and covers the interconnect layer to prevent the interconnect layer material from diffusing outward.

[0016] In one embodiment of the present application, the equivalent dielectric constant of the porous filler is 1-1.1.

[0017] To solve the above technical problems, another technical solution adopted in this application is to provide a semiconductor device. The semiconductor device includes: a semiconductor substrate, a porous filler, and a second layer structure; the semiconductor substrate includes a stacked substrate and a first layer structure, the first layer structure having air gaps; the porous filler fills the air gaps, and the dielectric constant of the porous filler is less than that of the first layer structure; and the second layer structure covers the first layer structure and the porous filler in the air gaps.

[0018] In one embodiment of the present application, the first layer structure includes a dielectric material layer, a plurality of contact plugs disposed in the dielectric material layer, and a plurality of interconnection layers;

[0019] The porous filler is provided in the dielectric material layer, and at least a portion of the porous filler is located between two adjacent interconnection layers; the dielectric constant of the porous filler is smaller than the dielectric constant of the dielectric material layer.

[0020] In one embodiment of the present application, the first layer structure further includes a diffusion barrier layer, which is provided on the dielectric material layer and covers the interconnect layer to prevent the interconnect layer material from diffusing outward.

[0021] In one embodiment of the present application, the first layer structure further includes a first etch stop layer;

[0022] The dielectric material layer includes a first dielectric material layer and a second dielectric material layer; the second dielectric material layer is located on the first dielectric material layer; the first etch stop layer is located between the first dielectric material layer and the second dielectric material layer; the contact plug is arranged in the first dielectric material layer, and the interconnection layer is arranged in the second dielectric material layer and the first etch stop layer; along the stacking direction of the first layer structure, the porous filler extends at least into the second dielectric material layer.

[0023] In one embodiment of the present application, the porous filler includes polysulfone and / or polyetheretherketone.

[0024] In one embodiment of the present application, the equivalent dielectric constant of the porous filler is 1-1.1.

[0025] The semiconductor device and its preparation method provided by the embodiments of the present application are characterized by forming a porous filler in the air gap pores and making the dielectric constant of the porous filler smaller than the dielectric constant of the first layer structure. In this way, the porous filler can optimize the effect of the air gap pores in the first layer structure in reducing parasitic capacitance, thereby minimizing the parasitic capacitance between interconnect layers in the same layer in the first layer structure, and even reducing the parasitic capacitance between two adjacent contact plugs in the first layer structure, thereby improving the RF performance of the semiconductor device. At the same time, after the porous filler is filled in the air gap pores, the second layer structure is formed. The second layer structure does not enter the air gap pores and does not affect the effect of the air gap pores in reducing parasitic capacitance. In addition, when selecting the material and formation method of the second layer structure, there is no need to consider the impact of the second layer structure on the volume of the air gap pores. The second layer structure can be used without being limited to the previous low step coverage chemical vapor deposition process, which broadens the material and process selection of the second layer structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0027] Figure 1 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0028] Figure 2 A schematic structural diagram of a semiconductor substrate provided in one embodiment of the present application;

[0029] Figure 3 A schematic structural diagram of a semiconductor substrate provided in a specific embodiment of the present application;

[0030] Figure 4 This is a schematic structural diagram of an embodiment of the present application after spin coating a polymer solution on a semiconductor substrate;

[0031] Figure 5 A schematic diagram of a structure for forming a porous filler in an air gap provided by an embodiment of the present application;

[0032] Figure 6 Schematic diagram of the structure for removing the porous filler on the surface of the first layer structure;

[0033] Figure 7 A schematic structural diagram of forming a second layer structure on a first layer structure according to an embodiment of the present application.

[0034] Description of Reference Numerals

[0035] Substrate 1; bottom semiconductor layer 11a; buried oxide layer 11b; top semiconductor layer 11c; source region 111; drain region 112; gate 12; sidewall 13; first layer structure 14; air gap 140; dielectric material layer 141; first dielectric material layer 141a; second dielectric material layer 141b; interconnect layer 142; first etch stop layer 143; second etch stop layer 144; contact plug 145; diffusion barrier layer 146; isolation structure 15; porous filler 17; polymer solution 18; second layer structure 19; third dielectric material layer 191. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0038] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0039] In RF devices, the Figure of Merit (FoM) is an important indicator for measuring RF devices. It reflects the switching performance of RF devices. The smaller the FoM, the better the performance of the RF device. FoM is defined as the product of the device's parasitic resistance and capacitance. Among them, the resistance and capacitance of the device part are mutually exclusive, and it is often relatively difficult to reduce FoM by adjusting the device parameters. Therefore, directly reducing parasitic capacitance becomes effective. Among them, common ways to reduce parasitic capacitance include reducing the dielectric constant of the dielectric layer or increasing the air gap structure between layers to reduce the effective dielectric constant.

[0040] In the related art, grooves are prepared between the interconnection layers by a dry etching process, and a chemical vapor deposition (CVD) process with poor step coverage is usually required to form the next dielectric material layer to leave air gaps between the interconnection layers. Since the dielectric constant of air is lower than that of the dielectric material layer, the parasitic capacitance between the interconnection layers is reduced. However, in the thin film deposition process, the next dielectric material layer will backfill part of the grooves, resulting in a reduction in the volume of the air gaps, thereby weakening the effect of the air gaps in reducing parasitic capacitance. In addition, for this product with an air gap design, the process for depositing the next dielectric material layer can only select a chemical vapor deposition process with poor step coverage, which limits the choice of materials and preparation processes for the next dielectric material layer.

[0041] Based on this, an embodiment of the present application provides a method for preparing a semiconductor device, which first forms a porous filler in the air gap hole and then deposits a subsequent dielectric material layer; in this way, an optimized air gap effect can be obtained, and the subsequent dielectric material layer will not affect the air gap. The subsequent dielectric material layer can be not limited to the previous low step coverage chemical vapor deposition process, which broadens the selectivity of the material and process of the subsequent dielectric material layer.

[0042] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0043] See also Figure 1 , Figure 1 This is a flow chart of a method for fabricating a semiconductor device according to one embodiment of the present application. The method for fabricating a semiconductor device according to the present application can reduce parasitic capacitance between interconnect layers on the same level, and can even reduce parasitic capacitance between adjacent contact plugs, thereby reducing the impact of the parasitic capacitance of the fabricated semiconductor device on its radio frequency performance. The fabrication method specifically includes:

[0044] Step S1: providing a semiconductor base, wherein the semiconductor base includes a substrate and a first layer structure on the substrate, wherein air gaps are formed in the first layer structure.

[0045] See also Figure 2 , Figure 2Schematic diagram of the structure of a semiconductor substrate provided in one embodiment of the present application. Substrate 1 may comprise any currently known or future developed semiconductor material, including but not limited to silicon, germanium, silicon carbide, III-V compound semiconductors, SOI (Semiconductor On Insulator) substrates, etc. For example, substrate 1 in the figure below takes an SOI substrate as an example, which includes a bottom semiconductor layer 11a, a buried oxide layer 11b, and a top semiconductor layer 11c stacked in sequence. Specifically, the top semiconductor layer 11c and the bottom semiconductor layer 11a may be silicon, and the buried oxide layer 11b may be silicon oxide or silicon oxynitride.

[0046] The semiconductor base also includes devices formed on the substrate 1, which can take the form of bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), lightly doped drain MOS transistors (LDMOSs), diodes, capacitors, or any active or passive devices known in the art, for realizing various electrical functions. The following figures take transistors as an example. The top semiconductor layer 11c has a source region 111 and a drain region 112. The source region 111 and the drain region 112 may be in contact with the buried oxide layer 11b; or they may not be in contact with the buried oxide layer 11b and be located above the buried oxide layer 11b, such as Figure 2 shown.

[0047] During implementation, a shallow trench isolation (STI) process may be employed to form a plurality of isolation structures 15 in substrate 1 to divide substrate 1 into multiple device regions. The regions corresponding to isolation structures 15 are defined below as isolation regions of substrate 1. The specific STI process flow can be found in the prior art and will not be further described here.

[0048] The device further includes a gate 12 and sidewall spacers 13 disposed on the substrate 1. The gate 12 is disposed on the channel region, and the sidewall spacers 13 are located on both sides of the gate 12.

[0049] The first structure layer 14 is disposed on the substrate 1 and wraps around the gate 12 and the spacer 13 .

[0050] The first layer structure 14 has air gaps 140 formed by photolithography and etching processes. Thus, after porous fillers 17 are subsequently formed in the air gaps 140, the porous fillers 17 can effectively reduce the parasitic capacitance between at least two adjacent interconnection layers 142.

[0051] In one embodiment, see Figure 3 , Figure 3A schematic structural diagram of a semiconductor substrate provided in a specific embodiment of the present application. The first layer structure 14 may include a dielectric material layer 141, a plurality of interconnect layers 142 disposed within the dielectric material layer 141, and a plurality of contact plugs 145. The dielectric material layer 141 covers the substrate 1. In a direction perpendicular to the stacking direction of the first layer structure 14, the plurality of interconnect layers 142 are spaced apart within the dielectric material layer 141. Air gaps 140 are specifically formed in the dielectric material layer 141, with at least a portion of the air gaps 140 located between two adjacent interconnect layers 142. The material of the dielectric material layer 141 may be silicon oxide. The interconnect layer 142 may specifically be a metal layer, such as a metal tungsten, copper, or silver layer.

[0052] In a specific embodiment, please refer to Figure 3 The first layer structure 14 also includes a first etch stop layer 143; the dielectric material layer 141 includes a first dielectric material layer 141a and a second dielectric material layer 141b. The first dielectric material layer 141a is disposed on the substrate 1 and wraps around the gate 12 and the sidewall 13; the second dielectric material layer 141b is located on the first dielectric material layer 141a. The material of the first dielectric material layer 141a and the second dielectric material layer 141b can specifically be silicon oxide, and the dielectric constant of silicon oxide is approximately 3.9. The first etch stop layer 143 is located on the first dielectric material layer 141a and vertically between the first dielectric material layer 141a and the second dielectric material layer 141b, and is used to isolate the second dielectric material layer 141b from the first dielectric material layer 141a in the vertical direction. The first etch stop layer 143 includes one or more electrically insulating materials with particularly high etching resistance, and is configured to prevent the first dielectric material layer 141a from being removed in subsequent processing. The first etch stop layer 143 may be silicon nitride. Contact plugs 145 are disposed in the first dielectric material layer 141 a. Interconnect layers 142 are disposed in the first etch stop layer 143 and the second dielectric material layer 141 b and extend to contact corresponding contact plugs 145 .

[0053] In this embodiment, the air gap 140 extends at least into the second dielectric material layer 141b along the stacking direction of the first layer structure 14. Specifically, along the stacking direction of the first layer structure 14, the air gap 140 may penetrate the upper and lower surfaces of the second dielectric material layer 141b and the first etch stop layer 143, thereby minimizing the parasitic capacitance between the two interconnection layers 142 adjacent to the air gap 140.

[0054] In another embodiment, Figure 3As shown, the air gap 140 may extend from the surface of the second dielectric material layer 141b to the first dielectric material layer 141a. Thus, after a porous filler 17 is subsequently formed in the air gap 140, the porous filler 17 may further reduce the parasitic capacitance between two adjacent contact plugs 145.

[0055] In one embodiment, please refer to Figure 3 The first layer structure 14 further includes a diffusion barrier layer 146 , which is disposed on the second dielectric material layer 141 b and covers the interconnection layer 142 to prevent the interconnection layer 142 material from diffusing outward.

[0056] In this embodiment, the air gap 140 may specifically extend from the surface of the diffusion barrier layer 146 into the second dielectric material layer 141b, or further extend into the first etch stop layer 143. Specifically, along the stacking direction of the first layer structure 14, the air gap 140 may penetrate the upper and lower surfaces of the diffusion barrier layer 146, the second dielectric material layer 141b, and the first etch stop layer 143, so as to minimize the parasitic capacitance between the two interconnection layers 142 adjacent to the air gap 140.

[0057] In another embodiment, Figure 3 As shown, the air gap 140 may extend from the surface of the diffusion barrier layer 146 into the first dielectric material layer 141a. Thus, after a porous filler 17 is subsequently formed in the air gap 140, the parasitic capacitance between two adjacent contact plugs 145 can be further reduced by the porous filler 17.

[0058] In the stacking direction of the first layer structure 14, the air gap 140 does not expose the surface of the gate 12; thus, damage to the gate 12 during the formation of the air gap 140 can be avoided. The air gap 140 can be located in the device region and / or isolation region of the substrate. The figures illustrate the air gap 140 located in the device region of the substrate as an example.

[0059] Of course, in a specific embodiment, Figure 3 As shown, the first layer structure 14 also includes a second etch stop layer 144, which is located on the substrate 1 and is used to isolate the overlying material from the device below in the vertical direction; the first dielectric material layer 141a is provided on the side surface of the second etch stop layer 144 facing away from the substrate 1. The second etch stop layer 144 includes one or more electrically insulating materials with particularly high etching resistance, which is configured to prevent the device below from being removed in subsequent processing. The second etch stop layer 144 can be formed on the upper surface and sidewalls of the device. The second etch stop layer 144 can include the same material as the first etch stop layer 143.

[0060] The contact plugs 145 are used to electrically couple portions of the device to an interconnect layer 142 located above the first layer structure 14. The contact plugs 145 may include a set of first contact plugs connected to the source region 111 of the transistor, and a set of second contact plugs connected to the drain region 112 of the transistor. The contact plugs 145 may include any conductive material, now known or later developed, that can form a conductive path between multiple conductive elements. In some embodiments, there may be multiple first contact plugs, all of which are connected to the same interconnect layer 142 to prevent a failure of a first contact plug from causing a loss of electrical connection between the source region 111 and the interconnect layer 142. Similarly, there may be multiple second contact plugs, all of which are connected to the same interconnect layer 142 to prevent a failure of a second contact plug from causing a loss of electrical connection between the drain region 112 and the interconnect layer 142.

[0061] Step S2: forming a porous filler in the air gap pores, the porous filler completely fills the air gap pores, and the dielectric constant of the porous filler is smaller than the dielectric constant of the first layer structure.

[0062] The porous filler 17 uniformly fills the entire air gap 140 . The dielectric constant of the porous filler 17 is smaller than the dielectric constants of the first dielectric material layer 141 a and the second dielectric material layer 141 b , and is also smaller than the dielectric constant of the first etch stop layer 143 .

[0063] In some embodiments, the porous filler 17 comprises a polymer and a vacuum, and its equivalent dielectric constant is 1-1.1, that is, greater than 1 and less than 1.1. The material of the porous filler 17 comprises polysulfone and / or polyetheretherketone.

[0064] In a specific embodiment, step S2 includes steps S21 to S24.

[0065] Step S21 : filling the air gap 140 with the polymer solution 18 .

[0066] The polymer solution 18 includes a polymer solute and a solvent. The polymer solute includes polysulfone and / or polyetheretherketone. The solvent can be a water-miscible solvent, for example, N,N-dimethylformamide (DMF) and / or N-methylpyrrolidone.

[0067] See also Figure 4 , Figure 4This is a schematic diagram of the structure after spin-coating a polymer solution on a semiconductor substrate according to one embodiment of the present application. The polymer solution 18 can be spin-coated onto the surface of the first structure layer 14, i.e., onto the surface of the diffusion barrier layer 146, in an anhydrous environment. After the polymer solution 18 has completely entered the air gaps 140, the polymer solution 18 is heat-treated at 100-200°C for 30-360 seconds. The polymer solution 18 can be allowed to stand for 10-60 seconds, for example, 20, 40, or 60 seconds, to allow the polymer solution 18 to completely enter the air gaps 140. Furthermore, since the polymer molecular chains will become oriented during the spin-coating process of the polymer solution 18, the addition of the heat treatment can relax the polymer molecular chains, thereby de-orienting and improving process stability. The heat treatment temperature can be 100°C, 150°C, 180°C, or 200°C. The heat treatment time can be 30, 80, 120, 200, 300, or 360 seconds.

[0068] The inventors of this application have discovered that if the concentration of polymer solution 18 is too low, the polymer solution 18 will not form a film within the air gaps 140, but will instead form particles, preventing the air gaps 140 from being filled. If the concentration of polymer solution 18 is too high, the viscosity of polymer solution 18 will be too high, preventing the polymer solution 18 from smoothly entering and filling the air gaps 140. Therefore, the preferred concentration of polymer solution 18 in this application is 3-10%, for example, 3%, 5%, 8%, or 10%.

[0069] The thermal decomposition temperature of the polymer solute is greater than 500° C., that is, the thermal decomposition temperature of the porous filler 17 is greater than 500° C. In this way, it can be ensured that the porous filler 17 can withstand the temperature of the latter stage of the preparation method.

[0070] Of course, in some embodiments, to increase the compatibility of the polymer solution 18 with the semiconductor substrate, before step S21, the process may further include: performing a hydrophobic treatment on the walls of the air gap 140. Specifically, HMDS (hexamethyldisilazane) may be used to treat the surface of the first layer 14 and the inner walls of the air gap 140 to form a hydrophobic surface on the inner walls of the air gap 140.

[0071] Step S22 : spraying deionized water on the surface of the polymer solution 18 to allow the polymer solution 18 to form a porous filler 17 through a phase separation process.

[0072] Deionized water is sprayed onto the surface of polymer solution 18 to form a solid porous polymer filler through a liquid-induced phase separation process. The deionized water spraying process can be continued for 5-15 minutes, for example, 5 minutes, 8 minutes, 10 minutes, or 15 minutes, to complete the phase separation. The specific duration of the deionized water spraying process depends on the concentration of polymer solution 18. The porosity of porous filler 17 is 90%-97%, for example, 90%, 950%, or 97%.

[0073] Step S23: removing deionized water and solvent.

[0074] The product structure after step S23 can be seen in Figure 5 , Figure 5 This is a schematic diagram of a structure for forming a porous filler in an air gap according to one embodiment of the present application. Specifically, a vacuum low-temperature heat treatment can be used to remove surface moisture and residual solvent from the semiconductor substrate. For example, vacuum treatment at temperatures below 400°C can be used to remove moisture and residual solvent.

[0075] In the specific implementation process, see Figure 6 , Figure 6 Schematic diagram of the structure for removing the porous filler on the surface of the first layer structure. After step S23, step S24 is also included: removing the porous filler 17 on the surface of the first layer structure 14. Specifically, etching gas, such as oxygen, can be used to etch and remove the porous filler 17 on the surface of the diffusion barrier layer 146.

[0076] Step S3: forming a second layer structure, wherein the second layer structure covers the first layer structure and the porous filler.

[0077] See also Figure 7 , Figure 7 A schematic diagram of a structure in which a second layer structure is formed on a first layer structure according to an embodiment of the present application is provided. Second layer structure 19 includes a third dielectric material layer 191. Third dielectric material layer 191 is stacked on diffusion barrier layer 146. The material of third dielectric material layer 191 can be the same as that of second dielectric material layer 141b. Since air gaps 140 are filled with porous filler 17, third dielectric material layer 191 is not limited to the conventional low-step coverage chemical vapor deposition process, which broadens the material and process options for third dielectric material layer 191.

[0078] The method for fabricating a semiconductor device provided in this embodiment forms a porous filler 17 within the air holes 140, and ensures that the dielectric constant of the porous filler 17 is less than that of the first layer structure 14. This reduces the dielectric constant through the porous filler 17, optimizing the parasitic capacitance reduction effect of the air holes 140 in the first layer structure 14. This minimizes the parasitic capacitance between interconnect layers 142 on the same level, and even reduces the parasitic capacitance between two adjacent contact plugs 145, thereby improving the RF performance of the semiconductor device. Furthermore, by forming the second layer structure 19 after the porous filler 17 is formed within the air holes 140, the second layer structure 19 does not enter the air holes 140 and does not affect the parasitic capacitance reduction effect of the air holes 140. Furthermore, the selection of materials and formation methods for the second layer structure 19 eliminates the need to consider its impact on the air holes 140. The second layer structure 19 can be formed using more than just the low-step coverage chemical vapor deposition process, broadening the material and process options for the second layer structure 19.

[0079] In one embodiment, see Figure 7 , provides a semiconductor device, which includes a semiconductor substrate, a porous filler 17 and a second layer structure 19.

[0080] The semiconductor base includes a substrate 1 and a first layer structure 14 on the substrate 1. The substrate 1 may be composed of any currently known or future developed semiconductor material, including but not limited to silicon, germanium, silicon carbide, III-V compound semiconductors, SOI (Semiconductor on Insulator) substrates, etc. For example, the substrate 1 in the accompanying drawings is an SOI substrate, which includes a bottom semiconductor layer 11a, a buried oxide layer 11b, and a top semiconductor layer 11c stacked in sequence. The top semiconductor layer 11c and the bottom semiconductor layer 11a may be silicon, and the buried oxide layer 11b may be silicon oxide or silicon oxynitride.

[0081] The semiconductor base also includes devices formed on the substrate 1. These devices may take the form of bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), lightly doped drain MOS transistors (LDMOSs), diodes, capacitors, or any other active or passive devices known in the art, to implement various electrical functions. The following figures illustrate transistors as an example. The top semiconductor layer 11c includes a source region 111 and a drain region 112. The source region 111 and the drain region 112 may be in contact with the buried oxide layer 11b, or may be located above the buried oxide layer 11b without contacting the buried oxide layer 11b.

[0082] The semiconductor body further includes a gate 12 and a sidewall spacer 13 disposed on the substrate 1. The gate 12 and the sidewall spacer 13 are disposed on the channel region of the substrate 1. The sidewall spacers 13 are located on both sides of the gate 12.

[0083] The first layer structure 14 is disposed on the substrate 1 and wraps around the gate 12 and the sidewall spacer 13. The first layer structure 14 has air gaps 140. The air gaps 140 are filled with a porous filler 17, and the dielectric constant of the porous filler 17 is less than that of the first layer structure 14. In this way, the porous filler 17 can optimize the effect of reducing parasitic capacitance of the air gaps 140 in the first layer structure 14, thereby minimizing the parasitic capacitance between interconnect layers 142 on the same level in the first layer structure 14, and even reducing the parasitic capacitance between adjacent contact plugs 145, thereby improving the radio frequency performance of the semiconductor device.

[0084] The porous filler 17 comprises a polymer and a vacuum, and has an equivalent dielectric constant of 1-1.1, that is, greater than 1 and less than 1.1. The porous filler 17 is made of a material comprising polysulfone and / or polyetheretherketone.

[0085] Specifically, the porosity of the porous filler 17 is 90%-97%, for example, the porosity is 90%, 95% or 97%, etc. The specific porosity of the porous filler 17 can be controlled by the concentration of the polymer solution 18 .

[0086] First layer structure 14 may include a dielectric material layer 141, a plurality of interconnect layers 142 disposed within dielectric material layer 141, and a plurality of contact plugs 145. Dielectric material layer 141 covers substrate 1. Multiple interconnect layers 142 are spaced apart within dielectric material layer 141 in a direction perpendicular to the stacking direction of first layer structure 14. Porous filler 17 is disposed within dielectric material layer 141, with at least a portion of porous filler 17 located between two adjacent interconnect layers 142. The dielectric constant of porous filler 17 is less than that of dielectric material layer 141. Dielectric material layer 141 may be made of silicon oxide. Interconnect layer 142 may be a metal layer, such as tungsten, copper, or silver.

[0087] The first layer structure 14 also includes a first etch stop layer 143. The dielectric material layer 141 includes a first dielectric material layer 141a and a second dielectric material layer 141b. The first dielectric material layer 141a is disposed on the substrate 1 and surrounds the gate 12 and the sidewall spacer 13. The second dielectric material layer 141b is disposed on the first dielectric material layer 141a. The first dielectric material layer 141a and the second dielectric material layer 141b can be made of silicon oxide, which has a dielectric constant of approximately 3.9. The first etch stop layer 143 is disposed on the first dielectric material layer 141a and vertically between the first and second dielectric material layers 141a, 141b, to vertically isolate the second dielectric material layer 141b from the first dielectric material layer 141a. The first etch stop layer 143 includes one or more electrically insulating materials with particularly high etching resistance and is configured to prevent the first dielectric material layer 141a from being removed during subsequent fabrication of other structures. The first etch stop layer 143 may be silicon nitride. Contact plugs 145 are disposed in the first dielectric material layer 141 a. Interconnect layers 142 are disposed in the first etch stop layer 143 and the second dielectric material layer 141 b and extend to contact corresponding contact plugs 145 .

[0088] In this embodiment, the porous filler 17 extends at least into the second dielectric material layer 141b along the stacking direction of the first layer structure 14. Specifically, the porous filler 17 may penetrate the upper and lower surfaces of the second dielectric material layer 141b and the first etch stop layer 143 along the stacking direction of the first layer structure 14, thereby minimizing the parasitic capacitance between the two interconnect layers 142 adjacent to the porous filler 17.

[0089] In another embodiment, Figure 7 As shown, the porous filler 17 may extend from the surface of the second dielectric material layer 141 b into the first dielectric material layer 141 a , so that the parasitic capacitance between two adjacent contact plugs 145 can be further reduced by the porous filler 17 .

[0090] In one embodiment, please refer to Figure 7 The first layer structure 14 further includes a diffusion barrier layer 146 . The diffusion barrier layer 146 is disposed on the surface of the second dielectric material layer 141 b and covers the interconnection layer 142 to prevent the interconnection layer 142 material from diffusing outward.

[0091] In this specific embodiment, the porous filler 17 can extend from the surface of the diffusion barrier layer 146 into the second dielectric material layer 141b, or further into the first etch stop layer 143. The dielectric constant of the porous filler 17 is lower than the dielectric constants of the diffusion barrier layer 146, the first etch stop layer 143, the first dielectric material layer 141a, and the second dielectric material layer 141b. Specifically, along the stacking direction of the first layer structure 14, the porous filler 17 can extend from the surface of the diffusion barrier layer 146 into the second dielectric material layer 141b; that is, the porous filler 17 penetrates the upper and lower surfaces of the diffusion barrier layer 146 and the second dielectric material layer 141b, so as to minimize the parasitic capacitance between the two interconnect layers 142 adjacent to the porous filler 17.

[0092] In another embodiment, Figure 7 As shown, the porous filler 17 may extend from the surface of the diffusion barrier layer 146 into the first dielectric material layer 141 a . In this way, the parasitic capacitance between two adjacent contact plugs 145 may be further reduced by the porous filler 17 .

[0093] The porous filler 17 can be spaced apart from the gate 12; thus, damage to the gate 12 can be avoided during the formation of the air gap 140. Specifically, the porous filler 17 can be located in the device region and / or isolation region of the semiconductor substrate, which is not limited in this application. Figure 7 In the figure, the porous filler 17 is located in the device region of the semiconductor substrate as an example.

[0094] The semiconductor device provided in an embodiment of the present application includes a semiconductor base, a porous filler 17, and a second layer structure 19. The semiconductor base includes a stacked substrate 1 and a first layer structure 14, wherein the first layer structure 14 has air gaps 140; the porous filler 17 fills the air gaps 140, and the dielectric constant of the porous filler 17 is less than the dielectric constant of the first layer structure 14; and the second layer structure 19 covers the first layer structure 14 and the porous filler 17. In this way, the dielectric constant can be reduced by the porous filler 17, and the effect of the air gaps 140 in the first layer structure 14 on reducing parasitic capacitance is optimized, thereby minimizing the parasitic capacitance between interconnect layers 142 on the same level in the first layer structure 14, and even reducing the parasitic capacitance between adjacent contact plugs 145, thereby improving the radio frequency performance of the semiconductor device. At the same time, the air gap 140 is filled with porous filler 17. During the process of forming the second layer structure 19, the second layer structure 19 will not enter the air gap 140, and the second layer structure 19 will not affect the volume of the air gap 140; and in the selection of materials and formation methods for the second layer structure 19, there is no need to consider the impact of the second layer structure 19 on the air gap 140. The second layer structure 19 is not limited to the previous low step coverage chemical vapor deposition process, which broadens the selectivity of materials and processes for the second layer structure 19.

[0095] The above is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor base, the semiconductor base comprising a substrate and a first layer structure on the substrate, wherein the first layer structure has air gaps formed therein; forming a porous filler in the air gap pores, wherein the porous filler fills the air gap pores, and the dielectric constant of the porous filler is smaller than the dielectric constant of the first layer structure; A second layer structure is formed, the second layer structure covering the first layer structure and the porous filler.

2. The method for preparing a semiconductor device according to claim 1, wherein: The first layer structure includes a dielectric material layer, a plurality of contact plugs disposed in the dielectric material layer, and a plurality of interconnection layers; The air gap holes are formed in the dielectric material layer, and at least a portion of the air gap holes is located between two adjacent interconnection layers; the dielectric constant of the porous filler is smaller than the dielectric constant of the dielectric material layer.

3. The method for preparing a semiconductor device according to claim 2, wherein: The first layer structure further includes a first etch stop layer; The dielectric material layer includes a first dielectric material layer and a second dielectric material layer; the second dielectric material layer is located on the first dielectric material layer; The first etch stop layer is located between the first dielectric material layer and the second dielectric material layer; The contact plug is provided in the first dielectric material layer, and the interconnect layer is provided in the second dielectric material layer and the first etch stop layer; Along the stacking direction of the first layer structure, the air gap holes extend at least into the second dielectric material layer.

4. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a porous filler in the air gap pores comprises: Filling the air gap pores with a polymer solution comprising a polymer solute and a solvent; spraying deionized water on the surface of the polymer solution to form a porous filler through a phase separation process; The deionized water and the solvent are removed.

5. The method for preparing a semiconductor device according to claim 1, wherein: Before the step of forming a porous filler in the air gap pores, the method further includes: The groove walls of the air gap holes are subjected to hydrophobic treatment.

6. The method for preparing a semiconductor device according to claim 1, wherein: The thermal decomposition temperature of the porous filler is greater than 500°C.

7. The method for preparing a semiconductor device according to claim 2, wherein: The first layer structure further includes a diffusion barrier layer, which is provided on the dielectric material layer and covers the interconnection layer to prevent the interconnection layer material from diffusing outward.

8. The method for preparing a semiconductor device according to any one of claims 1 to 7, wherein: The equivalent dielectric constant of the porous filler is 1-1.

1.

9. A semiconductor device, characterized in that: include: A semiconductor substrate comprises a substrate and a first layer structure on the substrate, wherein the first layer structure has air gaps; A porous filler, filling the air gap pores, wherein the dielectric constant of the porous filler is smaller than the dielectric constant of the first layer structure; The second layer structure covers the first layer structure and the porous filler in the air gap pores.

10. The semiconductor device according to claim 9, wherein The first layer structure includes a dielectric material layer, a plurality of contact plugs disposed in the dielectric material layer, and a plurality of interconnection layers; The porous filler is provided in the dielectric material layer, and at least a portion of the porous filler is located between two adjacent interconnection layers; the dielectric constant of the porous filler is smaller than the dielectric constant of the dielectric material layer.

11. The semiconductor device according to claim 10, wherein: The first layer structure further includes a diffusion barrier layer, which is provided on the dielectric material layer and covers the interconnection layer to prevent the interconnection layer material from diffusing outward.

12. The semiconductor device according to claim 10, wherein: The first layer structure further includes a first etch stop layer; The dielectric material layer includes a first dielectric material layer and a second dielectric material layer; the second dielectric material layer is located on the first dielectric material layer; The first etch stop layer is located between the first dielectric material layer and the second dielectric material layer; The contact plug is provided in the first dielectric material layer, and the interconnect layer is provided in the second dielectric material layer and the first etch stop layer; Along the stacking direction of the first layer structure, the porous filler extends at least into the second dielectric material layer.

13. The semiconductor device according to claim 9, wherein The porous filler includes polysulfone and / or polyetheretherketone.

14. The semiconductor device according to any one of claims 9 to 13, wherein: The equivalent dielectric constant of the porous filler is 1-1.1.

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