Semiconductor device, manufacturing method thereof and electronic equipment
By setting contact layers in semiconductor devices and optimizing transistor structures, the challenge of manufacturing more devices on a limited substrate is solved, the performance is improved and the manufacturing difficulty is reduced, making it suitable for high-density integration.
Patent Information
- Application Number
- CN202410287933.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-16
AI Technical Summary
As the critical dimensions of semiconductor devices shrink, the impact of tiny differences on device performance becomes increasingly significant. How to manufacture more devices on limited substrates and improve performance becomes a challenge.
By forming a patterned conductive layer and dielectric layer on the substrate, etching to form through holes and depositing conductive and semiconductor layers, a contact layer is set to reduce contact resistance, control channel length, and optimize transistor structure.
It improves the performance of semiconductor devices, especially the on-state current of transistors, reduces manufacturing difficulty and saves space, and is suitable for high-density integration.
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Figure CN120656994A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices. Specifically, the present application relates to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.
[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention
[0004] The present application proposes a semiconductor device and a manufacturing method thereof, and an electronic device, which can effectively improve the performance of the semiconductor device.
[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:
[0006] forming a patterned first conductive layer on a substrate;
[0007] forming a first dielectric layer covering the first conductive layer on the substrate;
[0008] forming a patterned second conductive layer on the first dielectric layer;
[0009] covering the second conductive layer with a second dielectric layer;
[0010] Sequentially etching the second dielectric layer and the second conductive layer to form an initial hole penetrating the second dielectric layer and the second conductive layer, wherein the initial hole stops at the first dielectric layer;
[0011] Depositing a conductive layer in the initial hole, removing the conductive layer on the first dielectric layer at the bottom of the initial hole, and retaining at least the conductive layer in contact with the second conductive layer and the second dielectric layer as a first contact layer;
[0012] Etching the first dielectric layer downward in the initial hole to form a via hole penetrating the second dielectric layer, the second conductive layer, and the first dielectric layer;
[0013] A semiconductor layer is deposited in the via hole, and the semiconductor layer covers the first contact layer, the first dielectric layer, and the first conductive layer; the semiconductor layer contacts the first contact layer and is electrically connected to the first conductive layer.
[0014] In some embodiments, after depositing the semiconductor layer in the via hole, the method further includes:
[0015] A first gate dielectric layer and a gate are deposited in the via hole.
[0016] In some embodiments, after forming a patterned first conductive layer on the substrate and before forming a first dielectric layer covering the first conductive layer on the substrate, the method further includes:
[0017] Depositing a second contact layer on a side of the first conductive layer away from the substrate;
[0018] And, depositing a semiconductor layer in the via hole, comprising:
[0019] A semiconductor layer is deposited in the via hole, where the semiconductor layer covers and contacts the first contact layer, the first dielectric layer and the second contact layer.
[0020] In some embodiments, the initial hole stops at the first dielectric layer, which includes: the initial hole stops at the upper surface of the first dielectric layer.
[0021] In some embodiments, the semiconductor layer is a metal oxide semiconductor layer;
[0022] The material of the first contact layer includes a metal oxide or a metal nitride of at least one of indium, tin, zinc, and titanium; and / or
[0023] The material of the second contact layer includes metal oxide or metal nitride of at least one of indium, tin, zinc, and titanium.
[0024] In a second aspect, an embodiment of the present application provides a semiconductor device, including:
[0025] A first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially stacked on the substrate;
[0026] a via hole passing through the second dielectric layer, the second conductive layer, and the first dielectric layer, and stopping at the first conductive layer;
[0027] a first contact layer located in the via hole and extending along the sidewall of the via hole, from the second dielectric layer through the area of the second conductive layer exposed in the via hole and stopping at the first dielectric layer, the first contact layer being in contact with the second conductive layer;
[0028] It also includes a semiconductor layer; the semiconductor layer is located in the via hole and connected to the first contact layer, the first dielectric layer and the first conductive layer; the semiconductor layer is in contact with each area of the first contact layer exposed in the via hole.
[0029] In some embodiments, in a cross section parallel to the substrate, the first contact layer is ring-shaped.
[0030] In some embodiments, a second contact layer is further included; the second contact layer is disposed on the first conductive layer, and the second contact layer contacts the semiconductor layer in an area exposed at the bottom of the via hole.
[0031] In some embodiments, the thickness of the first dielectric layer is equal to the channel length of the semiconductor device.
[0032] In some embodiments, the first contact layer extends along the sidewall of the via hole toward the substrate and does not extend beyond the first dielectric layer.
[0033] In some embodiments, the semiconductor layer is a metal oxide semiconductor layer;
[0034] The material of the first contact layer includes a metal oxide or a metal nitride of at least one of indium, tin, zinc, and titanium; and / or
[0035] The material of the second contact layer includes metal oxide or metal nitride of at least one of indium, tin, zinc, and titanium.
[0036] In a third aspect, an embodiment of the present application provides an electronic device comprising the above-mentioned semiconductor device.
[0037] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:
[0038] In the method for manufacturing a semiconductor device provided in an embodiment of the present application, the performance of the semiconductor device is effectively improved by forming a first contact layer at least between the second conductive layer and the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0040] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
[0041] Figure 2-11 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
[0042] Figure 12-18 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
[0043] Figure 19 A schematic structural diagram of a memory cell of a semiconductor device provided in an embodiment of the present application;
[0044] Figure 20 for Figure 19 A schematic diagram of a circuit principle of a memory cell of a semiconductor device;
[0045] Figure 21 A schematic structural diagram of a first transistor in a semiconductor device provided in an embodiment of the present application;
[0046] Reference numerals:
[0047] 100 - first transistor; 110 - substrate; 120 - first conductive layer; 130 - first dielectric layer; 140 - second conductive layer; 150 - second dielectric layer; 160 - first contact layer; 170 - semiconductor layer; 180 - first gate dielectric layer; 190 - gate;
[0048] 101 - initial hole; 102 - via hole; 103 - second contact layer; 104 - first initial dielectric layer; 105 - second initial conductive layer; 106 - second initial dielectric layer; 107 - initial semiconductor layer; 108 - first initial gate dielectric layer; 109 - initial gate;
[0049] 200 - second transistor; 210 - third conductive layer; 220 - third contact layer; 230 - third dielectric layer; 240 - fourth dielectric layer; 250 - second semiconductor layer; 260 - second gate dielectric layer; 270 - fourth conductive layer; 280 - second initial hole; 290 - second via hole;
[0050] 201 - third initial conductive layer; 202 - third initial dielectric layer; 203 - fourth initial dielectric layer; 204 - second initial semiconductor layer; 205 - second initial gate dielectric layer; 206 - fourth initial conductive layer;
[0051] 310 - fifth conductive layer. DETAILED DESCRIPTION
[0052] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0053] Those skilled in the art will understand that, unless otherwise stated, the terms "said" and "the" used herein may also include plural forms. It should be further understood that the term "including" used in the specification of this application refers to the presence of the described features, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".
[0054] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.
[0055] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.
[0056] The present invention provides a method for manufacturing a semiconductor device. Figure 1 As shown, the method for manufacturing a semiconductor device includes at least the steps of manufacturing a transistor on a substrate, and the method includes the following steps:
[0057] S101 : forming a patterned first conductive layer 120 on a substrate 110 .
[0058] S102 : forming a first dielectric layer 130 on the substrate 110 to cover the first conductive layer 120 .
[0059] S103 : forming a patterned second conductive layer 140 on the first dielectric layer 130 .
[0060] S104 : Covering the second conductive layer 140 with a second dielectric layer 150 .
[0061] S105 : etching the second dielectric layer 150 and the second conductive layer 140 in sequence to form an initial hole 101 penetrating the second dielectric layer 150 and the second conductive layer 140 . The initial hole 101 stops at the first dielectric layer 130 .
[0062] S106 : depositing a conductive layer in the initial hole 101 , removing the conductive layer on the first dielectric layer 130 at the bottom of the initial hole 101 , and retaining at least the conductive layer in contact with the second conductive layer 140 and the second dielectric layer 150 as the first contact layer 160 .
[0063] S107: Etching the first dielectric layer 130 downward in the initial hole 101 to form a via hole 102 penetrating the second dielectric layer 150 , the second conductive layer 140 , and the first dielectric layer 130 ;
[0064] S108 : depositing a semiconductor layer 170 in the via hole 102 , the semiconductor layer 170 covering the first contact layer 160 , the first dielectric layer 130 and the first conductive layer 120 ; the semiconductor layer 170 contacts the first contact layer 160 and is electrically connected to the first conductive layer.
[0065] The manufacturing method of the semiconductor device provided in the embodiment of the present application includes a process for manufacturing a transistor, wherein the second conductive layer includes the source or drain of the transistor, and a conductive layer is deposited as a first contact layer 160 in an initial hole 101 that penetrates the second dielectric layer 150 and the second conductive layer 140; then, etching is continued downward in the initial hole 101 to form a via 102 that penetrates the second dielectric layer 150, the second conductive layer 140, and the first dielectric layer 130. This can control the channel length of the transistor, and at the same time, can reduce the contact resistance between the channel and the source or drain, thereby increasing the on-state current of the transistor.
[0066] In the examples of this application, see Figure 2 As shown, the first electrode (drain or source) of the transistor is formed in a recess of the substrate. A first conductive layer 120 is formed on the substrate 110 through photolithography, etching, and metallization processes. A layer of conductive metal oxide or metal nitride is deposited on one side of the first conductive layer 120 to reduce the contact resistance between the semiconductor layer and the first conductive layer, forming a second contact layer 103. The first conductive layer 120 and the second contact layer 103 are contained within the first electrode, which includes the drain of the first transistor 100 and the first signal line, and is planarized.
[0067] In some embodiments, the first electrode is formed on the substrate rather than in a groove of the substrate.
[0068] The present application provides a second contact layer between the first conductive layer and the semiconductor layer, thereby reducing the contact resistance between the channel and the source or drain and increasing the on-state current of the transistor.
[0069] The metallization process can be a direct metal etching process or a damascene process. The metal of the first conductive layer 120 is generally tungsten, molybdenum, aluminum, copper, titanium nitride, cobalt, nickel, ruthenium, platinum, etc., which have high conductivity. The second contact layer 103 includes a metal oxide or metal nitride of at least one of indium, tin, zinc, and titanium. For example, the conductive metal oxide of the second contact layer 103 is IZO, ITO, TiN, etc.
[0070] The semiconductor layer 170 is a metal oxide semiconductor layer, such as a metal oxide semiconductor containing at least one of indium, gallium, zinc, tin, and aluminum.
[0071] In the embodiments of this application, Figure 3 As shown, a first initial dielectric layer 104 is deposited on the side of the second contact layer 103 and the substrate 110 that is not blocked by the second contact layer 103. The first initial dielectric layer 104 serves as an etch stop layer for the initial hole 101. The first initial dielectric layer 104 can be made of any insulating dielectric, such as aluminum oxide, silicon nitride, or silicon oxide. The first initial dielectric layer 104 can be deposited using methods such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition). The first initial dielectric layer 104 and the substrate 110 should be made of different materials and have different etching selectivities.
[0072] In the embodiments of this application, Figure 4 As shown, a second initial conductive layer 105 is formed on a side of the first initial dielectric layer 104 away from the substrate 110 through photolithography, etching and metallization processes.
[0073] In the embodiments of this application, Figure 5 As shown, a second initial dielectric layer 106 is deposited on a side of the second initial conductive layer 105 away from the substrate 110 .
[0074] In the embodiments of this application, Figure 6 As shown, an initial hole 101 is formed by photolithography and etching processes. The initial hole 101 penetrates the second initial dielectric layer 106 and the second initial conductive layer 105 and stops at the first initial dielectric layer 104. The second initial dielectric layer 106 is disconnected at the initial hole 101 to form the second dielectric layer 150, and the second initial conductive layer 105 is disconnected at the initial hole 101 to form the second conductive layer 140. In actual products, in order to ensure that the second initial conductive layer 105 is completely etched through, the initial hole 101 may have a small or negligible over-etching or an allowable error range, so as to be shown in FIG. Figure 6 The initial hole 101 is shown to extend beyond the lower surface of the second conductive layer.
[0075] In the embodiments of this application, Figure 7 As shown, a conductive layer 4 is deposited in the initial hole 101 by atomic layer deposition. The conductive layer may be made of a common conductive metal oxide such as IZO, ITO, or other materials that serve as contact layers. This application does not impose any specific restrictions on the materials.
[0076] In the embodiments of this application, Figure 8As shown, an anisotropic etching process is performed to remove the conductive layer on the first dielectric layer 130 at the bottom of the initial hole 101, leaving at least the conductive layer in contact with the second conductive layer 140 and the second dielectric layer 150, thereby forming a ring-shaped first contact layer 160 located on the sidewall of the hole. Next, the first initial dielectric layer 104 is etched downward within the initial hole 101 to expose the second contact layer 103, forming a via 102 that penetrates the second dielectric layer 150, the second conductive layer 140, and the first dielectric layer 130. The first contact layer 160 extends along a third direction c perpendicular to the substrate 110, covering the sidewalls of the second conductive layer 140. Together with the adjacent second conductive layer 140, it forms the source of the first transistor 100. The first contact layer 160 extends along the sidewalls of the via 102 toward the substrate 110 and does not extend beyond the first dielectric layer 130.
[0077] The first contact layer 160 includes a metal oxide or metal nitride of at least one of indium, tin, zinc, and titanium. For example, the first contact layer 160 includes IZO, ITO, TiN, etc. The semiconductor layer 170 is a metal oxide semiconductor layer, such as a metal oxide semiconductor containing at least one of indium, gallium, zinc, tin, and aluminum.
[0078] In the embodiments of this application, Figure 9 As shown, an initial semiconductor layer 107 is deposited in the via 102. The material of the initial semiconductor layer 107 includes indium gallium zinc oxide (IGZO), and the indium (In), gallium (Ga), and zinc (Zn) precursors do not contain metal-oxygen bonds. Alcohols are used as precursors for oxidation.
[0079] Optionally, in one embodiment of the present application, after step S108, a semiconductor layer 170 is deposited in the via hole 102, and the semiconductor layer 170 covers the first contact layer 160, the first dielectric layer 130 and the first conductive layer 120. Figure 10-11 As shown, it also includes:
[0080] A first initial gate dielectric layer 108 and an initial gate 109 are sequentially deposited in the via hole 102 .
[0081] Based on the patterning process, a first gate dielectric layer 180 formed by the first initial gate dielectric layer 108 and a gate 190 formed by the initial gate 109 are obtained.
[0082] like Figure 10 As shown, a first initial gate dielectric layer 108 and an initial gate electrode 109 are sequentially deposited in the via hole 102 to form a basic vertical channel transistor structure. The material of the first initial gate dielectric layer 108 includes common oxide semiconductors such as Al2O3, HfO2 or SiO2.
[0083] like Figure 11 As shown, through photolithography and etching processes, the excess film layers in the initial semiconductor layer 107, the first initial gate dielectric layer 108, and the initial gate 109 are removed to obtain a semiconductor layer 170 formed by the initial semiconductor layer 107, a first gate dielectric layer 180 formed by the first initial gate dielectric layer 108, and a gate 190 formed by the initial gate 109.
[0084] Optionally, in one embodiment of the present application, after step S101, after forming the patterned first conductive layer 120 on the substrate 110, and before step S102, and before forming the first dielectric layer 130 covering the first conductive layer 120 on the substrate 110, the process further includes:
[0085] The second contact layer 103 is deposited on the side of the first conductive layer 120 away from the substrate 110. Figure 2 shown.
[0086] And, in step S108, a semiconductor layer 170 is deposited in the via hole 102, and the semiconductor layer 170 covers the first contact layer 160, the first dielectric layer 130 and the first conductive layer 120. Figure 9 Shown, including:
[0087] A semiconductor layer 170 is deposited in the via hole 102 . The semiconductor layer 170 extends from the opening of the via hole 102 toward the substrate and contacts the first contact layer 160 , the first dielectric layer 130 and the second contact layer 103 .
[0088] The manufacturing method of the semiconductor device provided in the embodiments of the present application is relatively simple. A first conductive layer 120, a second contact layer 103, a first dielectric layer 130, a second conductive layer 140, a second dielectric layer 150, a first contact layer 160, and a semiconductor layer 170 are sequentially manufactured on one side of a substrate 110. When manufacturing the semiconductor layer 170, the first conductive layer 120 at the drain of the first transistor 100 is covered by the second contact layer 103, and the second conductive layer 140 at the source of the first transistor 100 is covered by the first contact layer 160. This prevents oxidation of the metals in the first conductive layer 120 and the second conductive layer 140 during deposition of the semiconductor layer 170, thereby reducing the contact resistance between the source and drain of the first transistor 100 and the semiconductor layer 170 and increasing the transistor's on-state current. Furthermore, the thicknesses of the first conductive layer 120 and the second conductive layer 140 are equal to the thicknesses of the source and drain, respectively.
[0089] Optionally, in one embodiment of the present application, the initial hole 101 stops at the first dielectric layer 130 , which includes: the initial hole 101 stops at the upper surface of the first dielectric layer 130 .
[0090] Furthermore, a conductive layer is deposited in the initial hole 101, and the conductive layer on the first dielectric layer 130 at the bottom of the initial hole 101 is removed to retain at least the conductive layer in contact with the second conductive layer 140 and the second dielectric layer 150 as a first contact layer 160, including:
[0091] A conductive layer is deposited in the initial hole 101 , and the conductive layer on the first dielectric layer 130 in the initial hole 101 is removed, leaving the conductive layer in contact with the second conductive layer 140 and the second dielectric layer 150 as the first contact layer 160 .
[0092] In the embodiment of the present application, the initial hole 101 stops at the upper surface of the first dielectric layer 130; along the extension direction of the initial hole 101, the first contact layer 160 contacts the second conductive layer 140 and the second dielectric layer 150 exposed in the initial hole 101, so that the channel length of the transistor is equal to the thickness of the first dielectric layer 130, and the length of the first contact layer 160 is related to the thickness of the second dielectric layer 150. Therefore, the channel length of the transistor can be controlled simply by controlling the thickness of the first dielectric layer 130.
[0093] Furthermore, a conductive layer is deposited in the initial hole 101, and the conductive layer on the first dielectric layer 130 at the bottom of the initial hole 101 is removed to retain at least the conductive layer in contact with the second conductive layer 140 and the second dielectric layer 150 as a first contact layer 160, including:
[0094] A conductive layer is deposited in the initial hole 101 , and the conductive layer on the first dielectric layer 130 at the bottom of the initial hole 101 is removed, leaving the conductive layer in contact with the second dielectric layer 150 , the second conductive layer 140 , and the first dielectric layer 130 at the sidewall of the initial hole 101 as the first contact layer 160 .
[0095] In the embodiment of the present application, the initial hole 101 stops inside the first dielectric layer 130. Along the extension direction of the initial hole 101, the second conductive layer 140, the second dielectric layer 150, and the first dielectric layer 130 exposed in the initial hole 101 are in contact with the first contact layer 160. In this embodiment, the channel length of the transistor can be controlled simply by controlling the thickness of the first dielectric layer 130, thereby reducing the difficulty of transistor manufacturing and improving device performance.
[0096] Optionally, after obtaining the first gate dielectric layer 180 formed by the first initial gate dielectric layer 108 and the gate 190 formed by the initial gate 109 through a patterning process, the second transistor 200 is further manufactured. The specific steps are as follows:
[0097] like Figure 12As shown, a third initial dielectric layer 202 is deposited on one side of the gate 190 and the second dielectric layer 150. This third initial dielectric layer 202 serves as an etch stop layer for the second initial hole 280. A third initial conductive layer 201 is formed on the side of the third initial dielectric layer 202 away from the substrate 110 through photolithography, etching, and metallization processes. A fourth initial dielectric layer 203 is deposited on the side of the third initial conductive layer 201 away from the substrate 110.
[0098] like Figure 13 As shown, a second initial hole 280 is formed through photolithography and etching processes. The second initial hole 280 penetrates the fourth initial dielectric layer 203 and the third initial conductive layer 201 and stops at the third initial dielectric layer 202. The fourth initial dielectric layer 203 is disconnected at the second initial hole 280 to form the fourth dielectric layer 240, and the third initial conductive layer 201 is disconnected at the second initial hole 280 to form the third conductive layer 210.
[0099] like Figure 14 As shown, a conductive layer is conformally deposited in the second initial hole 280 by an atomic layer deposition process. The material of the conductive layer includes common conductive metal oxides such as IZO, ITO, TiN, metal nitrides or other conductive materials.
[0100] like Figure 15 As shown, anisotropic etching is performed through an etching process to remove the conductive layer at the bottom of the second initial hole 280, the conductive layer on the side of the fourth dielectric layer 240 away from the substrate 110, and the third initial dielectric layer 202 until the gate 190 is exposed, thereby forming a second via hole 290. The conductive layer located on the sidewall of the second initial hole 280 forms a third contact layer 220. The third contact layer 220 extends along a third direction c perpendicular to the substrate 110, covers the sidewall of the third conductive layer 210, and together with the third conductive layer 210 adjacent thereto, forms the source of the second transistor 200.
[0101] like Figure 16 As shown, a second initial semiconductor layer 204 and a second initial gate dielectric layer 205 are conformally manufactured in the second via hole 290 .
[0102] like Figure 17 As shown, a fourth initial conductive layer 206 is fabricated on one side of the second initial gate dielectric layer 205 and the fourth dielectric layer 240 formed by the fourth initial dielectric layer 203 .
[0103] like Figure 18As shown, based on the patterning process, a second semiconductor layer 250 formed by the second initial semiconductor layer 204, a second gate dielectric layer 260 formed by the second initial gate dielectric layer 205, and a fourth conductive layer 270 formed by the fourth initial conductive layer 206 are obtained; the fourth conductive layer 270 includes a gate and a fourth signal line arranged at intervals along the first direction a, the second gate dielectric layer 160 and the second semiconductor layer 250 are sequentially arranged around the gate and located between the third contact layers 220; the fourth signal line is located on one side of the fourth dielectric layer.
[0104] Finally, if Figure 19 As shown, a fifth conductive layer 310 is obtained on one side of the fourth dielectric layer 240 and the fourth conductive layer 270 through a standard metallization process, and wiring is formed at each end to obtain the desired semiconductor device.
[0105] Based on the same inventive concept, the present invention provides a semiconductor device, such as Figure 19-21 As shown, the semiconductor device includes two transistors, one of which is a read transistor and the other is a write transistor.
[0106] The manufacturing method of any one of the read transistor or the write transistor can be obtained by the manufacturing method provided in the above embodiment.
[0107] Semiconductor devices specifically include:
[0108] A first conductive layer 120 , a first dielectric layer 130 , a second conductive layer 140 and a second dielectric layer 150 are sequentially stacked on the substrate 110 .
[0109] The via 102 passes through the second dielectric layer 150 , the second conductive layer 140 , and the first dielectric layer 130 , and stops at the first conductive layer 120 .
[0110] The first contact layer 160 is located in the via 102 and extends along the sidewall of the via 102 , from the second dielectric layer 150 through the area of the second conductive layer 140 exposed in the via 102 and stops at the first dielectric layer 130 . The first contact layer 160 is connected to each area of the second conductive layer 140 exposed in the via 102 .
[0111] In the semiconductor device provided by the embodiment of the present application, a via 102 penetrates the second dielectric layer 150, the second conductive layer 140, and the first dielectric layer 130, and stops at the first conductive layer 120. A first contact layer 160 is provided within the via 102 and extends along the sidewalls of the via 102. The first contact layer 160 extends from the second dielectric layer 150 through the exposed area of the second conductive layer 140 within the via 102 and stops at the first dielectric layer 130. The first contact layer 160 is connected to each area of the second conductive layer 140 exposed within the via 102. As a result, the channel length of the semiconductor device is related to the thickness of the first dielectric layer, and the length of the first contact layer is related to the thickness of the second dielectric layer. Therefore, the channel length of the transistor and the length of the first contact layer can be controlled simply by controlling the thickness of the first and second dielectric layers, thereby reducing the difficulty in controlling the process of the first contact layer and the channel length.
[0112] Optionally, in one embodiment of the present application, Figure 19 and Figure 21 As shown, the semiconductor device includes at least one of the following:
[0113] In a cross section parallel to the substrate 110 , the first contact layer 160 has a ring shape.
[0114] The material of the first contact layer 160 includes metal oxide or metal nitride.
[0115] In the embodiment of the present application, the material of the first contact layer 160 includes conductive metal oxides such as IZO, ITO, TiN, conductive metal nitrides, and other materials.
[0116] Optionally, in one embodiment of the present application, Figure 19 and Figure 21 As shown, the semiconductor device further includes a semiconductor layer 170 .
[0117] The semiconductor layer 170 is located in the via hole 102 and is connected to the first conductive layer 120 through the first contact layer 160 and the first dielectric layer 130 at the opening of the via hole 102. The semiconductor layer 170 contacts the exposed areas of the first contact layer 160 in the via hole 102. The material of the semiconductor layer 170 includes a metal oxide semiconductor.
[0118] In the embodiment of the present application, the material of the semiconductor layer 170 includes Indium Gallium Zinc Oxide (IGZO).
[0119] For example, the material of the semiconductor layer 170 may be a wide bandgap material, such as a metal oxide material having a bandgap greater than 1.65 eV.
[0120] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.
[0121] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. Materials such as the above can be used as long as the leakage current of the transistor can meet the requirements. The specific adjustment can be made according to the actual situation.
[0122] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10-15A to 10-18A, thereby improving the operating performance of the dynamic memory.
[0123] Optionally, in one embodiment of the present application, Figure 19 and Figure 21 As shown, the semiconductor device further includes a second contact layer 103 ; the second contact layer 103 is disposed on the first conductive layer 120 , and the second contact layer 103 contacts the semiconductor layer 170 in an area exposed at the bottom of the via hole 102 .
[0124] Optionally, in the embodiment of the present application, the first conductive layer 120 and the second contact layer 103 form a first electrode. The first electrode extends along a first direction a and includes the drain of the first transistor 100 and a first signal line. The second conductive layer 140 extends along a second direction b and includes a second signal line. The second direction b and the first direction a are both parallel to and intersect the substrate 110. The first contact layer 160 is located within the via 102 and extends along a third direction c perpendicular to the substrate 110. The first contact layer 160 is connected to the exposed areas of the second conductive layer 140 within the via 102. The first contact layer 160 and the second conductive layer 140 adjacent thereto form the source of the first transistor 100. The semiconductor layer 170 and the gate 190 are both disposed between the side of the first electrode away from the substrate 110 and the first contact layer 160. The semiconductor layer 170 is insulated and surrounds the gate 190.
[0125] In the semiconductor device provided in the embodiment of the present application, a first electrode is provided including a stacked first conductive layer 120 and a second contact layer 103, so that the semiconductor layer 170 is connected to the second contact layer 103; a first contact layer 160 is added between the second conductive layer 140 and the semiconductor layer 170, so that when the semiconductor layer 170 is manufactured, the metal of the first conductive layer 120 of the drain of the first transistor 100 and the second conductive layer 140 of the source of the first transistor 100 will not be oxidized, thereby reducing the contact resistance between the source and drain of the first transistor 100 and the semiconductor layer 170, and improving the on-state current of the first transistor 100 without increasing the occupied area of the semiconductor device.
[0126] Alternatively, as Figure 19 As shown, the semiconductor device further includes a second transistor 200, and the second transistor 200 includes:
[0127] A third dielectric layer 230 , a third conductive layer 210 , and a fourth dielectric layer 240 are sequentially stacked on one side of the gate 190 and the second dielectric layer 150 .
[0128] The second via hole 290 passes through the fourth dielectric layer 240 , the third conductive layer 210 and the third dielectric layer 230 , and stops at the gate 190 .
[0129] The third contact layer 220 is located in the second via hole 290 and extends along the sidewall of the via hole 290, from the fourth dielectric layer 240 through the area of the third conductive layer 210 exposed in the second via hole 290 and stops at the third dielectric layer 230. The third contact layer 220 is connected to the areas of the third conductive layer 210 exposed in the second via hole 290.
[0130] The second semiconductor layer 250 is located in the second via hole 290 and is connected to the gate 190 through the third contact layer 220 and the third dielectric layer 230 from the opening of the second via hole 290. The second semiconductor layer 250 contacts the areas of the third contact layer 220 exposed in the second via hole 290. The material of the second semiconductor layer 250 includes a metal oxide semiconductor.
[0131] In the embodiment of the present application, the third conductive layer 210 extends along the second direction b and includes a third signal line. The third contact layer 220 extends along a third direction c perpendicular to the substrate 110, covers the sidewalls of the third conductive layer 210, and together with the third conductive layer 210 adjacent thereto, forms the source of the second transistor 200. The fourth conductive layer of the second transistor 200 extends along the first direction a and includes the gate of the second transistor 200 and the fourth signal line. The second semiconductor layer 250 and the gate of the second transistor 200 are both disposed between the side of the gate 190 away from the substrate 110 and the third contact layer 220. The second semiconductor layer 250 is insulated and surrounds the gate of the second transistor 200.
[0132] In an embodiment of the present application, the semiconductor device includes a first transistor 100 and a second transistor 200, the first transistor is connected to the second transistor, and the second transistor 200 and the first transistor 100 are stacked in sequence along a third direction c perpendicular to the substrate 110. The first transistor 100 and the second transistor 200 form a multi-layer stacked structure, which makes the memory more compact in space, thereby saving area and facilitating high-density integration and manufacturing.
[0133] In the embodiment of the present application, the first transistor 100 and the second transistor 200 form a 2T0C memory cell. Figure 20 As shown, the first transistor 100 can be a read transistor, the first signal line can be a read bit line RBL, and the second signal line can be a read word line RWL; the second transistor 200 can be a write transistor, the third signal line can be a write bit line WBL, the fourth signal line can be a write word line WWL, and the gate 190 can be SN.
[0134] Optionally, in one embodiment of the present application, Figure 19 and Figure 21 As shown, when the first contact layer 160 stops at the upper surface of the first dielectric layer 130 , the thickness of the first dielectric layer 130 is equal to the channel length of the transistor.
[0135] When the first contact layer 160 stops inside the first dielectric layer 130 , the thickness of the first dielectric layer 130 corresponding to the first contact layer 160 is equal to the channel length of the transistor.
[0136] In the embodiment of the present application, along the third direction c, the channel length of the first transistor 100 of the semiconductor device is related to the thickness of the first dielectric layer 130. In practical applications, if the required channel length of the first transistor 100 is smaller, the thickness of the first dielectric layer 130 can be reduced.
[0137] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the semiconductor device of any embodiment.
[0138] It should be noted that, since the electronic device of the embodiment of the present application includes the semiconductor device of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the semiconductor device of the embodiment of the present application, which will not be elaborated here.
[0139] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal, etc.
[0140] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0141] The manufacturing method of the semiconductor device provided in the embodiment of the present application includes a process for manufacturing a transistor. Specifically, a patterned first conductive layer 120, a first dielectric layer 130, a second conductive layer 140, and a second dielectric layer 150 are sequentially formed on one side of a substrate 110. A conductive layer is deposited in an initial hole 101 penetrating the second dielectric layer 150 and the second conductive layer 140. The conductive layer on the first dielectric layer 130 at the bottom of the initial hole 101 is removed, and the conductive layer at least adjacent to the second conductive layer 140 and the second dielectric layer 150 is retained. 50 is contacted with the conductive layer as the first contact layer 160; then, etching is continued downward in the initial hole 101 to form a via hole 102 that penetrates the second dielectric layer 150, the second conductive layer 140, and the first dielectric layer 130, exposing the first conductive layer 120; a semiconductor layer 170 is deposited in the via hole 101, so that the semiconductor layer 170 is connected to the first conductive layer 120 from the opening of the via hole 102 through the first contact layer 160 and the first dielectric layer 130, and the semiconductor layer 170 is in contact with the first contact layer 160. Therefore, in this application, the channel length of the semiconductor device is related to the thickness of the first dielectric layer 130, and the length of the first contact layer 160 is related to the thickness of the second dielectric layer 150. By controlling the thickness of the first dielectric layer 130, the channel length of the transistor can be controlled, and by controlling the thickness of the second dielectric layer 150, the length of the first contact layer 160 can be controlled, thereby improving transistor performance while reducing the difficulty of the manufacturing process.
[0142] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.
[0143] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.
[0144] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.
[0145] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0146] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0147] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: forming a patterned first conductive layer on a substrate; forming a first dielectric layer covering the first conductive layer on the substrate; forming a patterned second conductive layer on the first dielectric layer; covering the second conductive layer with a second dielectric layer; Sequentially etching the second dielectric layer and the second conductive layer to form an initial hole penetrating the second dielectric layer and the second conductive layer, wherein the initial hole stops at the first dielectric layer; Depositing a conductive layer in the initial hole, removing the conductive layer on the first dielectric layer at the bottom of the initial hole, and retaining at least the conductive layer in contact with the second conductive layer and the second dielectric layer as a first contact layer; Etching the first dielectric layer downward in the initial hole to form a via hole penetrating the second dielectric layer, the second conductive layer, and the first dielectric layer; depositing a semiconductor layer in the via hole, wherein the semiconductor layer covers the first contact layer, the first dielectric layer and the first conductive layer; The semiconductor layer contacts the first contact layer and is electrically connected to the first conductive layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: After depositing the semiconductor layer in the via hole, the method further includes: A first gate dielectric layer and a gate are deposited in the via hole.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming a patterned first conductive layer on the substrate and before forming a first dielectric layer covering the first conductive layer on the substrate, the method further includes: Depositing a second contact layer on a side of the first conductive layer away from the substrate; And, depositing a semiconductor layer in the via hole, comprising: A semiconductor layer is deposited in the via hole, where the semiconductor layer covers and contacts the first contact layer, the first dielectric layer and the second contact layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The initial hole stops at the first dielectric layer, which includes: the initial hole stops at the upper surface of the first dielectric layer.
5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor layer is a metal oxide semiconductor layer; The material of the first contact layer includes a metal oxide or a metal nitride of at least one of indium, tin, zinc, and titanium; and / or The material of the second contact layer includes metal oxide or metal nitride of at least one of indium, tin, zinc, and titanium.
6. A semiconductor device, characterized in that: include: A first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially stacked on the substrate; a via hole passing through the second dielectric layer, the second conductive layer, and the first dielectric layer, and stopping at the first conductive layer; a first contact layer located in the via hole and extending along the sidewall of the via hole, from the second dielectric layer through the area of the second conductive layer exposed in the via hole and stopping at the first dielectric layer, the first contact layer being in contact with the second conductive layer; It also includes a semiconductor layer; the semiconductor layer is located in the via hole and is connected to the first contact layer, the first dielectric layer and the first conductive layer; The semiconductor layer contacts regions of the first contact layer exposed in the via holes.
7. The semiconductor device according to claim 6, wherein: In a cross section parallel to the substrate, the first contact layer has a ring shape.
8. The semiconductor device according to claim 6, wherein: It also includes a second contact layer; the second contact layer is arranged on the first conductive layer, and the second contact layer contacts the semiconductor layer in the area exposed at the bottom of the via hole.
9. The semiconductor device according to claim 6, wherein: The thickness of the first dielectric layer is equal to the channel length of the semiconductor device.
10. The semiconductor device according to claim 6, wherein The first contact layer extends along the sidewall of the via hole toward the substrate and does not extend beyond the first dielectric layer.
11. The semiconductor device according to any one of claims 6 to 10, wherein: The semiconductor layer is a metal oxide semiconductor layer; The material of the first contact layer includes a metal oxide or a metal nitride of at least one of indium, tin, zinc, and titanium; and / or The material of the second contact layer includes metal oxide or metal nitride of at least one of indium, tin, zinc, and titanium.
12. An electronic device, characterized in that: The semiconductor device comprises any one of claims 6 to 11.