Method for improving thermal stability of nickel-based silicide in semiconductor device

Abstract

The invention relates to a method for improving the thermal stability of nickel-based silicide in a semiconductor device, which comprises the following steps of: forming contact holes corresponding to source and drain regions, and carrying out source and drain doping; removing the oxide layer on the surface of the source-drain region; depositing metal nitride and metal nickel in the contact hole; forming a nickel-based silicide by adopting a heat treatment process, and removing unreacted metal nickel; and depositing a metal laminated layer to fill the contact hole. According to the invention, a layer of ultrathin metal nitride is deposited on the metal / semiconductor interface of the semiconductor device, the difference between the lattice constant of the metal nitride and the lattice constant of nickel is large, the mismatch degree is high, and pressure stress is generated at the interface, so that diffusion of nickel atoms is hindered; and nitrogen atoms in the metal nitride can form chemical bonding with silicon, so that the surface energy of the silicon is reduced, and NiSi2 nucleation is inhibited. Nickel atom diffusion is inhibited through the synergistic effect of a stress field and chemical bonding, and collaborative optimization of resistivity and thermal stability is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving the thermal stability of nickel-based silicide in semiconductor devices. Background Art

[0002] With the exponential increase in the integration density and performance requirements of semiconductor devices, the metal / semiconductor (metal-semiconductor) contact interface is facing the ultimate challenge of co-optimizing thermal-electrical performance. As the core material for source-drain contacts and gate metallization, nickel-based silicide (NiSi) dominates industry applications due to its ultra-low resistance characteristics and process compatibility, but its high-temperature thermal stability defects have become a "pain point" for large-scale mass production of advanced processes. In key processes such as high-temperature annealing, NiSi is prone to phase change to form high-resistance NiSi2, resulting in a surge in contact resistance and uncontrolled interface interdiffusion, which directly causes a surge in device leakage and a cliff-like drop in reliability. This contradiction is particularly acute in cutting-edge fields such as high-density three-dimensional integration and ultra-low power logic devices, forcing the industry to urgently overcome NiSi's high-temperature phase change suppression and interface thermal stability enhancement technology to break through the "thermal-electrical" performance limits of next-generation devices.

[0003] In view of this, the present invention is proposed. Summary of the Invention

[0004] The object of the present invention is to provide a method for improving the thermal stability of nickel-based silicide in semiconductor devices, which solves the problems raised by the above-mentioned background technology.

[0005] A first aspect of the present invention provides a method for improving the thermal stability of nickel-based silicide in a semiconductor device, comprising the following steps:

[0006] S1. forming contact holes corresponding to the source and drain regions, and performing source and drain doping;

[0007] S2, removing the oxide layer on the surface of the source and drain regions;

[0008] S3, depositing metal nitride and metal nickel in the contact hole;

[0009] S4, forming nickel-based silicide by a heat treatment process and removing unreacted metallic nickel;

[0010] S5. Deposit a metal stack to fill the contact holes.

[0011] Preferably, in step S2, the oxide layer on the surface of the source and drain regions is removed by a wet method, the solution used for the wet removal is HF solution or BOE solution, the processing time is 30 to 60 seconds, and the solution temperature is 20 to 30°C.

[0012] Preferably, in step S3, the metal nitride is any one or more of TaN, VN, WN, and TiAlN.

[0013] Preferably, in step S3, the deposition thickness of the metal nitride is 0-1 nm.

[0014] Preferably, in step S3, the deposition thickness of the metallic nickel is 3 to 5 nm.

[0015] Preferably, in step S4, the heat treatment process includes:

[0016] S41, the first step of annealing, the annealing temperature is 250 ~ 350 ° C, the time is 30 ~ 60 seconds, forming nickel-based silicide Ni2Si;

[0017] S42, the second step is annealing, the annealing temperature is 400-600°C, the time is 10-30s, and nickel-based silicide NiSi is formed.

[0018] Preferably, in step S4, SC1 solution is used to remove unreacted metallic nickel, the treatment time is 180 to 300 seconds, and the solution temperature is 40 to 60°C.

[0019] Preferably, in step S5, the metal stack is a Ti / TiN / AlCu stack.

[0020] Preferably, the Ti / TiN / AlCu stack includes at least three layers: the first layer is Ti with a thickness of 3 to 5 nm; the second layer is TiN with a thickness of 8 to 10 nm; and the third layer is AlCu with a thickness of 200 to 400 nm.

[0021] A second aspect of the present invention provides a semiconductor device manufactured using the above method.

[0022] Specifically, the semiconductor device includes: a substrate, with source and drain regions, a channel, a high-k / metal gate and an interlayer dielectric arranged above the substrate; the source and drain regions are located on both sides of the channel, and the upper surface of the source and drain regions has a nickel-based silicide prepared by the above method; sidewalls are provided between the high-k / metal gate and the source and drain regions; the interlayer dielectric is located above the source and drain regions and the high-k / metal gate; isolation structures are provided on both sides of the substrate, and device isolation can adopt any one of Mesa, STI and LOCOS technologies.

[0023] The present invention has at least the following beneficial effects:

[0024] The present invention deposits an ultrathin layer of metal nitride at the metal / semiconductor interface of a semiconductor device. Due to the significant lattice constant difference between the metal nitride and nickel, resulting in a high mismatch, compressive stress is generated at the interface, hindering the diffusion of nickel atoms. Furthermore, the nitrogen atoms in the metal nitride can chemically bond with silicon, reducing silicon's surface energy and inhibiting NiSi2 nucleation. This invention suppresses nickel atomic diffusion through the synergistic effect of stress field and chemical bonding, achieving a coordinated optimization of resistivity and thermal stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A schematic flow chart of a method for improving the thermal stability of nickel-based silicide in semiconductor devices provided by the present invention;

[0027] Figure 2 A schematic diagram of the structure after forming contact holes corresponding to the source and drain regions provided by the present invention;

[0028] Figure 3 This is a schematic diagram of the structure after source and drain doping provided by the present invention;

[0029] Figure 4 A schematic diagram of the structure after metal nitride and metal nickel are deposited in the contact hole provided by the present invention;

[0030] Figure 5 A schematic diagram of the structure of nickel-based silicide formed by a heat treatment process provided by the present invention;

[0031] Figure 6 A schematic diagram of the structure of removing unreacted metallic nickel provided by the present invention;

[0032] Figure 7 This is a schematic diagram of the structure after the contact hole is filled with deposited metal stacks provided by the present invention.

[0033] Explanation of the accompanying symbols: 1. substrate; 2. source and drain regions; 3. high-k / metal gate; 4. sidewall; 5. interlayer dielectric; 6. isolation structure; 7. contact hole; 8. metal nitride; 9. metal nickel; 10. nickel-based silicide; 11. metal stack. DETAILED DESCRIPTION

[0034] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0035] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular also includes the plural. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0036] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] Example

[0038] This embodiment provides a method for improving the thermal stability of nickel-based silicide in a semiconductor device, comprising the following steps:

[0039] S1. forming contact holes corresponding to the source and drain regions, and performing source and drain doping;

[0040] S2, removing the oxide layer on the surface of the source and drain regions;

[0041] S3, depositing metal nitride and metal nickel in the contact hole;

[0042] S4, forming nickel-based silicide by a heat treatment process and removing unreacted metallic nickel;

[0043] S5. Deposit a metal stack to fill the contact holes.

[0044] In this embodiment, in step S2, the oxide layer on the surface of the source and drain regions is removed by wet method. The solution used in the wet method is HF solution or BOE solution. The treatment time is 30-60 seconds and the solution temperature is 20-30°C.

[0045] In this embodiment, in step S3, the metal nitride is any one or more of TaN, VN, WN, and TiAlN.

[0046] In this embodiment, in step S3 , the deposition thickness of the metal nitride is 0-1 nm.

[0047] In this embodiment, in step S3 , the deposition thickness of the metal nickel is 3-5 nm.

[0048] In this embodiment, in step S4, the heat treatment process includes:

[0049] S41, the first step of annealing, the annealing temperature is 250 ~ 350 ° C, the time is 30 ~ 60 seconds, forming nickel-based silicide Ni2Si;

[0050] S42, the second step is annealing, the annealing temperature is 400-600°C, the time is 10-30s, and nickel-based silicide NiSi is formed.

[0051] In this embodiment, in step S4, SC1 solution is used to remove unreacted metallic nickel, the treatment time is 180-300 seconds, and the solution temperature is 40-60°C.

[0052] In this embodiment, in step S5 , the metal stack is a Ti / TiN / AlCu stack.

[0053] In this embodiment, the Ti / TiN / AlCu stack includes at least three layers: the first layer is Ti with a thickness of 3 to 5 nm; the second layer is TiN with a thickness of 8 to 10 nm; and the third layer is AlCu with a thickness of 200 to 400 nm.

[0054] like Figure 1 As shown, taking NMOS as an example, the preparation method of this embodiment is described in more detail with reference to the accompanying drawings:

[0055] For step S1, Figure 2 As shown, referring to the traditional NMOS device manufacturing process, a Si substrate 1 is provided to form a P well, and contact holes 7 corresponding to the source and drain regions 2 are formed by photolithography and etching processes.

[0056] Specifically, the material of the substrate 1 is not limited to Si, and other substrate materials such as SOI may also be selected.

[0057] like Figure 3 As shown, ion implantation forms n+ heavy doping in the P well, and P or As is implanted. Taking P as an example, the energy is 0.5-3keV and the dose is 1×10 15 cm -3 ~1×10 16 cm -3 In addition to ion implantation, the source and drain regions 2 may also be doped with P or As using an in-situ doping method.

[0058] In step S2, a wet method is used to remove the natural oxide layer on the surface of the source and drain regions 2 to ensure that there is no interference from oxygen elements at the interface. Specifically, the solution used for the wet removal is a diluted HF solution or a diluted BOE solution, the treatment time is 30 to 60 seconds, and the solution temperature is 25°C.

[0059] For step S3, Figure 4 As shown, an atomic layer deposition (ALD) process is used to sequentially deposit ultra-thin metal nitride 8 (such as TaN) and metal nickel 9 in situ in the contact hole 7 to ensure the continuity of the thin film deposition. The deposition thickness of the metal nitride 8 is 0 to 1 nm, and the deposition thickness of the metal nickel 9 is 3 to 5 nm. Before depositing the metal nickel 9, a layer of ultra-thin metal nitride 8 (such as TaN) with a high mismatch with the metal nickel 9 is first deposited. The lattice constant of TaN differs greatly from that of Ni, with a mismatch of about 20%, which generates compressive stress at the interface and hinders the diffusion of Ni atoms. Secondly, the N atoms in TaN form strong Ni-N-Si bonds with Si, reducing the surface energy of Si, inhibiting the nucleation of NiSi2, and achieving synergistic optimization of resistivity and thermal stability.

[0060] For step S4, Figure 5 As shown, a two-step rapid thermal processing (RTP) process is used to form a stable nickel-based silicide 10 . In this step, the metal nickel 9 only reacts with Si to form the nickel-based silicide 10 .

[0061] Specifically, the first annealing temperature is 250-350° C. and the time is 30-60 seconds to form nickel-based silicide Ni2Si; the second annealing temperature is 400-600° C. and the time is 10-30 seconds to form nickel-based silicide NiSi.

[0062] like Figure 6 As shown, SC1 solution (standard cleaning solution 1) is used to remove unreacted metallic nickel 9, the treatment time is 180-300 seconds, and the solution temperature is 40-60° C. SC1 solution only removes unreacted metallic nickel 9 and does not react with NiSi.

[0063] For step S5, Figure 7 As shown, a Ti / TiN / AlCu metal stack 11 is deposited to fill the contact hole 7 .

[0064] Specifically, the first layer is Ti with a thickness of 3 to 5 nm; the second layer is TiN with a thickness of 8 to 10 nm; and the third layer is AlCu with a thickness of 200 to 400 nm.

[0065] This embodiment also provides a semiconductor device, comprising: a substrate 1, with source and drain regions 2, a channel, a high-k / metal gate 3, and an interlayer dielectric 5 disposed above the substrate 1; the source and drain regions 2 are located on both sides of the channel, and the upper surface of the source and drain regions 2 has a nickel-based silicide prepared by the method of this embodiment; sidewalls 4 are disposed between the high-k / metal gate 3 and the source and drain regions 2; the interlayer dielectric 5 is located above the source and drain regions 2 and the high-k / metal gate 3; isolation structures 6 are disposed on both sides of the substrate, and device isolation can adopt any one of Mesa, STI, and LOCOS technologies.

[0066] Comparative Example

[0067] The difference between this comparative example and the embodiment is that in step S3, only metal nickel 9 is deposited, and no metal nitride 8 is deposited. The results show that high-resistance NiSi2 has begun to be generated after the second annealing step.

[0068] In summary, the present invention deposits an ultrathin layer of metal nitride at the metal / semiconductor interface of a semiconductor device. Due to the significant difference in lattice constant between the metal nitride and nickel, resulting in a high mismatch, compressive stress is generated at the interface, thereby hindering the diffusion of nickel atoms. Furthermore, the nitrogen atoms in the metal nitride can form chemical bonds with silicon, reducing silicon's surface energy and inhibiting NiSi2 nucleation. The present invention inhibits nickel atomic diffusion through the synergistic effect of stress field and chemical bonding, achieving synergistic optimization of resistivity and thermal stability, and possesses significant technological innovation and industrial application value.

[0069] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving the thermal stability of nickel-based silicide in semiconductor devices, characterized in that: The steps include: S1. forming contact holes corresponding to the source and drain regions, and performing source and drain doping; S2, removing the oxide layer on the surface of the source and drain regions; S3, depositing metal nitride and metal nickel in the contact hole; S4, forming nickel-based silicide by a heat treatment process and removing unreacted metallic nickel; S5. Deposit a metal stack to fill the contact holes.

2. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, wherein: In step S2, the oxide layer on the surface of the source and drain regions is removed by a wet method. The solution used in the wet removal is HF solution or BOE solution. The treatment time is 30 to 60 seconds and the solution temperature is 20 to 30°C.

3. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, wherein: In step S3, the metal nitride is any one or more of TaN, VN, WN, and TiAlN.

4. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, wherein: In step S3, the deposition thickness of the metal nitride is 0-1 nm.

5. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, wherein: In step S3, the deposition thickness of the metallic nickel is 3-5 nm.

6. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, characterized in that: In step S4, the heat treatment process includes: S41, the first step of annealing, the annealing temperature is 250 ~ 350 ° C, the time is 30 ~ 60 seconds, forming nickel-based silicide Ni2Si; S42, the second step is annealing, the annealing temperature is 400-600°C, the time is 10-30s, and nickel-based silicide NiSi is formed.

7. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, characterized in that: In step S4, SC1 solution is used to remove unreacted metallic nickel, the treatment time is 180-300 seconds, and the solution temperature is 40-60°C.

8. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 1, wherein: In step S5, the metal stack is a Ti / TiN / AlCu stack.

9. The method for improving the thermal stability of nickel-based silicide in semiconductor devices according to claim 8, characterized in that: The Ti / TiN / AlCu stack comprises at least three layers: the first layer is Ti with a thickness of 3 to 5 nm; the second layer is TiN with a thickness of 8 to 10 nm; and the third layer is AlCu with a thickness of 200 to 400 nm.

10. A semiconductor device, characterized in that: The method according to any one of claims 1 to 9 is used to prepare the product.

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