Semiconductor packaging structure for preventing underfill glue from overflowing and manufacturing method

Abstract

The invention discloses a semiconductor packaging structure for preventing underfill glue from overflowing and a manufacturing method. The semiconductor packaging structure comprises a packaging unit and a sealing ring wall, each packaging unit comprises a conductive composite structure, a chip electrically connected with the conductive composite structure, and a bottom filling glue layer for filling the bottom of the chip; the single semiconductor packaging structure is formed by cutting along a cutting channel of a packaging blank; the sealing ring wall is arranged in the edge area of the packaging unit in the circumferential direction of the cutting channel and located between the edge of the underfill layer and the cutting channel. The sealing ring wall is of a metal laminated structure formed through the patterning technology, and the sealing ring wall and the metal rewiring layer in the conductive composite structure are synchronously formed. According to the invention, the sealing ring wall is designed in the packaging structure, the underfill glue can be prevented from overflowing to the cutting channel while the RDL wiring density is not influenced, the chip is prevented from being mechanically damaged in the cutting process, the rigidity of the RDL intermediate layer can be improved, the warping is reduced, and the packaging reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a semiconductor packaging structure and a manufacturing method thereof for preventing underfill glue from overflowing. Background Art

[0002] In semiconductor fan-out packaging structures, underfill glue is commonly used in flip-chip structures, and its key function is to fill the gap between the chip and the RDL interposer. It can significantly enhance mechanical strength, effectively disperse stress, and prevent the package structure from cracking due to thermal expansion. However, during the underfill process, if the underfill glue overflows into the cutting area, the subsequent cutting process will face many difficult problems. When cutting the chip into single dies, the underfill glue will cause damage to the cutting knife, which not only increases the cost of tool replacement, but may also cause damage to the chip edge due to reduced cutting quality. Moreover, the debris of the overflowing glue can easily contaminate the chip surface or pads, thereby causing the electrical signal connection to fail, seriously damaging the reliability of the package.

[0003] To prevent underfill from overflowing onto the dicing lanes, existing package designs increase the distance between the dicing lanes and the underfill dispensing edge. While this strategy achieves its goals to a certain extent, it also creates new challenges. This design reduces the effective area for RDL routing, limiting increases in routing density. As chip packaging technology continues to evolve toward smaller sizes and higher densities, the limitations of this design become increasingly apparent, making it difficult to meet increasingly stringent package size and performance requirements, significantly hindering the further development of fan-out packaging technology. Summary of the Invention

[0004] In order to solve the above technical problems, the purpose of the present invention is to provide a semiconductor packaging structure and manufacturing method that prevents underfill glue from overflowing; the present invention designs a sealing ring wall in the packaging structure, which can prevent the underfill glue from overflowing to the cutting path without affecting the RDL wiring density, prevent the chip from being mechanically damaged during the cutting process, and improve the reliability of the packaging structure. At the same time, the design of the sealing ring wall can also increase the rigidity of the RDL interposer, reduce warping, and improve the reliability of the package.

[0005] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:

[0006] On one hand, the present invention provides a semiconductor packaging structure for preventing underfill glue from overflowing, comprising a packaging unit and a sealing ring wall;

[0007] The packaging unit includes a conductive composite structure, a chip electrically connected to the conductive composite structure, and an underfill layer for filling the bottom of the chip; a single semiconductor packaging structure is formed by cutting along the cutting path of the packaging blank;

[0008] The sealing ring wall is arranged at the edge area of ​​the packaging unit along the circumference of the cutting line and is located between the edge of the bottom filling layer and the cutting line;

[0009] The sealing ring wall is a metal stacking structure formed by a patterning process, and its bottom is formed synchronously with the metal redistribution layer in the conductive composite structure.

[0010] Furthermore, the height of the sealing ring wall is higher than the height of the underfill layer and lower than the height of the chip.

[0011] Furthermore, the distance between the sealing ring wall and the adjacent chip is 100-300 μm.

[0012] Furthermore, the distance between the chip and the side surface of the packaging unit close to the chip is 380-420 μm.

[0013] Furthermore, the width of the sealing ring wall is 30-50 μm.

[0014] Furthermore, the conductive composite structure includes a passivation layer, a metal redistribution layer, and a signal derivation structure electrically connected to the metal redistribution layer.

[0015] Furthermore, the packaging unit further includes a plastic packaging body plastic-sealed on one side of the chip.

[0016] Another aspect of the present invention provides a method for manufacturing a semiconductor packaging structure that prevents underfill glue overflow, comprising the following steps:

[0017] Step 1: providing a carrier wafer and coating a temporary bonding adhesive on the carrier wafer;

[0018] Step 2: forming a passivation layer and a metal redistribution layer on the temporary bonding adhesive by a patterning process, and simultaneously forming the bottom of the sealing ring wall by a patterning process when forming the metal redistribution layer;

[0019] Step 3: Continue to stack the metal structure on the bottom of the formed sealing ring wall to complete the production of the sealing ring wall with a certain height;

[0020] Step 4: flip the chip onto the metal redistribution layer, then fill the bottom of the chip with underfill and cure it;

[0021] Step 5: Using a plastic encapsulation process to encapsulate the structure formed in step 4 to form a plastic encapsulation body;

[0022] Step 6, removing the slide;

[0023] Step seven: forming a signal lead-out structure on the metal redistribution layer away from the chip.

[0024] Furthermore, in the above manufacturing method, the sealing ring wall is circumferentially arranged along the designed cutting path and is located between the edge of the bottom filling layer and the cutting path.

[0025] Furthermore, in the above-mentioned manufacturing method, the patterning process includes processes such as coating a passivation layer, exposure, development, electroplating, and etching.

[0026] The beneficial effects of the present invention are:

[0027] 1. Effectively prevent the bottom fill glue from overflowing into the cutting path

[0028] The present invention provides a sealing ring wall between the edge of the underfill glue layer and the cutting path. The sealing ring wall acts as a physical barrier to prevent the underfill glue from flowing and diffusing into the cutting path area under capillary action, thereby solving the overflow problem.

[0029] 2. Protect the cutting process and improve yield and reliability

[0030] Since overflow is effectively prevented, the cutting knife will not touch the hardened underfill glue during cutting, thereby avoiding damage to the cutting knife, reducing the cost of tool replacement, and avoiding chip edge cracking or damage caused by cutting glue, thereby improving the mechanical integrity of the single chip. At the same time, it prevents the underfill glue debris generated by cutting from contaminating the chip surface or pads, thereby avoiding the resulting electrical signal connection failure, and significantly improving the reliability of the package.

[0031] 3. Maintain / improve RDL routing density

[0032] Compared to existing methods that prevent flash by increasing the distance between the dicing lanes and the glue-dispensing margins (which sacrifices the RDL routing area), the seal ring wall structure of the present invention does not require additional active RDL routing area. The seal ring wall is located near the dicing lanes, has a relatively small width, and is fixed in position, essentially leaving no space for the core routing area. This enables higher-density RDL routing without increasing package size, meeting the miniaturization and high-integration requirements of advanced packaging.

[0033] 4. Enhance RDL interposer rigidity and reduce warpage

[0034] The sealing ring wall of the present invention is a metal stack structure formed simultaneously with the metal redistribution layer (RDL) through a patterning process. It can form a strong interface connection with the passivation layer and metal redistribution layer in the conductive composite structure. The sealing ring wall is arranged circumferentially along the designed cutting path, surrounding the edge area of ​​the packaging unit (the final single chip), forming a continuous, closed-loop metal frame structure with high strength and rigidity. Through its anchoring in the passivation layer of the conductive composite structure, it can effectively transfer and couple its own rigidity to the entire RDL interposer structure, thereby improving the rigidity of the metal redistribution layer, effectively resisting the stress generated during the packaging process (such as plastic sealing and temperature changes), and restraining the bending deformation tendency of the RDL layer. In particular, it suppresses the distortion and sag / warping of the edge area, significantly reducing the warping of the packaging structure.

[0035] 5. Good process compatibility and controllable manufacturing costs

[0036] The bottom of the sealing ring wall is formed simultaneously with the metal redistribution layer (RDL), utilizing existing graphic processes (photolithography, electroplating, etching, etc.) without the need for additional core lithography steps, reducing manufacturing costs and process complexity.

[0037] In summary, the present invention solves the core problem of underfill overflow contaminating the cutting lanes by introducing a metal sealing ring wall manufactured simultaneously with the RDL process at a critical location (between the underfill edge and the cutting lanes). Its technical effectiveness is not only reflected in its efficient prevention of overflow, protection of the cutting blade, and improved chip edge quality and electrical connection reliability, but more importantly, its advantage lies in not sacrificing valuable RDL wiring density, while also providing the significant benefits of enhanced structural rigidity and reduced warpage. This design fully utilizes existing processes, has good compatibility and cost-effectiveness, and provides an effective solution for the development of advanced packaging technologies such as fan-out towards higher density, smaller size, and higher reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic flow chart of the production method of the present invention.

[0039] Figure 2 FIG. 1 is a schematic diagram of a semiconductor package structure for preventing underfill glue overflow according to an embodiment of the present invention.

[0040] Figure 3 FIG. 1 is a partial structural diagram of a semiconductor package structure for preventing underfill glue overflow according to an embodiment of the present invention.

[0041] Figure 4 This is a partial structural schematic diagram of a package blank produced according to an embodiment of the present invention.

[0042] In the figure, 10: carrier, 20: temporary bonding glue, 30: passivation layer, 40: metal redistribution layer, 50: chip, 60: sealing ring wall, 70: bottom filling layer, 80: plastic package, 90: signal output structure, 100: cutting path. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0044] like Figure 2 and Figure 4 As shown, the present invention provides a semiconductor packaging structure for preventing underfill glue from overflowing, comprising a packaging unit and a sealing ring wall;

[0045] The packaging unit includes a conductive composite structure, a chip 50 electrically connected to the conductive composite structure, and an underfill layer 70 for filling the bottom of the chip 50. The single semiconductor packaging structure is formed by cutting along the cutting street 100 of the packaging blank.

[0046] The sealing ring wall 60 is disposed at the edge of the package unit along the circumference of the scribe line 100 and is located between the edge of the bottom fill layer 70 and the scribe line 100;

[0047] The sealing ring wall 60 is a metal stacked structure formed by a patterning process, and its bottom is formed simultaneously with the metal redistribution layer 40 in the conductive composite structure.

[0048] The height of the sealing ring wall 60 is higher than that of the underfill layer 70 and lower than that of the chip 50. The spacing between the sealing ring wall 60 and adjacent chips 50 is preferably 100-300 μm. The distance between the chip 50 and the side of the package unit adjacent to it is preferably 380-420 μm.

[0049] The width of the sealing ring wall 60 is preferably 30-50 μm.

[0050] Furthermore, the conductive composite structure includes a passivation layer 30, a metal redistribution layer 40, and a signal lead-out structure 90 electrically connected to the metal redistribution layer 40. The signal lead-out structure 90 is preferably a solder ball.

[0051] Furthermore, the packaging unit further includes a plastic packaging body 80 plastic-sealed on one side of the chip.

[0052] The method for manufacturing a semiconductor packaging structure for preventing underfill glue overflow comprises the following steps:

[0053] Step 1: providing a carrier wafer 10 and coating a temporary bonding adhesive 20 on the carrier wafer 10;

[0054] Step 2: forming a passivation layer 30 and a metal redistribution layer 40 on the temporary bonding adhesive 20 by a patterning process. When forming the metal redistribution layer 40, the bottom of the sealing ring wall 60 is simultaneously formed by a patterning process.

[0055] Step 3: Continue to stack the metal structure on the bottom of the formed sealing ring wall to complete the production of the sealing ring wall 60 with a certain height;

[0056] Step 4: flip-chip the chip 50 onto the metal redistribution layer 40, then fill the bottom of the chip 50 with underfill and cure it to form an underfill layer 70. The chip 50 may be a combination of multiple chips; for example, the chip may be a logic semiconductor device or a memory device. The logic semiconductor device may be selected from a central processing unit (CPU), a graphics processing unit (GPU), an integrated circuit chip (ASIC), or a system-on-chip (SOC); and the memory device may be selected from a high-bandwidth memory (HBM) chip.

[0057] Step 5: Using a plastic encapsulation process to encapsulate the structure formed in step 4 to form a plastic encapsulation body 80;

[0058] Step 6, removing the slide 10;

[0059] Step seven: forming a signal output structure 90 on the metal redistribution layer 40 away from the chip 50 .

[0060] In the above manufacturing method, the sealing ring wall 60 is circumferentially arranged along the designed scribe line 100 and is located between the edge of the underfill layer 70 and the scribe line 100 .

[0061] In the above-mentioned manufacturing method, the patterning process includes processes such as coating a passivation layer, exposure, development, electroplating, and etching.

[0062] The present invention will be further described below through specific examples.

[0063] The method for manufacturing a semiconductor package structure for preventing underfill glue overflow in this embodiment includes the following steps:

[0064] S1, coating a layer of temporary bonding glue 20 on the carrier wafer 10.

[0065] S2, RDL wiring is performed on the upper surface of the temporary bonding glue 20 and the bottom of the sealing ring wall is produced; the specific process of RDL is: a passivation layer 30 is coated on the upper surface of the temporary bonding glue 20, usually using photoresist or other suitable materials; the passivation layer 30 is exposed and developed through photolithography technology to form a conductive via opening; a baking process is performed to solidify the passivation layer and improve its stability; a seed layer is sputtered on the passivation layer 30, the thickness of the seed layer is generally 0.1-0.5 microns, and the material is usually a combination of Ti (titanium) and Cu (copper); the function of the seed layer is to provide a conductive path for the subsequent electroplating process; a layer of process glue (usually photoresist) is coated on the seed layer; a circuit opening is formed by exposing and developing the process glue; a baking process is performed again to solidify the process glue and improve its stability; metal is plated at the circuit opening through the electroplating process to form a metal redistribution layer 40; the process glue is removed; the excess seed layer is removed through the etching process, leaving the required metal redistribution layer 40.

[0066] The bottom of the seal ring wall is fabricated using a similar process to the RDL process, using a patterning process and forming simultaneously with the metal redistribution layer. The difference is that the seal ring wall is not a via structure. The seal ring wall 60 is arranged circumferentially along the designed scribe line (maintaining a certain distance from the inner side of the scribe line) and is made of copper. The bottom of the resulting seal ring wall 60 is embedded in the passivation layer 30.

[0067] S3. Repeat the patterning process and continue to stack the metal structure on the bottom of the sealing ring wall 60 to complete the production of the sealing ring wall 60 with a certain height.

[0068] S4. Two chips 50 are flip-chip mounted on the surface of the metal redistribution layer 40. Underfill glue is dispensed and cured on the bottom of the two chips 50 to form an underfill layer 70. During the underfill process, the sealing ring wall 60 forms a dam structure to prevent the underfill glue from overflowing.

[0069] The spacing L between the sealing ring wall 60 and the adjacent chip 50 can be 100-300 μm. The heights of the two chips 50 can be the same or different. The height of the sealing ring wall 60 is higher than the height of the underfill layer 70 and lower than the height of the chip 50 (the tallest chip). Preferably, the height of the chip 50 can be 700-900 μm. The height H of the sealing ring wall 60 can be 400-500 μm. The width W of the sealing ring wall 60 can be 30-50 μm.

[0070] S5. The structure formed after step S4 is encapsulated using a molding process to form a molded body 80. Specifically, a molding compound is applied to the surface of the structure and then solidified by closing the mold. The molding compound used is a liquid molding compound or a powdered molding compound. The upper surface of the molding compound is ground to expose the surface of the chip 50, which facilitates heat dissipation of the package structure.

[0071] S6. Debonding the carrier 10. The debonding method may be laser debonding, thermal release, chemical release, mechanical release, etc. After debonding, the temporary bonding glue is cleaned with a cleaning solution.

[0072] S7. Solder balls are formed on the side of the metal redistribution layer 40 of the structure formed in step S6, away from the chip 50, by electroplating, ball planting, or solder paste printing to form a signal output structure 90, thereby obtaining a package blank. Individual semiconductor package structures are obtained by cutting the package blank.

[0073] The semiconductor package structure obtained by the manufacturing method of this embodiment includes a package unit and a sealing ring wall; the package unit includes a passivation layer 30, a metal redistribution layer 40, a signal output structure (solder ball) 90 electrically connected to the metal redistribution layer 40, a chip 50 electrically connected to the metal redistribution layer 40, an underfill layer 70 filling the bottom of the chip 50, and a plastic package body 80 disposed on one side of the chip 50. The single semiconductor package structure is formed by cutting along the cutting line of the package blank; the sealing ring wall 60 is circumferentially arranged at the edge area of ​​the package unit along the cutting line 100 and is located between the edge of the underfill layer 70 and the cutting line 100; the sealing ring wall 60 is a metal stack structure formed by a patterning process, and its bottom is formed simultaneously with the metal redistribution layer 40 in the conductive composite structure.

[0074] A single semiconductor package structure has four sides and an overall rectangular shape. Chip 50 is separated from adjacent package unit sides by a predetermined distance. To prevent underfill overflow, this distance is typically 800μm-1500μm in the prior art. In embodiments of the present invention, the design of seal ring wall 60 reduces this distance to approximately 400μm, preventing underfill overflow onto dicing lanes 100 and increasing the effective area for RDL routing.

[0075] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

[0076] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A semiconductor packaging structure for preventing underfill glue overflow, characterized in that: including packaging unit and sealing ring wall; The packaging unit includes a conductive composite structure, a chip electrically connected to the conductive composite structure, and an underfill layer for filling the bottom of the chip; a single semiconductor packaging structure is formed by cutting along the cutting path of the packaging blank; The sealing ring wall is arranged at the edge area of ​​the packaging unit along the circumference of the cutting line and is located between the edge of the bottom filling layer and the cutting line; The sealing ring wall is a metal stacking structure formed by a patterning process, and its bottom is formed synchronously with the metal redistribution layer in the conductive composite structure.

2. The semiconductor packaging structure for preventing underfill glue overflow according to claim 1, wherein: The height of the sealing ring wall is higher than that of the bottom filling layer and lower than that of the chip.

3. The semiconductor packaging structure for preventing underfill glue overflow according to claim 1, wherein: The distance between the sealing ring wall and the adjacent chip is 100-300 μm.

4. The semiconductor packaging structure for preventing underfill glue overflow according to claim 1, wherein: The distance between the chip and the side surface of the package unit close to the chip is 380-420 μm.

5. The semiconductor packaging structure for preventing underfill glue overflow according to claim 1, wherein: The width of the sealing ring wall is 30-50 μm.

6. The semiconductor packaging structure for preventing underfill glue overflow according to claim 1, wherein: The conductive composite structure includes a passivation layer, a metal redistribution layer, and a signal derivation structure electrically connected to the metal redistribution layer.

7. The semiconductor packaging structure for preventing underfill glue overflow according to claim 1, wherein: The packaging unit further includes a plastic packaging body that is plastic-sealed on one side of the chip.

8. A method for manufacturing a semiconductor packaging structure for preventing underfill glue overflow, characterized in that: The steps include: Step 1: providing a carrier wafer and coating a temporary bonding adhesive on the carrier wafer; Step 2: forming a passivation layer and a metal redistribution layer on the temporary bonding adhesive by a patterning process, and simultaneously forming the bottom of the sealing ring wall by a patterning process when forming the metal redistribution layer; Step 3: Continue to stack the metal structure on the bottom of the formed sealing ring wall to complete the production of the sealing ring wall with a certain height; Step 4: flip-chip the chip onto the metal redistribution layer, then fill the bottom of the chip with underfill and cure it to form an underfill layer; Step 5: Using a plastic encapsulation process to encapsulate the structure formed in step 4 to form a plastic encapsulation body; Step 6, removing the slide; Step seven: forming a signal lead-out structure on the metal redistribution layer away from the chip.

9. The method for manufacturing a semiconductor packaging structure for preventing underfill glue overflow according to claim 8, wherein: The sealing ring wall is circumferentially arranged along the designed cutting path and is located between the edge of the bottom filling layer and the cutting path.

10. The method for manufacturing a semiconductor packaging structure for preventing underfill glue overflow according to claim 8, wherein: The patterning process includes coating a passivation layer, exposure, development, electroplating, and etching.

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