3D die stack redistribution layer for top side power transfer to backside die metallization in multi-chip composite devices

Abstract

The present disclosure relates to a 3D die stack redistribution layer for top side power transfer to backside die metallization in a multi-chip composite device. Microelectronic devices, assemblies, and systems include a multi-chip architecture having one or more integrated circuit dies over and bonded to a base die, and a metallization network over the integrated circuit die (s). A backside metallization of the integrated circuit die (s) is proximate to the metallization network, and a front side metallization of the integrated circuit die (s) is on an opposite side of the device layer from the backside metallization. A via transverse to the base die is coupled to the metallization network to provide electrical routing to the backside metallization of the integrated circuit die through the via and the metallization network.

Description

Background Art

[0001] Higher performance, lower cost, greater miniaturization, greater packaging density, and increased product flexibility in integrated circuit devices are ongoing goals for the electronics industry. Notably, heterogeneous integrated semiconductor devices are experiencing increasing power and computing bandwidth requirements. Data center central processing units (CPUs) and graphics processing units (GPUs) are expected to exceed 1000W in power consumption, and the demand for increased computing performance will require increased bandwidth and input / output (IO) routing challenges.

[0002] Current packaging architectures may not be able to meet future demands for CPU and GPU power and IO. These and other considerations necessitate the current improvements. As the desire for increased performance in computing devices and the corresponding need to remove heat from these devices become more prevalent, such improvements may become crucial. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The materials described herein are shown in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity.

[0004] Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. In the drawings:

[0005] Figure 1 shows a cross-sectional side view of a multi-chip composite device including a top-side metallization network to provide power routing to the back side of an integrated circuit die;

[0006] Figure 2 shows a cross-sectional side view of electrical routing in a multi-chip composite device;

[0007] Figure 3 Shown Figure 1 an enlarged cross-sectional side view of a region of a multi-chip composite device;

[0008] Figure 4 shows another enlarged cross-sectional side view of a multi-chip composite device having an inverted base die;

[0009] Figure 5 a cross-sectional side view of the IC die showing further details of the display device layers, front side metallization, and back side metallization;

[0010] Figure 6 shows a cross-sectional side view of a metallized die showing further detail of the metallization network;

[0011] Figure 7 shows a cross-sectional side view of electrical routing in a multi-chip composite device;

[0012] Figure 8 shows a cross-sectional side view of electrical routing in a multi-chip composite device having multiple integrated circuit dies;

[0013] Figure 9 shows a cross-sectional side view of electrical routing in a multi-chip composite device having multiple base dies;

[0014] Figure 10 shows a cross-sectional side view of a multi-chip composite device including a top-side metallization network made of one or more directly applied metallization levels to provide power routing to the back side of an integrated circuit die;

[0015] Figure 11 shows a cross-sectional side view of a multi-chip composite device including a second integrated circuit die level on a top-side metallization network;

[0016] Figure 12 showing a cross-sectional side view of a multi-chip composite device with components within the thickness of a top-side metallization network;

[0017] Figure 13 shows a cross-sectional side view of a multi-chip composite device having a bond wire top-side metallization network;

[0018] Figure 14 is a flow chart illustrating a method for forming a multi-chip composite device including a top-side metallization network to provide power routing to the back side of an integrated circuit die;

[0019] Figure 15 、 16 , 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 and 30 are as practice Figure 14 A cross-sectional side view of an integrated circuit (IC) device structure evolved by a method;

[0020] Figure 31 An example microelectronic device assembly is shown that includes a multi-chip composite device having a top-side metallization network to provide power routing to the back side of an integrated circuit die;

[0021] Figure 32 An exemplary system employing an IC assembly including a multi-chip composite device having a top-side metallization network to provide power routing to the back side of the integrated circuit die is shown; and

[0022] Figure 33is a functional block diagram of an electronic computing device, generally in accordance with some embodiments. DETAILED DESCRIPTION

[0023] One or more embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this specification. It will be apparent to those skilled in the art that the techniques and / or arrangements described herein can be used in a variety of other systems and applications in addition to the systems and applications described in detail herein.

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized and that structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used only to facilitate the description of features in the accompanying drawings. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

[0025] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some cases, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the present invention. Throughout this specification, reference to an "embodiment" or "one embodiment" means that the particular features, structures, functions, or characteristics described in conjunction with that embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in an embodiment" or "in one embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the present invention. Furthermore, in one or more embodiments, the particular features, structures, functions, or characteristics may be combined in any suitable manner. For example, the first embodiment may be combined with the second embodiment as long as the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0026] As used in the description of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0027] The terms "coupled" and "connected" and their derivatives may be used to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intervening elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a cause-and-effect relationship).

[0028] As used herein, the terms "above," "below," "between," "on," and the like refer to the relative position of one layer of material or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with both layers, or may have one or more intervening layers. In contrast, a first layer that is "above" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening features. The term "immediately adjacent" indicates that such features are in direct contact. Additionally, the terms "substantially," "close," "approximately," "near," and "approximately" generally refer to within + / - 10% of a target value.

[0029] The term "layer" and similar terms used herein (such as metallization or dielectric) can include a single material or multiple materials or a single component or multiple components. The term metallization generally refers to the metal layer (including metal lines or traces and vias) that provides routing for power, ground, I / O, etc. The metal layer is typically patterned to form metal structures, such as traces and vias. The metallization structures are separated by dielectric materials, or simply dielectrics, which generally refer to any number of non-conductive materials. As used in this specification and claims, a list of items connected by the term "at least one of" or "one or more of" can mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. The terms "lateral," "laterally adjacent," and similar terms indicate that two or more components are arranged along a plane that is orthogonal to the vertical direction of the overall structure. The terms "perpendicular," "vertically aligned," and similar terms indicate that two or more components are aligned along a vertical direction, typically in the build direction of the device structure. As used herein, the term "predominantly" means the predominant component (i.e., greater than 50% being the largest component in a layer or material). The term "substantially pure" means a component that is not less than 99% of the material. The term "pure" means a component that is not less than 99.5% of the material, while the term "completely pure" means a component that is not less than 99.9% of the material. As used herein, the terms "monolithic," "monolithically integrated," and similar terms mean that the components of a monolithic, unitary structure form an inseparable whole that cannot be reasonably separated.

[0030] As discussed, heterogeneous integrated semiconductor devices are expanding in both power and computational bandwidth requirements. Advanced packaging architectures will continue to evolve to meet these demands. Notably, in integrated circuit (IC) devices, front-side and back-side metallization have been introduced. In such an IC die, the device layer (e.g., the layer including the transistors) is located between a set of front-side metallization layers and a set of back-side metallization layers. By including back-side metallization layers in addition to the traditional front-side metallization layers, various advantages can be obtained. For example, power can be supplied from the back side, which frees up the front-side metallization layers for additional IO wiring. By routing around the base die, vias can be removed from the base die to reduce the base die size or provide additional computing on the base die. In addition, the back-side metallization can be thicker and have more direct routing to the device layers, which provides less power loss and other advantages. For example, the introduction of front-side and back-side metallization improves end-to-end power efficiency, eliminates routing constraints to allow for increased IO routing and computing area per square millimeter, and provides other advantages.

[0031] In current 3D packaging architectures, an interposer or base die (s) can be mounted to a package substrate, and a compute die can be mounted above the interposer or base die (s). In this architecture, both power and IO are provided to the second-level die (e.g., the compute die) through the interposer or base die (s). This results in base die area and IO routing limitations, which in turn limits total power delivery and end-to-end power efficiency. Power delivery can be improved by distributing package voltage regulators and improving the interconnect system, but IO and power routing limitations and other difficulties remain.

[0032] In some embodiments, the power routing from the package substrate through the base die to the second-level die (e.g., the compute die) is eliminated. The structures and architectures discussed herein route power (and optional IO) routing to a thick metal redistribution layer on top of the second-level die (e.g., the compute die). Power can be connected to the thick metal redistribution layer via distributed voltage regulator (VR) routing, power can be connected directly to the thick metal redistribution layer, or power can be delivered to the thick metal redistribution layer on top of the second-level die (e.g., the compute die) via alternative power delivery network components. Other routing to the thick metal redistribution layer can be used. This architecture utilizes the IC die discussed above, which includes a front-side metallization layer and a back-side metallization layer, such that the front-side metallization layer is adjacent to the interposer or base die(s), and the back-side metallization layer (located on the side of the device layer opposite the front-side metallization layer) is located on top of the second-level die (e.g., the compute die). Such a structure and architecture provides an efficient interface between the second-level die (e.g., the compute die) and the overall system. For example, the top-side power architecture and routing discussed herein reduces IR drop due to reduced routing length, eliminates via and routing constraints through the base die(s), reduces base die area requirements (e.g., due to the removal of vias and voltage regulators for power delivery), thereby reducing die size to reduce cost, and allows the addition of additional intellectual property modules (IP) to be moved to the base die(s), freeing up compute area for increased cores / compute blocks and efficiency. Other advantages will be apparent based on the following disclosure.

[0033] In some embodiments, the microelectronic device includes a multi-chip composite architecture that includes a base die and one or more integrated circuit (IC) dies attached to the base die. As used herein, the term "microelectronic device" means a device that includes one or more integrated circuits to provide one or more functions. The microelectronic device can be at any level, such as a packaged device, a component, an assembled motherboard, or a consumer product. The term "multi-chip composite device" means a device with multiple chips or dies that are integrated and form a quasi-monolithic structure. For example, a quasi-monolithic structure can have a quasi-monolithic hierarchical integration of IC dies that couples the base die, IC die, or chiplet to form a composite structure of a processing system. It is worth noting that the term "composite" means that the structure has multiple components, such as active dies, and dielectric materials on and between the active dies. As used herein, the terms "base die," "IC die," and "chiplet" mean a die or chip that is passive or has active circuits (i.e., circuits that provide electronic or device functions when in operation). For example, base die, IC die, and chiplets may include processor circuitry, memory circuitry, control circuitry, signal and power routing circuitry, etc. The term "IC die" may be used as an umbrella term, with the term "base die" referring to an IC die deployed as the bottom or foundational layer die of a multi-chip composite device. The term "chiplet" may be deployed to refer to the top or middle-level IC die of a multi-chip composite device, although these dies may be referred to simply as IC dies.

[0034] It is noteworthy that the base die may or may not include functional circuitry (and may include only integrated metallization wiring), while one or more advanced IC dies typically include functional circuitry. Such an IC die may include a device layer between the front and back metallization portions of the IC die. In some embodiments, a multi-chip composite device or architecture includes an IC die located above and coupled to the base die. The IC die has a device layer between a first and a second metallization layer stack, such that the first metallization layer stack is close to the base die. The first metallization layer stack is used to provide signal wiring to the device layer as received by the base die. The second metallization layer stack is used to provide power wiring (e.g., power and ground wiring) to the device layer, and the second stack typically has thicker and fewer metal lines for these purposes, as discussed further below.

[0035] The multi-chip composite device or architecture also includes a metallization network above the IC die and coupled to the second metallization layer stack. The metallization network includes one or more thick metallization layers (e.g., each metallization layer has a thickness that is not less than five times or ten times or more than the thickness of either the first or second metallization layer stack). Vias are adjacent to the base die and coupled to the metallization network and external interconnects to provide power routing for the second metallization layer stack on the top side of the IC die. The power routing may include external interconnects, vias, and a portion of the metallization network. The metallization network may be formed using any of the techniques discussed below.

[0036] In addition, the multi-chip composite device may include one or more dielectric materials that are laterally adjacent to one or more IC dies or chiplets over the area of ​​the base die, and / or laterally adjacent to the base die. For example, the dielectric material may be formed over or around the die to embed some or all of the die in the dielectric material. In some embodiments, the dielectric material includes one or more inorganic dielectric materials. As used herein, the term "inorganic dielectric material" refers to a material that does not have carbon-hydrogen bonds and is characterized as an electrical insulator. For example, the inorganic dielectric material may have a resistivity comparable to that of silicon dioxide. Although carbon may not be an essential component of the inorganic dielectric material, the inorganic dielectric material may include carbon, for example as a dopant. In some embodiments, the dielectric material includes one or more organic dielectric materials. As used herein, the term "organic dielectric material" refers to a material that has carbon-hydrogen bonds and carbon chains, and the material is characterized as an electrical insulator.

[0037] Figure 1 1 shows a cross-sectional side view of a multi-chip composite device 100 including a top-side metallization network 107 to provide power routing to the back side 119 of the integrated circuit die 101, arranged in accordance with some embodiments. Figure 3 Region 130 of the multi-chip composite device 100 is shown in more detail in . For example, the multi-chip composite device 100 can be deployed in any microelectronic device. The multi-chip composite device 100 can include any number of IC dies 101 (which can be characterized as chiplets) coupled to the top side surfaces of any number of base dies 102. In addition, the multi-chip composite device 100 can include any number of chiplets or components on the sides of the IC die 101 and / or base die 102, such as a voltage regulator (VR) die 103. Although described with respect to the VR die 103, where the VR die 103 can be a voltage regulator and / or power delivery network based on a silicon substrate, the multi-chip composite device 100 can omit the VR die 103 and use direct pass-through power delivery. In Figure 2In the example shown, two levels of dies are shown, but the multi-chip composite device 100 may include any number of levels of dies, such as three or more levels of dies.

[0038] The base die 102 includes through-hole vias 125 (e.g., through-silicon vias, TSVs). As discussed, the terms "IC die" and "chiplet" refer to active circuit devices (i.e., circuits that provide computing functionality when in operation). For example, an IC die or chiplet may contain circuits that perform a defined subset of functions, such as a memory chip, a microprocessor, a microcontroller, a commodity IC (e.g., a chip used for repetitive processing routines, simple tasks, application-specific ICs, etc.). The term "base die" also refers to an active circuit device and may also be characterized as an IC die. For example, IC dies such as chiplets and base dies may be individual dies that are connected to create the functionality of a monolithic IC. As shown, the base die 102 is located at the lowest or base layer of the multi-chip composite device 100. In addition, the base die 102 may be interconnected to the microelectronic substrate 104 via interconnect 111. For example, the interconnect 111 may be a package-level interconnect to couple to the microelectronic substrate 104, such as a package substrate, board, or motherboard. The interconnection 111 may be an interconnection pillar or pad, a solder bump or ball, an interconnection formed of a conductive film or conductive paste, or the like.

[0039] IC die 101 can be bonded to one or more base dies 102 using any suitable technique or techniques, such as hybrid bonding, to form die-level interconnect 112. In some embodiments, surfaces including metallization can be interspersed between dielectric materials formed on IC die 101 and each of the one or more base dies 102. In some embodiments, these surfaces are patterned to match metal to metal and dielectric to dielectric for hybrid bonding. These surfaces can then be brought together, optionally under pressure and / or heat, to fuse the metal to form die-level interconnect 112 and optionally fuse the dielectric material to form hybrid bonding. As shown relative to the enlarged view, in some embodiments, die-level interconnect 112 can include a misalignment 117 indicative of hybrid bonding. Misalignment 117 can include, for example, a misalignment between first sidewall 114 and second sidewall 116 such that a lateral offset 115 (i.e., measured in the x-dimension) is located therebetween. In some embodiments, lateral offset 113 is in the range of 10 to 200 nm. While any thickness may be used, in some embodiments, base die(s) 102 and IC die(s) 101 may have a thickness between 20 and 150 microns, and IC die 102 may have a thickness between 20 and 50 microns. Although hybrid bond interconnects are shown with respect to die-level interconnects 112, any interconnects may be deployed, such as solder balls or solder features.

[0040] As shown in more detail below, IC die 101 has a backside 119 and a frontside 120. These terms are used in accordance with generally accepted practices in the art and represent the build orientation of IC die 101 during fabrication. It is important to note that, in the context of a multi-chip composite device 100 or other structured assembly, the terms "frontside" and "backside" can be oriented with either side facing upward. For example, a device layer can be formed above a substrate on the frontside, with the frontside metallization located on or above the device layer. Accordingly, the backside is located on the side of the device layer opposite the frontside. The device layers of the IC die(s) 101 and / or base die(s) 102 can include any suitable devices, such as transistors, capacitors, resistors, and the like. The backside metallization can be formed on the opposite side of the frontside metallization relative to the device layer using any suitable technique or techniques, such as attachment to a carrier wafer, backside grinding to expose the device layer (and buried through vias), and metallization fabrication processes (dual damascene processes, etc.), as known in the art. In the context of the multi-chip composite device 100 , the metallized die 106 includes a substrate 108 and a metallization network 107 .

[0041] The metallization network 107 can be constructed on the substrate 108, and the metallization network 107 can include any number of relatively thick metallization levels 131 (including metal lines or wiring), such that the metallization levels 131 are interconnected by via levels 132 (e.g., via layers). The metallization levels 131 are thick relative to the metal layers of the front side metallization and the back side metallization of the IC die 101. For example, each metallization level 131 can have a thickness that is not less than five times the thickness of any metal layer of the front side metallization and the back side metallization of the IC die 101. In some embodiments, the metallization network 107 can be characterized as a redistribution layer, and the metallization die 106 can be characterized as a redistribution die or substrate. Although three metallization levels 131 are shown, the metallization network 107 can include any number of metallization levels, such as a single metal layer 131, two metallization levels 131, four metallization levels 131, or more metallization levels 131. In some embodiments, the metallization network 107 includes a plurality of metallization levels 131 formed on the substrate 108 and coupled to the IC die 101 and / or the VR die 103 via interconnects 109. Although solder balls or solder features are shown with respect to the interconnects 109, any interconnect, such as a hybrid bond interconnect, may be used. In some embodiments, the metallization network 107 includes a plurality of wire bonds or bond wires formed between the IC die 101 and / or the VR die 103. In some embodiments, the metallization network 107 includes a plurality of thick metal layers fabricated directly on or over the IC die 101 and / or the VR die 103.

[0042] As shown, the metallization network 107 is coupled to the microelectronic substrate 104 through one or more vias 110, which can be embedded in an inorganic dielectric material 128. The inorganic dielectric material 128 can be any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, etc. For example, the via 110 can be characterized as a through-dielectric via (TDV) or a pillar such as a copper pillar. The (multiple) vias 110 are laterally adjacent to the base die 102 and are coupled to the interconnect 111 for electrical attachment to the microelectronic substrate 104. As used herein, the term "laterally adjacent" means that at least a portion of the component is aligned in the xy plane (i.e., orthogonal to the vertical build direction in question). The (multiple) vias 110 can be made of any suitable one or more conductive materials, such as copper, silver, nickel, gold, and aluminum, alloys thereof, etc. In the context of the multi-chip composite device 100, relevant ones of the interconnects 111, the via(s) 110, the VR die(s) 103 (if deployed), and the metallization network 107 provide power routing (and optional IO routing) to the backside 119 of the IC die(s) 101, while relevant ones of the interconnects 111 and the base die(s) 102 provide IO routing to the frontside 120. As used herein, power refers to the power supply (and includes power and ground) used to operate the device, while IO refers to the signals required to operate the device.

[0043] The IC die(s) 101, base die(s) 102, and metallization die(s) 106 can include any suitable substrate and associated device components. In some embodiments, the IC die(s) 101 and / or base die(s) 102 are semiconductor dies having device layers and metallization layers fabricated using known semiconductor fabrication processes. In some embodiments, the substrate of any of the IC die(s) 101, base die(s) 102, and metallization die(s) 106 is a substantially single-crystalline semiconductor, such as silicon or germanium, although other material systems may be employed. In some embodiments, the substrate 108 of the metallization die(s) 106 is a silicon substrate, and the substrate 108 acts as a heat sink to remove heat from the IC die(s) 101. For example, the substrate 108 and / or the metallization network 107 can act as a heat sink to remove heat from the IC die(s) 101. In some embodiments, the substrate 108 is or includes a material that facilitates heat removal. In some embodiments, substrate 108 is or includes silicon, aluminum nitride, aluminum, copper, or other thermally conductive materials. In this case, substrate 108 can be characterized as a passive integrated heat sink. In some embodiments, metallization network 107 can be fabricated on an active heat removal device, such as a heat pipe, thermoelectric cooler, etc. In this case, the underlying device (on which metallization network 107 is fabricated) can be characterized as an active integrated heat sink.

[0044] In some embodiments, substrate 108 is a glass substrate. The glass substrate can have any suitable properties. In some embodiments, the glass substrate is or includes a glass layer (e.g., a glass core). In some embodiments, the glass substrate is an amorphous solid glass layer. In some embodiments, the glass substrate is or includes a glass layer, for example, the glass layer is one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and fused silica. The glass layer may include one or more additives, including Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, P2O3, ZrO2, Li2O, Ti, or Zn. For example, the glass layer may include an additive including one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, the glass layer may include silicon and oxygen and one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer comprises at least 23% silicon and at least 26% oxygen (by weight), and also comprises at least 5% aluminum (by weight). In some embodiments, the glass layer is rectangular in plan view. However, other shapes may be used. In some embodiments, the glass substrate does not contain any organic binder or other organic material.

[0045] As shown, the base die(s) 102 are coupled to the microelectronic substrate 104 via interconnects 111. The microelectronic substrate 104 can be any suitable structure or carrier. In some embodiments, the microelectronic substrate 104 includes a dielectric material layer, which can include a build-up film and / or a solder mask layer, and can be composed of any suitable dielectric material, including but not limited to bismaleimide triazine resin, flame retardant Class 4 material, polyimide material, silica-filled epoxy material, glass-reinforced epoxy material, low-temperature co-fired ceramic material, etc., as well as low-k and ultra-low-k dielectrics (dielectric constant less than about 3.6), including but not limited to carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, fluoropolymers, etc. The microelectronic substrate 104 can also include conductive wiring or metallization extending through the microelectronic substrate 104, such that, like the other metallization layers discussed herein, the conductive wiring can be a combination of conductive traces and conductive vias extending through the dielectric material layer. The conductive traces and conductive vias can be made of any suitable conductive material or materials, including but not limited to metals such as copper, silver, nickel, gold, and aluminum, alloys thereof, etc. The microelectronic substrate 104 can be a cored substrate or a coreless substrate. In some embodiments, components such as passive components 118 can be disposed on the back side of the microelectronic substrate 104.

[0046] As shown, the microelectronic substrate 104 includes an external interconnect 105 for coupling to an external device (not shown). In some embodiments, the external interconnect 105 can be provided on a bonding pad on a surface of the microelectronic substrate 104 opposite the surface of the interconnect 111. The external interconnect 105 can be any suitable conductive material, including but not limited to metal-filled epoxies and solders, such as tin, lead / tin alloys (e.g., 63% tin / 37% lead solder), and high-tin content alloys (e.g., 90% or more tin, such as tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, and similar alloys). The external interconnect 105 can be used to attach the microelectronic substrate 104 to an external substrate (not shown), such as a motherboard.

[0047] Figure 2 A cross-sectional side view of electrical routing 200 in a multi-chip composite device 100 arranged in accordance with some embodiments is shown. As shown, in some embodiments, power routing 121 is provided to the top side of one or more IC dies 101, including the back side 119 of the IC die 101 and corresponding back side metallization. Figure 2 , power routing 121 is illustrated using two bidirectional arrows having a darker shading relative to the IO routing 122. As discussed, power or power routing indicates routing of power for operating the device (and includes power and ground), such that power routing 121 includes any conductive vias, paths, metallizations, and any intervening devices between the power source and the device layers of one or more IC dies 101. Figure 2 In the context of FIG1 , power routing 121 includes one or more interconnects 111, vias 110, VR die 103, and metallization network 107, as well as die-level interconnects 112. However, in some embodiments, power routing 121 does not include VR die 103. For example, voltage regulation may be provided by components embedded within metallization network 107 (and mounted to substrate 108), components mounted on microelectronic substrate 104, or components otherwise disposed in multi-chip composite device 100.

[0048] also, Figure 2 Signal or IO wiring 122 is shown, which includes conductive vias, paths, metallizations, any intervening devices, etc., to provide signal routing to the one or more IC dies 101. As shown, the IO wiring 122 is provided to the bottom side of the one or more IC dies 101, which includes the front side 120 of the IC die 101 and the corresponding front side metallization. The IO wiring 122 is again shown using two bidirectional arrows, and the IO wiring 122 provides the signals required to operate the device. The IO wiring 122 includes any conductive vias, paths, metallizations, and any intervening devices between the external signal paths and the device layers of the one or more IC dies 101. In Figure 2In the context of , IO routing 122 includes one or more interconnects 111 , base die 102 (using through vias 125 ), and die-level interconnects 112 .

[0049] By removing the power routing 121 from the same path and physical space as used by the IO routing 122, the advantages discussed are achieved, namely, freeing up the front side metallization layer of the IC die 101 and the through vias 125 for additional IO routing, having a thicker power delivery path by deploying the top side metallization network 107, having more direct routing to the device layers, and other advantages.

[0050] Figure 3 An enlarged cross-sectional side view 300 of a region 130 of a multi-chip composite device 100 is shown, arranged in accordance with some embodiments. Figure 3 As shown, multi-chip composite device 100 includes a metallization network 107 above IC die 101 and coupled to IC die 101 via interconnect 109. For example, interconnect 109 can be part of interconnect layer 133. IC die 101 is above base die 102 and coupled to base die 102 via die-level interconnect 112. For example, die-level interconnect 112 can be part of die-level interconnect layer 138. As shown, IC die 101 includes a device layer 135 between front-side metallization 136 and back-side metallization 134.

[0051] As discussed, the front side metallization 136 is formed over the front side of the device layer 135, and subsequently, the back side metallization 134 can be formed on the side of the device layer 135 opposite the front side metallization 136 (via carrier wafer attachment, back side grinding, and metallization). In addition, the metallization network 107 provides power delivery through the back side metallization 134, while the base die 102 provides IO wiring through the front side metallization 136. In some embodiments, the back side metallization 134 includes thicker metallization (e.g., metal lines or layers having a greater thickness in the z dimension) than the front side metallization 136. In addition, the metallization 136 can have fewer metallization layers (e.g., metal line layers) than the metallization layers of the front side metallization 136. For example, thicker metallization can provide more efficient power delivery, while more metallization layers are required for the complexity of IO signal transmission.

[0052] The metallization network 107 may include any number of metallization levels 131 and intervening via levels 132. The term "metallization level" refers to a network of substantially coplanar metal lines or conductive wiring. A via level includes a network of substantially coplanar metal vias or conductive plugs that interconnect the metallization levels. In the illustrated example, the metallization network 107 has four metallization levels (M0, M1, M2, M3) and three intervening via levels (V1, V2, V3). However, any number of metallization levels and via levels may be used. In some embodiments, a single metallization level is deployed. Similarly, the backside metallization 134 and the frontside metallization 136 each include multiple metallization levels and intervening via levels. Individual metallization levels and intervening via levels of the backside metallization 134 and the frontside metallization 136 are further illustrated below.

[0053] In some embodiments, each metallization level of the backside metallization 134 has a thickness Tbs, which can be the same at each metallization level of the backside metallization 134, or the thickness Tbs of each level can increase as it moves away from the device layer (i.e., in the positive z-direction). Similarly, each metallization level of the frontside metallization 136 has a thickness Tfs, which can also be the same at each metallization level of the frontside metallization 136, or the thickness Tfs of each level can increase as it moves away from the device layer (i.e., in the negative z-direction). Also as shown, each metallization level of the metallization network 107 has a thickness Tn. Like other metallization layers, each metallization level of the metallization network 107 can have the same thickness, or the thickness Tn of each level can increase as it moves away from the IC die 101 (i.e., in the positive z-direction).

[0054] In some embodiments, each metallization level of the back side metallization 134 is thicker than each metallization level of the front side metallization 136. That is, the thickest metallization level in the front side metallization 136 may have a thickness Tfs that is less than the thickness Tbs of the thinnest metallization level in the back side metallization 134. In some embodiments, each metallization level of the back side metallization 134 is at least as thick as each metallization level of the front side metallization 136. For example, the thickest metallization level in the front side metallization 136 may have a thickness Tfs that is less than or equal to the thickness Tbs of the thinnest metallization level in the back side metallization 134.

[0055] Furthermore, the backside metallization 134 may have fewer metallization levels than the number of metallization levels of the frontside metallization 136. In some embodiments, the number of metallization levels of the backside metallization 134 is less than the number of metallization levels of the frontside metallization 136. In some embodiments, the difference between the number of metallization levels of the frontside metallization 136 and the number of metallization levels of the backside metallization 134 is no less than three. In some embodiments, the difference between the number of metallization levels of the frontside metallization 136 and the number of metallization levels of the backside metallization 134 is no less than four or more.

[0056] Each metallization level 131 of the metallization network 107 is much thicker than each metallization level of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level in the metallization network 107 is a multiple of or has an order of magnitude greater than the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level in the metallization network 107 is not less than five times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level in the metallization network 107 is not less than ten times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level in the metallization network 107 is not less than 25 times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level in the metallization network 107 is not less than 50 times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level in the metallization network 107 is not less than 100 times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134.

[0057] In some embodiments, the metallization levels 131 of the metallization network 107 are thicker than the metallization levels of the backside metallization 134, which are thicker than the metallization levels of the frontside metallization 136. In some embodiments, the thickness Tfs of each metallization level of the frontside metallization 136 is no more than 1 micron thick. In some embodiments, the thickness Tfs of each metallization level of the frontside metallization 136 is no more than 500 nm thick. In some embodiments, the thickness Tbs of each metallization level of the backside metallization 134 is on the order of 1 micron thick. In some embodiments, the thickness Tbs of each metallization level of the backside metallization 134 is no more than 1.5 microns thick. In some embodiments, the thickness Tbs of each metallization level of the backside metallization 134 is no more than 1.0 micron thick.

[0058] In contrast, the metallization levels 131 of the metallization network 107 are several orders of magnitude larger. In some embodiments, the thickness Tn of each metallization level 131 of the metallization network 107 is no less than 10 microns thick. In some embodiments, the thickness Tn of each metallization level 131 of the metallization network 107 is no less than 25 microns thick. In some embodiments, the thickness Tn of each metallization level 131 of the metallization network 107 is no less than 50 microns thick. In some embodiments, the thickness Tn of each metallization level 131 of the metallization network 107 is in the range of 10 to 100 microns thick. The metallization network 107 also has a total thickness Tnt (total network thickness). As described below, components can be embedded within the total thickness Tnt of the metallization network 107.

[0059] That is, the thickest metallization level in the front side metallization 136 may have a thickness Tfs that is less than the thickness Tbs of the thinnest metallization level in the back side metallization 134. In some embodiments, each metallization level of the back side metallization 134 is at least as thick as each metallization level of the front side metallization 136. For example, the thickest metallization level in the front side metallization 136 may have a thickness Tfs that is less than or equal to the thickness Tbs of the thinnest metallization level in the back side metallization 134.

[0060] In some embodiments, the IC die 101 also includes a substrate layer 137 that includes a through via 144. The via 144 extends from the die-level interconnect layer 138 to the front-side metallization 136, and the via 144 can be made of any suitable conductive material, such as copper. In some embodiments, the IC die 101 includes a backside via 143 that extends from the interconnect layer 138 to the backside metallization 134. The backside via 143 can also be any suitable conductive material, such as copper. The via 144 and the backside via 143 can be formed using any suitable technique or techniques and can extend through the substrate layer 137, which provides structural support during manufacturing. In some embodiments, one or both of the via 144 and the backside via 143 are not deployed.

[0061] Also as shown, the base die 102 may include a device layer 141 between the front side metallization 140 and the back side metallization 139. In some embodiments, the base die 102 does not include such a layer, but rather includes only through vias 125. In some embodiments, the base die 102 also includes vias 145 and front side vias 145. The device layer 141, front side metallization 140, back side metallization 139, vias 145, and front side vias 145 may have any of the characteristics discussed above with respect to the device layer 135, front side metallization 136, back side metallization 134, vias 144, and back side vias 143. Notably, in Figure 3 In the context of , the front side metallization 136 and the back side metallization 139 are close to each other.

[0062] Figure 4 An enlarged cross-sectional side view 400 of a region 130 of a multi-chip composite device 100 with an inverted base die 102 arranged in accordance with some embodiments is shown. Figure 4 As shown, the base die 102 may be relative to Figure 3 The multi-chip composite device 100 is inverted so that the front side metallization 136 and the front side metallization 140 are adjacent to each other. In other aspects, the components of the multi-chip composite device 100 can have any of the features discussed herein. It should also be noted that the base die 102 may not include the device layer 141, such that it only provides redistribution, and the base die 102 can be characterized as an interposer. In other examples, the base die 102 may include only the front side metallization 140 (e.g., the base die 102 may not have the back side metallization 139). Other base die 102 architectures may be used.

[0063] Figure 5 A cross-sectional side view 500 of the IC die 101 is shown showing further details of the device layer 135, the front-side metallization 136, and the back-side metallization 134 arranged in accordance with some embodiments. The front-side metallization 136 and the back-side metallization 134 can be formed using any suitable technique or techniques, such as dual damascene techniques, single damascene techniques, subtractive metallization patterning techniques, and the like. As discussed, interconnectivity, signal routing, IO routing, and the like can be provided by the front-side metallization 136. The front-side metallization 136 includes any number of metallization and via levels 501, such that the via levels are located between and interconnect the metallization levels. For example, metal wiring or lines 503 of the metallization levels are interconnected through vias, such as vias 504.

[0064] As shown, in some embodiments, a front side metallization 136 is formed over one side of a device layer 135, which may include a transistor structure 160. Figure 5 In the context of FIG, the transistor structure 160 is a gate-all-around field-effect transistor (GAA-FET), however, the transistor structure 60 can be any suitable device, such as a planar FET, a FinFET, etc., or the device layer 135 can include other functional device structures. In the example shown, the front side metallization 136 includes M0, V0, M1, M2 / V1, M3 / V2, M4 / V3, M5 / V4, M6 / V5, M7 / V6, and M8 / V7. However, M4 / V3 can include any number of metallization levels and corresponding via levels, such as six, eight, or more metallization layers.

[0065] Similarly, the backside metallization 134, which includes any number of thicker metallizations and via-level metallizations and via levels 502 (as discussed above), can include, for example, backside metallization level 0 (BM0), backside via level 0 (BV0), backside metallization level 1 (BM1), backside via level 1 (BV1), backside metallization level 2 (BM2), and so on. As shown, the interconnect 109 can contact the backside metallization levels of the backside metallization 134 to interconnect to the metallization network 107. The backside metallization 134 is formed above and immediately adjacent to the device layer 135, and on the side of the device layer 135 opposite the frontside metallization 136. In the example shown, the metallization levels of the backside metallization 134 include BM0, BM1, and BM2, with a via layer in between. However, the backside metallization 134 may include any number of metallization levels, such as four, five, or more metallization layers.

[0066] Figure 6 A cross-sectional side view 600 of the metallization die 106 is shown showing further details of the metallization network 107 arranged in accordance with some embodiments. The metallization network 107 can be formed using any suitable technique or techniques, such as a dual damascene technique, a single damascene technique, a subtractive metallization patterning technique, and the like. In the example shown, the metallization network 107 is fabricated on a substrate 108, which is part of the metallization die 106. However, in other cases, the metallization network 107 can be formed directly above the IC die 101 or formed according to wire bonding techniques, as discussed further below. The metallization network 107 provides top-side power routing to the IC die(s) 101 through connections via interconnects 109. In some embodiments, the metallization network 107 can also provide optional IO routing, as discussed further below.

[0067] The metallization network 107 can include any number of thicker metallization levels 131 and via levels 132. For example, the metallization levels 131 and via levels 132 can include power network metallization level 0 (NM0), power network via level 0 (NV0), power network metallization level 1 (NM1), power network via level 1 (NV1), power network metallization level 2 (NM2), and so on. As shown, the interconnect 109 can contact the backside or via metallization level of the metallization network 107 to interconnect with the IC die 101 using the interconnect 109. In some embodiments, the metallization network 107 is formed above or on the substrate 108. In the example shown, the metallization network 107 includes three metallization levels 131 and two intervening via levels 132. However, the metallization network 107 can include any number of metallization layers, such as one, two, four, five, or more metallization layers.

[0068] Figure 7 A cross-sectional side view of electrical routing 700 in a multi-chip composite device 100 is shown, arranged in accordance with some embodiments. Figure 2 As discussed, in some embodiments, power routing 121 is provided to the top side of the IC die 101 to couple directly to the backside metallization of the IC die 101, and signal or IO routing 122 is routed through the base die 102 to the frontside metallization of the IC die 101.

[0069] like Figure 7 As shown, in some embodiments, the signal or IO wiring 122 includes a first wiring 704 from the microelectronic substrate 104 through the interconnect 111 to the base die 102, and a second wiring 703 from the base die 102 through the die-level interconnect 112 to the IC die 101. For example, the base die 102 can passively connect the IO wiring 122 from the microelectronic substrate 104 to the IC die 101 (e.g., using a through-hole 125), or the base die 102 can handle signals as part of the IO wiring 122. Figure 7 As shown, power may be provided to the base die 102 via power wiring 701. In some embodiments, the power wiring 701 extends from the microelectronic substrate 104 through the interconnects 111 to the base die 102.

[0070] Figure 8 1 shows a cross-sectional side view of electrical routing 800 in a multi-chip composite device 100 having a plurality of integrated circuit dies 101 arranged in accordance with some embodiments. Figure 8 As shown, power wiring 121 can be provided to the top side of any number of IC dies 101 through the metallization network 107. In addition, in some embodiments, the signal or IO wiring 122 can also include a third wiring 801 from the base die 102 to another IC die 101 through the die-level interconnect 112. The base die 102 can passively provide the second wiring 703 and the third wiring 801, or the base die 102 can manipulate signals as part of the IO wiring 122.

[0071] Likewise Figure 8As shown, in addition to the power routing 121, the metallization network 107 can be used to provide signal or IO routing 802 between the IC dies 101. For example, the signal or IO routing 802 can extend from the front-side metallization of a first IC die 101 in the IC dies 101, through a particular interconnect 109 in the interconnects 109, through the metallization network 107, through a plurality of interconnects 109 in the interconnects 109, to a second IC die 101 in the IC dies 101. For example, in addition to the routing and architectural flexibility provided by moving the power routing 121 to the metallization network 107, the metallization network 107 can provide additional routing and architectural flexibility. In some embodiments, the signal or IO routing 802 can be characterized as an IO bridge, and the signal or IO routing 802 can relieve a portion of the IO routing burden of the base die.

[0072] Figure 9 1 shows a cross-sectional side view of electrical routing 900 in a multi-chip composite device 100 having a plurality of base dies 102 arranged in accordance with some embodiments. Figure 9 As shown, power routing 121 is provided to the top side of IC die 101 to couple directly to the backside metallization of IC die 101. In addition, electrical routing 900 includes a plurality of IO routings 122, each IO routing 122 including a first routing 704 from microelectronic substrate 104 through interconnect 111 to one of base dies 102, and a second routing 703 from each base die 102 through die-level interconnect 112 to IC die 101. Base die 102 can passively route the IO routing 122, or base die 102 can manipulate signals as part of the IO routing 122.

[0073] Figure 10 A cross-sectional side view of a multi-chip composite device 1000, arranged in accordance with some embodiments, is shown, the multi-chip composite device including a top-side metallization network 107 fabricated from one or more directly applied metallization levels 1001 to provide power routing to a backside 119 of an integrated circuit die 101. As discussed, in some embodiments, the top-side metallization network 107 may be formed on a substrate 108 as part of a metallization die 106, and the metallization die 106 may be coupled to the backside 119 of the IC die 101.

[0074] In other embodiments, the metallization network 107 can be formed above the IC die, for example, on the surface of the interconnect layer 133. For example, the top surface of the interconnect layer 133 can include exposed portions of the interconnects 109 that are substantially coplanar with the dielectric material 1002. The metallization network 107 is then formed on the surface using any suitable technique or techniques. In some embodiments, the metallization network 107 is formed using additive processing techniques. In some embodiments, the metallization network 107 is formed using screen printing techniques. Any number of metallization levels (i.e., one or more) and intervening via levels (if multiple metallization levels are deployed) can be fabricated, and the metallization network 107 (without the substrate 108) can have any of the characteristics discussed elsewhere herein.

[0075] Figure 11 A cross-sectional side view of a multi-chip composite device 1100 including a second integrated circuit die level on a top-side metallization network 107 arranged in accordance with some embodiments is shown. For example, after attaching an IC die 1101 to the metallization network 107 and forming a dielectric material 1102, the multi-chip composite device 1100 is similar to the multi-chip composite device 1000. In some embodiments, the multi-chip composite device 1100 is similar to the multi-chip composite device 1000 using a top-side metallization network 107. Figure 10 The metallization network 107 is fabricated using the additive techniques discussed so that the top surface of the metallization network 107 is exposed for attaching the IC die 1101. In other embodiments, the substrate 108 can be removed to expose the metallization network 107 for attaching the IC die 1101. For example, the substrate 108 can be removed using a grinding technique, an etching technique, or a combination thereof.

[0076] IC die 1101 can have any of the characteristics discussed herein with respect to IC die 101, such that IC die 1101 includes backside metallization at backside 119 and frontside metallization at frontside 120. The backside metallization at backside 119 is on the side of the device layer opposite the frontside metallization at frontside 120 (see FIG. Figure 5 ). Notably, the backside 119 of both IC die 101 and IC die 1101 are adjacent to the metallization network 107 for delivering power directly to the backside metallization layers of IC die 101 and IC die 1101. Signal and IO routing can be provided to IC die 1101 through the metallization network 107 and IC die 101 or through alternative routing laterally adjacent to the metallization network 107, IC die 101, and base die 102.

[0077] Figure 12 1 shows a cross-sectional side view of a multi-chip composite device 1200 with a component 1201 within the thickness of a top-side metallization network 107 arranged in accordance with some embodiments. Figure 3 、 Figure 4 and Figure 6As shown, the metallization network 107 has a total thickness Tnt. In some embodiments, the total thickness Tnt of the metallization network 107 is in the range of approximately 25 to 500 microns. In some embodiments, this total thickness of the metallization network 107 allows the component 1201 to be completely inserted within the total thickness of the metallization network 107. For example, both opposing surfaces of the component 1201 orthogonal to the z-direction can be completely within the total thickness Tnt of the metallization network 107.

[0078] Component 1201 can be any suitable active or passive component, such as an IC die, a voltage regulator, a capacitor, an inductor, or a circuit including these devices. In some embodiments, component 1201 is attached to the surface of substrate 108, and a metallization network 107 including metallization level 131, via level 132, and dielectric material 128 is constructed adjacent to component 1201. In some embodiments, component 1201 is an inductor that is directly attached to the surface of substrate 108, such that metallization network 107 is on the same surface of substrate 108. In some embodiments, components such as inductors are disposed on microelectronic substrate 104.

[0079] Figure 13 A cross-sectional side view of a multi-chip composite device 1300 having a top-side metallization network 107 with bond wires 1301 arranged in accordance with some embodiments is shown. As discussed herein, the metallization network 107 may include multiple metallization levels 131 with via levels 132 therebetween (see Figure 4 ), such that the metallization level 131 includes substantially planar metallization features, such as conductive traces or metal lines. In some embodiments, the metallization network 107 instead includes a plurality of bonding wires 1301 embedded in a molding material 1302.

[0080] The bond wires 1301 can be formed using any suitable technique or techniques to couple bond pads between the IC die 101 and the VR die 103. In some embodiments, the bond wires 1301 form an inductor between the IC die 101 and the VR die 103. For example, the molding material 1302 can be a magnetic material. The bond wires 1301 can have any thickness discussed herein with respect to the metallization levels 131 to form an effective metallization network 107. In some embodiments, the thickness of each bond wire 1301 can be a diameter or width of the bond wire 1301 that is orthogonal to the linear dimension of each bond wire 1301.

[0081] In some embodiments, the width of each bond wire 1301 of the metallization network 107 is no less than five times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the width of each bond wire 1301 of the metallization network 107 is no less than ten times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the width of each bond wire 1301 of the metallization network 107 is no less than 25 times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the width of each bond wire 1301 of the metallization network 107 is no less than 50 times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134. In some embodiments, the width of each bonding wire 1301 of the metallization network 107 is not less than 100 times the thickness Tbs of the thickest metallization level in the front side metallization 136 and the back side metallization 134 .

[0082] Figure 14 is a flow chart illustrating a method 1400 for forming a multi-chip composite device including a topside metallization network to provide power routing to the backside of an integrated circuit die, arranged in accordance with at least some embodiments of the present disclosure. Figure 15 、 16 , 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 and 30 are cross-sectional side views of integrated circuit (IC) device structures that evolve as method 1400 is practiced, arranged according to some embodiments of the present disclosure.

[0083] Method 1400 begins at input operation 1401, where a workpiece is received for processing. For example, fully or partially manufactured IC dies, base dies, VR dies, metallization dies, and other components may be received for processing. The received dies may be part of a substrate structure, or they may be separated from a substrate. In some embodiments, the multi-chip composite device discussed may be manufactured on a reconstructed wafer such that the IC die is coupled to the base die (as a reconstructed base die wafer), or the base die is coupled to the IC die using die-to-wafer bonding (as a reconstructed IC die wafer). In some embodiments, wafer-to-wafer bonding technology is used. In addition, other components may be manufactured before or after attachment, such as through dielectric vias adjacent to the base die or a metallization network above the IC die. For example, method 1400 includes exemplary manufacturing methods that may be performed out of order, or other techniques may be used to manufacture the multi-chip composite devices discussed herein.

[0084] Processing continues at operations 1402 and 1404. At operation 1402, the segmented or singulated IC die are tested, and those die that pass the test are attached to a carrier wafer with the front side metallization facing up (i.e., away from the carrier wafer). Testing can be performed using any suitable technique or techniques, such as coupling probe pins to conductive pads on the IC die and probing (using a test circuit) various paths of the IC die. Those die that pass the test are attached to the carrier wafer using any suitable technique or techniques (such as die-to-wafer bonding using an adhesive, laminate, tape, etc.). Similarly, at operation 1404, the segmented or singulated base die are tested and again attached to the carrier wafer with the front side metallization facing up (i.e., away from the carrier wafer). Testing can be performed using any suitable technique or techniques (such as those discussed with respect to operation 1402).

[0085] Figure 15 A cross-sectional side view 1500 of an integrated circuit die 101 under test is shown. IC die 101 includes or is attached to a substrate 1501. IC die 101 also includes front-side metallization 136, a device layer 135, back-side metallization 134, and an optional substrate layer 137. As shown, IC die 101 can be attached or mounted to a thermal head 1502, which provides temperature control and optional temperature stress during testing. Probe pins 1503 are coupled to back-side metallization 134 and are used to test various components of IC die 101, such as active or test components of device layer 135.

[0086] Figure 16 A cross-sectional side view of a device structure 1600 is shown, which includes a plurality of IC die 101 attached to a carrier wafer 1601 such that the backside metallization 134 is proximal to the carrier wafer 1601 and the frontside metallization 136 faces upward and away from the carrier wafer 1601 (i.e., the frontside metallization 136 is away from the carrier wafer 1601). The carrier wafer 1601 can be any suitable material in any suitable form. For example, the carrier wafer 1601 can be a single crystal silicon wafer. Although discussed with respect to a wafer form, any carrier form can be used, such as a panel. The IC die 101 can be attached to the carrier wafer 1601 using adhesives, laminates, tapes, etc., as known in the art.

[0087] Back to Figure 14, processing continues from operation 1402 to operation 1403, where a dielectric or molding material is formed around the attached IC die and over the carrier substrate. Backside grinding is then performed to remove the substrate from over the front side metallization and provide a flat surface relative to the dielectric or molding material. Alternatively, the substrate can be removed, the dielectric material or molding material can be formed, and a planarization operation can be performed. Subsequently, the IC die and carrier wafer are singulated so that each IC die now has exposed front side metallization and is ready to be coupled with a base die, as discussed further below.

[0088] Figure 17 A cross-sectional side view of a device structure 1700 similar to device structure 1600 is shown, with dielectric material 1701 formed over and around IC die 101, such that IC die 101 is embedded in dielectric material 1701. Dielectric material 1701 can be any suitable dielectric material, such as an inorganic or organic dielectric material. In some embodiments, dielectric material 1701 is or includes one or more of silicon dioxide, silicon nitride, and silicon carbon nitride. In some embodiments, dielectric material 1701 is or includes a polymer material. In some embodiments, dielectric material 1701 is a molding material. Dielectric material 1701 can be formed using any suitable deposition technique or techniques.

[0089] Figure 18 A cross-sectional side view of a device structure 1800 similar to device structure 1700 is shown after backside material operation(s) to remove the substrate 1501 and portions of the dielectric material 1701. The backside material operation(s) may include any suitable technique, such as a backside grinding operation, a chemical removal or etching operation, a planarization operation, etc. As discussed, in some embodiments, the dielectric material 1701 is applied after the substrate 1501 is removed, followed by planarization. As shown, a substantially planar surface 1802 of each IC die 101 is exposed for die attach. In the embodiment shown, the optional substrate layer 137 remains and is exposed, however, in some embodiments, the front side metallization 136 is exposed. In addition, the device structure 1800 shows example separation lines or scribe lines 1801 by which the IC die 101 may be separated or segmented from the carrier wafer 1601. Then, as described below with respect to Figure 23 As discussed, such singulated IC dies 101 may be attached to a base die.

[0090] Reference Figure 14 As discussed, at operation 1404, the segmented or singulated base dies are tested and attached to a carrier wafer with the front side metallization facing up (ie, away from the carrier wafer).

[0091] Figure 19 A cross-sectional side view 1900 of a base die 102 under test is shown. The base die 102 includes or is attached to a substrate 1901, and the base die 102 may also include a front side metallization 140, a device layer 141, a back side metallization 139, and an optional substrate layer 142. As discussed herein, in some embodiments, the base die 102 does not include a device layer 141, but instead includes IO wiring. In this case, device testing is not required, but wiring testing can still be performed. The base die 102 can be attached or mounted to a thermal head 1502 and can be tested using probe pins 1503 coupled to the back side metallization 139.

[0092] Figure 20 A cross-sectional side view of a device structure 2000 is shown, including a base die 102 attached to a carrier wafer 2001. Although a single base die 102 is shown attached to the carrier wafer 2001, any number of base dies can be attached to the carrier wafer 2001 for processing. As shown, the backside metallization 139 is proximal to the carrier wafer 2001, and the frontside metallization 140 faces upward and away from the carrier wafer 2001. The carrier wafer 2001 can be any suitable material in any suitable form, such as those discussed with respect to the carrier wafer 1601. The base die can be attached to the carrier wafer 2001 using adhesives, laminates, tape, and the like.

[0093] Back to Figure 14 , processing continues from operation 1404 to operation 1405, where a dielectric or molding material is formed around the attached base die and over the carrier substrate. Backside grinding is then performed to remove the substrate from over the front side metallization and provide a flat surface relative to the dielectric or molding material. Alternatively, the substrate can be removed, the dielectric material or molding material can be formed, and a planarization operation can be performed. Subsequently, through-dielectric vias are fabricated near the base die such that the vias are laterally adjacent to the base die and extend through the entire thickness of the base die. The fabricated vias will become part of the power routing to the backside metallization of one or more IC dies, as discussed herein.

[0094] Figure 21A cross-sectional side view of a device structure 2100 similar to device structure 2000 is shown after removing substrate 1901 and after forming dielectric material 2101 laterally adjacent to base die 102. For example, dielectric material 2101 can be formed over and around base die 102 such that base die 102 is embedded in dielectric material 2101, and backside material operation(s) can be performed to remove portions of substrate 1901 and dielectric material 2101. Alternatively, dielectric material 2101 can be applied after removing substrate 1901, followed by planarization operation(s). Dielectric material 2101 can be any of the materials discussed with respect to dielectric material 1701. As shown, a substantially planar surface 2102 of device structure 2100 is exposed for die attach. In the illustrated embodiment, optional substrate layer 142 remains and is exposed, however, in some embodiments, frontside metallization 140 is exposed.

[0095] Figure 22 A cross-sectional side view of a device structure 2200 similar to device structure 2100 is shown after fabrication of a via 110 (which can be characterized as a through-dielectric via). The via 110 can be fabricated using any suitable technique or techniques. In some embodiments, an opening or hole is formed in the dielectric material 2101 using photolithography and etching techniques, laser drilling techniques, or other patterning techniques. The resulting opening or hole can then be filled with a conductive material using deposition and / or plating techniques, followed by a planarization operation to restore a substantially flat surface 2102. As shown, the via 110 is laterally adjacent to the base die 102 (i.e., in the xy plane) and extends vertically (i.e., in the z direction) through the entire thickness of the base die 102. Thus, power routing can bypass the base die 102 using the via 110.

[0096] Back to Figure 14 , processing continues from operations 1403 and 1405 to operation 1406, where the IC die formed at operation 1403 is mounted to the reconstructed base die wafer formed at operation 1405. Although the IC die are discussed as being mounted to a reconstructed base die wafer, method 1400 can be used to form singulated base dies (including adjacent dielectric material and through-dielectric vias) mounted to a reconstructed IC die wafer. In other embodiments, wafer-to-wafer bonding can be used. At operation 1405, the singulated IC die can be mounted to the reconstructed base die wafer using any suitable technique or techniques, such as hybrid bonding techniques.

[0097] For example, the metal patterning of the surfaces of the IC die and base wafer is metal-to-metal and dielectric-to-dielectric matching for hybrid bonding. Such surfaces can then be brought together, optionally under pressure and / or heat, to fuse the metal to form a die-level interconnect and optionally fuse the dielectric material to form a hybrid bond. Although hybrid bonding for die-level interconnects is discussed, other interconnect technologies and structures can be used, such as solder bonding using solder balls or similar components.

[0098] Figure 23 A cross-sectional side view of a device structure 2300 similar to device structure 2200 is shown after bonding a plurality of IC dies 101 and VR die(s) to a substantially planar surface 2102. As discussed, such bonding may be performed using any suitable technique or techniques, such as hybrid bonding, solder interconnects, etc. For clarity of presentation, such die-level interconnects are not shown. Figure 23 21. By mounting the IC die(s) 101 and the VR die(s) to the substantially flat surface 2102, any number of multi-chip composite devices 100 or die composites can be formed above the carrier wafer 2001. Additional manufacturing operations can be performed, and such multi-chip composite devices 100 or die composites can then be singulated or separated from the carrier wafer 2001. Notably, in the device structure 2300, the backside metallization 134 is exposed at the top of the device structure 2300 for bonding to the metallization network.

[0099] Back to Figure 14 , processing continues at operation 1407, where a metallization network is formed on the IC die mounted at operation 1406. In some embodiments, the metallization network is formed on a separate one or more metallization dies, and the one or more metallization dies are mounted to the exposed backside metallization of the mounted IC die. In some embodiments, the metallization network is formed directly over the exposed backside metallization layer of the mounted IC die. For example, the metallization network may be formed using screen printing techniques or on Figure 10 In some embodiments, the metallization network is formed by wirebonding between the IC die(s) and adjacent IC die(s) and / or adjacent VR die or components. In some embodiments, such wirebonds can be used to fabricate an inductor by embedding the wirebonds in a magnetic material, such as a magnetic molding material. For example, the metallization network can be formed by wirebonds embedded in a dielectric material or a magnetic material, such as a magnetic molding material, as described with respect to FIG. Figure 13 discussed.

[0100] Figure 24A cross-sectional side view of a device structure 2400 similar to device structure 2300 is shown after removing the remaining portion of carrier wafer 1601 and after forming dielectric material 2401 laterally adjacent to IC die(s) 101 and VR die(s) 103. For example, dielectric material 2401 can be formed over and around IC die(s) 101 and VR die(s) 103 such that IC die(s) 101 and VR die(s) 103 are embedded in dielectric material 2401, and backside material operation(s) can be performed to remove the remaining portion of carrier wafer 1601 and portions of dielectric material 2401. Alternatively, dielectric material 2401 can be applied after removing the remaining portion of carrier wafer 1601, followed by planarization operation(s). Dielectric material 2401 can be any of the materials discussed with respect to dielectric material 1701. As shown, a substantially planar surface 2402 of device structure 2400 is exposed to form a metallization network. Notably, the backside metallization 134 of the IC die 101 is exposed so that a metallization network can be formed close to the backside metallization 134 .

[0101] Figure 25 A cross-sectional side view 2500 of the fabrication of a metallized die 106 is shown. The metallized die 106 includes a substrate 108 and a metallization level 131, a via level 132, and a dielectric material 128 formed over the substrate 108 using any suitable technique or techniques. In some embodiments, the metallization level 131, the via level 132, and the dielectric material 128 are formed using a damascene or dual damascene approach. In some embodiments, the metallization level 131, the via level 132, and the dielectric material 128 are formed using an additive bulk metallization process followed by patterning. As shown, an interconnect 109 can be formed on or over the metallization network 107.

[0102] Figure 26 A cross-sectional side view of a device structure 2600 similar to device structure 2400 is shown after bonding a plurality of metallized dies 106 to a substantially planar surface 2402. Such bonding may be performed using any suitable technique or techniques, such as solder interconnects, hybrid bonding, etc. Figure 26 In the context of FIG. 1 , multiple metallization dies 106 are deployed to form a metallization network 107. In some embodiments, one or more metallization dies 106 are interconnected across the IC die(s) 101 and the VR die(s) 103 (i.e., interconnect the individual dies), and one or more metallization dies 106 are interconnected within individual dies in the IC die(s) 101 and the VR die(s) 103. In some embodiments, the metallization network 107 is formed by mounting a single metallization die 106 for each multi-chip composite device 100 or die composite, as described above (see FIG. 1 ). Figure 1 In some embodiments, a single metallization die 106 can span (e.g., in the xy plane) across each of the VR die 103 and the IC die 101 to couple to each of the VR die 103 and the IC die 101. In some embodiments, a single metallization die 106 can span the entire lateral area covered by the metallization die 106, or an even larger lateral area (such as Figure 26 the entire area shown) or more.

[0103] The device structure 2600 shows the formation of the metallization network 107 using one or more metallization dies 106, such that the metallization network or portions thereof are formed on (a plurality of) separate metallization dies 106, and the (a plurality of) metallization dies 106 are mounted over the exposed backside metallization 134 of the IC die 101. In some embodiments, the metallization network 107 is formed directly on the exposed backside metallization 134 of the IC die 101. Figure 10 , the metallization network 107 can be formed using screen printing techniques or other additive metallization techniques to apply the metallization network 107 directly to the substantially flat surface 2402. In some embodiments, the metallization network 107 is formed from wire bonds by a wire bonding process. Figure 13 , the metallization network 107 may be formed from bond wires 1301 fabricated using any suitable technique or techniques to interconnect the IC die(s) 101 and the VR die(s) 103 over the substantially planar surface 2402 .

[0104] 101 . In addition, the device structure 2600 shows vias 110 that are laterally adjacent to the base die 102 and extend vertically through the thickness of the base die 102 to the VR die 103. In some embodiments, the VR die 103 is not used, and in such cases, the vias 110 are laterally adjacent to the base die 102 and the IC die(s) 101 (i.e., in the xy plane) and extend vertically (i.e., in the z direction) through the entire thickness established by the base die 102 and the IC die(s) 101. Thus, power routing can bypass the base die 102 and the IC die(s) 101 and couple directly to the metallization network 107. For example, such vias can be formed within the device structure 2400, as described with respect to FIG. Figure 22 In some embodiments, openings or holes are formed in dielectric material 2401 and dielectric material 2101 using photolithography and etching techniques, laser drilling techniques, or other patterning techniques, and the openings or holes are filled with a conductive material using deposition and / or plating techniques, followed by a planarization operation to restore substantially planar surface 2402.

[0105] Figure 27 A cross-sectional side view of a device structure 2700 similar to device structure 2600 is shown after forming a dielectric material 2701 laterally adjacent to the metallized die(s) 106. For example, dielectric material 2701 can be formed over and around the metallized die(s) 106 such that the metallized die(s) 106 are embedded in dielectric material 2701, and backside material operation(s) can be performed to remove a portion of dielectric material 2701 and form a substantially planar surface 2702. In some embodiments, all or a portion of substrate 108 can be removed. For example, backside material operation(s) can also remove the remaining substrate 108. Alternatively, dielectric material 2701 can be applied after substrate 108 is removed, followed by planarization operation(s). Dielectric material 2701 can be any of the materials discussed with respect to dielectric material 1701. The substantially planar surface 2702 of device structure 2700 can be used to mount a heat removal device as described herein.

[0106] Back to Figure 14 , processing continues at operation 1408, where the carrier wafer that hosts the base die, IC die and / or VR die and the metallization network are removed, and package-level interconnects are formed. In some embodiments, the die composite structure provides sufficient structural support for the package-level interconnects, and another carrier wafer or supporting substrate does not need to be deployed during such processing. However, an additional carrier wafer close to the metallization network may be used. The carrier wafer may be removed using any suitable technique or techniques, such as UV or thermal release (when using a UV- or thermal-releasable adhesive), grinding or chemical removal operations, etc. Package-level interconnects are then formed using any suitable technique or techniques, such as solder ball pick and place and reflow or similar operations. Although described with respect to solder-based package-level interconnects, any suitable interconnect, such as copper pillars, may be used.

[0107] Figure 28 A cross-sectional side view of a device structure 2800 similar to device structure 2700 is shown after removal of carrier wafer 2001 and after formation of interconnect 111. Notably, device structure 2800 is flipped relative to device structure 2700. As discussed, carrier wafer 2001 can be removed by application of UV light and / or thermal release, mechanical operations such as grinding, and / or chemical removal operations, among others. Interconnect 111 is then formed on or over vias 110 and front-side metallization 140 using any suitable technique or techniques, such as solder formation, bond pad and solder formation, among others. In some embodiments, a carrier wafer or panel (not shown) is positioned beneath substantially planar surface 2702 for added support, particularly in embodiments where substrate 108 is removed.

[0108] Back to Figure 14 , processing continues at operation 1409, where the manufactured multi-chip composite device or die composite is singulated, tested, and packaged. Such testing may be performed before or after singulation, and such multi-chip composite device or die composite testing may be performed using any suitable technique or techniques, such as coupling probe pins to conductive pads to probe (using test circuitry) various paths and components of the multi-chip composite device or die composite. As is known in the art, those devices that pass testing are passed for further processing. Such processing may include singulation, packaging, assembly, etc. The resulting device (e.g., a packaged multi-chip composite device or die composite) may then be implemented in any suitable form factor device, such as a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant, ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, etc.

[0109] Figure 29 A cross-sectional side view 2900 of a multi-chip composite device 100 under test is shown. IC die 101 includes or is attached to substrate 1501. IC die 101 also includes front-side metallization 136, device layer 135, back-side metallization 134, and an optional substrate layer 137. As shown, IC die 101 can be attached or mounted to a thermal head 1502, which provides temperature control and optional temperature stress during testing. Probe pins 1503 are coupled to back-side metallization 134 and are used to test various components of IC die 101, such as active or test components of device layer 135.

[0110] Figure 30 A cross-sectional side view of a device structure 3000 similar to device structure 2800 is shown after singulation or segmentation to separate the multi-chip composite device 100 and mounting the multi-chip composite device 100 to the microelectronic substrate 104. The multi-chip composite device 100 can be mounted and electrically coupled to the microelectronic substrate 104 using any suitable technique or techniques, such as a controlled collapse chip attach process, etc. An underfill material 3001 can be formed around the interconnects 111 to protect the interconnects 111 from moisture and provide structural support.

[0111] The multi-chip composite devices discussed herein offer advantages in power delivery, I / O routing efficiency, and other aspects. Notably, the thermal performance of the multi-chip composite devices discussed herein can be comparable to existing structures or architectures, or can be improved based on the improved power delivery efficiency. Additional advantages will become apparent based on this disclosure.

[0112] Figure 31An example microelectronic device assembly 3100 is shown that includes a multi-chip composite device 100 having a top-side metallization network 107 to provide power routing to the back side 119 of the integrated circuit die 101, in accordance with some embodiments. Figure 31 In the illustrative example of FIG, a multi-chip composite device 100 is shown. However, any multi-chip composite device, microelectronic device, or any other structure or architecture discussed herein may be deployed in the microelectronic device assembly 3100. As shown, the microelectronic device assembly 3100 includes a base die 102 attached to a microelectronic substrate 104 via an interconnect 111. The microelectronic device assembly 3100 also includes an IC die 101 and a VR die 103, and a metallization network 107 to provide top-side power (and optional additional IO) routing from the microelectronic substrate 104 and through vias 110 to the IC die 102, wherein the IC die 101 and the VR die 103 are located above the base die 102 and coupled to the base die 102 through die-level interconnects 112. As discussed, in some embodiments, the VR die 103 is not deployed, but is directly connected to the metallization network 107 through the vias 110. Additionally, base die 102 provides IO routing to IC die 101, such that the IO routing passes through the front-side metallization of IC die 101, while top-side power (and optionally additional IO) routing is provided through the back-side metallization of IC die 101. In some embodiments, the power routing originates from a power supply device, such as a battery, a voltage converter, a power supply circuit, or the like. Figure 32 shown.

[0113] Microelectronic device assembly 3100 also includes a thermal interface material (TIM) 3101 disposed, for example, on the top surface of substrate 108. In such an embodiment, substrate 108 can serve as an integrated heat spreader (IHS) for multi-chip composite device 100. In other embodiments, TIM 3101 can be located on a molding material or dielectric, for example, including bond wires or thick metallization. TIM 3101 can include any suitable thermal interface material and can be characterized as TIM 1. An integrated heat spreader 3102 having a surface on TIM 3101 extends above multi-chip composite device 100 and is mounted to microelectronic substrate 104. As discussed, microelectronic substrate 104 can include any suitable substrate, such as a package substrate, a motherboard, an interposer, etc. Additionally or alternatively, microelectronic substrate 104 can be mounted to a motherboard. Microelectronic device assembly 3100 also includes a TIM 3103 disposed on the top surface of integrated heat spreader 3102. TIM 3103 can include any suitable thermal interface material and can be characterized as TIM 2. TIM 3101 and TIM 3103 can be the same material, or they can be different materials. Heat sink 3104 (e.g., an exemplary heat sink or thermal solution) is located on TIM 3103 and dissipates heat generated by multi-chip composite device 100. Although described with respect to microelectronic device assembly 3100, the various multi-chip composite devices discussed herein can be deployed in any suitable architecture and form factor. For example, microelectronic device assembly 3100 can be used in desktop and server form factors. In other cases, thermal solutions such as heat pipes, heat sinks, or thermoelectric coolers can be mounted directly on TIM 3101, or substrate 108 can be replaced by solutions such as heat pipes or thermoelectric coolers. Such assemblies can be used in devices with smaller form factors.

[0114] Figure 32An exemplary system employing an IC assembly according to some embodiments is shown, the IC assembly including a multi-chip composite device having a top-side metallization network to provide power routing to the back side of the integrated circuit die. The system can be, for example, a mobile computing platform 3205 and / or a data server machine 3206. Either can employ a component assembly including a multi-chip composite device having a top-side metallization network for transmitting power to the back side of the IC die, as described elsewhere herein. The server machine 3206 can be any commercial server, for example, including any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing, and in an exemplary embodiment, includes an IC die assembly 3250 having a multi-chip composite device having a top-side metallization network for transmitting power to the back side of the IC die, as described elsewhere herein. The mobile computing platform 3205 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 3205 can be any of a tablet computer, a smartphone, a laptop computer, etc., and can include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 3210, and a battery 3215. Although described with respect to the mobile computing platform 3205, in other examples, the chip-level or package-level integrated system 3210 and the battery 3215 can be implemented in a desktop computing platform, an automotive computing platform, an Internet of Things platform, etc. As described below, in some examples, the disclosed system can include a subsystem 3260, such as a system on a chip (SOC) or an integrated system of multiple ICs, which is shown with respect to the mobile computing platform 3205.

[0115] Whether provided within the integrated system 3210 shown in the expanded diagram 3220 or as a standalone packaged device within the data server machine 3206, the subsystem 3260 may include memory circuitry and / or processor circuitry 3240 (e.g., RAM, a microprocessor, a multi-core microprocessor, a graphics processor, etc.), a power management integrated circuit (PMIC) 3230, a controller 3235, and a radio frequency integrated circuit (RFIC) 3225 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies, such as the memory circuitry and / or processor circuitry 3240, may be assembled and implemented such that one or more of them comprise a multi-chip composite device having a top-side metallization network for delivering power to the back side of the IC die, as described herein. In some embodiments, the RFIC 3225 includes a digital baseband and an analog front-end module, the analog front-end module also including a power amplifier in the transmit path and a low-noise amplifier in the receive path. Functionally, the PMIC 3230 can perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to the battery 3215 and an output that provides current supply to other functional modules. Figure 32 As further shown, in an exemplary embodiment, RFIC 3225 has an output coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. Memory circuits and / or processor circuits 3240 can provide memory functions for subsystem 3260 and high-level control, data processing, etc. for subsystem 326. In alternative embodiments, each SOC module can be integrated into a separate IC coupled to a package substrate, interposer, or board.

[0116] Figure 33is a functional block diagram of an electronic computing device 3300 according to some embodiments. For example, according to any embodiment described elsewhere herein, the device 3300 can employ a multi-chip composite device having a top-side metallization network for transmitting power to the back side of the IC die via any suitable component therein. The device 3300 also includes a motherboard or packaging substrate 3302 that carries multiple components, such as, but not limited to, a processor 3304 (e.g., an application processor). The processor 3304 can be physically and / or electrically coupled to the packaging substrate 3302. In some examples, the processor 3304 is located within an IC assembly that includes a multi-chip composite device having a top-side metallization network for transmitting power to the back side of the IC die, as described elsewhere herein. In general, the term "processor" or "microprocessor" can refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be further stored in registers and / or memory.

[0117] In various examples, one or more communication chips 3306 may also be physically and / or electrically coupled to the package substrate 3302. In further embodiments, the communication chip 3306 may be part of the processor 3304. Depending on its application, the computing device 3300 may include other components that may or may not be physically and electrically coupled to the package substrate 3302. These other components include, but are not limited to, volatile memory (e.g., DRAM 3332), non-volatile memory (e.g., ROM 3335), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 3330), a graphics processor 3322, a digital signal processor, a cryptographic processor, a chipset 3312, an antenna 3325, a touch screen display 3315, a touch screen controller 3365, a battery 3316, an audio codec, a video codec, a power amplifier 3321, a global positioning system (GPS) device 3340, a compass 3345, an accelerometer, a gyroscope, a speaker 3320, a camera 3341, and mass storage devices (such as hard disk drives, solid-state drives (SSDs), compact disks (CDs), digital versatile disks (DVDs), etc.), etc.

[0118] The communication chip 3306 can implement wireless communications for transmitting data to or from the computing device 3300. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not include any wires, although in some embodiments they may not. The communication chip 3306 can implement any of a variety of wireless standards or protocols, including but not limited to those described elsewhere in this document. As discussed, the computing device 3300 can include multiple communication chips 3306. For example, a first communication chip can be dedicated to short-range wireless communications, such as Wi-Fi and Bluetooth, while a second communication chip can be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0119] Although certain features set forth herein have been described with reference to various embodiments, this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the embodiments described herein, as well as other embodiments obvious to those skilled in the art to which the present disclosure pertains, are deemed to be within the spirit and scope of the present disclosure.

[0120] It will be appreciated that the invention is not limited to the embodiments thus described, but may be practiced through modification and alteration without departing from the scope of the appended claims.For example, the above embodiments may include specific combinations of features as further provided below.

[0121] The following relates to exemplary embodiments.

[0122] In one or more first embodiments, a device includes: an integrated circuit die above and coupled to a base die, the integrated circuit die including a device layer between a first metallization layer stack and a second metallization layer stack, the first metallization layer stack being proximate to the base die and having more metallization layers than the second metallization layer stack; a metallization network above and coupled to the second metallization layer stack, the metallization network including one or more metallization layers, each metallization layer having a thickness not less than five times the thickness of either the first metallization layer stack or the second metallization layer stack; and a via laterally adjacent to the base die, the via being coupled to the metallization network.

[0123] In one or more second embodiments, in addition to the first embodiment, the apparatus further comprises a metallized die comprising a substrate and the metallization network, such that the substrate comprises silicon and the metallization network comprises metal traces embedded in an inorganic dielectric material.

[0124] In one or more third embodiments, in addition to the first or second embodiment, the apparatus further comprises a voltage regulator between the via and the metallization network.

[0125] In one or more fourth embodiments, in addition to the first to third embodiments, the base die includes a plurality of through vias, the vias, the voltage regulator and the metallization network include power routing to the second metallization layer stack, and the through vias include input / output routing to the first metallization layer stack.

[0126] In one or more fifth embodiments, in addition to the first to fourth embodiments, the device also includes a second integrated circuit die, which is above the base die and coupled to the base die, and the second integrated circuit die is laterally adjacent to the integrated circuit die, so that the metallization network includes a signal path between the integrated circuit die and the second integrated circuit die.

[0127] In one or more sixth embodiments, in addition to the first to fifth embodiments, the device also includes a second integrated circuit die, which is directly coupled to the metallization network, so that the second integrated circuit die includes a second device layer between a third metallization layer stack and a fourth metallization layer stack, and the third metallization layer stack is adjacent to the metallization network and has fewer metallization layers than the fourth metallization layer stack.

[0128] In one or more seventh embodiments, in addition to the first to sixth embodiments, the metallization network has a total thickness, and the device further comprises: a component in contact with the metallization network and within the total thickness of the metallization network.

[0129] In one or more eighth embodiments, in addition to the first to seventh embodiments, the metallization network includes one of a plurality of substantially planar metal lines or a plurality of wire bonds.

[0130] In one or more ninth embodiments, in addition to the first to eighth embodiments, the thickest metallization layer in the first metallization layer stack has a first thickness that is less than a second thickness of the thinnest metallization layer in the second metallization layer stack.

[0131] In one or more tenth embodiments, in addition to the first to ninth embodiments, each metallization layer of the metallization network has a thickness no less than ten times the thickness of either the first metallization layer stack or the second metallization layer stack.

[0132] In one or more eleventh embodiments, in addition to the first to tenth embodiments, the apparatus further comprises a microelectronic board, such that the via and the base die are mounted to the microelectronic board.

[0133] In one or more twelfth embodiments, a system includes an integrated circuit package of any one of the apparatuses of the first to tenth embodiments, and a microelectronic board coupled to the integrated circuit package.

[0134] In one or more thirteenth embodiments, an apparatus includes: an integrated circuit die over and coupled to a base die, the integrated circuit die comprising a device layer between a front side metallization and a back side metallization, the front side metallization being proximate to the base die; a metallization network over and coupled to the back side metallization; and vias laterally adjacent to the base die, the vias coupled to the metallization network and extending to external interconnects.

[0135] In one or more fourteenth embodiments, in addition to the thirteenth embodiment, the device further comprises a metallized die comprising a substrate and the metallization network, such that the substrate comprises silicon and the metallization network comprises metal traces embedded in an inorganic dielectric material.

[0136] In one or more fifteenth embodiments, in addition to the thirteenth or fourteenth embodiment, the device further comprises a voltage regulator between the via and the metallization network, such that the base die comprises a plurality of through vias, the vias, the voltage regulator and the metallization network comprise power routing to the backside metallization, and the through vias comprise input / output routing to the frontside metallization.

[0137] In one or more sixteenth embodiments, in addition to the thirteenth to fifteenth embodiments, the device also includes a second integrated circuit die that is directly coupled to the metallization network, so that the second integrated circuit die includes a second device layer between a third metallization layer stack and a fourth metallization layer stack, and the third metallization layer stack is adjacent to the metallization network and has fewer metallization layers than the fourth metallization layer stack.

[0138] In one or more seventeenth embodiments, in addition to the thirteenth to sixteenth embodiments, the apparatus further comprises a microelectronic board, such that the via and the base die are mounted to the microelectronic board.

[0139] In one or more eighteenth embodiments, a system includes an integrated circuit package of any one of the apparatuses of the thirteenth to sixteenth embodiments, and a microelectronic board coupled to the integrated circuit package.

[0140] In one or more nineteenth embodiments, a method includes: mounting a first die to a second die, the first die including a device layer between a front side metallization layer and a back side metallization layer, wherein the front side metallization layer of the first die is mounted proximate to the second die; forming a via laterally adjacent to the second die; and forming a metallization network over and proximate to the back side metallization layer of the first die, the metallization network coupled to the via and the metallization network including one or more metallization layers, each metallization layer having a thickness not less than five times the thickness of any of the front side metallization layer and the back side metallization layer.

[0141] In one or more twentieth embodiments, in addition to the nineteenth embodiment, mounting the first die to the second die includes one of the following operations: placing the first die on a first reconstructed wafer including the second die, or placing the second die on a second reconstructed wafer including the first die.

[0142] In one or more twenty-first embodiments, in addition to the nineteenth or twentieth embodiments, forming the metallization network includes one of the following operations: wire bonding the second die to an adjacent third die, applying the metallization network directly to the second die, or placing a metallization die including a substrate and the metallization network on the second die.

[0143] In one or more twenty-second embodiments, in addition to the nineteenth to twenty-first embodiments, mounting the first die to the second die includes hybrid bonding the first die to the second die, and wherein forming the metallization network includes bonding a metallization die solder bump comprising a substrate and the metallization network to the second die.

[0144] However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may include only a subset of the features, a different order of the features, a different combination of the features, and / or other features in addition to those explicitly listed. Accordingly, the scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: an integrated circuit die over and coupled to a base die, the integrated circuit die including a device layer between a first metallization layer stack and a second metallization layer stack, the first metallization layer stack being proximate to the base die and having more metallization layers than the second metallization layer stack; a metallization network over the integrated circuit die and coupled to the second metallization layer stack, the metallization network comprising one or more metallization layers, each metallization layer having a thickness not less than five times the thickness of either the first metallization layer stack or the second metallization layer stack; as well as A via is laterally adjacent to the base die, the via being coupled to the metallization network.

2. The apparatus according to claim 1, further comprising: A metallized die comprises a substrate and the metallization network, wherein the substrate comprises silicon and the metallization network comprises metal traces embedded in an inorganic dielectric material.

3. The apparatus according to claim 1, further comprising: A voltage regulator is provided between the via and the metallization network.

4. The device according to claim 3, wherein The base die includes a plurality of through vias, wherein the vias, the voltage regulator, and the metallization network include power routing to the second metallization layer stack, and wherein the through vias include input / output routing to the first metallization layer stack.

5. The apparatus according to claim 4, further comprising: A second integrated circuit die is over and coupled to the base die, the second integrated circuit die being laterally adjacent to the integrated circuit die, wherein a metallization network includes a signal path between the integrated circuit die and the second integrated circuit die.

6. The apparatus according to any one of claims 1 to 5, further comprising: A third integrated circuit die is directly coupled to the metallization network, wherein the third integrated circuit die includes a second device layer between a third metallization layer stack and a fourth metallization layer stack, the third metallization layer stack being adjacent to the metallization network and having fewer metallization layers than the fourth metallization layer stack.

7. The device according to any one of claims 1 to 5, wherein The metallization network has a total thickness, and the apparatus further comprises: A component in contact with the metallization network and within the total thickness of the metallization network.

8. The device according to any one of claims 1 to 5, wherein The metallization network includes one of a plurality of substantially planar metal lines or a plurality of wire bonds.

9. The device according to any one of claims 1 to 5, wherein The thickest metallization layer in the first metallization layer stack has a first thickness that is less than a second thickness of the thinnest metallization layer in the second metallization layer stack.

10. The device according to claim 9, wherein Each metallization layer of the metallization network has a thickness no less than ten times the thickness of either the first metallization layer stack or the second metallization layer stack.

11. The apparatus according to any one of claims 1 to 5, further comprising: A microelectronic board is provided, wherein the via and the base die are mounted to the microelectronic board.

12. A device comprising: an integrated circuit die over and coupled to a base die, the integrated circuit die including a device layer between a front side metallization and a back side metallization, the front side metallization being proximate to the base die; a metallization network over the integrated circuit die and coupled to the backside metallization; as well as A via is laterally adjacent to the base die, the via being coupled to the metallization network and extending to an external interconnect.

13. The apparatus according to claim 12, further comprising: A metallized die comprises a substrate and the metallization network, wherein the substrate comprises silicon and the metallization network comprises metal traces embedded in an inorganic dielectric material.

14. The apparatus according to claim 12, further comprising: A voltage regulator is provided between the via and the metallization network.

15. The device according to claim 14, wherein The base die includes a plurality of through vias, wherein the vias, the voltage regulator, and the metallization network include power routing to the backside metallization, and wherein the through vias include input / output routing to the frontside metallization.

16. The apparatus according to claim 12, further comprising: A second integrated circuit die is over and coupled to the base die, the second integrated circuit die being laterally adjacent to the integrated circuit die, wherein a metallization network includes a signal path between the integrated circuit die and the second integrated circuit die.

17. The apparatus according to any one of claims 12 to 16, further comprising: A third integrated circuit die is directly coupled to the metallization network, wherein the third integrated circuit die includes a second device layer between a second front-side metallization and a second back-side metallization.

18. The device according to any one of claims 12 to 16, wherein The metallization network has a total thickness, and the apparatus further comprises: A component in contact with the metallization network and within the total thickness of the metallization network.

19. The device according to any one of claims 12 to 16, wherein The metallization network includes one of a plurality of substantially planar metal lines or a plurality of wire bonds.

20. The device according to any one of claims 12 to 16, wherein The thickest metallization layer in the front-side metallization has a first thickness that is smaller than a second thickness of the thinnest metallization layer in the back-side metallization.

21. The apparatus according to any one of claims 12 to 16, further comprising: A microelectronic board is provided, wherein the via and the base die are mounted to the microelectronic board.

22. A method comprising: mounting a first die to a second die, the first die comprising a device layer between a front-side metallization layer and a back-side metallization layer, wherein the front-side metallization layer of the first die is mounted proximate to the second die; forming a via laterally adjacent to the second die; and A metallization network is formed over and proximate the backside metallization layer of the first die, the metallization network coupled to the via and comprising one or more metallization layers, each metallization layer having a thickness not less than five times a thickness of any of the frontside metallization layer and the backside metallization layer.

23. The method according to claim 22, wherein Mounting the first die to the second die comprises one of the following operations: placing the first die on a first reconstituted wafer including the second die; or The second die is placed on a second reconstituted wafer including the first die.

24. The method according to claim 22 or 23, wherein Forming the metallization network includes one of the following operations: wire bonding the second die to an adjacent third die; applying the metallization network directly to the second die; or A metallization die including a substrate and the metallization network is placed on the second die.

25. The method according to claim 22 or 23, wherein The mounting the first die to the second die includes hybrid bonding the first die to the second die, and wherein the forming the metallization network includes solder bump bonding a metallization die including a substrate and the metallization network to the second die.

Images