Semiconductor device and semiconductor module

Abstract

Embodiments of the present disclosure may provide a semiconductor device. The semiconductor device includes: a first semiconductor chip including a first power supply signal bump and a plurality of first input and output (input / output) bumps, the plurality of first input / output bumps including first power supply control input / output bumps; a second semiconductor chip including a second power signal bump and a plurality of second input / output bumps; a first power signal package ball electrically connected to the first power signal bump through a first power signal line; a second power signal packaging ball electrically connected to the second power signal bump through a second power signal line; and a power control package ball electrically connected to the first power control input / output bump through a power control line and electrically connected to the second power signal package ball through a connection line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0035519, filed on March 14, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor device and a semiconductor module. Background Art

[0004] As an example of a semiconductor device, a storage device may include a memory storing data. The storage device may include a controller controlling the operation of the memory.

[0005] In some cases, a storage device may include multiple memories or multiple controllers.

[0006] As the number of semiconductor chips such as memories and controllers included in a storage device increases, it may not be easy to implement a wiring structure for supplying signals to the plurality of semiconductor chips or to implement a method for operating the plurality of semiconductor chips. Summary of the Invention

[0007] The embodiments of the present disclosure may provide a method for easily implementing a structure for supplying signals to a semiconductor device including a plurality of semiconductor chips, and a method for simply implementing a method for operating the plurality of semiconductor chips included in the semiconductor device.

[0008] An embodiment of the present disclosure may provide a semiconductor device comprising: a first semiconductor chip comprising a first power signal bump and a plurality of first input and output (input / output) bumps, the plurality of first input / output bumps including a first power control input / output bump; a second semiconductor chip comprising a second power signal bump and a plurality of second input / output bumps; a first power signal package ball electrically connected to the first power signal bump through a first power signal line; a second power signal package ball electrically connected to the second power signal bump through a second power signal line; and a power control package ball electrically connected to the first power control input / output bump through a power control line and electrically connected to the second power signal package ball through a connecting line.

[0009] Embodiments of the present disclosure may provide a semiconductor device comprising: a first controller including a first power signal bump and a plurality of first input and output (input / output) bumps, the first power signal bump being electrically connected to a first power signal package ball; a second controller including a second power signal bump and a plurality of second input / output bumps, the second power signal bump being electrically isolated from the first power signal bump and electrically connected to at least one of the plurality of first input / output bumps; and at least one memory receiving a signal from at least one of the first controller or the second controller.

[0010] An embodiment of the present disclosure may provide a semiconductor module, comprising: a bottom substrate; a packaging substrate, arranged on the bottom substrate and comprising a first power signal packaging ball, a second power signal packaging ball and a power control packaging ball; a first semiconductor chip, arranged on the packaging substrate and comprising a first power signal bump and a first power control input and output (input / output) bump, the first power signal bump being electrically connected to the first power signal packaging ball through a first power signal line, and the first power control input / output bump being electrically connected to the power control packaging ball through a power control line; and a second semiconductor chip, arranged on the packaging substrate and comprising a second power signal bump, the second power signal bump being electrically connected to the second power signal packaging ball through a second power signal line, and being electrically connected to the first power control input / output bump.

[0011] According to the embodiments of the present disclosure, a structure for supplying signals to a plurality of semiconductor chips included in a semiconductor device and an operation method according to the signal supply can be simply implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a schematic configuration of a storage device according to an embodiment of the present disclosure;

[0013] Figure 2A and Figure 2B is a diagram showing a structure of a semiconductor module in which a memory device is provided according to an embodiment of the present disclosure;

[0014] Figure 3 is a diagram illustrating a schematic configuration of a plurality of controllers included in a storage device according to an embodiment of the present disclosure;

[0015] Figure 4 is a diagram illustrating a structure for providing signals to a plurality of controllers included in a storage device according to an embodiment of the present disclosure;

[0016] Figure 5 is a diagram illustrating another structure for providing signals to a plurality of controllers included in a storage device according to an embodiment of the present disclosure;

[0017] Figure 6 and Figure 7 It shows Figure 5 A diagram illustrating a method for starting multiple controllers included in a storage device;

[0018] Figure 8 is a diagram illustrating a connection structure between a plurality of controllers included in a storage device according to an embodiment of the present disclosure; and

[0019] Figure 9 and Figure 10 is a diagram illustrating another structure for providing signals to a plurality of controllers included in a storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In the following description of the embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of example, and the same reference numerals and symbols may be used in the drawings to represent the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of the embodiments of the present disclosure, when it is determined that the detailed description of well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure less clear, these descriptions will be omitted. Terms such as "including", "having", "comprising", "consisting of", and "formed of" used herein are generally intended to allow for the addition of other components unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0021] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0022] When it is mentioned that a first element is “connected or coupled”, “contacted or overlapped”, etc. with a second element, it should be understood that the first element may not only be “directly connected or coupled” or “directly contacted or overlapped” with the second element, but also that a third element may be “interposed” between the first and second elements, or that the first and second elements may be “connected or coupled”, “contacted or overlapped” with each other via a fourth element, etc. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled”, “contacted or overlapped”, etc. with each other.

[0023] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0024] Furthermore, when referring to any dimensions, relative sizes, etc., the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of the elements or features should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Furthermore, the term "may" fully encompasses all meanings of the term "can."

[0025] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a diagram illustrating a schematic configuration of a storage device 100 according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , the memory device 100 may include at least one memory 110. The memory device 100 may include a controller 120 that controls the operation of the memory 110. In the present disclosure, the memory device 100 may be referred to as a semiconductor device or a semiconductor package. In the present disclosure, the memory 110 and the controller 120 included in the memory device 100 may be referred to as a semiconductor chip or a chipset (chiplet).

[0028] The memory 110 may be, for example, a volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the memory 110 may be a non-volatile memory such as NAND flash memory, three-dimensional (3D) NAND flash memory, or NOR flash memory. In other embodiments, a portion of the memory 110 included in the storage device 100 may be a volatile memory, while another portion may be a non-volatile memory.

[0029] In some embodiments, memory 110 may be one of various types of memory, such as resistive RAM, phase change memory, magnetoresistive memory, ferroelectric memory, or spin injection magnetization reversal memory. In other embodiments, memory 110 may be internal processing memory (processing-in-memory) that includes arithmetic or data processing functions. In this disclosure, memory 110 may be referred to as a memory device.

[0030] The memory 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. The plurality of memory blocks may be divided into a plurality of banks, which are units controlled by the controller 120.

[0031] The controller 120 may receive a command from the outside (eg, the host device 200 ) and control the operation of the memory 110 based on the received command.

[0032] The controller 120 may transmit a command or address for controlling the operation of the memory 110 to the memory 110. The controller 120 may control, for example, an operation of writing data to the memory 110. The controller 120 may control an operation of reading data written to the memory 110. Data may be transmitted and received between the controller 120 and the memory 110.

[0033] The controller 120 may control a data saving operation (eg, a refresh operation or a patrol scrub operation) or an erase operation on data written into the memory 110 according to the type of the memory 110 .

[0034] The controller 120 may control the operation of the memory 110 based on a command received from the host device 200 .

[0035] The host device 200 may be, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital voice recorder, a digital voice player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or a mobile device capable of traveling under human control or autonomously (e.g., a vehicle, robot, or drone). Alternatively, the host device 200 may be a virtual / augmented reality (VR / AR) device that provides two-dimensional (2D) or three-dimensional (3D) virtual reality images or augmented reality images. The host device 200 may be any of various electronic devices requiring a storage device 100 capable of storing data.

[0036] The host device 200 may include at least one operating system. The operating system may generally manage and control the functions and operations of the host device 200, and may control the mutual operation between the host device 200 and the storage device 100. Depending on the mobility of the host device 200, the operating system may be divided into a general operating system and a mobile operating system.

[0037] The controller 120 and the host device 200 may be separate devices. In some embodiments, the controller 120 and the host device 200 may be integrated and implemented as a single device, or some components or functions of the controller 120 may be implemented as included in the host device 200. Hereinafter, for convenience, the controller 120 and the host device 200 are described as separate devices.

[0038] Each of the controller 120 and the memory 110 included in the storage device 100 can be provided as a semiconductor chip. The controller 120 and the memory 110 can be provided in the form of separate semiconductor packages. Alternatively, the controller 120 and the memory 110 can be provided in the form of a single semiconductor package. In some embodiments, the storage device 100 may include a semiconductor package having a semiconductor chip in addition to the controller 120 and the memory 110.

[0039] Figure 2A and Figure 2B 1 is a diagram illustrating a structure of a semiconductor module in which a memory device 100 is provided according to an embodiment of the present disclosure.

[0040] Reference Figure 2A and Figure 2B , shows a structure in which the controller 120 and the memory 110 included in the storage device 100 are implemented in a single package. The controller 120 and the memory 110 may be provided on a package substrate 130, for example. The package substrate 130 may be a substrate formed of silicon, for example, but the embodiments of the present disclosure are not limited thereto.

[0041] Each of the controller 120 and the memory 110 may be coupled to a plurality of bumps BMP. In some cases, the plurality of bumps BMP may be part of the controller 120 or the memory 110. Each of the plurality of bumps BMP may be electrically connected to the package substrate 130. The package substrate 130 may include a plurality of package balls PKGB. Each of the plurality of package balls PKGB may be electrically connected to the bump BMP.

[0042] A semiconductor package including the controller 120 and the memory 110 may be provided on the base substrate 400 .

[0043] The base substrate 400 and the semiconductor package provided on the base substrate 400 may be collectively referred to as a semiconductor module. The semiconductor module may include at least one semiconductor chip or circuit in addition to a semiconductor package such as the memory device 100.

[0044] For example, a power management circuit or a power management integrated circuit (PMIC) 300 may be provided on the base substrate 400. The power management circuit 300 may be located outside the memory device 100. In some embodiments, the power management circuit 300 may be included in the memory device 100. In this case, the controller 120, the memory 110, and the power management circuit 130 are provided in the form of a single semiconductor package and may constitute the memory device 100.

[0045] The power management circuit 300 is located outside the memory device 100 and can supply power to the memory device 100. The power management circuit 300 can be electrically connected to the package balls PKGB included in the package substrate 130 of the memory device 100. The power supplied by the power management circuit 300 can be supplied to a semiconductor chip such as the controller 120 or the memory 110 through the package balls PKGB and the bumps BMP electrically connected to the package balls PKGB.

[0046] The controller 120 or the memory 110 included in the storage device 100 may receive other power or control signals through another package ball PKGB included in the package substrate 130. For example, the controller 120 may receive power or control signals from the package ball PKGB and the bump BMP. Figure 1 The host device 200 transmits the signal.

[0047] The memory device 100 may include a plurality of memories 110, or may include a plurality of controllers 120. The plurality of controllers 120 included in the memory device 100 may provide various control structures.

[0048] Figure 3 is a diagram illustrating a schematic configuration of a plurality of controllers 120 included in a storage device 100 according to an embodiment of the present disclosure.

[0049] Reference Figure 3 , the storage device 100 may include a plurality of controllers 120 , for example, a first controller 121 and a second controller 122 . In some embodiments, the storage device 100 may include at least one memory 110 . Figure 3 An embodiment in which the storage device 100 includes two controllers 120 is shown, but embodiments of the present disclosure may be applicable even if three or more controllers 120 are included in the storage device 100 .

[0050] The first controller 121 may include a first host interface 121a, a first memory interface 121b, and a first link interface (LINK 1) 121c. The first host interface 121a may be referred to as a first host control terminal (HCT1), and the first memory interface 121b may be referred to as a first device control terminal (DCT1). The second controller 122 may include a second host interface 122a, a second memory interface 122b, and a second link interface (LINK 2) 122c. The second host interface 122a may be referred to as a second host control terminal (HCT2), and the second memory interface 122b may be referred to as a second device control terminal (DCT2).

[0051] The first host interface 121a and the second host interface 122a can provide Figure 1 The function of communicating with the host device 200.

[0052] In some embodiments, one of the first host interface 121a and the second host interface 122a can communicate with the host device 200. For example, the first host interface 121a can communicate with the host device 200, and the second host interface 122a can be in an inactive state. The first controller 121 can be referred to as a main controller, and the second controller 122 can be referred to as a sub-controller.

[0053] The first memory interface 121b and the second memory interface 122b may provide Figure 1 The number of memory interfaces included in each controller 120 may be two or more. Some memories 110 may be controlled by the first controller 121, and other memories 110 may be controlled by the second controller 122.

[0054] All memory interfaces included in each controller 120 may be activated to communicate with the individual memories 110 .

[0055] Optionally, some of the memory interfaces included in each controller 120 may be activated. For example, the second memory interface 122b included in the second controller 122 may be in an activated state, and the first memory interface 121b included in the first controller 121 may be in an inactivated state.

[0056] The first link interface 121c and the second link interface 122c may provide a function of performing communication between the controllers 120. When the first controller 121 communicates with the host device 200, a command or data may be transmitted to the second controller 122 through the first link interface 121c.

[0057] As such, communication between the host device 200 , the controller 120 , and the memory 110 may be performed through each interface included in the first controller 121 and the second controller 122 .

[0058] As in the above-described embodiment, the components included in the first controller 121 and the second controller 122 may correspond to each other, and some of the components may be activated and operated. Alternatively, the components included in the first controller 121 and the second controller 122 may be different from each other. For example, the first controller 121 may include a first host interface 121a and a first link interface 121c, and the second controller 122 may include a second memory interface 122b and a second link interface 122c.

[0059] Each of the first controller 121 and the second controller 122 may be implemented in the form of a single chip. Alternatively, the various interfaces included in each of the first controller 121 and the second controller 122 may be implemented in the form of a separate chipset. Each interface may be implemented as a chipset, or some functions of each interface may be combined to be implemented as a chipset.

[0060] Since the storage device 100 includes a plurality of controllers 120 and each of the plurality of controllers 120 provides various interfaces, the capacity of the memory 110 provided by the storage device 100 can be increased and the performance can be improved.

[0061] The embodiments of the present disclosure may provide a method of efficiently implementing a structure of providing a signal to each semiconductor chip in a structure in which the number of semiconductor chips included in the memory device 100 increases.

[0062] Figure 4 is a diagram illustrating a structure for providing signals to a plurality of controllers 120 included in a storage device 100 according to an embodiment of the present disclosure.

[0063] Reference Figure 4 The storage device 100 includes a first controller 121 and a second controller 122. The first controller 121 may include a first host interface 121a, a first memory interface 121b, and a first link interface (LINK1) 121c. The first host interface 121a may be referred to as a first host control terminal (HCT1), and the first memory interface 121b may be referred to as a first device control terminal (DCT1). The second controller 122 may include a second host interface 122a, a second memory interface 122b, and a second link interface (LINK2) 122c. The second host interface 122a may be referred to as a second host control terminal (HCT2), and the second memory interface 122b may be referred to as a second device control terminal (DCT2).

[0064] Some components included in the first controller 121 and the second controller 122 may be in an active state or an inactive state. In some embodiments, the first controller 121 and the second controller 122 may include only active components.

[0065] Each of the first controller 121 and the second controller 122 may include a plurality of bumps BMP. Each of the first controller 121 and the second controller 122 may receive power or a signal through the plurality of bumps BMP.

[0066] The first controller 121 may include, for example, a first power signal bump PS_BMP_1 , first mode signal bumps MS_BMP_11 , MS_BMP_12 , and a plurality of first input and output (input / output) bumps IO_BMP_1 .

[0067] The second controller 122 may include, for example, a second power signal bump PS_BMP_2 , second mode signal bumps MS_BMP_21 , MS_BMP_22 , and a plurality of second input / output bumps IO_BMP_2 .

[0068] At least some of the plurality of bumps BMP included in the first and second controllers 121 and 122 may be electrically connected to the package balls PKGB included in the package substrate 130 .

[0069] The first power signal bump PS_BMP_1 may be electrically connected to the first power signal package ball PS_PKGB_1 through the first power signal line 131 , and the second power signal bump PS_BMP_2 may be electrically connected to the second power signal package ball PS_PKGB_2 through the second power signal line 132 .

[0070] The first power signal bump PS_BMP_1 and the second power signal bump PS_BMP_2 may be electrically isolated from each other. The first power signal line 131 and the second power signal line 132 may be lines disposed on or included in the package substrate 131 .

[0071] The first power signal package ball PS_PKGB_1 and the second power signal package ball PS_PKGB_2 can receive power signals from the outside.

[0072] For example, the first power signal package ball PS_PKGB_1 and the second power signal package ball PS_PKGB_2 may receive power from the power management circuit 300 and provide the power to the first controller 121 and the second controller 122 .

[0073] Each of the first and second controllers 121 and 122 may operate based on power received through the first and second power signal bumps PS_BMP_1 and PS_BMP_2 .

[0074] The first mode signal bumps MS_BMP_11 and MS_BMP_12 may be electrically connected to the first mode signal package balls MS_PKGB_11 and MS_PKGB_12 through the first mode signal line 133. The second mode signal bumps MS_BMP_21 and MS_BMP_22 may be electrically connected to the second mode signal package balls MS_PKGB_21 and MS_PKGB_22 through the second mode signal line 134.

[0075] The first mode signal line 133 and the second mode signal line 134 may be provided on the package substrate 130 or may be included in the package substrate 130 .

[0076] The first controller 121 and the second controller 122 may operate as a main controller or a sub-controller based on a signal input through a mode signal bump.

[0077] For example, a signal "1" may be input to one first mode signal bump MS_BMP_11 of the first controller 121, and a signal "0" may be input to another first mode signal bump MS_BMP_12. A signal "0" may be input to one second mode signal bump MS_BMP_21 of the second controller 122, and a signal "1" may be input to another second mode signal bump MS_BMP_22. The first controller 121 may operate as a main controller, and the second controller 122 may operate as a sub-controller. The first controller 121 may communicate with the host device 200 and the second controller 122. The first controller 121 may communicate with the memory 110. The second controller 122 may communicate with both the first controller 121 and the memory 110.

[0078] Among the bumps BMP included in the first controller 121 and the second controller 122, bumps other than the power signal bump and the mode signal bump may share a package ball PKGB. For example, the first input / output bump IO_BMP_1 and the second input / output bump IO_BMP_2 may be electrically connected to the same input / output package ball IO_PKGB through the input / output line 135.

[0079] The first and second input / output bumps IO_BMP_1 and IO_BMP_2 may be electrically connected to the input / output package balls IO_PKGB.

[0080] The first input / output bump IO_BMP_1 and the second input / output bump IO_BMP_2 electrically connected to the shared input / output package ball IO_PKGB may be one of various bumps BMP included in the first and second controllers 121 and 122 .

[0081] For example, the first input / output bump IO_BMP_1 and the second input / output bump IO_BMP_2 may include a bump BMP for communication, such as an inter-integrated circuit (I2C) and an improved inter-integrated circuit (I3C), a bump BMP for a control signal, such as a general-purpose input / output (GPIO), and a bump BMP for debugging, such as a universal asynchronous receiver / transmitter (UART).

[0082] The first input / output bump IO_BMP_1 and the second input / output bump IO_BMP_2 may include bumps BMP for testing.

[0083] The bumps BMP for testing may include, for example, a test mode bump, a test input bump, and a test output bump. The test type of the controller 120 may be determined based on the signal input to the test mode bump. The input signal for testing may be received through the test input bump, and the output signal according to the test may be output through the test output bump.

[0084] The package ball PKGB electrically connected to the test input / output bump may be referred to as a test package ball.

[0085] Even when the test input / output bumps of the first controller 121 and the test input / output bumps of the second controller 122 are electrically connected to a shared test package ball, a test can be performed on each controller 120 by controlling the input / output states of the bumps BMP of the first controller 121 and the second controller 122. The control of the input / output states can be performed through signals transmitted and received between the first controller 121 and the second controller 122.

[0086] Alternatively, the controller 120 to be tested may be determined based on a signal input through a mode signal bump.

[0087] Each of the first and second controllers 121 and 122 may set an input / output state of the test input / output bumps based on signals input to the first and second mode signal bumps MS_BMP_11 and MS_BMP_12 and MS_BMP_21 and MS_BMP_22 .

[0088] A test can be performed on the controller 120, wherein the input / output state of the test input / output bump of the controller 120 to be tested between the first controller 121 and the second controller 122 is set to the output state, and the input / output state of the test input / output bump of the other controller 120 is set to the input state, thereby setting the input / output state of the test input / output bump to the output state.

[0089] By sharing the package balls PKGB connected to various input / output bumps in addition to the bumps BMP connected to input / output signals for testing as described above, the number of package balls PKGB included in the memory device 100 can be reduced.

[0090] In a structure where the package balls PKGB included in the memory device 100 are shared by a plurality of controllers 120, the power signal bumps of each controller 120 may be electrically connected to separate package balls PKGB. The first power signal package ball PS_PKGB_1 and the second power signal package ball PS_PKGB_2 may be provided separately from each other.

[0091] The first controller 121 and the second controller 122 may operate based on power received through the first power signal package ball PS_PKGB_1 and the second power signal package ball PS_PKGB_2 , respectively.

[0092] The first controller 121 and the second controller 122 may perform a boot operation based on signals received through the first power signal package ball PS_PKGB_1 and the second power signal package ball PS_PKGB_2, respectively. The boot operations of the first controller 121 and the second controller 122 may be performed based on signals transmitted and received between the first controller 121 and the second controller 122.

[0093] Figure 5 is a diagram illustrating another structure for providing signals to a plurality of controllers 120 included in a memory device 100 according to an embodiment of the present disclosure.

[0094] Reference Figure 5 , the first controller 121 may include a first power signal bump PS_BMP_1 , first mode signal bumps MS_BMP_11 and MS_BMP_12 , a first input / output bump IO_BMP_1 , a first boot image input / output bump BIIO_BMP_1 , and a first power control input / output bump PCIO_BMP_1 .

[0095] The second controller 122 may include a second power signal bump PS_BMP_2 , second mode signal bumps MS_BMP_21 and MS_BMP_22 , a second input / output bump IO_BMP_2 , a second boot image input / output bump BIIO_BMP_2 , and a second power control input / output bump PCIO_BMP_2 .

[0096] The first power signal bump PS_BMP_1 may be electrically connected to the first power signal package ball PS_PKGB_1 through the first power signal line 131. The first mode signal bumps MS_BMP_11 and MS_BMP_12 may be electrically connected to the first mode signal package balls MS_PKGB_11 and MS_PKGB_12 through the first mode signal line 133.

[0097] The second power signal bump PS_BMP_2 may be electrically connected to the second power signal package ball PS_PKGB_2 through the second power signal line 132. The second mode signal bumps MS_BMP_21 and MS_BMP_22 may be electrically connected to the second mode signal package balls MS_PKGB_21 and MS_PKGB_22 through the second mode signal line 134.

[0098] The first and second input / output bumps IO_BMP_1 and IO_BMP_2 may be electrically connected to a shared input / output package ball IO_PKGB through an input / output line 135 .

[0099] Among the first input / output bumps IO_BMP_1, the first power control input / output bump PCIO_BMP_1 may be electrically connected to the power control package ball PCIO_PKGB through the power control line 136. The power control package ball PCIO_PKGB may be electrically connected to the second power signal package ball PS_PKGB_2 through the connection line 401. For example, the connection line 401 may be provided on the base substrate 400 or may be included in the base substrate 400.

[0100] In some embodiments, the first power control input / output bump PCIO_BMP_1 may be electrically connected to the second power signal bump PS_BMP_2 through a line on the package substrate 130 .

[0101] A structure may be provided in which a signal output through the first power control input / output bump PCIO_BMP_1 may be input to the second power signal bump PS_BMP_2 through the second power signal package ball PS_PKGB_2.

[0102] The first power control input / output bump PCIO_BMP_1 may be electrically connected to the second power control input / output bump PCIO_BMP_2 through the power control line 136. The second power control input / output bump PCIO_BMP_2 may be electrically connected to the power control package ball PCIO_PKGB.

[0103] The first boot image input / output bump BIIO_BMP_1 of the first input / output bump IO_BMP_1 can be electrically connected to the boot image package ball BIIO_PKGB through the boot image line 137. The boot image package ball BIIO_PKGB can be electrically connected to the boot memory 500, in which a boot image used during booting is stored. The boot memory 500 can be a non-volatile memory, such as a flash memory, but the embodiment is not limited thereto.

[0104] The first boot image input / output bump BIIO_BMP_1 may be electrically connected to the second boot image input / output bump BIIO_BMP_2 through a boot image line 137. The second boot image input / output bump BIIO_BMP_2 may be electrically connected to the boot image package ball BIIO_PKGB.

[0105] In a structure in which some of the package balls PKGB are shared by the first and second controllers 121 and 122 , startup operations of the first and second controllers 121 and 122 may be performed by electrically connecting the first power control input / output bump PCIO_BMP_1 of the first controller 121 and the second power signal bump PS_BMP_2 of the second controller 122 .

[0106] Figure 6 and Figure 7 It shows Figure 5 FIG. 1 is a diagram illustrating a method for starting multiple controllers included in the storage device 100.

[0107] Reference Figure 6 , the first controller 121 can perform a startup operation based on a signal received via the first power signal package ball PS_PKGB_1, as shown in ①. For example, the first controller 121 can receive a power-good signal from the power management circuit 300. The power-good signal can be a signal indicating that the power output from the power management circuit 300 is normal. The power management circuit 300 can output the power-good signal when the power is equal to or greater than a required threshold level, or when the power is within the range required to operate the memory device 100.

[0108] When a power good signal is received according to the power supply of the power management circuit 300 , as shown in ②, the first controller 121 may perform a boot operation by receiving a boot image from the boot memory 500 .

[0109] The first controller 121 may maintain the signal level of the first power control input / output bump PCIO_BMP_1 at the first level during a period in which the booting operation is performed.

[0110] When the boot operation is completed, the first controller 121 may change the signal level of the first power control input / output bump PCIO_BMP_1 to a second level different from the first level. According to the change in the signal level of the first power control input / output bump PCIO_BMP_1, a signal indicating the start of the boot operation may be input to the second power signal bump PS_BMP_2.

[0111] The second controller 122 may perform a startup operation based on a signal input to the second power signal bump PS_BMP_2. When the startup operation of the first controller 121 is performed and the signal level of the first power control input / output bump PCIO_BMP_1 is at the first level, the second controller 122 may wait for a period of time. When the signal level of the first power control input / output bump PCIO_BMP_1 changes to the second level, the second controller 122 may perform a startup operation based on the corresponding signal.

[0112] In some embodiments, the second controller 122 may also receive a power good signal from the power management circuit 300 via the second power signal package ball PS_PKGB_2 and perform a startup action. In some embodiments, the startup timing of the first controller 121 and the second controller 122 may be controlled by the power management circuit 300 or an external control signal.

[0113] Since the second controller 122 performs the boot-up operation based on the signal received from the first controller 121 , the boot-up operation may be sequentially performed in a semiconductor package including a plurality of semiconductor chips.

[0114] The signal provided to the second power signal package ball PS_PKGB_2 can be provided through the power control package ball PCIO_PKGB shared by the first power control input / output bump PCIO_BMP_1 of the first controller 121 and the second power control input / output bump PCIO_BMP_2 of the second controller 122. A structure for sequential startup operation of the first controller 121 and the second controller 122 can be implemented without adding the package ball PKGB.

[0115] When a signal indicating the start of a boot operation is received via the second power signal bump PS_BMP_2, the second controller 122 can receive a boot image from the boot memory 500 via the boot image package ball BIIO_PKGB, as shown in FIG. The boot image can be input to the second controller 122 via the boot image line 137 and the second boot image input / output bump BIIO_BMP_2. During the corresponding time period, the input / output state of the first boot image input / output bump BIIO_BMP_1 of the first controller 121 can be set to an input state, thereby not affecting the operation of the second controller 122 using the second boot image input / output bump BIIO_BMP_2.

[0116] The process of the booting operation performed by the first controller 121 and the second controller 122 may be divided as follows.

[0117] Reference Figure 7 , the startup operations performed by the first controller 121 and the second controller 122 are shown separately. Figure 7 In the embodiment, the first controller 121 is referred to as a first chipset, and the second controller 122 is referred to as a second chipset.

[0118] The first controller 121 may receive a power good signal from the power management circuit 300 (S710). After receiving the power good signal, the first controller 121 may perform a boot operation (S711). The first controller 121 may load a boot image (BI) from the boot memory (e.g., flash memory) 500 (S712). The first controller 121 may perform a boot operation by loading the main firmware (FW or F / W) from the boot memory 500 (S713). The main firmware stored in the secure area may be loaded into the non-secure area. The secure area and the non-secure area may be physical memory areas. The secure area may represent an area that only the controller 120 can access and use. The first controller 121 may complete the boot operation (S714).

[0119] When the booting operation is completed, the first controller 121 may set an input / output (I / O or IO) state of the input / output bump ( S715 ).

[0120] For example, the first controller 121 may set the input / output state of the first input / output bump IO_BMP_1 to an input state.

[0121] The first controller 121 may set the input / output state of the first input / output bump IO_BMP_1 to the input state of the shared package ball PKGB (ie, shared ball IO direction input), and may not affect the operation of the second controller 122 that is to perform a subsequent boot operation.

[0122] The first controller 121 may set only the input / output state of the first power control input / output bump PCIO_BMP_1 to an output state, and set the input / output states of the remaining first input / output bumps IO_BMP_1 to an input state. For example, the first controller 121 may change only the setting value GPIO[xx] corresponding to the first power control input / output bump PCIO_BMP_1 from "0" to "1" (S716).

[0123] Based on a change in the signal level or set value of the first power control input / output bump PCIO_BMP_1, the second controller 122 may begin a boot operation (S720). The second controller 122 may load a boot image (BI) from the boot memory (e.g., flash memory) 500 (S721). The second controller 122 may perform a boot operation by loading the main firmware (F / W) from the boot memory 500 (S722). The main firmware stored in the secure area may be loaded into the non-secure area. The secure area and the non-secure area may be physical memory regions. The secure area may represent an area that only the controller 120 can access and use. The boot operation of the second controller 122 may then be completed (S723).

[0124] When the booting operation is completed, the second controller 122 may set an input / output state of the second input / output bump IO_BMP_2 ( S724 ).

[0125] Since the booting of the first and second controllers 121 and 122 is completed, the first and second controllers 121 and 122 may communicate with each other through the first and second link interfaces 121 c and 122 c to set input / output states of the first and second input / output bumps IO_BMP_1 and IO_BMP_2 ( S725 ).

[0126] In a structure sharing the input / output package balls IO_PKGB electrically connected to the first and second input / output bumps IO_BMP_1 and IO_BMP_2, operations of the first and second controllers 121 and 122 may be normally performed by adjusting input / output states of the first and second input / output bumps IO_BMP_1 and IO_BMP_2.

[0127] In some embodiments, even if three or more controllers 120 are included in the storage device 100 , the booting method of the controller 120 included in the storage device 100 according to an embodiment of the present disclosure may be similarly applied.

[0128] Figure 8is a diagram illustrating a connection structure between a plurality of controllers 120 included in a storage device 100 according to an embodiment of the present disclosure.

[0129] Reference Figure 8 The storage device 100 includes N controllers 121, 122, 123, and 124. The N controllers 120 included in the storage device 100 can be connected using a daisy chain method, for example. In this embodiment, the startup operation of the second controller 122 can be initiated based on the output signal of the first controller 121, and the startup operation of the third controller 123 can be initiated based on the output signal of the second controller 122.

[0130] Alternatively, as Figure 8 As shown, the startup operations of the remaining controllers 120 may be performed based on the output signal of the first controller 121 corresponding to the main controller.

[0131] For example, the first controller 121 may perform a boot operation based on the power good signal output from the power management circuit 300. When the boot operation is completed, the first controller 121 may transmit a signal indicating the start of the boot operation to the second controller 122.

[0132] When the booting operation of the second controller 122 is completed, the first controller 121 may transmit a signal indicating the start of the booting operation to the third controller 123 .

[0133] In some embodiments, the power control package ball PCIO_PKGB electrically connected to the first power control input / output bump PCIO_BMP_1 of the first controller 121 may be electrically connected to the second power signal package ball PS_PKGB_2 electrically connected to the second power signal bump PS_BMP_2 of the second controller 122 and to the third power signal package ball electrically connected to the third power signal bump of the third controller 123. By adjusting the input / output states of the input / output bumps of the controller 120 that has completed the boot operation, the boot operations of the plurality of controllers 120 may be sequentially performed.

[0134] Since the booting operations of the remaining controllers 120 are controlled by the first controller 121 , even if an operation error occurs in one of the sub-controllers (the remaining controllers 120 ), the booting operations of the remaining sub-controllers can be performed normally, compared to the daisy chain method.

[0135] As described above, embodiments of the present disclosure can facilitate implementation of a semiconductor device by arranging at least some of the package balls PKGB in a shared structure, such as a memory device 100 including multiple semiconductor chips. Furthermore, the startup operations of the multiple semiconductor chips can be sequentially performed by electrically connecting the input / output bumps of the main controller (main semiconductor chip) and the power signal bumps of the sub-controllers (sub-semiconductor chips).

[0136] Furthermore, the embodiments of the present disclosure can further reduce the number of package balls PKGB included in the semiconductor device through a shared structure of the package balls PKGB except for the power signal package balls.

[0137] Figure 9 and Figure 10 is a diagram illustrating another structure for providing signals to a plurality of controllers 120 included in a memory device 100 according to an embodiment of the present disclosure.

[0138] Reference Figure 9 The first controller 121 may include a first power signal bump PS_BMP_1, first mode signal bumps MS_BMP_11 and MS_BMP_12, and a first input / output bump IO_BMP_1. The second controller 121 may include a second power signal bump PS_BMP_2, second mode signal bumps MS_BMP_21 and MS_BMP_22, and a second input / output bump IO_BMP_2.

[0139] The first power signal bump PS_BMP_1 may be electrically connected to the first power signal package ball PS_PKGB_1 through the first power signal line 131 , and the second power signal bump PS_BMP_2 may be electrically connected to the second power signal package ball PS_PKGB_2 through the second power signal line 132 .

[0140] One of the first mode signal bumps MS_BMP_11 and MS_BMP_12 may be electrically connected to the first mode signal package ball MS_PKGB_1 through the first mode signal line 133. One of the second mode signal bumps MS_BMP_21 and MS_BMP_22 may be electrically connected to the first mode signal package ball MS_PKGB_1 through the first mode signal line 133.

[0141] The other of the first mode signal bumps MS_BMP_11 and MS_BMP_12 may be electrically connected to the second mode signal package ball MS_PKGB_2 through the second mode signal line 134. The other of the second mode signal bumps MS_BMP_21 and MS_BMP_22 may be electrically connected to the second mode signal package ball MS_PKGB_2 through the second mode signal line 134.

[0142] In a structure in which the first and second mode signal bumps MS_BMP_11 and MS_BMP_12 share a package ball PKGB with the second mode signal bumps MS_BMP_21 and MS_BMP_22 , modes of the first and second controllers 121 and 122 may be controlled by signals supplied to the first and second mode signal package balls MS_PKGB_1 and MS_PKGB_2 .

[0143] For example, a signal of level "1" may be provided to the first mode signal package ball MS_PKGB_1, and a signal of level "0" may be provided to the second mode signal package ball MS_PKGB_2. The first controller 121 may receive "10" via the first mode signal bumps MS_BMP_11 and MS_BMP_12, and the second controller 122 may receive "01" via the second mode signal bumps MS_BMP_21 and MS_BMP_22. The first controller 121 may operate as a master controller, and the second controller 122 may operate as a slave controller.

[0144] Thus, the operation modes of the plurality of controllers 120 included in the memory device 100 can be set while further reducing the number of package balls PKGB.

[0145] Furthermore, in some embodiments, the number of mode signal package balls may be further reduced, and the operation mode of the controller 120 may be set.

[0146] Reference Figure 10 The first controller 121 may include various bumps BMP and may include first mode signal bumps MS_BMP_11 and MS_BMP_12. The second controller 122 may include various bumps BMP and may include second mode signal bumps MS_BMP_21 and MS_BMP_22.

[0147] One of the first mode signal bumps MS_BMP_11 and MS_BMP_12 and one of the second mode signal bumps MS_BMP_21 and MS_BMP_22 may be electrically connected to the first mode signal package ball MS_PKGB_1 through the first mode signal line 133 .

[0148] The other of the first mode signal bumps MS_BMP_11 and MS_BMP_12 and the other of the second mode signal bumps MS_BMP_21 and MS_BMP_22 may be electrically connected to each other and grounded, so that a signal of level 0 may be input to the corresponding mode signal bumps.

[0149] The first controller 121 and the second controller 122 may set an operation mode based on a signal input through the first mode signal package ball MS_PKGB_1 and a signal input through the grounded second mode signal line 134 and operate as a main controller or a sub-controller.

[0150] In a structure in which a plurality of controllers 120 are included in the memory device 100 , it is possible to reduce the number of package balls PKGB and simply implement a structure of operation mode setting and signal supply for operations of the plurality of controllers 120 .

[0151] Based on the above-described embodiments of the present disclosure, the operation delay time of the memory system can be advantageously reduced or minimized. In addition, based on the embodiments of the present disclosure, the overhead incurred in the process of calling specific functions can be advantageously reduced or minimized. Although various embodiments of the present disclosure have been described with specific details and variations for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions, and substitutions can be made based on the content disclosed or shown in this disclosure without departing from the spirit and scope of the present disclosure as defined in the following claims. In addition, the embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device comprising: A first semiconductor chip including a first power signal bump and a plurality of first input and output bumps, i.e., a plurality of first input / output bumps, the plurality of first input / output bumps including a first power control input / output bump; a second semiconductor chip comprising a second power signal bump and a plurality of second input / output bumps; a first power signal package ball electrically connected to the first power signal bump through a first power signal line; a second power signal package ball electrically connected to the second power signal bump through a second power signal line; as well as The power control package ball is electrically connected to the first power control input / output bump through a power control line and is electrically connected to the second power signal package ball through a connection line.

2. The semiconductor device according to claim 1, wherein The first semiconductor chip performs a startup operation when receiving a power control signal through the first power signal bump, and maintains a signal level of the first power control input / output bump at a first level while performing the startup operation.

3. The semiconductor device according to claim 2, wherein When the startup operation is completed, the first semiconductor chip changes the signal level of the first power control input / output bump from the first level to a second level.

4. The semiconductor device according to claim 3, wherein When the signal level of the first power control input / output bump changes to the second level, the second semiconductor chip performs the startup operation.

5. The semiconductor device according to claim 3, wherein When the signal level of the first power control input / output bump changes to the second level, the first semiconductor chip sets the input / output state of at least one remaining input / output bump other than the first power control input / output bump among the plurality of first input / output bumps to an input state. The semiconductor device according to claim 2 , wherein: The plurality of first input / output bumps include a first boot image input / output bump, and The first semiconductor chip receives a boot image from the outside through the first boot image input / output bump and performs the boot operation based on the boot image.

7. The semiconductor device according to claim 6, wherein The plurality of second input / output bumps include second boot image input / output bumps electrically connected to the first boot image input / output bumps through a boot image line. 8 . The semiconductor device according to claim 7 , further comprising a boot image package ball electrically connected to the first boot image input / output bump and the second boot image input / output bump through the boot image line.

9. The semiconductor device according to claim 1, further comprising at least one mode signal package ball, in, The first semiconductor chip further includes at least one first mode signal bump, the second semiconductor chip further includes at least one second mode signal bump, and The at least one mode signal package ball is electrically connected to at least one of the at least one first mode signal bump or the at least one second mode signal bump.

10. The semiconductor device according to claim 9, wherein The at least one mode signal package ball comprises: at least one first mode signal package ball electrically connected to the at least one first mode signal bump through a first mode signal line; and At least one second-mode signal package ball is electrically connected to the at least one second-mode signal bump through a second-mode signal line electrically isolated from the first-mode signal line.

11. The semiconductor device according to claim 9, wherein The at least one mode signal package ball includes a first mode signal package ball electrically connected to one of the at least one first mode signal bump and one of the at least one second mode signal bump through a first mode signal line.

12. The semiconductor device according to claim 11, wherein The at least one mode signal package ball further includes a second mode signal package ball electrically connected to another one of the at least one first mode signal bump and another one of the at least one second mode signal bump through a second mode signal line.

13. The semiconductor device according to claim 11, wherein Another one of the at least one first mode signal bump and another one of the at least one second mode signal bump are electrically connected to each other and to ground.

14. The semiconductor device according to claim 9, further comprising at least one test package ball, in, The plurality of first input / output bumps include at least one first test input / output bump, and the plurality of second input / output bumps include at least one second test input / output bump, and The at least one test package ball is electrically connected to at least one of the at least one first test input / output bump or the at least one second test input / output bump.

15. The semiconductor device according to claim 14, wherein A test target is determined between the first semiconductor chip and the second semiconductor chip based on a test control signal input through the at least one first mode signal bump and the at least one second mode signal bump.

16. The semiconductor device according to claim 1, wherein The first power signal package ball and the second power signal package ball are electrically isolated from each other.

17. The semiconductor device according to claim 1, further comprising a third semiconductor chip including a third power signal bump and a plurality of third input / output bumps, in, The third power signal bump is electrically isolated from the plurality of second input / output bumps and is electrically connected to at least one of the plurality of first input / output bumps except the first power control input / output bump.

18. A semiconductor device comprising: A first controller including a first power signal bump and a plurality of first input and output bumps, i.e., a plurality of first input / output bumps, wherein the first power signal bump is electrically connected to the first power signal package ball; a second controller including a second power signal bump and a plurality of second input / output bumps, the second power signal bump being electrically isolated from the first power signal bump and electrically connected to at least one of the plurality of first input / output bumps; as well as At least one memory receives a signal from at least one of the first controller or the second controller.

19. A semiconductor module comprising: bottom substrate; A packaging substrate, disposed on the base substrate and comprising a first power signal packaging ball, a second power signal packaging ball, and a power control packaging ball; a first semiconductor chip disposed on the package substrate and comprising a first power signal bump and a first power control input and output bump, i.e., a first power control input / output bump, the first power signal bump being electrically connected to the first power signal package ball via a first power signal line, the first power control input / output bump being electrically connected to the power control package ball via a power control line; and A second semiconductor chip is disposed on the package substrate and includes a second power signal bump electrically connected to the second power signal package ball through a second power signal line and electrically connected to the first power control input / output bump.

20. The semiconductor module according to claim 19, further comprising a power management circuit provided on the base substrate, in, The first power signal package ball is electrically connected to the power management circuit, and The second power signal package ball is electrically connected to the power control package ball through a connection line included in the base substrate.

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