Semiconductor element with neck layer and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method of the semiconductor element. The semiconductor element comprises a substrate; at least a two-bit line structure located on the substrate; a contact layer located on the substrate and located between the at least two bit line structures; and a conductive neck layer on the contact layer and between the at least two bit line structures. A width of an upper surface of the conductive neck layer is greater than a width of a lower surface of the conductive neck layer.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2024106250199, filed on May 20, 2024, with the invention name of "Semiconductor element with neck layer and preparation method thereof". Application No. 2024106250199 claims priority and benefits of U.S. formal application No. 18 / 606,384 filed on March 15, 2024. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a neck layer and a method for manufacturing the semiconductor device having the neck layer. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor device sizes are steadily shrinking to meet the increasing demand for computing power. However, during this process of shrinking, various challenges arise, and these challenges continue to increase. Consequently, achieving improvements in quality, yield, performance, and reliability, while reducing complexity, remains a constant challenge.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor device comprising a substrate; at least two bit-line structures disposed on the substrate; a contact layer disposed on the substrate and between the at least two bit-line structures; and a conductive neck layer disposed on the contact layer and between the at least two bit-line structures. The conductive neck layer has an upper surface with a width greater than a lower surface with a width.

[0006] Another embodiment of the present disclosure provides a semiconductor device comprising a substrate; at least two bit-line structures disposed on the substrate and spaced apart from each other, each comprising a bit-line conductive layer disposed on the substrate and a bit-line capping layer disposed on the bit-line conductive layer; a plurality of inner gap sub-layers conformally disposed on respective sides of the at least two bit-line structures; a plurality of outer gap sub-layers conformally disposed on the plurality of inner gap sub-layers; a contact layer disposed on the substrate and between the at least two bit-line structures; and a conductive neck layer disposed on the contact layer and between the at least two bit-line structures. A width of an upper surface of the bit-line capping layer is smaller than a width of a lower surface of the bit-line capping layer.

[0007] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising providing a substrate; forming at least two bitline structures on the substrate; forming at least two separation layers on the substrate, wherein the at least two separation layers and the at least two bitline structures together surround a contact opening; forming a contact layer on the substrate and within the contact opening; and forming a conductive neck layer on the contact layer to completely fill the contact opening. A width of an upper surface of the conductive neck layer is greater than a width of a lower surface of the conductive neck layer.

[0008] Due to the design of the semiconductor element disclosed herein, the overlap window between the conductive neck layer and the landing pad can be increased by adopting a wider upper surface of the conductive neck layer, thereby reducing defects and complexity in manufacturing the semiconductor element.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When with Figure 1 Various aspects of the present disclosure will be best understood from the following detailed description when read together. It should be understood that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0013] Figure 3 is a cross-sectional schematic diagram, illustrating Figure 2 Sections along the median lines A-A', B-B', and C-C'.

[0014] Figure 4 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0015] Figure 5 is a cross-sectional schematic diagram, illustrating Figure 4Sections along the median lines A-A', B-B', and C-C'.

[0016] Figure 6 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0017] Figure 7 is a cross-sectional schematic diagram, illustrating Figure 6 Sections along the median lines A-A', B-B', and C-C'.

[0018] Figure 8 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0019] Figure 9 and Figure 10 is a cross-sectional schematic diagram, illustrating Figure 8 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 11 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0021] Figure 12 is a cross-sectional schematic diagram, illustrating Figure 11 Sections along the median lines A-A', B-B', and C-C'.

[0022] Figure 13 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0023] Figure 14 and Figure 15 is a cross-sectional schematic diagram, illustrating Figure 13 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 16 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0025] Figure 17 is a cross-sectional schematic diagram, illustrating Figure 16 Sections along the median lines A-A', B-B', and C-C'.

[0026] Figure 18 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0027] Figure 19 、 Figure 20 and Figure 21 is a cross-sectional schematic diagram, illustrating Figure 18The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device according to an embodiment of the present disclosure.

[0028] Figure 22 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0029] Figure 23 and Figure 24 is a cross-sectional schematic diagram, illustrating Figure 22 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 25 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0031] Figure 26 is a cross-sectional schematic diagram, illustrating Figure 25 Sections along the median lines A-A', B-B', and C-C'.

[0032] Figure 27 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0033] Figure 28 is a cross-sectional schematic diagram, illustrating Figure 27 Sections along the median lines A-A', B-B', and C-C'.

[0034] Figure 29 and Figure 30 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0035] The description of the accompanying drawings is as follows:

[0036] 10: Preparation method

[0037] 1A: Semiconductor components

[0038] 1B: Semiconductor components

[0039] 1C: Semiconductor components

[0040] 101: Base

[0041] 103: Isolation layer

[0042] 105: Impurity region

[0043] 105-1: Shared source region

[0044] 105-3: Drain region

[0045] 107: Lower dielectric layer

[0046] 109: Upper dielectric layer

[0047] 200: Character line structure

[0048] 201: word line dielectric layer

[0049] 203: Character line barrier layer

[0050] 205: word line conductive layer

[0051] 207: Character line cover layer

[0052] 300: Bit line structure

[0053] 300S: Side

[0054] 301: conductive layer on the bit line

[0055] 303: Bit line intermediate conductive layer

[0056] 305: Bit line conductive layer

[0057] 307: Bit line mask layer

[0058] 307BS: lower surface

[0059] 307TS: upper surface

[0060] 309: Bit line contact

[0061] 401: Inner gap sublayer

[0062] 401TS: Top surface

[0063] 403: Outer gap sublayer

[0064] 403TS: Top surface

[0065] 501: Contact layer

[0066] 503: Conductive neck layer

[0067] 503BS: bottom surface

[0068] 503TS: Top surface

[0069] 505: Landing Pad

[0070] 601: Separator layer

[0071] 601TS: Top surface

[0072] 701: First mask layer

[0073] 801: Sacrificial layer

[0074] 803: Isolation materials

[0075] 805: First conductive material

[0076] 807: Second conductive material

[0077] AA: Active Area

[0078] CP1: Arrow

[0079] CP2: Arrow

[0080] CP3: Arrow

[0081] FS: First Side

[0082] OP1: Partition opening

[0083] OP2: contact opening

[0084] P1: Line pattern

[0085] S11: Steps

[0086] S13: Steps

[0087] S15: Steps

[0088] S17: Steps

[0089] SS: Second side

[0090] TR: character line groove

[0091] W1: width

[0092] W2: width

[0093] W3: Width

[0094] W4: Width

[0095] W5: width

[0096] X: Direction

[0097] Y: direction

[0098] Z: Direction DETAILED DESCRIPTION

[0099] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0100] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0101] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0102] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0103] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, terms such as substantially the same, substantially equal, or substantially planar may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable variance, which may occur, for example, due to a manufacturing process.

[0104] In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor devices.

[0105] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0106] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 3 is a cross-sectional schematic diagram, illustrating Figure 2Sections along the median lines A-A', B-B', and C-C'. Figure 4 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 5 is a cross-sectional schematic diagram, illustrating Figure 4 Sections along the median lines A-A', B-B', and C-C'.

[0107] Please refer to Figures 1 to 5 In step S11 , a substrate 101 is provided, an isolation layer 103 is formed in the substrate 101 to define a plurality of active areas AA, and a plurality of word line structures 200 may be formed in the substrate 101 and intersect the plurality of active areas AA.

[0108] Please refer to Figure 2 and Figure 3 The substrate 101 may include a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other Group III-V compound semiconductors or Group II-VI compound semiconductors; or a combination thereof.

[0109] In some embodiments, the substrate 101 may include a semiconductor-on-insulator structure, which consists of a processing substrate, an insulator layer, and a topmost semiconductor material layer from bottom to top. The processing substrate and the topmost semiconductor material layer may include the same materials as the aforementioned bulk semiconductor substrate. The insulator layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulator layer may be a dielectric oxide, such as silicon oxide. As another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulator layer may include a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulator layer may have a thickness between about 10 nm and about 200 nm. The insulator layer may eliminate leakage current between adjacent components in the substrate 101 and reduce parasitic capacitance associated with the source / drain.

[0110] It should be understood that the use of the term "about" in the description of the present disclosure refers to variations in the amounts of ingredients, compositions, or reactants of the present disclosure, such as variations in amounts that may occur due to typical measurements and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used to make compositions or implement methods, and the like. In one aspect, the term "about" refers to within 10% of the reported value. In another aspect, the term "about" refers to within 5% of the reported value. Furthermore, in another aspect, the term "about" refers to within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0111] Please refer to Figure 2 and Figure 3 , an isolation layer 103 can be formed in the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A lithography process and a subsequent etching process, such as an anisotropic dry etching process, can be performed to form a plurality of trenches that penetrate the pad oxide layer, the pad nitride layer and extend to the substrate 101. An insulating material can be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, can be subsequently performed until the upper surface of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the isolation layer 103. For example, the insulating material can be silicon oxide or other suitable insulating materials. The isolation layer 103 can define a plurality of active areas AA in the substrate 101.

[0112] It should be understood that in the description of this disclosure, the surface of a component (or feature) located at the highest vertical plane along the Z axis is referred to as the upper surface of the component (or feature). The surface of a component (or feature) located at the lowest vertical plane along the Z axis is referred to as the lower surface of the component (or feature).

[0113] It should be understood that each of the plurality of active areas AA may include a portion of the substrate 101 and a space above the portion of the substrate 101. Describing an element as being disposed on the active area AA means that the element is disposed on the upper surface of the portion of the substrate 101. Describing an element as being disposed in the active area AA means that the element is disposed in the portion of the substrate 101; however, the upper surface of the element may be flush with the upper surface of the portion of the substrate 101. Describing an element as being disposed above the active area AA means that the element is disposed above the upper surface of the portion of the substrate 101.

[0114] Please refer to Figure 2 and Figure 3, multiple impurity regions 105 can be formed in multiple active regions AA respectively. In some embodiments, the manufacturing technology of the multiple impurity regions 105 can include an implantation process. That is, the multiple impurity regions 105 can be transformed from multiple parts of the multiple active regions AA. The dopants of the implantation process can include p-type impurities (dopants) or n-type impurities (dopants). P-type impurities can be added to the intrinsic semiconductor to produce valence electron defects. In a silicon-containing substrate, examples of p-type dopants (i.e., impurities) include boron, aluminum, gallium, and indium, but are not limited thereto. N-type impurities can be added to the intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants (i.e., impurities) include antimony, arsenic, and phosphorus, but are not limited thereto. In some embodiments, the doping concentration of the multiple impurity regions 105 can be about 1E19 atoms / cm 3 to about 1E21 atoms / cm 3 After the implantation process, the plurality of impurity regions 105 may have an electrical type such as n-type or p-type.

[0115] Please refer to Figure 4 and Figure 5 , a plurality of word line trenches TR may be formed in the substrate 101 to define the positions of the plurality of word line structures 200. The fabrication technology of the plurality of word line trenches TR may include a lithography process and a subsequent etching process. In some embodiments, the plurality of word line trenches TR may have a linear cross-sectional profile and extend along the direction X and cross (or intersect) the plurality of impurity regions 105 in the top view. For example, each impurity region 105 may intersect two word line trenches TR. The plurality of word line trenches TR may divide each of the plurality of impurity regions 105 into a plurality of common source regions 105-1 and a plurality of drain regions 105-3. For one impurity region 105, one common source region 105-1 may be formed between the two word line trenches TR, and two drain regions 105-3 may be formed respectively between the isolation layer 103 and the two word line trenches TR.

[0116] Please refer to Figure 4 and Figure 5 Multiple word line structures 200 (e.g., two word line structures 200) can be formed in corresponding word line trenches TR (e.g., two word line trenches TR). For brevity, clarity, and convenience, only one word line structure 200 is described. The word line structure 200 may include a word line dielectric layer 201, a word line barrier layer 203, a word line conductive layer 205, and a word line cap layer 207.

[0117] Please refer to Figure 4 and Figure 5, the word line dielectric layer 201 can be conformally formed on the inner surface of the word line trench TR. The word line dielectric layer 201 can have a U-shaped cross-sectional profile. In other words, the word line dielectric layer 201 can be formed inwardly in the active area AA. In some embodiments, the fabrication technology of the word line dielectric layer 201 can include a thermal oxidation process. For example, the fabrication technology of the word line dielectric layer 201 can include oxidizing the inner surface of the word line trench TR. In some embodiments, the fabrication technology of the word line dielectric layer 201 can include a deposition process, such as chemical vapor deposition or atomic layer deposition. The word line dielectric layer 201 can include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer (not shown for clarity), the fabrication technology of the word line dielectric layer 201 can include free radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the fabrication technique of the word line dielectric layer 201 may include radical oxidation of the pad silicon nitride layer.

[0118] In some embodiments, the high-k material may include a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0119] Please refer to Figure 4 and Figure 5 The wordline barrier layer 203 may be conformally formed on the wordline dielectric layer 201 and within the wordline trench TR. In some embodiments, for example, the wordline barrier layer 203 may include titanium nitride, titanium, or a combination thereof. In some embodiments, for example, the wordline barrier layer 203 may include titanium nitride. In some embodiments, for example, the wordline barrier layer 203 may be formed using atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0120] Please refer to Figure 4 and Figure 5 A wordline conductive layer 205 may be formed on the wordline barrier layer 203 and within the wordline trench TR. In some embodiments, to form the wordline conductive layer 205, a conductive layer (not shown for clarity) may be formed to fill the wordline trench TR, and a recessing process may then be performed. The recessing process may be performed as an etch-back process or as a planarization process and an etch-back process performed sequentially. The wordline conductive layer 205 may have a recessed shape that partially fills the wordline trench TR. That is, the upper surface of the wordline conductive layer 205 may be lower than the upper surface of the substrate 101.

[0121] In some embodiments, the word line conductive layer 205 may include a metal, a metal nitride, or a combination thereof. For example, the word line conductive layer 205 may include titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, the titanium nitride / tungsten may have a structure in which tungsten is used to partially fill the word line trench TR. Titanium nitride or tungsten may be used alone for the word line conductive layer 205. In some embodiments, for example, the word line conductive layer 205 may include a conductive material such as doped polysilicon, doped polysilicon germanium, or a combination thereof. In some embodiments, for example, the word line conductive layer 205 may include tungsten, aluminum, titanium, copper, the like, or a combination thereof.

[0122] Please refer to Figure 4 and Figure 5 For example, a dielectric material (not shown) may be deposited by chemical vapor deposition to completely fill the word line trench TR and cover the upper surface of the substrate 101. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps and to form the word line capping layer 207. In some embodiments, for example, the word line capping layer 207 may include silicon nitride or other suitable dielectric materials.

[0123] Figure 6 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 7 is a cross-sectional schematic diagram, illustrating Figure 6 Sections along the median lines A-A', B-B', and C-C'. Figure 8 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 9 and Figure 10 is a cross-sectional schematic diagram, illustrating Figure 8 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure.

[0124] Please refer to Figure 1 and Figures 6 to 10 In step S13 , a plurality of bit line structures 300 may be formed on the substrate 101 , an inner gap sub-layer 401 may be conformally formed over the substrate 101 , and an outer gap sub-layer 403 may be conformally formed on the inner gap sub-layer 401 .

[0125] Please refer to Figure 6 and Figure 7, a lower dielectric layer 107 may be formed on the substrate 101. In some embodiments, the lower dielectric layer 107 may include a material having an etch selectivity to the substrate 101 and the isolation layer 103. In some embodiments, for example, the lower dielectric layer 107 may include silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, silicon boron carbon nitride, or a combination thereof. In some embodiments, for example, the lower dielectric layer 107 may include silicon nitride. In some embodiments, for example, the fabrication technique of the lower dielectric layer 107 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0126] Please refer to Figure 6 and Figure 7 A plurality of bit line contacts 309 may be formed to respectively penetrate the lower dielectric layer 107 and extend to the plurality of common source regions 105-1. In some embodiments, for example, the plurality of bit line contacts 309 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. In some embodiments, the plurality of bit line contacts 309 may have a square cross-sectional profile in top view, but is not limited to this shape. In some embodiments, the plurality of bit line contacts 309 may have a rectangular, circular, or other suitable cross-sectional profile in top view.

[0127] Please refer to Figure 8 and Figure 9 , multiple bit line structures 300 can be formed on the lower dielectric layer 107 and electrically connected to the multiple bit line contacts 309, respectively. In the top view, the multiple bit line structures 300 can extend along the direction Y and be spaced apart from each other. In other words, in the top view, the multiple bit line structures 300 can intersect the multiple word line structures 200. For the sake of brevity, clarity, and convenience, only one bit line structure 300 is described. In some embodiments, the bit line structure 300 can include a bit line conductive layer 301 and a bit line cap layer 307.

[0128] A bitline conductive layer 301 may be formed on and electrically connected to the bitline contact 309. In some embodiments, for example, the bitline conductive layer 301 may include titanium nitride, tungsten, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof. A bitline capping layer 307 may be formed on the bitline conductive layer 301. In some embodiments, for example, the bitline capping layer 307 may include silicon nitride or other suitable insulating materials.

[0129] Please refer to Figure 10An inner gap sub-layer 401 may be formed over the substrate 101 to cover the plurality of bit line structures 300 and the lower dielectric layer 107. Specifically, the inner gap sub-layer 401 may be conformally formed on the lower dielectric layer 107, the side edges 300S of the plurality of bit line structures 300, and the upper surfaces 307TS of the plurality of bit line structures 300. In some embodiments, for example, the inner gap sub-layer 401 may include silicon oxide or other suitable insulating oxides. In some embodiments, for example, the inner gap sub-layer 401 may be fabricated using atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0130] Please refer to Figure 10 The outer gap sub-layer 403 can be conformally formed on the inner gap sub-layer 401. In some embodiments, the outer gap sub-layer 403 can include the same material as the bit line cap layer 307. In some embodiments, for example, the outer gap sub-layer 403 can include silicon nitride or other suitable insulating materials. In some embodiments, for example, the outer gap sub-layer 403 can be formed using atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0131] Figure 11 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 12 is a cross-sectional schematic diagram, illustrating Figure 11 Sections along the median lines A-A', B-B', and C-C'. Figure 13 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 14 and Figure 15 is a cross-sectional schematic diagram, illustrating Figure 13 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure. Figure 16 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 17 is a cross-sectional schematic diagram, illustrating Figure 16 Sections along the median lines A-A', B-B', and C-C'.

[0132] It should be understood that some elements are omitted in the top view for clarity.

[0133] Please refer to Figure 1 and Figures 11 to 17In step S15, a sacrificial layer 801 may be formed between the plurality of bit line structures 300, a first mask layer 701 including a line pattern P1 may be formed on the sacrificial layer 801 to partially expose the sacrificial layer 801 and the outer gap sub-layer 403, the sacrificial layer 801 may be selectively partially removed to form a plurality of partition openings OP1, and a plurality of partition layers 601 may be formed in the plurality of partition openings OP1.

[0134] Please refer to Figure 11 and Figure 12 , a sacrificial layer 801 can be formed over the lower dielectric layer 107 to cover the plurality of bit line structures 300, the inner gap sub-layer 401, and the outer gap sub-layer 403. In some embodiments, for example, the sacrificial layer 801 can include a material having an etching selectivity to the outer gap sub-layer 403. In some embodiments, for example, the sacrificial layer 801 can include silicon oxynitride, silicon nitride oxide, or other suitable materials. In some embodiments, for example, the fabrication technique of the sacrificial layer 801 can include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, can be performed until the upper surface 403TS of the outer gap sub-layer 403 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0135] It should be understood that in the description of this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0136] Please refer to Figure 11 and Figure 12 A first mask layer 701 may be formed on the sacrificial layer 801. In some embodiments, the first mask layer 701 may be a photoresist layer. In a top view, the line pattern P1 of the first mask layer 701 may include a plurality of rectangular spaces extending along the X-direction and alternately arranged along the Y-direction. These spaces partially expose the sacrificial layer 801 and the outer gap sub-layer 403.

[0137] Please refer to Figure 13 and Figure 14 , the sacrificial layer 801 exposed by the line pattern P1 of the first mask layer 701 can be selectively removed. In some embodiments, the sacrificial layer 801 can be removed by an anisotropic etching process, such as an anisotropic dry etching process. After removing the sacrificial layer 801, a plurality of partition openings OP1 can be formed at locations where the sacrificial layer 801 is exposed by the line pattern P1 of the first mask layer 701. After forming these partition openings OP1, the first mask layer 701 can then be removed.

[0138] Please refer to Figure 15 A layer of isolation material 803 may be formed over the sacrificial layer 801 to completely fill the plurality of partition openings OP1. In some embodiments, the isolation material 803 may be a material having an etch selectivity to the sacrificial layer 801. In some embodiments, the isolation material 803 may be the same material as the bit line cap layer 307 or the outer gap sub-layer 403. In some embodiments, for example, the isolation material 803 may include silicon nitride or other suitable insulating materials. In some embodiments, for example, the layer of isolation material 803 may be formed using chemical vapor deposition or other suitable deposition processes.

[0139] Please refer to Figure 16 and Figure 17 A planarization process, such as chemical mechanical polishing, may be performed until the upper surface 403TS of the outer spacer sub-layer 403 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and convert the layer of isolation material 803 into a plurality of spacer layers 601. In top view, each of the plurality of spacer layers 601 may have a linear (or rectangular) cross-sectional profile extending along the X-direction. The plurality of spacer layers 601 may be arranged alternately along the X-direction, with each corresponding bit line structure 300 located between two adjacent spacer layers 601. In the Y-direction, the plurality of spacer layers 601 may be arranged alternately with sacrificial layers 801 interposed therebetween. In top view, the configuration of the plurality of spacer layers 601 and the plurality of bit line structures 300 may divide the sacrificial layer 801 into a plurality of segments.

[0140] Figure 18 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 19 and Figure 21 is a cross-sectional schematic diagram, illustrating Figure 18 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure. Figure 22 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 23 and Figure 24 is a cross-sectional schematic diagram, illustrating Figure 22 The cross sections along the lines AA′, BB′, and CC′ illustrate a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure. Figure 25 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 26 is a cross-sectional schematic diagram, illustrating Figure 25 Sections along the median lines A-A', B-B', and C-C'. Figure 27 FIG. 1 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 28 is a cross-sectional schematic diagram, illustrating Figure 27 Sections along the median lines A-A', B-B', and C-C'.

[0141] Please refer to Figure 1 and Figures 18 to 28 In step S17, the sacrificial layer 801 may be selectively removed to form a plurality of contact openings OP2, a plurality of contact layers 501 may be formed in the plurality of contact openings OP2, a plurality of conductive neck layers 503 may be formed on the plurality of contact layers 501, and a plurality of landing pads 505 may be formed on the plurality of conductive neck layers 503.

[0142] Please refer to Figure 18 and Figure 19 , the sacrificial layer 801 can be selectively removed by an etching process. For example, the removal of the sacrificial layer 801 can be achieved by an anisotropic etching process. After removing the sacrificial layer 801, a plurality of contact openings OP2 can be formed in the positions previously occupied by the sacrificial layer 801 (in a multi-segment form). For the sake of brevity, clarity and convenience of description, only one contact opening OP2 is described. In the cross-sectional view, the contact opening OP2 can be disposed on the lower dielectric layer 107. In the top view, the contact opening OP2 can be surrounded by two spacer layers 601 adjacent in the Y direction and two bit line structures 300 adjacent in the X direction (with an inner gap sublayer 401 and an outer gap sublayer 403 disposed therebetween).

[0143] In some embodiments, during the anisotropic etching process, the etch selectivity for silicon oxide and the etch selectivity for silicon nitride can be similar. In some embodiments, the etch selectivity for silicon oxide can be slightly greater than the etch selectivity for silicon nitride. For example, during the anisotropic etching process, the etch rate ratio of silicon oxide to silicon nitride can be between about 3.0 and about 1.1, between about 2.0 and about 1.1, or between about 1.5 and about 1.2. Due to the comparable etch rates of silicon oxide and silicon nitride, the inner gap sub-layer 401, the outer gap sub-layer 403, and the bit line cap layer 307 can also be partially consumed during the removal of the sacrificial layer 801.

[0144] In some embodiments, the inner gap sub-layer 401, the outer gap sub-layer 403, and the bit line capping layer 307 adjacent to the sacrificial layer 801 may be consumed first. As a result, upper portions of the outer gap sub-layer 403, the inner gap sub-layer 401, and the bit line capping layer 307 adjacent to the plurality of contact openings OP2 may be thinned during the anisotropic etching process, resulting in tapered cross-sectional profiles and sloped side edges 300S in these regions, as indicated by arrows CP1 and CP2.

[0145] In contrast, in some embodiments, the outer gap sub-layer 403, the inner gap sub-layer 401, and the bit line capping layer 307 adjacent to the plurality of spacer layers 601 may experience less consumption than the outer gap sub-layer 403, the inner gap sub-layer 401, and the bit line capping layer 307 adjacent to the plurality of contact openings OP2. Therefore, the outer gap sub-layer 403, the inner gap sub-layer 401, and the bit line capping layer 307 adjacent to the plurality of spacer layers 601 may maintain a rectangular cross-sectional profile and vertical sides 300S in a cross-sectional view, as indicated by arrow CP3.

[0146] Please refer to Figure 20 A breakdown etching process may be performed to remove portions of the outer gap sub-layer 403, the inner gap sub-layer 401, and the lower dielectric layer 107 exposed through the plurality of contact openings OP2. In some embodiments, the etching process may be an anisotropic dry etching process. The anisotropic dry etching process may deepen the plurality of contact openings OP2 into the substrate 101. The breakdown etching process may separate the lower dielectric layer 107, the inner gap sub-layer 401, and the outer gap sub-layer 403 into a plurality of portions, respectively. After the breakdown etching process, the plurality of drain regions 105-3 may be exposed through the plurality of contact openings OP2.

[0147] Please refer to Figure 21 A layer of first conductive material 805 can be conformally formed to fill the plurality of contact openings OP2. In some embodiments, for example, the first conductive material 805 can be doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. In some embodiments, the first conductive material 805 can include a p-type dopant or an n-type dopant. In some embodiments, for example, the first conductive material 805 can be fabricated using atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0148] Please refer to Figure 22 and 23 , an etch-back process may be performed to remove portions of the first conductive material 805. After the etch-back process, the remaining first conductive material 805 may be converted into a plurality of contact layers 501 within the plurality of contact openings OP2, respectively. For the sake of brevity, clarity, and convenience of description, only one contact layer 501 is described. In some embodiments, in a top view, the contact layer 501 may have a square or rectangular cross-sectional profile. The contact layer 501 may be surrounded by two adjacent separation layers 601 along the Y direction and two adjacent bit line structures 300 along the X direction (with an inner gap sublayer 401 and an outer gap sublayer 403 disposed therebetween). The contact layer 501 may be electrically connected to the corresponding drain region 105-3.

[0149] Please refer to Figure 24A layer of second conductive material 807 may be formed to completely fill the plurality of contact openings OP2 and cover the outer spacer sub-layer 403, the inner spacer sub-layer 401, the plurality of bit line structures 300, and the plurality of separation layers 601. In some embodiments, for example, the second conductive material 807 may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. In some embodiments, for example, the second conductive material 807 may be titanium nitride, titanium, tungsten, or a combination thereof.

[0150] Please refer to Figure 25 and Figure 26 A planarization process, such as chemical mechanical polishing, can be performed until the upper surfaces 307TS of the plurality of bitline cap layers 307 are exposed, thereby removing excess material and providing a substantially flat surface for subsequent processing steps. After the planarization process, the remaining second conductive material 807 can be transformed into a plurality of conductive neck layers 503. The plurality of conductive neck layers 503 can be formed on the plurality of contact layers 501, respectively.

[0151] For simplicity, clarity, and convenience, only one conductive neck layer 503 is described. In some embodiments, in a top view, the conductive neck layer 503 may be surrounded by two adjacent spacer layers 601 along the Y direction and two adjacent bit line structures 300 along the X direction (with the inner gap sublayer 401 and the outer gap sublayer 403 disposed therebetween). In some embodiments, the width W1 of the top surface 503TS of the conductive neck layer 503 may be greater than the width W2 of the bottom surface 503BS of the conductive neck layer 503. In some embodiments, the ratio of the width W1 of the top surface 503TS of the conductive neck layer 503 to the width W2 of the bottom surface 503BS of the conductive neck layer 503 may be between approximately 2.0 and approximately 1.3, between approximately 1.8 and approximately 1.3, and between approximately 1.7 and approximately 1.4.

[0152] In some embodiments, the conductive neck layer 503 may include two first side edges FS. The two first side edges FS may contact the side edges 300S of the corresponding pair of adjacent bit line structures 300, with the inner gap sublayer 401 and the outer gap sublayer 403 disposed therebetween. Specifically, the inner gap sublayer 401 may be disposed between the bit line structure 300 and the conductive neck layer 503, while the outer gap sublayer 403 may be disposed between the inner gap sublayer 401 and the conductive neck layer 503. In some embodiments, the two first side edges FS may be inclined to conform to the contour of the outer gap sublayer 403. The inclined first side edges FS may enable the conductive neck layer 503 to have a cross-sectional profile that tapers toward the contact layer 501. In some embodiments, the conductive neck layer 503 may include two second side edges SS. The two second side edges SS may contact the corresponding spacer layer 601. In some embodiments, the two second side edges SS may be perpendicular to the first side edges FS.

[0153] In some embodiments, a width W3 of the upper surface 307TS of the bit line capping layer 307 adjacent to the conductive neck layer 503 may be narrower than a width W4 of the upper surface 307TS of the bit line capping layer 307 adjacent to the separation layer 601. Therefore, in the top view, the widths W3 and W4 of the upper surface 307TS of the bit line structure 300 may alternately vary along the direction Y.

[0154] In some embodiments, a width W3 of the upper surface 307TS of the bit line cap layer 307 adjacent to the conductive neck layer 503 may be narrower than a width W5 of the lower surface 307BS of the bit line cap layer 307 .

[0155] In some embodiments, the upper surface 307TS of the bit line structure 300 , the upper surface 401TS of the inner gap sub-layer 401 , the upper surface 403TS of the outer gap sub-layer 403 , the upper surface 503TS of the conductive neck layer 503 , and the upper surface 601TS of the spacer layer 601 may be substantially coplanar.

[0156] Please refer to Figure 27 and Figure 28 , an upper dielectric layer 109 can be formed over the substrate 101 to completely cover the plurality of spacer layers 601, the plurality of inner gap sub-layers 401, the plurality of outer gap sub-layers 403, the plurality of conductive neck layers 503, and the plurality of bit line structures 300. In some embodiments, for example, the upper dielectric layer 109 can include silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric layer, a chemical vapor deposited low-k dielectric layer, or a combination thereof. The term "low-k" as used throughout this disclosure refers to a dielectric material having a dielectric constant less than that of silicon dioxide. In some embodiments, the upper dielectric layer 109 can include a self-planarizing material, such as spin-on glass or a spin-on low-k dielectric material, such as SiLK TMThe use of a self-planarizing dielectric material can avoid the need to perform a subsequent planarization step. In some embodiments, for example, the fabrication technique of the upper dielectric layer 109 can include a deposition process including chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating.

[0157] Please refer to Figure 27 and Figure 28 , a plurality of landing pads 505 may be formed to penetrate the upper dielectric layer 109. The plurality of landing pads 505 may be formed on the plurality of conductive neck layers 503, respectively. For the sake of brevity, clarity, and convenience of description, only one landing pad 505 is described. In some embodiments, in a top view, the landing pad 505 may partially overlap with the conductive neck layer 503. In some embodiments, the landing pad 505 may include the same material as the conductive neck layer 503. In some embodiments, for example, the landing pad 505 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof.

[0158] By adopting a wider upper surface 503TS of the conductive neck layer 503, the overlap window of the conductive neck layer 503 and the landing pad 505 can be increased. As a result, defects (eg, stack misalignment) and complexity in manufacturing the semiconductor element 1A can be reduced.

[0159] Figure 29 and Figure 30 1 is a schematic cross-sectional view illustrating semiconductor elements 1B and 1C according to some embodiments of the present disclosure.

[0160] Please refer to Figure 29 , the semiconductor element 1B may have a structure that Figure 28 The structure shown is similar. Figure 29 Zhongyu Figure 28 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0161] In the semiconductor device 1B, the bit-line structure 300 may include a bit-line lower conductive layer 305 , a bit-line intermediate conductive layer 303 , a bit-line upper conductive layer 301 , and a bit-line cap layer 307 .

[0162] The bit line under-conductive layer 305 may be disposed on the bit line contact 309. In some embodiments, for example, the bit line under-conductive layer 305 may include doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the dopant for the bit line under-conductive layer 305 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus.

[0163] The bit line intermediate conductive layer 303 may be disposed on the bit line lower conductive layer 305. In some embodiments, the bit line intermediate conductive layer 303 may include, for example, titanium silicide, nickel silicide, platinum nickel silicide, tantalum silicide, or cobalt silicide. In some embodiments, the bit line intermediate conductive layer 303 may have a thickness between approximately 2 nm and approximately 20 nm.

[0164] The bit line upper conductive layer 301 may be disposed on the bit line intermediate conductive layer 303. In some embodiments, for example, the bit line upper conductive layer 301 may include titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof.

[0165] The bit line capping layer 307 may be disposed on the bit line conductive layer 301. In some embodiments, for example, the bit line capping layer 307 may include silicon nitride or other suitable insulating materials.

[0166] Please refer to Figure 30 , the semiconductor element 1C may have a structure that Figure 28 The structure shown is similar. Figure 30 Zhongyu Figure 28 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0167] In the semiconductor element 1C, as Figure 28 As shown, there is no word line barrier layer 203. The word line conductive layer 205 can be directly disposed on the word line dielectric layer 201. In this embodiment, the word line conductive layer 205 can include titanium nitride.

[0168] One embodiment of the present disclosure provides a semiconductor device comprising a substrate; at least two bit-line structures disposed on the substrate; a contact layer disposed on the substrate and between the at least two bit-line structures; and a conductive neck layer disposed on the contact layer and between the at least two bit-line structures. The conductive neck layer has an upper surface with a width greater than a lower surface with a width.

[0169] Another embodiment of the present disclosure provides a semiconductor device comprising a substrate; at least two bit-line structures disposed on the substrate and spaced apart from each other, each comprising a bit-line conductive layer disposed on the substrate and a bit-line capping layer disposed on the bit-line conductive layer; a plurality of inner gap sub-layers conformally disposed on respective sides of the at least two bit-line structures; a plurality of outer gap sub-layers conformally disposed on the plurality of inner gap sub-layers; a contact layer disposed on the substrate and between the at least two bit-line structures; and a conductive neck layer disposed on the contact layer and between the at least two bit-line structures. A width of an upper surface of the bit-line capping layer is smaller than a width of a lower surface of the bit-line capping layer.

[0170] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising providing a substrate; forming at least two bitline structures on the substrate; forming at least two separation layers on the substrate, wherein the at least two separation layers and the at least two bitline structures together surround a contact opening; forming a contact layer on the substrate and within the contact opening; and forming a conductive neck layer on the contact layer to completely fill the contact opening. A width of an upper surface of the conductive neck layer is greater than a width of a lower surface of the conductive neck layer.

[0171] Due to the design of the semiconductor element of the present disclosure, the overlap window of the conductive neck layer 503 and the landing pad 505 can be increased by adopting a wider upper surface 503TS of the conductive neck layer 503. As a result, defects and complexity in manufacturing the semiconductor element 1A can be reduced.

[0172] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0173] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor device comprising: a base; At least two bit line structures are located on the substrate, spaced apart from each other, and each comprises: A conductive layer on a bit line on the substrate; and a bit line cap layer located on the bit line conductive layer; a plurality of inner gap sub-layers conformally positioned on respective sides of the at least two bit-line structures; a plurality of outer gap sub-layers conformally positioned on the plurality of inner gap sub-layers; a contact layer on the substrate and between the at least two bit line structures; and a conductive neck layer located on the contact layer and between the at least two bit line structures; A width of an upper surface of the bit line cover layer is smaller than a width of a lower surface of the bit line cover layer.

2. The semiconductor device of claim 1 , wherein the upper surface of the bit line cap layer, the upper surfaces of the inner spacer sub-layers, the upper surfaces of the outer spacer sub-layers, and an upper surface of the conductive neck layer are substantially coplanar.

3. The semiconductor device of claim 2 , wherein the at least two bit line structures extend along a first direction in a top view, and the conductive neck layer comprises two first sides contacting the plurality of outer gap sub-layers, and the two first sides gradually taper toward the contact layer.

4. The semiconductor device as claimed in claim 3, further comprising at least two separation layers, located on the substrate, spaced apart from each other, located between the at least two bit line structures, and combined with the at least two bit line structures to jointly surround the contact layer and the conductive neck layer. 5 . The semiconductor device as claimed in claim 4 , wherein the conductive neck layer comprises two second side edges contacting the at least two separation layers, and the two second side edges are substantially perpendicular to the two first side edges. 6 . The semiconductor device as claimed in claim 5 , further comprising a landing pad located on the conductive neck layer. 7 . The semiconductor device as claimed in claim 6 , wherein the landing pad and the conductive neck layer partially overlap when viewed from a top view. The semiconductor device as claimed in claim 6 , wherein the conductive neck layer and the landing pad comprise the same material. 9 . The semiconductor device as claimed in claim 6 , wherein the plurality of inner spacer sub-layers comprise silicon oxide. 10 . The semiconductor device of claim 6 , wherein the plurality of outer spacer sub-layers comprise silicon nitride.

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