Semiconductor device

Abstract

A semiconductor device integrates a series of die dies mounted on an interposer, each die die being configurable as a separate semiconductor chip. Each die die is equipped with a die-to-die interface that enables connectivity between them. A die-to-die interface in each die die includes: a first connection module within a first die die, the first connection module having a plurality of first modules; and a second connection module located in the second core grain bare chip, wherein the second connection module comprises a plurality of second modules. Selection circuitry is used to select a particular second module aligned with a corresponding one of the first connection modules.

Description

Technical Field

[0001] The present inventive concept relates to semiconductor devices and, more particularly, to a die-to-die interface between chiplet dies of a semiconductor device. Background Art

[0002] An electronic device configured to process data can perform various operations by accessing memory. For example, the electronic device can process data read from the memory or write data to the memory. Due to the performance and functional requirements of the system, it may include various electronic devices communicating via links that provide high bandwidth and low latency.

[0003] A chiplet die (often shortened to just a chiplet) is a smaller, modular semiconductor component that can be combined with other chiplets to form larger, more complex processors or systems. System-in-Package (SIP) can use a chiplet-based architecture that combines multiple specialized dielets into a single package. System performance can depend not only on the operating speed of each chiplet, but also on the communication efficiency and access time between chiplets.

[0004] The problem stems from power constraints, which limit the wiring length of connections between chiplets. Given that the interfaces of these interconnects are fixed in position, if the wiring length exceeds a feasible length, then the connection between chiplets is impossible. Therefore, this requires the creation of new chiplets with interface locations that adapt to the required wiring length.

[0005] Creating new chiplets with customized interface locations to accommodate specific wiring lengths introduces several disadvantages, including increased cost and development time, which can delay product release. It also complicates supply chain logistics and reduces system scalability due to the need for multiple specialized designs. Furthermore, this approach is resource-intensive, requiring significant financial, physical, and human resources, making it less effective for scenarios where cost, speed, and flexibility are important. Summary of the Invention

[0006] Embodiments of the inventive concept may provide an interface structure of a chip die that is not limited by the design and size of existing chip dies and improves efficiency, and a semiconductor device including the interface structure.

[0007] According to one aspect of the present invention, a semiconductor device is provided, comprising a plurality of core dies and an interposer. The core dies can be configured as semiconductor chips. The core dies are mounted on the interposer. Each of the plurality of core dies includes a die-to-die interface for connecting to each other. The die-to-die interface includes: a first connection module included in a first core die among the core dies; a second connection module included in a second core die among the core dies; and a selection circuit. The first connection module includes a plurality of first modules, and the second connection module includes a plurality of second modules. The selection circuit is configured to select a second module in the second modules that is aligned with a corresponding first module in the first modules.

[0008] According to another aspect of the present inventive concept, a semiconductor device is provided, comprising a first core die and a second core die. The first core die comprises a first die-to-die interface, and the second core die comprises a second die-to-die interface. The first core die and the second core die are adjacent to each other. The lengths of the surfaces of the first core die and the second core die adjacent to each other are different. The first die-to-die interface comprises N modules for connecting to the second core die, and the second die-to-die interface comprises M modules for connecting to the first core die, where N is a value different from M, and N and M are natural numbers. The second die-to-die interface comprises a selection circuit configured to select one or more modules among the M modules that are aligned with corresponding modules among the N modules.

[0009] According to another aspect of the present invention, a semiconductor device is provided, comprising: a plurality of core dies capable of being configured as semiconductor chips; and an interposer on which the plurality of core dies are mounted, wherein the plurality of core dies each include a die-to-die interface for connecting to each other, a first die-to-die interface included in a first core die among the core dies includes N modules, and a second die-to-die interface included in a second core die among the core dies includes M modules, wherein the N modules are configured so that all of the N modules are connected to another core die, and the M modules are configured so that only some of the M modules are connected to another core die, and N and M are natural numbers. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a perspective view showing a semiconductor device according to an embodiment; Figures 2A to 2C is a diagram for explaining a die-to-die connection structure according to a comparative example; Figure 3A is a diagram for explaining the connection of a bare chip according to a comparative example, and Figure 3B is a diagram for explaining the connection of a die according to an embodiment; Figure 4A and Figure 4B is a diagram for explaining a connection structure of a die according to an embodiment; Figure 5A and Figure 5B for explaining the connection of a die according to an embodiment; Figure 6A and Figure 6B is a block diagram illustrating an example of a die-to-die interface according to an embodiment; Figure 7A and Figure 7B is a block diagram illustrating an example of a die-to-die interface according to an embodiment; Figure 8A and Figure 8B is a block diagram illustrating an example of a die-to-die interface according to an embodiment; and Figure 9 is a block diagram for explaining a system of an electronic device including a D2D interface according to an embodiment. DETAILED DESCRIPTION

[0011] At least one embodiment relates to a semiconductor device that integrates a series of core die mounted on an interposer, each core die being configurable as a separate semiconductor chip. Each core die is equipped with a die-to-die interface that enables connection between them. The die-to-die interface in each core includes two connection modules: a first connection module within a first core die composed of a plurality of first modules, and a second connection module within a second core die comprising a plurality of second modules. A selection circuit can select a specific second module that is aligned with a corresponding first module in the first connection modules. This configuration facilitates inter-core communication and optimizes the modular architecture of the device to enhance performance and scalability in complex semiconductor systems.

[0012] Hereinafter, various embodiments are described with reference to the accompanying drawings.

[0013] Figure 1 is a perspective view showing a semiconductor device 1 according to an embodiment.

[0014] refer to Figure 1 , a semiconductor device 1 may include a substrate 2 , an interposer 3 , a first semiconductor chip 4 and at least one second semiconductor chip 5 .

[0015] The substrate 2 may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape board, or the like. According to an example, the substrate 2 may be a large-area package substrate for mounting the high-performance first semiconductor chip 4 and the high-performance second semiconductor chip 5. For example, the substrate 2 may have a planar shape such as a square or a rectangle, and the horizontal width and / or vertical width of the substrate 2 may be 40 millimeters (mm) or greater.

[0016] The interposer 3 may be placed on the upper surface of the substrate 2. The upper surface of the substrate 2 may face the lower surface of the interposer 3. According to an example, the interposer 3 may include a silicon interposer substrate having silicon vias (TSVs), but is not limited thereto.

[0017] The first semiconductor chip 4 and the second semiconductor chip 5 according to the example may be mounted on the interposer 3. The first semiconductor chip 4 and the second semiconductor chip 5 may be placed adjacent to each other on the upper surface of the interposer 3. For example, the second semiconductor chip 5 may be placed around the first semiconductor chip 4. The number of the first semiconductor chips 4 and the second semiconductor chips 5 is not limited to the number shown in the figure, and dummy chips may be placed in addition.

[0018] According to an example, the first semiconductor chip 4 may be a logic semiconductor chip. For example, the first semiconductor chip 4 may include an application processor (AP), such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), etc., but is not limited thereto.

[0019] According to an example, the second semiconductor chip 5 may include a memory semiconductor chip. For example, the second semiconductor chip 5 may include a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a non-volatile memory such as a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM), or a high-performance memory device such as a high-bandwidth memory (HBM) or a hybrid memory cube (HMC).

[0020] For example, the first semiconductor chip 4 may include an ASIC such as a GPU, and the second semiconductor chip 5 may include a stacked memory such as HBM. Stacked memory may be configured with multiple integrated circuits stacked on top of each other. The stacked integrated circuits may be electrically connected via silicon vias (TSVs).

[0021] According to an embodiment, the first semiconductor chip 4 and / or the second semiconductor chip 5 is a semiconductor core die. A core die may be a unit constituting a semiconductor die including one or more cores. The core die may be assembled to work as one semiconductor die. According to an example, each core die working as one semiconductor die may be personalized and may be configured as a personalized upper package. The personalized upper package may be mounted on a lower module substrate, and the personalized upper package may be electrically connected through the lower module substrate. When the individualized upper package is mounted on the lower module substrate, the semiconductor package module including the lower module substrate may be configured as a package capable of performing the functions of one semiconductor die.

[0022] According to an example, a chiplet die may represent the individual chips that make up a multi-chip module (MCM). For example, a chiplet die may include at least one of an input / output circuit, an analog circuit, a memory circuit, and a serial-to-parallel conversion circuit. Alternatively, a chiplet die may include at least one of a CPU, a GPU, and an FPGA. The number of chiplets mounted on interposer 3 is not particularly limited, and a greater number of chiplets than shown in the figure may be mounted on interposer 3.

[0023] The die dies according to the example can be coupled to each other via one or more die-to-die (D2D) interfaces. In addition, the die dies can be coupled to one or more interposers 3, which can be configured to enable communication between the die and other components (e.g., acting as a bridge or conduit to allow electrical signals to pass between internal components and external components).

[0024] According to an embodiment, a die die may include adjustable modules that enable interconnection between the die dies when the die design and chip size are specified. According to an embodiment, a die-to-die interface may overcome limitations in existing die designs by equipping the die with multiple modules and using a selected combination of these modules to interface with other dies.

[0025] Hereinafter, the configuration of the die-to-die interface according to the embodiment will be described in more detail. Hereinafter, the terms "chip die" and "die" may be used interchangeably. The description of the die described below may be applied to the reference die. Figure 1 Describes the die.

[0026] According to an embodiment, the configuration of the D2D interface of the chiplet die can be implemented to increase the number of HBMs connected to the GPU in a structure including both GPUs and HBMs. According to an embodiment, the configuration of the D2D interface of the chiplet die can also be implemented to increase the reusability of the die in the chiplet structure.

[0027] The semiconductor device 1 according to an example may be a semiconductor package and may be a 2.5D package.

[0028] Figures 2A to 2C It is a diagram for explaining a die-to-die connection structure according to a comparative example.

[0029] refer to Figure 2A , die 10 of A and dies 21, 22, and 23 of B are arranged side by side, and die-to-die interfaces 10a, 10b, 10c, 21a, 22a, and 23a for connecting die 10 of A and dies 21, 22, and 23 of B are shown, respectively. According to an example, die 10 of A includes die-to-die interfaces 10a, 10b, and 10c for connecting to dies 21, 22, and 23 of B. According to an example, dies 21, 22, and 23 of B each include die-to-die interfaces 21a, 22a, and 23a for connecting to die 10 of A. According to an example, the die-to-die interface is a D2D PHY, but is not limited thereto.

[0030] Die-to-die interconnects in a chiplet architecture can be constrained by routing lengths. This means the linear distance between the interconnect PHYs in each die is constrained, and if this linear distance exceeds the routing length, inter-die connectivity may become impossible. Because the D2D PHYs are located in a fixed position within a conventional chiplet, configuration limitations may arise when reusing the same chiplet within a chiplet.

[0031] refer to Figure 2A , when connecting two or more dies to each other, there may be a constraint that a wiring length of 2 mm needs to be met. Therefore, when two or more dies such as Figure 2A When the die-to-die interfaces are connected to each other in the embodiment, the die-to-die interfaces can be arranged by aligning the central axes of the die-to-die interfaces included in each die with each other. Figure 2A The arrangement of the dies in can be according to the arrangement of the chip design.

[0032] In the present invention, the meaning of modules or interfaces being aligned can be the same as the meaning of being aligned to a die-to-die interface included in another die, and aligning the modules or interfaces can mean arranging or selecting modules positioned at the same height or width in the X-axis or Y-axis direction to correspond to the connection modules included in the die-to-die interface to be connected. In other words, alignment can mean selecting a portion of the core structure that corresponds in position to the D2D interface in the corresponding chip.

[0033] refer to Figure 2AIt can be observed that the D2D interface 10a included in A's die 10 and the D2D interface 21a included in B's die 21 are aligned, the D2D interface 10b included in A's die 10 and the D2D interface 22a included in B's die 22 are aligned, and the D2D interface 10c included in A's die 10 and the D2D interface 23a included in B's die 23 are aligned.

[0034] refer to Figure 2B , A's die 10' and B's die 24, 25, 26 and 27 are arranged side by side, and die-to-die interfaces 10d, 10e, 10f, 10g, 24a, 25a, 26a and 27a for connecting A's die 10' and B's die 24, 25, 26 and 27 are shown respectively. Figure 2B In the core particle design of Figure 2A The die 10 of A has a new die 10' of the same size but with a different die-to-die interface structure, while reusing the Figure 2A B's bare die.

[0035] In accordance with Figure 2B In the chip design of FIG. 1 , the number of B dies corresponding to one side of A' die 10' is increased to 4. In this case, the arrangement positions of the die-to-die interfaces 24a, 25a, 26a and 27a included in the B dies 24, 25, 26 and 27 can be as follows: Figure 2A The central part of each die. Figure 2A The die 10 of A has the same side lengths as the die 10′ of A′, and the die-to-die interfaces 10 d and 10 g included in the die 10′ of B, and the die-to-die interfaces 24 a and 27 a included in the dies 24 and 27 of B may not be aligned in a straight line. However, if the die-to-die interfaces 10 d and 10 g and the die-to-die interfaces 24 a and 27 a are not aligned in a straight line, it is difficult to resolve the wiring length constraint as described above.

[0036] In order to align these components in a straight line, the length of the long side of the die 10' of A' can be increased in length. However, in current semiconductor processes, due to the limitations of photolithography, the length of the long side of each die is generally limited to a maximum of 33 mm. However, since the length of the long side of the die 10' of A' may already be at its maximum, it may not be feasible to align the interfaces in a straight line even if a new die 10' of A' is manufactured. This will result in the inability to meet the 2 mm wiring length requirement. In addition, the need to manufacture a new die 10' of A' may cause further complexity.

[0037] Alternatively, the dies 24, 25, 26, and 27 of B can be made smaller, but this would also require making new dies, and making smaller dies may not be easy. Alternatively, while increasing the wiring length is possible, this may violate design rules and result in higher power consumption.

[0038] In accordance with Figure 2C In the core particle design of Figure 2B The same chip design as in FIG. 1 , but shows an example of die-to-die alignment for a newly fabricated corresponding die in that chip design.

[0039] refer to Figure 2C , the configuration of the die 10' of A' and the die-to-die interfaces 10d, 10e, 10f and 10g included in the die 10' of A' is the same as Figure 2B and the die 28 of B' and the die-to-die interface 28a included in the die 28 of B' and the die 29 of B' and the die-to-die interface 29a included in the die 29 of B' can be the same as Figure 2B Different.

[0040] refer to Figure 2C , the position of the die-to-die interface 28a included in the die 28 of B' can be changed to align with the die-to-die interface 10d included in the die 10' of A', and the position of the die-to-die interface 29a included in the die 29 of B'' can be changed to align with the die-to-die interface 10g included in the die 10' of A'.

[0041] refer to Figures 2A to 2C To facilitate inter-die connectivity by changing the die design, the fixed position of the die-to-die interface on a previously manufactured die may require the fabrication of a new die for proper alignment. However, this may limit the design diversity of the die design or impose additional costs due to the need to produce more die.

[0042] Figure 3A is a diagram illustrating the connection of a bare chip according to a comparative example, and Figure 3B is a diagram illustrating connections of dies according to an embodiment.

[0043] refer to Figure 3A , shows a structure in which die C 30, die D 40, and die E 50 are arranged according to a chiplet design. Each die may include a die-to-die interface. Die C 30 includes die-to-die interfaces 30 a and 30 b, die D 40 includes die-to-die interface 40 a, and die E 50 includes die-to-die interface 50 a.

[0044] refer to Figure 3A, the die-to-die interface 30b of die 30 of C and the die-to-die interface 40a of die 40 of D are already aligned, so there is no problem connecting them. However, the die-to-die interface 30a of die 30 of C and the die-to-die interface 50a of die 50 of E are not aligned, which may result in exceeding the 2mm wiring length constraint. If die 30 of C, die 40 of D and die 50 of E are pre-existing core die with fixed die-to-die interface positions, this arrangement may cause limitations when trying to integrate them into a single core. Overcoming these limitations typically requires manufacturing new core die. However, according to an embodiment, a core die structure is proposed that allows connection to various die without the need to manufacture new core die.

[0045] refer to Figure 3B , die 30 of C, die 40 of D, and die 51 of E′ are provided to illustrate the embodiment.

[0046] Because the configuration of the die 30 of C and the die 40 of D is the same as that of the reference Figure 3A The descriptions given are the same, so the descriptions already given are omitted. The die 51 of E' includes a die-to-die interface 51a. Figure 3B The die-to-die interface 51a of the die 51 of E' shown in FIG is different from Figure 3A The die-to-die interface 50a of the die 50 of E. The die-to-die interface 51a according to the example includes an area 51a' that is aligned with the die-to-die interface 30a of the adjacent die 30 of C. According to an embodiment, the introduction of a die-to-die interface that can select a variable alignment position as opposed to a fixed position eliminates the need to manufacture new die according to the arrangement structure of the die. This allows for more efficient die to be provided. According to an embodiment, additional design can be performed from the perspective of a D2D configuration that connects the die to the die, and the die can be configured by selecting only necessary modules among a plurality of modules.

[0047] Figure 4A and Figure 4B is a diagram illustrating a connection structure of a die according to an embodiment.

[0048] refer to Figure 4A , showing a first die 100 and a second die 200. According to an example, the first die 100 and the second die 200 are arranged at positions adjacent to each other. In addition, it is assumed that they are dies coupled to each other. According to an example, the first die 100 and the second die 200 may be chip dies.

[0049] The first die 100 may include a first die-to-die interface 110, and the second die 200 may include a second die-to-die interface 210. The first die-to-die interface 110 and the second die-to-die interface 210 may connect the first die 100 and the second die 200. In this embodiment, "connectable" may mean communicatively connected for information transmission between the dies.

[0050] exist Figure 4A In the drawings, for convenience of explanation, the first die 100 and the second die 200 are shown as blocks of the same size, but the lengths of the surfaces of the first die 100 and the second die 200 that contact each other may be different.

[0051] refer to Figure 4B , a block diagram is shown to illustrate components included in each of the first die-to-die interface 110 a and the second die-to-die interface 210 a .

[0052] refer to Figure 4B , the first die-to-die interface 110a may include a connection module 111a, a selection circuit 112a, and a connection circuit 113a, and the second die-to-die interface 210a may include a connection module 211a, a selection circuit 212a, and a connection circuit 213a.

[0053] According to an example, the connection modules 111a and 211a may include a number of modules that is equal to or greater than the number of bits that each die can connect to other dies. According to an example, the connection module 111a included in the first die-to-die interface 110a of the first die 100 may include N modules that can connect to other dies. According to an example, the connection module 111a included in the first die-to-die interface 110a may be a fixed module. In this embodiment, a fixed module may refer to a module that is connected to another die by using all of the multiple modules included in the connection module 111a. According to an example, the connection module 211a included in the second die-to-die interface 210a of the second die 200 may include M modules that can connect to another die. According to an example, the connection module 211a included in the second die-to-die interface 210a may be a variable module. In this embodiment, a variable module may refer to a module that is connected to another die by using only some of the multiple modules included in the connection module 211a. According to an example, both N and M are natural numbers greater than or equal to 1. According to an example, the first die 100 may include a fixed module, and the second die 200 may include a variable module.

[0054] According to an example, selection circuits 112a and 212a may be circuits for selecting some of the modules included in connection modules 111a and 211a. As described above, if connection module 111a is a fixed module, since all modules included in connection module 111a are used, selection circuit 112a connected to connection module 111a can be omitted. If connection module 211a is a variable module, selection circuit 212a for selecting some of the modules included in connection module 211a may be provided. According to an example, selection circuit 212a may include a multiplexer for selecting one of a plurality of inputs and outputting it, but is not limited thereto.

[0055] The connection circuits 113a and 213a may include an interface for connecting the outputs of the connection module 111a and the selection circuits 112a and 212a to an adjacent die. According to an example, the connection circuits 113a and 213a may include a physical interface. According to an example, the first die 100 and the second die 200 arranged adjacent to each other may be communicatively connected via the connection circuits 113a and 213a. According to an example, the connection circuits 113a and 213a may support the Universal Chip Interconnect Express (UCIe) protocol for communication between the first die 100 and the second die 200. According to an example, the connection circuits 113a and 213a may include one of a PHY or a link, a controller, and an adapter.

[0056] In this embodiment, a case is described where one of the first die-to-die interface 110a and the adjacent second die-to-die interface 210a is a fixed module and the other is a variable module, but both the adjacent first die-to-die interface 110a and the adjacent second die-to-die interface 210a can be variable modules. According to an embodiment, the second die 200 including the variable module can be a die with sufficient free space. According to an example, the second die 200 including the variable module can be an HBM die. According to an example, the second die 200 including the variable module can be a die including a certain percentage or more of free space. According to an example, the second die 200 including the variable module can be a die with 30% or more of free space.

[0057] Additionally, in the embodiment, an example is shown in which the die-to-die interface is formed adjacent to one side of the die, but the die-to-die interface may be formed adjacent to the other side of the die, respectively, or may be formed on two or more sides of the die.

[0058] According to an example, the connection module 211a may include multiple D2D interface groups, and the actual D2D interface group used among the D2D interface groups may be selected by the selection circuit 212a for wiring alignment. The D2D interface group may be a single copy or a group that shares a portion with each other. Figure 6AA method of forming a group using a plurality of modules is described below.

[0059] Figure 5A and Figure 5B is a diagram illustrating connections of dies according to an embodiment.

[0060] refer to Figure 5A , showing four dies and a plurality of connection modules included in each die. Figure 5A and Figure 5B In the figure, for the convenience of explanation, only the connection module among the components included in the die-to-die interface is shown.

[0061] According to an example, the third die 300 , the fourth die 400 , the fifth die 500 , and the sixth die 600 are respectively arranged according to a chip design.

[0062] The third die 300 may include a first connection module 311, the fourth die 400 may include a second connection module 411, the fifth die 500 may include third connection modules 511a and 511b, and the sixth die 600 may include a fourth connection module 611. The first connection module 311 of the third die 300 may be a fixed module for connecting with the fourth die 400. According to an example, the second connection module 411 of the fourth die 400 is a variable module for connecting with the third die 300 and the fifth die 500. The third connection modules 511a and 511b of the fifth die 500 may be fixed modules for connecting with the fourth die 400 and the sixth die 600. The fourth connection module 611 of the sixth die 600 may be a fixed module for connecting with the fifth die 500.

[0063] According to an example, the fixing modules included in the third die 300 , the fifth die 500 , and the sixth die 600 may be used to align with modules of a counterpart die by using all of the plurality of modules included in the fixing modules.

[0064] exist Figure 5A Among the connection modules shown, modules filled with patterns may represent modules selected for connection with the facing die, and blank modules not filled with patterns among the connection modules may represent modules not used for connection with the facing die. According to an example, fixed modules may include only modules filled with patterns, and variable modules may include both modules filled with patterns and blank modules not filled with patterns.

[0065] like Figure 5AAs shown, modules having the same pattern included in different dies are shown as connection modules aligned with each other. According to an example, the connection module aligned with the first connection module 311 included in the third die 300 may be a module having the first pattern P1 among the second connection modules 411 included in the fourth die 400. According to an example, the connection module aligned with the third connection module 511a included in the fifth die 500 may be a module having the second pattern P2 among the second connection modules 411 included in the fourth die 400. The connection module aligned with the third connection module 511b included in the fifth die 500 may be a module having the third pattern P3 among the fourth connection modules 611 included in the sixth die 600.

[0066] In this manner, in a case where the second connection module 411 includes a variable module, connection between dies may be performed by selecting a module aligned with a connection module included in an adjacent die among a plurality of modules.

[0067] refer to Figure 5B , the third die 300 a , the fourth die 400 a , the fifth die 500 a and the sixth die 600 a may be arranged respectively according to the chip design.

[0068] The third die 300a may include a first connection module 311a, the fourth die 400a may include a second connection module 411a, the fifth die 500a may include third connection modules 511c and 511d, and the sixth die 600a may include a fourth connection module 611a.

[0069] The configurations of the third die 300a, the fifth die 500a, and the sixth die 600a may correspond to those described above with reference to Figure 5A The description of the third die 300 , the fifth die 500 , and the sixth die 600 are described, and therefore, descriptions that have been previously given are omitted.

[0070] According to the example, Figure 5B The fourth die 400a may be arranged at a position different from Figure 5A The position where the fourth die 400 is arranged. Figure 5B The fourth die 400a may be placed at a position that is larger than Figure 5A In this case, because the position of the fourth die 400a has changed, the connection module aligned with the first connection module 311a of the third die 300a and the connection module aligned with the third connection module 511c of the fifth die 500a can be aligned. Figure 5A The situation is different compared to the previous one.

[0071] refer to Figure 5A and Figure 5B , the module selected for alignment among the second connection modules 411 a included in the fourth die 400 a may vary according to the arrangement positions of the connection modules included in the adjacent die.

[0072] In the D2D interface according to the example, the number of modules required to connect to adjacent dies can be determined based on the amount of bandwidth used. For example, if one module covers a bandwidth of A GB / s and the bandwidth required between chips is B, the number of modules required for connection can be an integer C greater than B / A. According to the comparative example, the D2D interface includes C modules, but in this embodiment, it can include D modules (greater than C), and only C modules can be selected and used among the D modules.

[0073] Figure 6A and Figure 6B is a block diagram illustrating an example of a die-to-die interface according to an embodiment.

[0074] refer to Figure 6A , discloses the configuration of the connection module 1110, the selection circuit 1120, the connection circuit 1130 and the bus 1140. According to an example, Figure 6A The configuration of the connection module 1110, the selection circuit 1120 and the connection circuit 1130 may correspond to Figure 4B The configuration of the connection module 111a, the selection circuit 112a and the connection circuit 113a is shown.

[0075] According to an example, the connection module 1110 may include a plurality of groups G1, ..., GA. According to an example, A may be a natural number greater than or equal to 2. According to an example, each of the plurality of groups may include N modules required for D2D connection. According to an example, N may be a natural number greater than or equal to 2. That is, in this case, the total number of modules included in the connection module 1110 may be N. A. That is, the total number of modules included in the connection module 1110 may be an integer multiple of the number of modules included in each group. According to an example, each of the multiple groups may include the same number of modules. According to an example, the number of modules included in the multiple groups may correspond to the number of fixed modules included in the die to be connected.

[0076] The selection circuit 1120 may be connected to the output terminals of the plurality of groups G1, ..., GA. According to an example, the selection circuit 1120 may include a multiplexer. The multiplexer included in the selection circuit 1120 may select one of the plurality of groups G1, ..., GA and output the selected group to the connection circuit 1130. According to an example, the selection circuit 1120 may select a group formed at a corresponding position among the plurality of groups G1, ..., GA based on the positions of the connection modules included in the adjacent dies.

[0077] The connection circuit 1130 may include an adapter, but is not limited thereto. The connection circuit 1130 may be connected to the bus 1140 and may transmit information output from the selection circuit 1120 to another die.

[0078] Figure 6B Shown is the corresponding Figure 6A Embodiments of a die-to-die interface.

[0079] refer to Figure 6B , discloses a first die-to-die interface 1100 including a variable module and a second die-to-die interface 1100′ including a fixed module. The first die-to-die interface 1100 may include a connection module 1110a, a selection circuit 1120a, and a connection circuit 1130a, and the second die-to-die interface 1100′ may include a connection module 1110a′ and a connection circuit 1130a′. The connection circuit 1130a of the first die-to-die interface 1100 and the connection circuit 1130a′ of the second die-to-die interface 1100′ may be connected via a bus 1140a.

[0080] According to an example, the connection module 1100a of the first die-to-die interface 1100 may include a plurality of groups G1, G2, and G3. Each of the plurality of groups G1, G2, and G3 may include four modules. According to an example, since the connection module 1100a may include a total of three groups, and each group may include four modules, the connection module 1100a may include a total of twelve modules. Here, the reason why the plurality of groups include four modules may be because the number of connection modules 1110a' included in the adjacent die is four.

[0081] According to an example, the selection circuit 1120a selects a group aligned with the position of the connection module 1110a' of the adjacent die. According to an example, the selection circuit 1120a selects the group G3 aligned with the position of the connection module 1110a' and sends the result of its selection to the connection circuit 1130a. In this way, the connection module 1110a can include multiple groups G1, G2, and G3, and can select and connect the group G3 aligned with the adjacent die among the multiple groups G1, G2, and G3.

[0082] In some drawings of the present inventive concept, in order to illustrate the alignment of connection modules included in different dies, vertically extending dashed lines are used.

[0083] Figure 7A and Figure 7B is a block diagram illustrating an example of a die-to-die interface according to an embodiment.

[0084] refer to Figure 7A , shows the configuration of the connection module 3110, the selection circuit 3120, the connection circuit 3130 and the bus 3140. According to the example, Figure 7A The configuration of the connection module 3110, the selection circuit 3120 and the connection circuit 3130 may correspond to Figure 4B The configuration of the connection module, selection circuit and connection circuit shown.

[0085] The connection module 3110 may include multiple modules. According to an example, the connection module 3110 may include M modules. M may be a natural number greater than or equal to 2.

[0086] The selection circuit 3120 may include a plurality of multiplexers. According to an example, each of the plurality of multiplexers may select a starting module from a plurality of modules included in the connection module 3110 and configure a group consisting of N modules including the corresponding module. Figure 7A In the example, N=4.

[0087] According to an example, the number of multiplexers included in the selection circuit 3120 may be M-N+1. In this case, M may represent the number of modules included in the connection module 3110, and N may be the number of modules included in the die adjacent to the corresponding die and to be connected. M and N may be natural numbers. For example, M may have a value greater than N.

[0088] exist Figure 7A In the case of the embodiment, groups may be sequentially formed among the M modules included in the connection module 3110, and a plurality of multiplexers for selecting each group may be disclosed. Figure 7A Examples and Figure 6A The difference between the embodiments is that Figure 7A In , groups are formed sequentially for sequentially formed modules, but in Figure 6A In the case of , a group is formed for copies that are copies of the corresponding module. That is, in Figure 6A In the case of multiple groups, the configurations of the modules included are exactly the same, but Figure 7A In some cases, the configurations of modules included in multiple groups may be different.

[0089] Figure 7BShown is the corresponding Figure 7A Embodiments of a die-to-die interface.

[0090] refer to Figure 7B , shows a first die-to-die interface 3100 and a second die-to-die interface 4100. The first die-to-die interface 3100 may include a connection module 3110a, a selection circuit 3120, and a connection circuit 3130a, and the second die-to-die interface 4100 may include a connection module 4110a and a connection circuit 4130a. The first die-to-die interface 3100 and the second die-to-die interface 4100 may be connected via a bus 3140a based on the connection circuits 3130a and 4130a included in the first die-to-die interface 3100 and the second die-to-die interface 4100, respectively.

[0091] The connection module 3110 a of the first die-to-die interface 3100 may include a plurality of groups G1 , G2 , G3 , and G4 . Figure 7B Group and Figure 6B The difference between the groups is that Figure 6B The groups formed in do not have overlapping modules between groups, but Figure 7B Groups can have overlapping modules. Figure 7B Each of the groups G1, G2, G3 and G4 may be a group formed by sequentially cutting out three modules from a plurality of modules. The first group G1 according to the example may be a group formed by grouping the first module, the second module and the third module among the six modules of the connection module 3110a. The second group G2 according to the example may be a group formed by grouping the second module, the third module and the fourth module among the six modules of the connection module 3110a. The third group G3 according to the example may be a group formed by grouping the third module, the fourth module and the fifth module among the six modules of the connection module 3110a. The fourth group G4 according to the example may be a group formed by grouping the fourth module, the fifth module and the sixth module among the six modules of the connection module 3110a. Here, the reason for sequentially forming a plurality of modules by cutting or dividing a plurality of modules into three may be because the number of connection modules 4110a included in adjacent dies is three. If this situation is replaced to Figure 7A In the example, it may be the case when M=6 and N=3.

[0092] A selection circuit 3120 for selecting one of the four groups G1, G2, G3, and G4 can be connected to the connection module 3110a. The selection circuit 3120 may include a first multiplexer 3120a, a second multiplexer 3120b, a third multiplexer 3120c, and a fourth multiplexer 3120d. The first multiplexer 3120a may be connected to the multiple modules included in the first group G1 to select the first group G1. The second multiplexer 3120b may be connected to the multiple modules included in the second group G2 to select the second group G2. The third multiplexer 3120c may be connected to the multiple modules included in the third group G3 to select the third group G3. The fourth multiplexer 3120d may be connected to the multiple modules included in the fourth group G4 to select the fourth group G4. The selection circuit 3120 includes multiple multiplexers and may select a multiplexer to select the connection module corresponding to the connection module 4110a of the adjacent die and output the corresponding result.

[0093] refer to Figure 7B Since the group of the first die-to-die interface 3100 aligned with the connection module 4110a included in the second die-to-die interface 4100 is the fourth group G4, in order to select the fourth group G4, the selection circuit 3120 may transmit the output of the fourth multiplexer 3120d to the connection circuit 3130a.

[0094] Figure 8A and Figure 8B is a block diagram illustrating an example of a die-to-die interface according to an embodiment.

[0095] refer to Figure 8A , shows the configuration of the connection module 5110, the selection circuit 5120, the connection circuit 5130 and the bus 5140. According to the example, Figure 8A The configuration of the connection module 5110, the selection circuit 5120 and the connection circuit 5130 may correspond to Figure 4B The configuration of the connection module, selection circuit and connection circuit shown.

[0096] refer to Figure 8A , the connection module 5110 may include M modules. According to an example, the selection circuit 5120 may include a multiplexer. Figure 8A In the embodiment, M can be 5.

[0097] According to an example, the multiplexer included in the selection circuit 5120 may be connected to only some of the plurality of modules included in the connection module 5110. Figure 8A , only the first module and the fifth module among the multiple modules included in the connection module 5110 can be connected to the multiplexer included in the selection circuit 5120.

[0098] According to an embodiment, some modules within the connection module 5110 may be fixed for use independent of the selection circuit. Furthermore, a selection circuit 5120 may be disclosed for determining which of these fixed modules to utilize. According to an embodiment, this method can be cost-effective and area-efficient by reducing the number of multiplexers.

[0099] According to an embodiment, when the relationship between the number M of modules in the connection module 5110 and the number N of modules required for the dies to be connected satisfies the condition: N>M / 2, the configuration method for selecting a circuit may be applied.

[0100] At this time, the fixed module among the multiple modules included in the connection module 5110 can correspond to the 2N-M modules located in the middle.

[0101] According to an embodiment, in the case where a group formed by a plurality of modules included in the connection module 5110 shares some modules in a fixed order, the shared modules may be fixed and directly connected to the connection circuit 5130, and the remaining modules may be selected by the selection circuit 5120 and output.

[0102] refer to Figure 8A , Figure 8A It is a graph assuming that M=5 and N=4. Figure 8A In the connection module 5110, the number of modules to be fixed is 3.

[0103] refer to Figure 8B , showing the corresponding Figure 8A Embodiments of a die-to-die interface.

[0104] refer to Figure 8B , shows a first die-to-die interface 5100 and a second die-to-die interface 6100. The first die-to-die interface 5100 may include a connection module 5110a, a selection circuit 5120a, and a connection circuit 5130a, and the second die-to-die interface 6100 may include a connection module 6110a and a connection circuit 6130a. The first die-to-die interface 5100 and the second die-to-die interface 6100 may be connected via a bus 5140a based on the connection circuits 5130a and 6130a included in the first die-to-die interface 5100 and the second die-to-die interface 6100, respectively.

[0105] According to an embodiment, the connection module 5110 a of the first die-to-die interface 5100 may include a plurality of groups G1 and G2 . Figure 8B Group and Figure 6B The difference between the groups is that Figure 6B The groups formed in do not have overlapping modules between groups, but in Figure 8BIn the groups, there are modules that overlap with each other. Figure 8B The groups G1 and G2 may be groups formed by sequentially cutting out four modules from a plurality of modules. Here, the reason for forming the groups by sequentially cutting out four modules from a plurality of modules may be because the number of connection modules 6110a included in the adjacent die is four. If this situation is replaced to Figure 8A In the example, M=5 and N=4 may be used.

[0106] The first group G1 according to the embodiment may be a group formed by grouping the first module, the second module, the third module, and the fourth module among the five modules of the connection module 5110a. The second group G2 according to the embodiment may be a group formed by grouping the second module, the third module, the fourth module, and the fifth module among the five modules of the connection module 5110a.

[0107] According to an embodiment, the plurality of groups G1 and G2 may share the second module, the third module, and the fourth module. Therefore, the second module, the third module, and the fourth module commonly included in the plurality of groups G1 and G2 do not need to pass through the selection circuit 5120a and can be directly connected to the connection circuit 5130a without being connected to the selection circuit 5120a. That is, in order to select one of the plurality of groups G1 and G2, only the first module included in the first group G1 and the fifth module included in the second group G2 can be connected to the selection circuit 5120a.

[0108] According to an embodiment, because the second group G2 is selected to be aligned with the connection module 6110 a included in the second die-to-die interface 6100 , the selection circuit 5120 a may output the fifth module.

[0109] According to the reference Figures 6A to 8B Given the description, the configuration of the selection circuit can be divided into three types. Figure 6A and Figure 6B A selection circuit for selecting one group among a plurality of groups included in the connection module may be provided. Figure 7A and Figure 7B A selection circuit can be provided to select some modules among the plurality of modules and configure a group aligned with the corresponding connection modules. Figure 8A and Figure 8B , a selection circuit may be provided that fixes some modules among the plurality of modules and selects only the remaining modules to form an entire group.

[0110] Although only three types of selection circuits are discussed above, embodiments are not limited thereto. For example, various configurations of selection circuits capable of selecting some modules among a plurality of modules may be provided.

[0111] In an embodiment, each module within the die is provided with physical or electronic markings, such as notches, pins, or coded data that identify its location or function. These markings can be read by a selection circuit (e.g., 112a). When the die is integrated into a system, the selection circuit scans these markings to identify the characteristics of each module and its physical or logical location relative to other modules.

[0112] In one embodiment, the selection circuitry is powered by a software algorithm that processes data about each module's capabilities (such as speed, bandwidth, and electrical characteristics) to determine compatibility. When a new die is activated or inserted, the system's controller (part of the selection circuitry) runs the algorithm to evaluate which modules on the new die best align with modules on existing dies based on predetermined criteria.

[0113] In an embodiment, integrated sensors in each die detect physical alignment (via optical or contact sensors) or electronic signals (such as impedance, signal integrity testing) to determine the proximity and orientation of adjacent modules. When the die is placed into the system, these sensors provide real-time feedback to the selection circuitry, which then uses this information to activate the appropriate module that meets the alignment criteria.

[0114] Figure 9 is a block diagram for explaining a system 2000 of an electronic device including a D2D interface according to an embodiment.

[0115] refer to Figure 9 System 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor 2800 (hereinafter referred to as "AP"). System 2000 may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet personal computer, a wearable device, a medical device, or an Internet of Things (IoT) device. Furthermore, system 2000 may be implemented as a server or a personal computer.

[0116] The camera 2100 can capture still images or moving images according to user control and can store the captured image / video data or transmit the captured image / video data to the display 2200. The audio processor 2300 can process audio data included in the flash memories 2600a and 2600b or the contents of the network. The modem 2400 can modulate and transmit signals for wired / wireless data transmission and reception and can demodulate the signals at the receiving end to restore the original signals. The I / O devices 2700a and 2700b may include devices that provide digital input and / or output functions, such as a universal serial bus (USB), a storage device, a digital camera, a secure digital (SD) card, a digital versatile disk (DVD), a network adapter, a touch screen, etc.

[0117] AP 2800 can control the overall operation of system 2000. AP 2800 may include a controller 2810, an accelerator 2820 or an accelerator chip 2820, and an interface 2830. AP 2800 may control display 2200 so that a portion of the content stored in flash memories 2600a and 2600b is displayed on display 2200. When user input is received through I / O devices 2700a and 2700b, AP 2800 may perform control operations corresponding to the user input. AP 2800 may include an accelerator block as a dedicated circuit for artificial intelligence (AI) data operations, or may have an accelerator chip 2820 separate from AP 2800. DRAM 2500b may be additionally mounted on accelerator block or accelerator chip 2820. The accelerator 2820 is a functional block specialized in performing specific functions of the AP 2800 and may include: a GPU, which is a functional block specialized in processing graphic data; a neural processing unit (NPU), which is a block specialized in performing AI calculations and reasoning; and a data processing unit (DPU), which is a block specialized in data transmission.

[0118] System 2000 may include multiple DRAMs 2500a and 2500b. AP 2800 can control DRAMs 2500a and 2500b by configuring command and mode registers (MRS) that conform to the Joint Electron Device Engineering Council (JEDEC) standard specifications, or it can communicate by configuring the DRAM interface protocol to utilize unique company features, such as low voltage, high speed, reliability, and cyclic redundancy check (CRC) and error correction code (ECC) functions. For example, AP 2800 can communicate with DRAM 2500a using an interface that conforms to JEDEC standard specifications, such as LPDDR4 and LPDDR5, while the accelerator block or accelerator chip 2820 can control DRAM 2500b, an accelerator with higher bandwidth than DRAM 2500a, by configuring the new DRAM interface protocol for communication.

[0119] exist Figure 9 , only DRAMs 2500a and 2500b are shown, but embodiments are not limited thereto, and any memory such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM may be used as long as it meets the bandwidth, response speed, and voltage requirements of the AP 2800 or the accelerator chip 2820. DRAMs 2500a and 2500b have relatively lower latency and bandwidth than I / O devices 2700a and 2700b or flash memories 2600a and 2600b. DRAMs 2500a and 2500b can be used as a temporary storage location for an operating system and application data, or as an execution space for various software codes by being initialized and having an operating system and application data loaded when the system 2000 is powered on.

[0120] In DRAM 2500a and 2500b, the four basic operations of addition / subtraction / multiplication / division as well as vector operations, address operations, or fast Fourier transform (FFT) operations can be performed. In addition, functions for performing inference can be performed in DRAM 2500a and 2500b. Here, inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training operation for learning a model through various data and an inference operation for recognizing data using the learned model. As an embodiment, an image captured by a user through camera 2100 is signal-processed and stored in DRAM 2500b, and the accelerator block or accelerator chip 2820 can perform AI data operations that use the data stored in DRAM 2500b and the function for inference to recognize the data.

[0121] System 2000 may include multiple storage devices or multiple flash memories 2600a and 2600b with larger capacities than DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use the flash memories 2600a and 2600b to perform training operations and AI data operations. In an embodiment, the flash memories 2600a and 2600b include a memory controller 2610 and a flash memory device 2620. The operation mechanism provided in the memory controller 2610 can more efficiently perform training operations and inference AI data operations performed by the AP 2800 and / or the accelerator chip 2820. The flash memories 2600a and 2600b can store images captured by the camera 2100 or data transmitted over a data network. For example, the flash memories 2600a and 2600b can store augmented reality / virtual reality, high-definition (HD), or ultra-high-definition (UHD) content.

[0122] In system 2000, AP 2800 and DRAMs 2500a and 2500b can be interconnected via the D2D interface described with reference to the above figures. Furthermore, memory controller 2610 and flash memory device 2620 of flash memories 2600a and 2600b can also be interconnected via the D2D interface. According to an embodiment, the D2D interface can include a die-to-die interface that allows selection of variably aligned positions, enabling the creation of efficient chip dies without the need to manufacture new chip dies based on their layout structure. According to an embodiment, additional design can be performed from the perspective of a D2D configuration connecting die to die, and the chip die can be configured by selecting only necessary modules from among the modules.

[0123] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of die, the plurality of die being configurable as semiconductor chips; as well as an interposer on which the plurality of die are mounted, wherein each of the plurality of core dies comprises a die-to-die interface for connecting to each other, Wherein, the die-to-die interface comprises: A first connection module, the first connection module being included in a first die among the die, the first connection module including a plurality of first modules; a second connection module, the second connection module being included in a second die among the die, the second connection module including a plurality of second modules; and A selection circuit is configured to select a second module in the second modules that is aligned with a corresponding first module in the first modules.

2. The semiconductor device according to claim 1, wherein The number of the first modules is different from the number of the second modules.

3. The semiconductor device according to claim 2, wherein The number of the second modules is an integer multiple of the number of the first modules.

4. The semiconductor device according to claim 3, wherein The number of the multiplexers included in the selection circuit is one.

5. The semiconductor device according to claim 2, wherein The number of the first modules is N, and The number of the second modules is M, in, M is a value greater than N, and M and N are natural numbers.

6. The semiconductor device according to claim 5, wherein The number of multiplexers included in the selection circuit is M-N+1.

7. The semiconductor device according to claim 5, wherein Among the M second modules, A second modules are fixed and aligned, The selection circuit includes a multiplexer for connecting the remaining second modules except the A second modules, and A is a natural number, and A has a value smaller than M and smaller than N.

8. A semiconductor device, comprising: a first chip die comprising a first die-to-die interface; as well as a second chip die comprising a second die-to-die interface, wherein the first die and the second die are adjacent to each other, wherein the lengths of the surfaces of the first die and the second die adjacent to each other are different, wherein the first die-to-die interface comprises N modules for connecting to the second die, and the second die-to-die interface comprises M modules for connecting to the first die, Where N is different from M, and N and M are natural numbers, and The second die-to-die interface includes a selection circuit configured to select one or more modules among the M modules that are aligned with corresponding modules among the N modules.

9. The semiconductor device according to claim 8, wherein The M modules include modules that can be aligned with the N modules.

10. The semiconductor device according to claim 8, wherein M is an integer multiple of N.

11. The semiconductor device according to claim 8, wherein The selection circuit includes at least one multiplexer.

12. The semiconductor device according to claim 8, wherein The selection circuit includes a multiplexer for selecting a group corresponding to the N modules from among the M modules.

13. The semiconductor device according to claim 8, wherein The selection circuit includes M-N+1 multiplexers for selecting sequential groups corresponding to the N modules from among the M modules.

14. The semiconductor device according to claim 8, wherein The selection circuit includes a multiplexer for selecting the remaining modules except for the fixedly provided modules among the M modules.

15. A semiconductor device, comprising: a plurality of die, the plurality of die being configurable as semiconductor chips; as well as an interposer on which the plurality of die are mounted, wherein each of the plurality of core dies comprises a die-to-die interface for connecting to each other, A first die-to-die interface included in a first die among the plurality of die includes N modules, and A second die-to-die interface included in a second die among the plurality of die includes M modules, wherein the N modules are configured such that all of the N modules are connected to another die, and The M modules are configured such that only some of the M modules are connected to another chip die, and N and M are natural numbers.

16. The semiconductor device according to claim 15, wherein The second die-to-die interface further includes a selection circuit for selecting some of the M modules.

17. The semiconductor device according to claim 16, wherein The selection circuit includes at least one multiplexer.

18. The semiconductor device according to claim 17, wherein The selection circuit includes a multiplexer for selecting a group corresponding to the N modules from among the M modules.

19. The semiconductor device according to claim 17, wherein The selection circuit includes M-N+1 multiplexers for selecting sequential groups corresponding to the N modules from among the M modules.

20. The semiconductor device according to claim 17, wherein The selection circuit includes a multiplexer for selecting the remaining modules except for the fixedly provided modules among the M modules.

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