Mainboard double-circuit power supply input source control circuit and chip

Abstract

The embodiment of the invention provides a mainboard double-circuit power supply input source control circuit and a chip, the circuit comprises a logic judgment module, a level conversion module and a switch module, the logic judgment module comprises a first AND gate and a second AND gate, the first AND gate is used for judging the current working state according to an SLPS3 signal and an SLPS5 signal, and the second AND gate is used for judging the current working state according to the SLPS3 signal and the SLPS5 signal; the second AND gate is used for outputting a level control signal according to the main power supply signal; the level conversion module comprises a first MOS tube and a second MOS tube and is used for isolating the level control signal output by the logic judgment module and converting the level control signal into a first voltage signal and a second voltage signal which are used for controlling the switch module; the switch module comprises a first power MOS tube and a second power MOS tube, the first voltage signal and the second voltage signal are respectively used for controlling the switching of the second power MOS tube and the first power MOS tube, and the input source of the P5VDUAL is maintained at a high level when the system state is switched by controlling the switching time of the first power MOS tube and the second power MOS tube.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of electronic device power control, and in particular, to a mainboard dual-power input source control circuit and chip. Background Art

[0002] In modern computer systems, power management technology is becoming increasingly important as electronic devices continue to increase in functionality and demand for low power consumption. Electronic circuits are increasingly required to function immediately upon power-up. For example, USB On-The-Go (OTG) functionality (allowing USB devices to connect and exchange data directly) requires power to peripherals in all system states (S5 shutdown, S3 sleep, and S0 operating). In both S3 and S0 states, data in memory must remain powered to support rapid system recovery.

[0003] In traditional ATX power supply designs, the P5V_STBY (standby power) signal still provides 5V power when the system is off (S5 state) to support functions such as motherboard standby mode and USB port powering. However, the 5V_STBY current of traditional ATX power supplies is low (typically a maximum of 2A), which may not be sufficient to support some high-power peripherals or components. Many motherboard designs use more efficient power control to improve power supply capabilities under different operating conditions. For example, PWR_OK is used to control the input source of P5V_DUAL (dual power supply). PWR_OK is a signal from the ATX power supply that indicates that the power supply output has stabilized and can begin supplying power to the motherboard. Typically, the PWR_OK signal is sent to the motherboard after the 12V voltage stabilizes, triggering the motherboard power system to enter normal operation. However, there is a delay of approximately 360ms in the PWR_OK signal. This delay can cause the PWR_OK signal to fail to trigger the P5V_DUAL input voltage supply in time between the S3 and S0 states, resulting in a system failure to successfully boot or enter the S3 state. If P5V_DUAL does not have sufficient input source, the motherboard will fail to start, affecting the normal operation of the device.

[0004] Although controlling the P5V_DUAL input source through the uP7501M8 logic integrated circuit can more accurately manage power switching and avoid issues caused by PWR_OK signal delays, integrated circuits like the uP7501M8 are expensive, and there is a lack of alternative chips with the same functionality on the market. This increases costs for mass-produced motherboards and affects market competitiveness. Summary of the Invention

[0005] In order to ensure stable power switching of the system under various working states while reducing circuit costs, the embodiments described herein provide a mainboard dual-power input source control circuit and chip.

[0006] According to a first aspect of the present disclosure, a mainboard dual-power input source control circuit is provided, comprising: a logic judgment module, a level conversion module, and a switch module. The logic judgment module includes a first and a second AND gate, the first AND gate being used to judge the current operating state based on an SLP_S3 signal and an SLP_S5 signal, and the second AND gate being used to output a level control signal based on a main power supply signal. The level conversion module includes a first MOS transistor and a second MOS transistor, and is used to isolate the level control signal output by the logic judgment module and convert the level control signal into a first voltage signal and a second voltage signal for controlling the switch module. The switch module includes a first power MOS transistor and a second power MOS transistor, and by controlling the switching time of the first and second power MOS transistors, the input source of P5V_DUAL is maintained at a high level when the system state switches.

[0007] In some embodiments of the present disclosure, the level control signal is used to control the input source switching of P5V_DUAL. When the main power signal is present, the second power MOS tube is turned on, and the input source of P5V_DUAL comes from the 5V main power supply; when the main power signal does not exist, the first power MOS tube is turned on, and the input source of P5V_DUAL comes from the 5V standby voltage.

[0008] In some embodiments of the present disclosure, the logic judgment module also includes a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor. The first input terminal and the second input terminal of the first AND gate are respectively connected to the SLP_S3 signal and the SLP_S5 signal of the system, and the SLP_S3 signal and the SLP_S5 signal of the system are both controlled by the CPU; one end of the first resistor is connected to the first input terminal of the first AND gate, and the other end is grounded; one end of the second resistor is connected to the second input terminal of the first AND gate, and the other end is grounded; the power supply terminal of the first AND gate is connected to the 3.3V power supply voltage, and the output terminal of the first AND gate is connected to the second input terminal of the second AND gate through the third resistor; the first input terminal of the second AND gate is connected to the 5V power supply voltage through the fourth resistor, and the first input terminal of the second AND gate is grounded through the fifth resistor; the power supply terminal of the second AND gate is connected to the 3.3V power supply voltage.

[0009] In some embodiments of the present disclosure, the first resistor and the second resistor are pull-down resistors, which are used to fix the states of the system's SLP_S3 signal and SLP_S5 signal when the CPU is initialized; the third resistor is used to suppress signal reflection and ringing in the logic judgment module; the fourth resistor and the fifth resistor are used to divide the 5V power supply voltage into a 3.3V voltage as the input signal of the first input terminal of the second AND gate.

[0010] In some embodiments of the present disclosure, the level conversion module further includes a sixth resistor and a seventh resistor, the source of the first MOS tube and the source of the second MOS tube are both connected to the output end of the second AND gate, the gate of the first MOS tube is connected to the 3.3V power supply voltage through the sixth resistor, and the gate of the second MOS tube is connected to the 3.3V power supply voltage through the seventh resistor.

[0011] In some embodiments of the present disclosure, when the second AND gate outputs a high level, the first MOS transistor and the second MOS transistor are in the off state, the drain voltage of the first MOS transistor is pulled up to 5V, and the drain voltage of the second MOS transistor is pulled up to 12V.

[0012] In some embodiments of the present disclosure, the switch module further includes an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor;

[0013] The drain voltage of the second MOS transistor is connected to the drain of the first power MOS transistor via the first capacitor, connected to the source of the first power MOS transistor via the second capacitor, and connected to the gate of the first power MOS transistor; the drain of the first power MOS transistor is connected to P5V_DUAL; one end of the eighth resistor is grounded and the other end is connected to P5V_DUAL; one end of the ninth resistor is connected to the gate of the first power MOS transistor and the other end is connected to the 5V standby voltage; the source of the first power MOS transistor is connected to the third capacitor, the fourth capacitor, and the fifth capacitor; one end of the third capacitor, the fourth capacitor, and the fifth capacitor are grounded and the other end is connected to the 5V standby voltage;

[0014] The drain voltage of the first power MOS tube is connected to the source of the second power MOS tube via the eighth capacitor, and is also connected to the gate of the second power MOS tube; the drain of the second power MOS tube is connected to P5V_DUAL and is grounded through the sixth and seventh capacitors; one end of the tenth resistor is connected to the gate of the second power MOS tube, and the other end is connected to the 12V power supply voltage; the source of the second power MOS tube and the common end of the ninth and tenth capacitors are connected to the 5V power supply voltage, and the other ends of the ninth and tenth capacitors are grounded.

[0015] In some embodiments of the present disclosure, the first power MOS transistor uses WMS16P03T1, and the second power MOS transistor uses WMS032N04LG2; when the system state changes from SLP_S3=0, SLP_S5=1 to SLP_S3=1, SLP_S5=1, the on-time of the second power MOS transistor is controlled to be 15 ns, and the off-time of the first power MOS transistor is controlled to be 105 ns, so that when the gate levels of the first power MOS transistor and the second power MOS transistor change from 0 to 1, P5V_DUAL maintains a high level; when the system state changes from SLP_S3=1, SLP_S5=1 to SLP_S3=0, SLP_S5=1, the on-time of the first power MOS transistor is controlled to be 33.5 ns, and the off-time of the second power MOS transistor is controlled to be 38.6 ns, so that when the gate levels of the first power MOS transistor and the second power MOS transistor change from 1 to 0, P5V_DUAL maintains a high level.

[0016] In some embodiments of the present disclosure, the capacitance values ​​of the first capacitor, the second capacitor, and the eighth capacitor are 0.01 μF, and the capacitance values ​​of the fifth capacitor and the seventh capacitor are 0.1 μF, which are used to filter the signal; the capacitance values ​​of the third capacitor, the fourth capacitor, the sixth capacitor, the ninth capacitor, and the tenth capacitor are 10 μF, which are used to stabilize the power supply voltage; the eighth resistor is used to quickly discharge P5V_DUAL when the power is off; the ninth resistor and the tenth resistor are used to limit the current passing through the 5V and 12V lines.

[0017] According to a second aspect of the present disclosure, a chip is provided. The chip includes the mainboard dual-power input source control circuit according to the first aspect of the present disclosure.

[0018] According to the mainboard dual-power input source control circuit chip provided by the embodiment of the present disclosure, the working state of the system is judged according to the SLP_S3 signal and the SLP_S5 signal, and the input source switching is controlled in combination with the main power signal, which can ensure that the system can obtain the required stable power supply under different working states, and will not cause system failures due to insufficient power supply or untimely switching. Level conversion not only effectively avoids interference between different signal sources, but also can convert the control signal into a voltage signal suitable for controlling the switch module, thereby improving the stability and reliability of the circuit. By accurately controlling the switching time of the power MOS tube in the switch module, the system can provide a smooth transition when switching states, avoiding system instability or restart due to power supply fluctuations or instantaneous voltage changes, while reducing circuit costs and improving the stability of the system during long-term operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0020] Figure 1 1 is a schematic structural diagram of a mainboard dual-power input source control circuit according to an embodiment of the present disclosure;

[0021] Figure 2 is a system sequential logic control truth table according to an embodiment of the present disclosure;

[0022] Figure 3 is a circuit schematic diagram of a logic judgment module according to an embodiment of the present disclosure;

[0023] Figure 4 is a circuit schematic diagram of a level conversion module according to an embodiment of the present disclosure;

[0024] Figure 5 4 is a circuit diagram of a switch module according to an embodiment of the present disclosure.

[0025] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0028] In order to maintain a stable power supply for electronic devices in various working states (such as S5, S3, and S0) to ensure rapid startup and stable operation of the system, the embodiment of the present disclosure provides a motherboard dual-power input source control circuit. Through the coordinated work of modules such as logic judgment, level conversion, and MOS switch control, it ensures stability during the power switching process and avoids power-off and restart problems caused by dead time.

[0029] Figure 1 Schematic diagram of the structure of the mainboard dual-power input source control circuit according to the embodiment of the present disclosure. Figure 1 As shown, the motherboard dual power input source control circuit includes a logic judgment module, a level conversion module, and a switch module. The logic judgment module includes a first AND gate and a second AND gate. The first AND gate is used to determine the current operating state based on the SLP_S3 and SLP_S5 signals, and the second AND gate is used to output the level control signal VCC_ON based on the main power signal P5V. The level conversion module includes a first MOS transistor and a second MOS transistor, which are used to isolate the level control signal output by the logic judgment module and convert the level control signal VCC_ON into a first voltage signal 5VCC_DRV and a second voltage signal 5VSB_DRV for controlling the switch module. The switch module includes a first power MOS transistor and a second power MOS transistor. The first voltage signal 5VCC_DRV and the second voltage signal 5VSB_DRV are used to control the switching of the second power MOS transistor and the first power MOS transistor, respectively. By controlling the switching time of the first and second power MOS transistors, the input source of P5V_DUAL is maintained at a high level during system state switching.

[0030] In some embodiments of the present disclosure, a level control signal is used to control the input source switching of P5V_DUAL, a first voltage signal is used to control the switch of a first power MOS tube, and a second voltage signal is used to control the switch of a second power MOS tube. When the main power signal does not exist, the first power MOS tube is turned on, and the input source of P5V_DUAL comes from the 5V standby voltage, indicating that the system is in standby or off state at this time, with low power consumption. The current of P5V_STBY of ATX alone can meet the power consumption requirements of P5V_DUAL in the system at this time. When the main power signal exists, the second power MOS tube is turned on, and the input source of P5V_DUAL comes from the 5V main power supply, indicating that the system is in working state at this time.

[0031] Figure 2 is a system sequential logic control truth table according to an embodiment of the present disclosure. Figure 2As shown in the figure, the state of P5V_DUAL is output according to different combinations of four input signals: SLP_S5, SLP_S3, 5VCC, and 5VSB. Among them, 5VCC is the 5V main power signal, 5VSB is the 5V standby voltage signal, and P5V_DUAL is the final power output.

[0032] SLP_S3=1 and SLP_S5=1, the system is in the power-on state (S0). At this time, when the main power signal exists (5VCC=1), the input source of P5V_DUAL comes from the 5V main power supply. When the main power signal does not exist (5VCC=0), the input source of P5V_DUAL comes from the 5V standby voltage.

[0033] SLP_S5=1 and SLP_S3=0, the system is in sleep state (S3). At this time, regardless of whether the main power signal exists, the input source of P5V_DUAL comes from the 5V standby voltage.

[0034] SLP_S5=0, SLP_S3=X (X=0 or 1), the system is in the shutdown state (S5). At this time, when the standby power signal 5VSB is high (5VSB=1), the input source of P5V_DUAL comes from the 5V standby voltage, otherwise there is no voltage input.

[0035] Figure 3 : is a circuit diagram of a logic judgment module according to an embodiment of the present disclosure. Figure 3 As shown, the logic judgment module includes a first AND gate U44, a second AND gate U45, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first and second input terminals of the first AND gate U44 are respectively connected to the system's SLP_S3 and SLP_S5 signals, both of which are controlled by the CPU. One end of the first resistor R1 is connected to the first input terminal of the first AND gate U44, and the other end is grounded. One end of the second resistor R2 is connected to the second input terminal of the first AND gate U44, and the other end is grounded. The power supply terminal of the first AND gate U44 is connected to the 3.3V power supply voltage P3V3_STBY. Since the voltages of SLP_S3 and SLP_S5 are 3.3V, the logic AND gate U44 needs to operate in the S5 state, so the voltage of U44 selects P3V3_STBY.

[0036] The output end of the first AND gate U44 is connected to the second input end of the second AND gate U45 via the third resistor R3; the first input end of the second AND gate U45 is connected to the 5V power supply voltage P5V via the fourth resistor R4, and the first input end of the second AND gate U45 is grounded via the fifth resistor R5; the power supply end of the second AND gate U45 is connected to the 3.3V power supply voltage P3V3_STBY.

[0037] According to one embodiment of the present disclosure, the first and second AND gates U44 and U45 utilize an Aip74LVC1G08GA logic chip. The first and second resistors R1 and R2 are pull-down resistors, with a resistance value of 10kΩ. They are used to stabilize the state of the system's SLP_S3 and SLP_S5 signals during CPU initialization to prevent signal fluctuations. The third resistor R3, with a resistance value of 22Ω, is used to suppress signal reflections and ringing in the logic judgment module. The fourth and fifth resistors R4 and R5 are used to divide the 5V power supply voltage into 3.3V, which serves as the input signal for the first input terminal of the second AND gate U45.

[0038] The level conversion module is used to convert the input 3.3V signal into different voltage outputs (5V and 12V) to drive switch modules with different voltage requirements and play a role in electrical isolation. Figure 4 : is a circuit diagram of a level conversion module according to an embodiment of the present disclosure. Figure 4 As shown, the level conversion module includes a first MOS transistor Q44, a second MOS transistor Q45, a sixth resistor R6, and a seventh resistor R7. The first MOS transistor Q44 and the second MOS transistor Q45 are WM05N02M, which is an N-channel MOSFET suitable for use in power control circuits.

[0039] The source S of the first MOS transistor Q44 and the source S of the second MOS transistor Q45 are both connected to the output terminal of the second AND gate U45. The gates G of the first and second MOS transistors Q44 and Q45 are connected to the 3.3V power supply voltage P3V3_STBY via a sixth resistor and a seventh resistor, respectively. When the second AND gate U45 outputs a high level (VCC_ON output is 3.3V), the gates of Q44 and Q45 are both pulled up to 3.3V, resulting in a gate-source voltage difference of 0V. Therefore, the first and second MOS transistors Q44 and Q45 are not conducting. At this time, the drain voltages of Q44 and Q45 determine the voltage of the output signal. That is, when these MOSFETs are turned off, their drain voltages are affected by the pull-up voltage on their drains. The drain voltage of the first MOS transistor Q44 is pulled up to 5V (5VSB_DRV), and the drain voltage of the second MOS transistor Q45 is pulled up to 12V (5VCC_DRV). These converted voltage signals are further transmitted to the switch module to drive the circuits with corresponding voltage requirements.

[0040] Furthermore, the level shifter module achieves electrical isolation through the design of MOS transistors and pull-up resistors, ensuring that the 5VSB_DRV and 5VCC_DRV voltages do not interfere with each other. Although the 5VSB_DRV and 5VCC_DRV voltages on the back end are different, they can operate independently due to electrical isolation without affecting each other.

[0041] In this system, the P5V_DUAL power supply must always remain high. If there's a dead time during the MOSFET switching process (i.e., both MOSFETs are turned off simultaneously), P5V_DUAL may briefly drop to 0V, causing the system to mistakenly detect a power outage and reboot. This is unacceptable in practical applications. The switch module design focuses on ensuring the stability of the P5V_DUAL power supply. When the state changes, this prevents the system from detecting a power outage and rebooting due to the dead time during MOSFET switching. By properly selecting MOSFET specifications and adjusting the MOSFET switching time, P5V_DUAL is ensured to always remain high.

[0042] Figure 5 : is a circuit diagram of a switch module according to an embodiment of the present disclosure. Figure 5 As shown, the switch module includes a first power MOS transistor PQ29, a second power MOS transistor PQ30, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10.

[0043] Figure 4 The drain voltage 5VSB_DRV of the second MOS transistor Q45 is connected to the drain D (pins 5, 6, 7, and 8) of the first power MOS transistor PQ29 via the first capacitor C1, and to the source S (pins 1, 2, and 3) of the first power MOS transistor PQ29 via the second capacitor C2. The drain D (pins 5, 6, 7, and 8) of the first power MOS transistor PQ29 is also connected to the gate G (pin 4) of the first power MOS transistor PQ29. The drain D (pins 5, 6, 7, and 8) of the first power MOS transistor PQ29 is connected to P5V_DUAL. One end of an eighth resistor R8 is grounded, and the other end is connected to P5V_DUAL. One end of a ninth resistor is connected to the gate G (pin 4) of the first power MOS transistor PQ29, and the other end is connected to the 5V standby voltage P5V_STBY. The source S (pins 1, 2, 3) of the first power MOS transistor PQ29 is connected to the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5. One end of the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is grounded, and the other end is connected to the 5V standby voltage P5V_STBY.

[0044] Figure 4The drain voltage 5VCC_DRV of the first MOS transistor Q44 is connected to the source S (pins 1, 2, and 3) of the second power MOS transistor PQ30 via the eighth capacitor C8, and is also connected to the gate G (pin 4) of the second power MOS transistor PQ30. The drain D (pins 5, 6, 7, and 8) of the second power MOS transistor PQ30 is connected to P5V_DUAL and grounded via the seventh and sixth capacitors C7 and C6. One end of the tenth resistor R10 is connected to the gate G (pin 4) of the second power MOS transistor PQ30, and the other end is connected to the 12V power supply voltage P12V. The source S (pins 1, 2, and 3) of the second power MOS transistor PQ30 and the common end of the ninth and tenth capacitors C9 and C10 are connected to the 5V power supply voltage P5V. The other ends of the ninth and tenth capacitors C9 and C10 are grounded.

[0045] According to one embodiment of the present disclosure, the first power MOS tube PQ29 uses WMS16P03T1, and the second power MOS tube PQ30 uses WMS032N04LG2. WMS16P03T1 is a P-channel MOSFET whose low on-resistance characteristic can reduce power loss and is suitable for applications that require fast switching. WMS032N04LG2 is an N-channel MOSFET that can provide better conductivity and response speed and is suitable for high-voltage power supply applications. Their switching characteristics (Turn-on time and Turn-off time) are crucial to the stability of the power supply. The capacitance value of the first capacitor, the second capacitor, and the eighth capacitor is 0.01μF, and the capacitance value of the fifth capacitor and the seventh capacitor is 0.1μF, which are used to filter the signal and improve and stabilize the switching performance. The capacitance value of the third capacitor, the fourth capacitor, the sixth capacitor, the ninth capacitor, and the tenth capacitor is 10μF, which is used to stabilize the power supply voltage.

[0046] During a power outage, P5V_DUAL may continue to maintain a certain voltage due to the presence of capacitors. If no action is taken, the residual charge in the capacitors may prevent the circuit from being completely disconnected or may generate noise. The eighth resistor provides a fast discharge path for the capacitors, ensuring that the P5V_DUAL voltage drops to zero as quickly as possible after power is lost. The ninth and tenth resistors are used to limit the current through the 5V and 12V lines to prevent excessive current from damaging other components in the circuit or causing overheating. The presence of current limiting resistors can help protect the power supply circuit and the load circuit, ensuring that the system does not malfunction due to overload during operation.

[0047] When the system state changes from SLP_S3 = 0, SLP_S5 = 1 to SLP_S3 = 1, SLP_S5 = 1, the turn-on time of the second power MOS transistor PQ30 is controlled to 15ns, and the turn-off time of the first power MOS transistor PQ29 is controlled to 105ns. This ensures that when the gate levels of the first and second power MOS transistors PQ29 and PQ30 change from 0 to 1, P5V_DUAL remains high, avoiding dead time. When the system state changes from SLP_S3 = 1, SLP_S5 = 1 to SLP_S3 = 0, SLP_S5 = 1, the turn-on time of the first power MOS transistor PQ29 is controlled to 33.5ns, and the turn-off time of the second power MOS transistor PQ30 is controlled to 38.6ns. This ensures that when the gate levels of the first and second power MOS transistors PQ29 and PQ30 change from 1 to 0, P5V_DUAL remains high, avoiding temporary power outages in the system.

[0048] When the SLP_S3 state changes, the system will directly use the SLP_S5 and SLP_S3 signals to control the P5V_DUAL input source, thereby ensuring that at the moment the device starts, the 5V_DUAL power supply can quickly switch to the 5VCC input source with sufficient current supply capability, avoiding the current supply shortage problem caused by delay, ensuring that the system can have stable power supply, and thus ensuring the normal operation of the system.

[0049] An embodiment of the present disclosure further provides a chip, which includes a mainboard dual-power input source control circuit according to an embodiment of the present disclosure.

[0050] In summary, according to the embodiment of the present disclosure, the mainboard dual-power input source control circuit chip provided by the embodiment of the present invention determines the working state of the system according to the SLP_S3 signal and the SLP_S5 signal, and then controls the input source switching in combination with the main power signal, which can ensure that the system can obtain the required stable power supply under different working states, and will not cause system failures due to insufficient power supply or untimely switching. Level conversion not only effectively avoids interference between different signal sources, but also can convert the control signal into a voltage signal suitable for controlling the switch module, thereby improving the stability and reliability of the circuit. By precisely controlling the switching time of the power MOS tube in the switch module, the system can provide a smooth transition when switching states, avoiding system instability or restart due to power supply fluctuations or instantaneous voltage changes, while reducing circuit costs and improving the stability of the system during long-term operation.

[0051] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0052] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0053] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A motherboard dual-power input source control circuit, characterized in that: include: Logic judgment module, level conversion module and switch module; The logic judgment module includes a first AND gate and a second AND gate, the first AND gate is used to judge the current working state according to the SLP_S3 signal and the SLP_S5 signal, and the second AND gate is used to output a level control signal according to the main power signal; The level conversion module includes a first MOS transistor and a second MOS transistor, which are used to isolate the level control signal output by the logic judgment module and convert the level control signal into a first voltage signal and a second voltage signal for controlling the switch module; The switch module includes a first power MOS transistor and a second power MOS transistor. The first voltage signal and the second voltage signal are used to control the switching of the second power MOS transistor and the first power MOS transistor, respectively. By controlling the switching time of the first power MOS transistor and the second power MOS transistor, the input source of P5V_DUAL is maintained at a high level when the system state is switched.

2. The mainboard dual power input source control circuit according to claim 1, characterized in that: The level control signal is used to control the input source switching of P5V_DUAL. When the main power signal exists, the second power MOS tube is turned on, and the input source of P5V_DUAL comes from the 5V main power supply; when the main power signal does not exist, the first power MOS tube is turned on, and the input source of P5V_DUAL comes from the 5V standby voltage.

3. The motherboard dual power input source control circuit according to claim 1, characterized in that: The logic judgment module also includes a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor. The first input terminal and the second input terminal of the first AND gate are respectively connected to the system's SLP_S3 signal and SLP_S5 signal, and the SLP_S3 signal and the SLP_S5 signal are both controlled by the CPU; one end of the first resistor is connected to the first input terminal of the first AND gate, and the other end is grounded; one end of the second resistor is connected to the second input terminal of the first AND gate, and the other end is grounded; the power supply terminal of the first AND gate is connected to a 3.3V power supply voltage, and the output terminal of the first AND gate is connected to the second input terminal of the second AND gate via the third resistor; the first input terminal of the second AND gate is connected to a 5V power supply voltage via the fourth resistor, and the first input terminal of the second AND gate is grounded via the fifth resistor; the power supply terminal of the second AND gate is connected to a 3.3V power supply voltage.

4. The mainboard dual power input source control circuit according to claim 3, characterized in that: The first and second resistors are pull-down resistors, used to fix the states of the system's SLP_S3 and SLP_S5 signals during CPU initialization; the third resistor is used to suppress signal reflection and ringing in the logic judgment module; the fourth and fifth resistors are used to divide the 5V power supply voltage into a 3.3V voltage as the input signal of the first input terminal of the second AND gate.

5. The mainboard dual power input source control circuit according to claim 1, characterized in that: The level conversion module also includes a sixth resistor and a seventh resistor. The source of the first MOS transistor and the source of the second MOS transistor are both connected to the output end of the second AND gate. The gate of the first MOS transistor is connected to the 3.3V power supply voltage through the sixth resistor, and the gate of the second MOS transistor is connected to the 3.3V power supply voltage through the seventh resistor.

6. The mainboard dual power input source control circuit according to claim 5, characterized in that: When the second AND gate outputs a high level, the first MOS transistor and the second MOS transistor are in a turned-off state, the drain voltage of the first MOS transistor is pulled up to 5V, and the drain voltage of the second MOS transistor is pulled up to 12V.

7. The mainboard dual power input source control circuit according to claim 5, characterized in that: The switch module further includes an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor; The drain voltage of the second MOS transistor is connected to the drain of the first power MOS transistor via the first capacitor, connected to the source of the first power MOS transistor via the second capacitor, and connected to the gate of the first power MOS transistor; the drain of the first power MOS transistor is connected to P5V_DUAL; one end of the eighth resistor is grounded and the other end is connected to P5V_DUAL; one end of the ninth resistor is connected to the gate of the first power MOS transistor and the other end is connected to the 5V standby voltage; the source of the first power MOS transistor is connected to the third capacitor, the fourth capacitor, and the fifth capacitor; one end of the third capacitor, the fourth capacitor, and the fifth capacitor are grounded and the other end is connected to the 5V standby voltage; The drain voltage of the first power MOS transistor is connected to the source of the second power MOS transistor via the eighth capacitor, and is also connected to the gate of the second power MOS transistor; the drain of the second power MOS transistor is connected to P5V_DUAL and is grounded through the sixth and seventh capacitors; one end of the tenth resistor is connected to the gate of the second power MOS transistor, and the other end is connected to a 12V power supply voltage; the source of the second power MOS transistor and the common end of the ninth and tenth capacitors are connected to a 5V power supply voltage, and the other ends of the ninth and tenth capacitors are grounded.

8. The mainboard dual power input source control circuit according to claim 7, characterized in that: The first power MOS tube adopts WMS16P03T1, and the second power MOS tube adopts WMS032N04LG2; When the system state changes from SLP_S3=0, SLP_S5=1 to SLP_S3=1, SLP_S5=1, the on-time of the second power MOS transistor is controlled to be 15ns, and the off-time of the first power MOS transistor is controlled to be 105ns, so that when the gate levels of the first power MOS transistor and the second power MOS transistor change from 0 to 1, P5V_DUAL maintains a high level; When the system state changes from SLP_S3=1, SLP_S5=1 to SLP_S3=0, SLP_S5=1, the on-time of the first power MOS tube is controlled to be 33.5ns, and the off-time of the second power MOS tube is controlled to be 38.6ns, so that when the gate levels of the first power MOS tube and the second power MOS tube change from 1 to 0, P5V_DUAL maintains a high level.

9. The mainboard dual power input source control circuit according to claim 7, characterized in that: The capacitance values ​​of the first capacitor, the second capacitor, and the eighth capacitor are 0.01 μF, and the capacitance values ​​of the fifth capacitor and the seventh capacitor are 0.1 μF, which are used to filter the signal; the capacitance values ​​of the third capacitor, the fourth capacitor, the sixth capacitor, the ninth capacitor, and the tenth capacitor are 10 μF, which are used to stabilize the power supply voltage; the eighth resistor is used to quickly discharge P5V_DUAL when the power is off, and the ninth resistor and the tenth resistor are used to limit the current passing through the 5V and 12V lines.

10. A chip, wherein: It comprises the mainboard dual power input source control circuit according to any one of claims 1-9.

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