Software and hardware cooperation power supply protection circuit of power distribution automation terminal

Abstract

The invention provides a software and hardware cooperation power supply protection circuit of a power distribution automation terminal, which comprises a power supply input protection circuit, a voltage conversion circuit, a power failure detection circuit, a voltage maintenance protection circuit and a clock backup battery protection circuit, and is characterized in that the power failure detection circuit adopts a photoelectric isolation technology to monitor a power supply input state in real time; when it is detected that the power supply is disconnected or powered down, a specific level signal is output, and power down event detection is triggered; on the software level, the function of a power failure detection pin is defined in an equipment tree, the power failure detection pin is configured to be an interrupt trigger pin, the power failure detection pin is initialized, interrupt is requested, an interrupt trigger condition is set to be level change, and a power failure detection event is triggered when the interrupt trigger condition occurs. According to the method, system damage caused by accidental power failure is eliminated in a software and hardware combination mode, the reliability of the terminal is remarkably improved, the service life of the terminal is remarkably prolonged, the software has enough time to complete file operation through power failure protection, and therefore the purpose of protecting the file system is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of power automation equipment, and specifically to a software-hardware coordinated power supply protection circuit for a distribution automation terminal. The circuit is suitable for scenarios with high requirements on power supply stability, such as distribution automation terminals, smart meters, and power monitoring equipment, and is especially suitable for anti-power-off data protection needs under operating systems such as Linux. Background Art

[0002] Power supply design is crucial for power products like distribution automation terminals. The quality of the power supply directly impacts the stability of the product, especially with the widespread use of operating systems like Linux. A power outage during data writing to memory can cause data loss at best, or even damage operating system files and paralyze the system. Despite various power-loss-resistant file systems, system crashes are still possible. Therefore, the impact of power outages should be considered in power supply design, allowing the operating system time to complete file system operations, release peripherals, and power down, minimizing damage to the system.

[0003] Although existing technologies implement basic protection through power-loss resistant file systems (such as UBIFS) or relays, the following problems still exist: 1. Relays respond slowly and have a limited lifespan (contacts age easily). 2. Software-based power-off protection alone cannot cover hardware-level faults (such as momentary reverse power connection). 3. The backup battery charging and discharging circuit lacks precise control, which may cause system restart failure.

[0004] Therefore, there is an urgent need to design a power protection solution that combines software and hardware to meet the anti-interference requirements of power industry standards (such as GB / T17626.11-2023). Summary of the Invention

[0005] In response to various problems existing in the prior art, the present invention provides a software and hardware coordinated power supply protection circuit for a distribution automation terminal. By combining software and hardware, it eliminates system damage caused by accidental power outages, significantly improves the reliability and service life of the terminal, and through the protection masking processing of power-off protection, the software has enough time to complete file operations, thereby achieving the purpose of protecting the file system.

[0006] The present invention achieves the above-mentioned purpose through the following technical solutions: A software and hardware coordinated power protection circuit for a distribution automation terminal, characterized in that it includes a main board and a core board, wherein the main board includes the following components: Power input protection circuit, used to control the connection and disconnection of input power; The voltage conversion circuit is connected to the power input protection circuit and is used to convert the input power voltage into the operating voltage of each module; The power-off detection circuit uses optoelectronic isolation technology to monitor the power input status in real time. When the power input is normal, it outputs a first-level signal. When a power disconnection or power failure is detected, it outputs a second-level signal, triggering power-off event detection. At the software level, the power-off detection pin is defined in the device tree and configured as an interrupt trigger pin. The power-off detection pin is initialized and an interrupt is requested. The interrupt trigger condition is set to a level change. When the interrupt trigger condition occurs, a power-off detection event is triggered. This event includes a delayed confirmation event and an execution event of the power-off handling function. The voltage maintenance protection circuit is connected to the voltage conversion circuit and is used to perform a discharge operation through the first supercapacitor to maintain normal power supply to the core board key load when an abnormality occurs in the main power supply; The clock backup battery protection circuit is connected to the clock chip and uses a second supercapacitor as a backup battery. When an abnormality occurs in the main power supply, it automatically switches to the second supercapacitor for power supply to ensure the continuous operation of the clock chip.

[0007] According to a software and hardware coordinated power supply protection circuit of a distribution automation terminal provided by the present invention, the power input protection circuit adopts an anti-reverse connection diode D37 and an electronic overvoltage protection circuit composed of a PNP transistor Q30 and a P-channel field effect transistor N2. The anti-reverse connection diode D37 is connected in series in the input path of the external input voltage. When the positive and negative poles of the power supply are reversed, the reverse is cut off, the circuit is not conductive, and the reverse voltage is prevented from entering the system; the base of the PNP transistor Q30 is connected between the cathode of the anti-reverse connection diode D37 and the cathode of the voltage regulator diode D36, the anode of the voltage regulator diode D36 is grounded, and the collector of the PNP transistor Q30 is connected to the gate of the P-channel field effect transistor N2; the source of the P-channel field effect transistor N2 is connected to the 24V DC power input, and its drain is connected to the 24V power output.

[0008] According to a software and hardware coordinated power supply protection circuit for a distribution automation terminal provided by the present invention, an external input voltage is detected. When the external input voltage is less than a preset threshold voltage, the voltage regulator diode D36 is in a cut-off state, so that the PNP transistor Q30 lacks a conduction loop and its collector is in a low voltage state. When the external voltage is greater than the preset threshold voltage of 24V and the voltage difference between the base and emitter of the PNP transistor Q30 reaches the conduction voltage of the PN junction, the PNP transistor Q30 is turned on. At this time, the collector voltage of the PNP transistor Q30 is substantially equal to the external input voltage. The collector voltage of the PNP transistor Q30 is used as the control signal for the P-channel field-effect transistor N2. When the external input voltage is lower than the preset threshold voltage, the collector of the PNP transistor Q30 is at a low voltage, that is, the gate voltage of the field-effect transistor N2 is also at a low voltage. In this case, the drain and source of the P-channel field-effect transistor N2 are turned on, allowing the external input voltage to be output normally through the field-effect transistor. When the external voltage is greater than 24V and the PNP transistor Q30 is turned on, causing the gate voltage of the P-channel field-effect transistor N2 to be substantially equal to its source voltage, the P-channel field-effect transistor N2 is turned off, cutting off the output path of the external input voltage to prevent overvoltage from damaging the internal circuit.

[0009] According to a software and hardware coordinated power supply protection circuit for a distribution automation terminal provided by the present invention, the power-off detection circuit includes an optical isolator U2, a voltage regulator diode D4, a voltage regulator diode D6, and an output pin PA8. The cathode of the voltage regulator diode D4 is connected to the input voltage VCC-DCIN, and its anode is connected to pin 1 of the optical isolator U2. The cathode of the voltage regulator diode D6 is connected between pin 1 of the optical isolator U2 and a resistor R16. The anode of the voltage regulator diode D6 is connected to pin 2 of the optical isolator U2 and ground, and is used to perform voltage regulation protection on the input side of the optical isolator U2. Pin 4 of the optical isolator U2 is connected to the power supply VDD_3V3, and pin 3 of the optical isolator U2 is connected to the output pin PA8 through a resistor R17. The output pin PA8 serves as the output end of the power-off detection signal. When PA8 outputs a high level, it indicates that the input voltage VCC-DCIN is normal; when PA8 is a low level, it indicates that the input voltage VCC-DCIN is disconnected or powered off, triggering power-off event detection.

[0010] According to the present invention, a software and hardware coordinated power supply protection circuit for a distribution automation terminal is provided. A voltage zener diode D4 is provided as a voltage detection element, and a specific voltage threshold range is preset. When the input voltage VCC - DCIN is greater than a specific value K1 within the threshold range, the voltage zener diode D4 meets the conduction condition and enters the on state, providing an input signal to the optical isolator U2. When the input voltage VCC - DCIN is disconnected or powered off, and the voltage value is less than the specific value K1, the voltage zener diode D4 cannot meet the conduction condition and enters the off state. At this time, no voltage is input to pin 1 of the optical isolator U2. The optical isolator U2 is used as a key component for signal transmission and isolation. When there is voltage input to pin 1 of the optical isolator U2, pins 4 and 3 of the optical isolator U2 are turned on, causing the output pin PA8 to output a high-level signal, indicating that the power input is in a normal state; when there is no voltage input to pin 1 of the optical isolator U2, pins 4 and 3 of the optical isolator U2 cannot be turned on, and the output pin PA8 outputs a low-level signal, which serves as a detection signal for power disconnection or power failure.

[0011] According to a software and hardware coordinated power supply protection circuit of a distribution automation terminal provided by the present invention, the voltage maintenance protection circuit includes a diode D1, a first supercapacitor composed of a supercapacitor E1 and a supercapacitor E2, an overvoltage protection circuit U1, an overvoltage protection circuit U2, and a voltage monitoring circuit composed of a voltage regulator D3 and a PNP transistor Q2. The anode of the diode D1 is connected to a 5V power supply, the cathode of the diode D1 is connected to the positive electrode of the first supercapacitor, and the VCC pins of the overvoltage protection circuit U1 and the overvoltage protection circuit U2 are respectively connected to the supercapacitor E1 and the supercapacitor The positive pole of E2, the IOUT pins of the overvoltage protection circuit U1 and the overvoltage protection circuit U2 are connected to the ground through the current discharge resistors R3 and R4 respectively; the base of the PNP transistor Q2 is connected to the anode of the Zener diode D3 through the resistor R6, and the cathode of the Zener diode D3 is connected to the gate of the field effect transistor Q1. When the voltage is higher than the Zener diode voltage regulation value, it is turned on. The emitter of the PNP transistor Q2 is grounded, the collector of the PNP transistor Q2 is connected to the gate and source of the field effect transistor Q1, and the drain of the field effect transistor Q1 is connected to the +5V_CORE pin of the core board.

[0012] According to the present invention, a software and hardware coordinated power supply protection circuit of a distribution automation terminal also includes a mainboard power supply circuit, which includes a power supply chip U10, a 5V input power supply, an input filter circuit and an output filter circuit. The signal input by the 5V input power supply is converted into voltage through the power supply chip U10. During the power conversion process, the signal is filtered and output through the input filter circuit and the output filter circuit; the power supply chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power supply chip. When each power supply module in the core board reaches a stable working state, the PG_V33 signal is set to a valid state, triggering the power supply chip U10 to start working and complete the power-on of the peripheral IO port; wherein, the PG_V33 signal is the last power good signal sent by the core board to indicate that the mainboard power-on is completed.

[0013] According to a software and hardware coordinated power supply protection circuit of a distribution automation terminal provided by the present invention, the clock backup battery protection circuit includes a real-time clock chip, a second supercapacitor E3, and an LED lamp. The anode of the LED lamp is connected to a 5V input power supply, the cathode of the LED lamp is connected to the positive electrode of the second supercapacitor E3 and the VBAT pin of the real-time clock chip, the negative electrode of the second supercapacitor E3 is grounded, and the SCL and SDA pins of the real-time clock chip are used for I2C communication and are respectively connected to an external I2C bus; A filter capacitor is connected to the VBAT pin of the real-time clock chip, one end of which is connected to the VBAT pin of the real-time clock chip and the other end is grounded, for filtering high-frequency noise on the power supply line.

[0014] According to a software and hardware coordinated power protection circuit for a distribution automation terminal provided by the present invention, the power failure processing function implements interrupt response and system protection through the following steps, and works in conjunction with the optical isolation device U2 and the device tree configuration: The optical isolator U2 monitors the power input status in real time and converts the level change on the power side into the optical signal strength change on the isolation side. When the power input is normal, the output side of the optical isolator U2 is turned on and outputs a first level signal to the power-off detection pin of the core board. When it detects that the power is disconnected or the voltage drops below the threshold, the output side of the optical isolator U2 is cut off and outputs a second level signal to the power-off detection pin, triggering a level change interrupt. Define the function parameters of the power-down detection pin in the device tree, including the pin number, the interrupt type triggered by the level change, and the default level state; When the system is initialized, the following operations are completed according to the device tree configuration: Set the power-down detection pin to input mode and enable the internal pull-up / pull-down resistor; Register the power-down processing function to the interrupt vector table and set the interrupt priority to the highest level. The interrupt trigger condition is: when the power-down detection pin level jumps from the first level to the second level, the MCU jumps to the interrupt service routine and executes the delayed confirmation event. After a delay confirming that the power-off detection pin remains at the second level, the power-off processing function is executed: the current system operating status is written to the MCU's built-in retention RAM, and a command is sent to the power management chip via the I2C / SPI interface to disconnect the main power path and enable the supercapacitor as a backup power source. The dynamic voltage adjustment algorithm is then started to gradually reduce the MCU operating frequency based on the remaining energy in the supercapacitor. Turn off all non-essential peripheral clocks and keep only the RTC running to record the power-off timestamp; set the power-off flag in the Retention RAM for identification when power is restored.

[0015] According to a software and hardware coordinated power supply protection circuit of a distribution automation terminal provided by the present invention, the delayed confirmation event includes: When the power-off detection pin level is detected to jump from the first level to the second level, the current timestamp is recorded immediately T detect, as the starting reference point of the delay; Start the hardware timer to execute software delay T delay , satisfying the formula: T delay = T threshold -Δ T error in, Tthreshold is the preset power-off confirmation threshold time; Δ T error It is the timer accuracy compensation value; During the delay period, when the hardware timer triggers an interrupt, a delay completion flag is generated. Flag delay_done ; when Flag delay_done =1, read the level status of the power-down detection pin again V PA8 , and execute the following decision logic: like V PA8 =First level, it is determined to be power supply noise interference, clear the interrupt flag and exit; like V PA8 = The second level confirms that the power-off event is valid and triggers the power-off processing function. At this time, the total response time of the system is T response Satisfies the formula: T response = T detect + T delay + T process in, T process This is the execution time of the power-off processing function.

[0016] It can be seen that compared with the existing technology, the software and hardware coordinated power supply protection circuit of the distribution automation terminal proposed in the present invention has significant advantages in ensuring the stable operation of the distribution automation terminal, data security, and improving system reliability by designing multiple key circuit modules such as power input protection, voltage conversion, power failure detection, voltage maintenance, and clock backup battery protection, combined with precise configuration and coordinated control at the software level. The specific beneficial effects are as follows: 1. The present invention effectively filters these undesirable power signals through the power input protection circuit, preventing them from damaging subsequent circuits. When a serious anomaly occurs in the input power, such as overvoltage, undervoltage, or short circuit, the power connection is quickly disconnected to prevent the fault from escalating. This protects the various modules within the distribution automation terminal from the effects of power failure, providing a solid foundation for stable equipment operation.

[0017] 2. The power-off detection circuit of the present invention uses optoelectronic isolation technology to monitor the power input status in real time and accurately. The application of optoelectronic isolation technology effectively isolates the interference signal on the power supply side, improving the accuracy and reliability of power-off detection. When the power input is normal, the circuit outputs a first level signal; once it detects that the power is disconnected or the power is off, it immediately outputs a second level signal to quickly trigger the power-off event detection. At the software level, by accurately defining the function of the power-off detection pin in the device tree, it is configured as an interrupt trigger pin, and the relevant parameters are initialized, and the interrupt trigger condition is set to a level change. When the interrupt trigger condition occurs, the power-off detection event can be quickly triggered, including a delayed confirmation event and an execution event of the power-off processing function. The power-off detection mechanism of the software and hardware collaboration provided by the present invention achieves a rapid response to power anomalies, which gains valuable time for subsequent power-off protection operations.

[0018] 3. It plays a key role in the event of an abnormality in the main power supply. When the main power supply fails or loses power, the present invention can quickly start the discharge operation of the supercapacitor through the voltage maintenance protection circuit, and can provide stable power support for the key loads of the core board in a short time, maintaining its normal operation. In this way, the distribution automation terminal can still complete some key operations such as data preservation and status reporting in the event of a main power outage, avoiding data loss and system disorder caused by sudden power outages, and improving system reliability and data security.

[0019] 4. When the main power supply is functioning normally, the clock chip is powered by the main power supply. If an anomaly occurs in the main power supply, the circuit automatically and seamlessly switches to a secondary supercapacitor for power. Supercapacitors, with their low self-discharge rate and long lifespan, provide the clock chip with a stable power supply for extended periods, ensuring continuous operation. Accurate system time is crucial for distribution automation terminals, as it involves key functions such as data logging timestamps and the execution of scheduled tasks. The clock backup battery protection circuit ensures system time accuracy, avoids the accumulation of time errors caused by clock interruptions, and improves overall system performance and reliability.

[0020] 5. The power protection circuit of this invention achieves deep synergy between hardware circuitry and software control. The hardware circuitry provides a solid physical foundation for power protection, while the software control enables precise configuration and flexible scheduling of the hardware circuitry. Through software-level device tree configuration, interrupt trigger settings, and the development of power-loss handling functions, intelligent management of the power protection circuitry is achieved. This fully leverages the high performance of the hardware and the flexibility of the software, enabling dynamic adjustment of power protection strategies based on different application scenarios and requirements, thereby improving the overall performance and adaptability of the entire distribution automation terminal system.

[0021] 6. The present invention reasonably designs the power-on sequence of the mainboard power supply and the core board so that the mainboard power supply is powered on later than the core board, thereby effectively preventing the occurrence of power backflow. In electronic equipment, power backflow may cause damage to the core board main chip, seriously affecting the performance and life of the equipment. The power protection design of this solution avoids the occurrence of this situation, provides a safe operating environment for the core board main chip, and ensures the stability and reliability of the product during long-term use. It is crucial for power terminal equipment that needs to run continuously for a long time. It can reduce equipment failures caused by power problems, reduce maintenance costs, and improve the overall operating efficiency of the power system.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of an embodiment of a software and hardware coordinated power protection circuit of a distribution automation terminal of the present invention.

[0024] Figure 2 It is a circuit principle diagram of a power input protection circuit in an embodiment of a software and hardware coordinated power protection circuit of a distribution automation terminal of the present invention.

[0025] Figure 3 It is a circuit principle diagram of a power failure detection circuit in an embodiment of a software and hardware coordinated power protection circuit of a distribution automation terminal of the present invention.

[0026] Figure 4 It is a circuit principle diagram of a voltage maintenance protection circuit in an embodiment of a software and hardware coordinated power protection circuit of a distribution automation terminal of the present invention.

[0027] Figure 5 It is a circuit schematic diagram of a mainboard power supply circuit in an embodiment of a software and hardware coordinated power protection circuit of a distribution automation terminal of the present invention.

[0028] Figure 6 The present invention is a circuit schematic diagram of a clock backup battery protection circuit in an embodiment of a software and hardware coordinated power supply protection circuit for a distribution automation terminal. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0030] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] An embodiment of a software and hardware coordinated power supply protection circuit for a distribution automation terminal See also Figure 1 This embodiment provides a software and hardware coordinated power protection circuit for a distribution automation terminal, including a main board and a core board. The main board includes the following components: Power input protection circuit, used to control the connection and disconnection of input power; The voltage conversion circuit is connected to the power input protection circuit and is used to convert the input power voltage into the operating voltage of each module; The power-off detection circuit uses optoelectronic isolation technology to monitor the power input status in real time. When the power input is normal, it outputs a first-level signal. When a power disconnection or power failure is detected, it outputs a second-level signal, triggering power-off event detection. At the software level, the power-off detection pin is defined in the device tree and configured as an interrupt trigger pin. The power-off detection pin is initialized and an interrupt is requested. The interrupt trigger condition is set to a level change. When the interrupt trigger condition occurs, a power-off detection event is triggered. This event includes a delayed confirmation event and an execution event of the power-off handling function. The voltage maintenance protection circuit is connected to the voltage conversion circuit and is used to perform a discharge operation through the first supercapacitor to maintain normal power supply to the core board key load when an abnormality occurs in the main power supply; The clock backup battery protection circuit is connected to the clock chip and uses a second supercapacitor as a backup battery. When an abnormality occurs in the main power supply, it automatically switches to the second supercapacitor for power supply to ensure the continuous operation of the clock chip.

[0032] like Figure 2 As shown, the power input protection circuit uses an anti-reverse polarity diode D37 and an electronic overvoltage protection circuit composed of a PNP transistor Q30 and a P-channel field-effect transistor N2. The anti-reverse polarity diode D37 is connected in series in the input path of the external input voltage. When the positive and negative poles of the power supply are reversed, the reverse polarity is cut off, the circuit is non-conductive, and reverse voltage is prevented from entering the system. The base of the PNP transistor Q30 is connected between the cathode of the anti-reverse polarity diode D37 and the cathode of the Zener diode D36. The anode of the Zener diode D36 is grounded. The collector of the PNP transistor Q30 is connected to the gate of the P-channel field-effect transistor N2. The source of the P-channel field-effect transistor N2 is connected to the 24V DC power input, and its drain is connected to the 24V power output.

[0033] The external input voltage is detected. When the external input voltage is less than a preset threshold voltage, the voltage regulator diode D36 is in the cut-off state, resulting in the lack of a conduction loop for the PNP transistor Q30, and its collector is in a low voltage state. When the external voltage is greater than the preset threshold voltage of 24V and the voltage difference between the base and emitter of the PNP transistor Q30 reaches the conduction voltage of the PN junction, the PNP transistor Q30 is turned on. At this time, the collector voltage of the PNP transistor Q30 is substantially equal to the external input voltage. The collector voltage of the PNP transistor Q30 is used as the control signal for the P-channel field-effect transistor N2. When the external input voltage is lower than the preset threshold voltage, the collector of the PNP transistor Q30 is at a low voltage, that is, the gate voltage of the field-effect transistor N2 is also at a low voltage. In this case, the drain and source of the P-channel field-effect transistor N2 are turned on, allowing the external input voltage to be output normally through the field-effect transistor. When the external voltage is greater than 24V and the PNP transistor Q30 is turned on, causing the gate voltage of the P-channel field-effect transistor N2 to be substantially equal to its source voltage, the P-channel field-effect transistor N2 is turned off, cutting off the output path of the external input voltage to prevent overvoltage from damaging the internal circuit.

[0034] Specifically, when the positive and negative poles of the reverse polarity protection diode D37 are connected in reverse, the reverse cutoff circuit does not conduct. When the reverse polarity is connected during on-site installation, the voltage cannot enter the system, thereby protecting the equipment. The overvoltage protection circuit is composed of the PNP transistor Q30 and the P-channel field effect transistor N2.

[0035] When the external voltage is less than 24V, the Zener diode D36 does not reach the conduction voltage and does not conduct. The PNP transistor Q30 has no conduction loop, so the 3rd pin of the PNP transistor Q30 is at a low voltage, that is, the G level of the P-channel field effect transistor N2 is at a low voltage, the D and S poles of the P-channel field effect transistor N2 are turned on, the 24V voltage passes through the field effect transistor, and the 24V voltage is output.

[0036] When the voltage is greater than 24V, Zener diode D36 conducts, stabilizing the voltage at 24V. When the voltage between pins 2 and 1 of PNP transistor Q30 exceeds the PN conduction voltage, the entire input voltage is approximately 25V. At this point, pins 2 and 3 of PNP transistor Q30 conduct, and the voltage at pin 3 of PNP transistor Q30 is essentially equal to 24V. This means that the G-pole voltage of P-channel field-effect transistor N2 is essentially equal to the S-pole voltage, and the N2 field-effect transistor is cut off. The 24V output has no voltage, thus protecting the internal circuit.

[0037] When choosing Figure 2In the case of the NCE01PO5S FET shown in the middle P-channel FET N2, since VDS = -100V, the input voltage can reach 100V without breakdown, ensuring that subsequent circuits are not affected. Therefore, choosing a FET with a high VDS can effectively protect subsequent circuits.

[0038] Therefore, the power input protection circuit provided in this embodiment primarily utilizes voltage regulator diodes, triodes, and field-effect transistors. Conventional circuits utilize relays, which introduce a certain amount of time delay, have limited service life, and have reliability issues with their contacts. The power input protection circuit provided in this embodiment utilizes entirely electronic components, avoiding these drawbacks and ensuring reliable circuit operation. Furthermore, the input protection voltage is increased to 100V.

[0039] like Figure 3 As shown, the power-off detection circuit includes an optical isolator U2, a Zener diode D4, a Zener diode D6, and an output pin PA8. The cathode of the Zener diode D4 is connected to the input voltage VCC - DCIN, and its anode is connected to pin 1 of the optical isolator U2. The cathode of the Zener diode D6 is connected between pin 1 of the optical isolator U2 and a resistor R16. The anode of the Zener diode D6 is connected to pin 2 of the optical isolator U2 and ground, which is used to provide voltage regulation protection for the input side of the optical isolator U2. Pin 4 of the optical isolator U2 is connected to the power supply VDD_3V3, and pin 3 of the optical isolator U2 is connected to the output pin PA8 through a resistor R17. The output pin PA8 serves as the output end of the power-off detection signal. When PA8 outputs a high level, it indicates that the input voltage VCC - DCIN is normal; when PA8 is a low level, it indicates that the input voltage VCC - DCIN is disconnected or powered off, triggering power-off event detection.

[0040] A Zener diode D4 is set as a voltage detection element, and a specific voltage threshold range is preset. When the input voltage VCC - DCIN is greater than a specific value K1 within the threshold range, the Zener diode D4 meets the conduction condition and enters the on state, providing an input signal to the optical isolator U2. When the input voltage VCC - DCIN is disconnected or powered off, and the voltage value is less than the specific value K1, the Zener diode D4 cannot meet the conduction condition and enters the off state. At this time, there is no voltage input to pin 1 of the optical isolator U2. The optical isolator U2 is used as a key component for signal transmission and isolation. When there is voltage input to pin 1 of the optical isolator U2, pins 4 and 3 of the optical isolator U2 are turned on, causing the output pin PA8 to output a high-level signal, indicating that the power input is in a normal state; when there is no voltage input to pin 1 of the optical isolator U2, pins 4 and 3 of the optical isolator U2 cannot be turned on, and the output pin PA8 outputs a low-level signal, which serves as a detection signal for power disconnection or power failure.

[0041] Specifically, the input voltage VCC-DCIN is the total power input of the entire power distribution terminal equipment, and the voltage range is 12V, 24V and 48V. Through the voltage regulator diode D4-BZT52C6V2, when the input voltage is greater than 6.2V (5.8~6.6V range), the voltage regulator diode D4 is turned on, and the optical isolator U2 has input, so that the 4th and 3rd pins of the optical isolator U2 are turned on, PA8 outputs a high level, and works normally.

[0042] When the input voltage VCC-DCIN is disconnected or powered off, the voltage is less than 6.2V. Pin 1 of the opto-isolator U2 has no voltage input, and pins 4 and 3 of the opto-isolator U2 are inoperative. PA8 is at a low level. U2 is an opto-isolator, which improves the detection circuit's anti-interference capability.

[0043] like Figure 4 As shown, the voltage maintenance protection circuit includes a diode D1, a first supercapacitor composed of supercapacitor E1 and supercapacitor E2, an overvoltage protection circuit U1, an overvoltage protection circuit U2, and a voltage monitoring circuit composed of a voltage regulator D3 and a PNP transistor Q2. The anode of the diode D1 is connected to a 5V power supply, the cathode of the diode D1 is connected to the positive electrode of the first supercapacitor, the VCC pins of the overvoltage protection circuit U1 and the overvoltage protection circuit U2 are connected to the positive electrodes of the supercapacitor E1 and the supercapacitor E2 respectively, and the overvoltage protection circuit U1 , the IOUT pin of the overvoltage protection circuit U2 is connected to the ground through the current discharge resistors R3 and R4 respectively; the base of the PNP transistor Q2 is connected to the anode of the Zener diode D3 through the resistor R6, and the cathode of the Zener diode D3 is connected to the gate of the field effect transistor Q1. When the voltage is higher than the Zener diode voltage regulation value, it is turned on, the emitter of the PNP transistor Q2 is grounded, the collector of the PNP transistor Q2 is connected to the gate and source of the field effect transistor Q1, and the drain of the field effect transistor Q1 is connected to the +5V_CORE pin of the core board.

[0044] Specifically, when the power is off, if the CPU is to continue working, it is necessary to ensure that the CPU power supply part remains normal when the power is off. This part is mainly completed by the supercapacitor charging and discharging circuit.

[0045] Supercapacitors E1 and E2 are 10F / 2.7V supercapacitors that store energy. Diode D1 is a unidirectional design that prevents the supercapacitor's stored energy from not powering the backplane, ensuring that only the core board of the system is powered.

[0046] The overvoltage protection circuit U1 and U2 are capacitor monomer overvoltage protection circuits, R3 and R4 are current bleeder resistors, ensuring that the protection voltage accuracy is within 1%. The BW6101 chip is used to replace the original TL431, XC61C and other discrete component solutions. It has a simple circuit, small peripheral devices and high voltage accuracy. It is a special chip developed specifically for supercapacitor protection.

[0047] The BW6101 uses a high-precision internal voltage reference to ensure that the protection voltage accuracy is within 1%. The built-in power tube can provide large current discharge capability. Without an external current expansion tube, it can provide a current discharge capacity of 200mA. If large current discharge protection is required, an external current expansion MOS tube can be added. The maximum discharge capacity can reach several amperes or even tens of amperes, meeting the protection requirements of large-capacity farad capacitor modules.

[0048] Zener diode D3 and PNP transistor Q2 form a voltage monitoring circuit. Voltage is applied to the core board's main power supply only when the voltage is above 3.3V (Zener diode) + 0.66V (Q2's BE conduction voltage) = 3.96V. This ensures that in the event of a power outage, if the voltage falls below the core board's operating voltage, power is quickly cut off, facilitating a rapid system restart upon the next power call. If the supercapacitor is allowed to discharge slowly, the system will fail to boot when power is restored. The supercapacitor must be fully discharged before power can be restored.

[0049] The calculation formula is as follows:

[0050] The voltage drop of diode D1 (SS34) is about 0.3V when fully charged. The voltage of supercapacitors E1+E2 is 4.7V, Vwork=4.70V, Vmin=3.96V, and the total capacity of two 10F supercapacitors in series is 5F. The calculation is as follows: t=(5F)X(22.09-15.6816) / (8.66X0.5)=5X6.4084 / 4.33=7.4S Based on the above formula, we can calculate that this circuit can maintain an effective operating voltage for approximately 7.4 seconds. To increase the effective standby time, the supercapacitor capacity can be adjusted. For example, if E1 = E2 = 20F / 2.7V, the total capacity after series connection is 10F, which can maintain a standby voltage of 14.8 seconds. As long as the system can complete file operations and power down, the longer the standby time, the better.

[0051] like Figure 5 As shown, this embodiment also includes a mainboard power supply circuit, which includes a power chip U10, a 5V input power supply, an input filter circuit and an output filter circuit. The signal input by the 5V input power supply is converted into voltage through the power chip U10. During the power conversion process, the signal is filtered and output through the input filter circuit and the output filter circuit; the power chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power chip. When each power module in the core board reaches a stable working state, the PG_V33 signal is set to a valid state, triggering the power chip U10 to start working and complete the power-on of the peripheral IO port; wherein, the PG_V33 signal is the last power good signal sent by the core board to indicate that the mainboard power-on is completed.

[0052] Specifically, the GPIO of core board CPU SOC is pulled up to the mainboard power domain by a pull-up resistor. If the mainboard power domain is powered on first than the power supply domain of the GPIO corresponding to SOC, backflow will occur, and it is possible to cause SOC to work abnormally for a long time. After the core board is powered on, a signal will be sent to drive the power chip of the mainboard to work. Wherein PG_V33 is the signal that the last power supply completed by the power-on that the core board sends is intact, indicating that the mainboard chip is powered on. The mainboard can use this signal to open the power supply of the baseboard and enable it, and complete the power-on of the peripheral IO port. The consequences that may be produced by backflow of current have uncertainty, diversity, and the concealment of the problem in terms of symptoms. If the IO port of unknown cause appears abnormal in the system, it will cause the faults such as system crash in a serious way, and it is possible that backflow of current causes it. Therefore, the seemingly very simple circuit processing of the present embodiment can avoid these inexplicable faults from occurring, especially in the application environment where the power system requires the equipment to be relatively high.

[0053] like Figure 6 As shown, the clock backup battery protection circuit includes a real-time clock chip U16, a second supercapacitor E3, and an LED lamp (NCD1206R1). The anode of the LED lamp is connected to a 5V input power supply, the cathode of the LED lamp is connected to the positive electrode of the second supercapacitor E3 and the VBAT pin of the real-time clock chip U16, the negative electrode of the second supercapacitor E3 is grounded, and the SCL and SDA pins of the real-time clock chip U16 are used for I2C communication and are respectively connected to an external I2C bus; wherein, a filter capacitor is connected to the VBAT pin of the real-time clock chip U16, one end of which is connected to the VBAT pin of the real-time clock chip U16 and the other end is grounded, for filtering out high-frequency noise on the power supply line.

[0054] In this embodiment, as an electrical device, the accuracy and stability of the clock are unquestionable. Since the selected clock chip is SD3078, the required power supply range of the VBAT backup battery is 2.3V~3.6V. A 5.5V / 1F supercapacitor is selected as the backup battery. It has the characteristics of long life and can theoretically achieve unlimited charge and discharge. In addition, this embodiment directly uses LED lights in series with the circuit. On the one hand, it takes advantage of its charging voltage drop of 1.6V. On the other hand, it also plays a role in current limiting. The current itself is below 25mA. As a light-emitting diode, it can also serve as a charging indicator light. The closer it is to full charge, the dimmer the light. It can be seen from the parameter table that the light-emitting diode also has a very small reverse current. The actual measurement is only about 0.3uA, with only very small loss, which can meet the requirements of power-off protection.

[0055] In this embodiment, the power-off handling function implements interrupt response and system protection through the following steps, and works in conjunction with the optical isolator U2 and the device tree configuration: The optical isolator U2 monitors the power input status in real time and converts the level change on the power side into the optical signal strength change on the isolation side. When the power input is normal, the output side of the optical isolator U2 is turned on and outputs a first level signal to the power-off detection pin of the core board. When it detects that the power is disconnected or the voltage drops below the threshold, the output side of the optical isolator U2 is cut off and outputs a second level signal to the power-off detection pin, triggering a level change interrupt. Define the function parameters of the power-down detection pin in the device tree, including the pin number, the interrupt type triggered by the level change, and the default level state; When the system is initialized, the following operations are completed according to the device tree configuration: Set the power-down detection pin to input mode and enable the internal pull-up / pull-down resistor; Register the power-down processing function to the interrupt vector table and set the interrupt priority to the highest level. The interrupt trigger condition is: when the power-down detection pin level jumps from the first level to the second level, the MCU jumps to the interrupt service routine and executes the delayed confirmation event. After a delay confirming that the power-off detection pin remains at the second level, the power-off processing function is executed: the current system operating status is written to the MCU's built-in retention RAM, and a command is sent to the power management chip via the I2C / SPI interface to disconnect the main power path and enable the supercapacitor as a backup power source. The dynamic voltage adjustment algorithm is then started to gradually reduce the MCU operating frequency based on the remaining energy in the supercapacitor. Turn off all non-essential peripheral clocks and keep only the RTC running to record the power-off timestamp; set the power-off flag in the Retention RAM for identification when power is restored.

[0056] In this embodiment, the delayed confirmation event includes: When the power-off detection pin level is detected to jump from the first level to the second level, the current timestamp is recorded immediately T detect, as the starting reference point of the delay; Start the hardware timer to execute software delay T delay , satisfying the formula: T delay = T threshold -Δ T error in, T threshold is the preset power-off confirmation threshold time; Δ T error It is the timer accuracy compensation value; During the delay period, when the hardware timer triggers an interrupt, a delay completion flag is generated. Flag delay_done ; when Flag delay_done =1, read the level status of the power-down detection pin again V PA8 , and execute the following decision logic: like V PA8 =First level, it is determined to be power supply noise interference, clear the interrupt flag and exit; like V PA8 = The second level confirms that the power-off event is valid and triggers the power-off processing function. At this time, the total response time of the system is T response Satisfies the formula: T response = T detect + T delay + T process in, T process This is the execution time of the power-off processing function.

[0057] In this embodiment, a dynamic voltage adjustment algorithm is started to gradually reduce the MCU operating frequency according to the remaining energy of the supercapacitor. The specific implementation steps are as follows: Real-time monitoring of supercapacitor voltage V sc and current I sc , calculate the supercapacitor in a period of time Δ by integrationt Energy released within E sc , and its calculation formula is:

[0058] in, V sc ( t )and I sc ( t ) are respectively the moments t The voltage and current of the supercapacitor.

[0059] Record the initial energy of the supercapacitor E sc0 , then the remaining energy of the supercapacitor at the current moment is E sc for: in, n is the number of times the energy calculation has been performed, Δ E sci For the i The energy released by the supercapacitor is calculated.

[0060] Preset the maximum operating frequency of the MCU f max and minimum operating frequency f min , these parameters are determined according to the hardware characteristics of the MCU and the system performance requirements. For example, f ma x =500 MHz , f min =100 MHz .

[0061] The remaining energy of the supercapacitor is converted to E sc Mapping to MCU operating frequency f mcu Within the adjustment range, the lower limit of the supercapacitor energy threshold is set to E th1 , the upper limit is E th2 ( E th1 < E th2 ), when the remaining energy of the supercapacitor E sc exist E th1 arrive Eth2 When the MCU operating frequency is between f mcu The remaining energy of the supercapacitor E sc The relationship is:

[0062] when E sc < E th1 To ensure the basic operation of the system, set the MCU operating frequency to the lowest operating frequency f min ,Right now f mcu = f min ;when E sc > E th2 To give full play to the system performance, set the MCU operating frequency to the highest operating frequency. f max ,Right now f mcu = f max .

[0063] According to the above calculation, the MCU operating frequency f mcu , send frequency adjustment instructions to the MCU through the MCU's clock control register or related interface, and gradually adjust the MCU's operating frequency to the calculated f mcu For example, for an MCU with a programmable clock controller, the clock division factor is changed by writing a specific register value, thereby adjusting the operating frequency.

[0064] During the MCU operating frequency adjustment process, the system's operating status is monitored in real time. If a system anomaly occurs (such as a task execution timeout or data transmission error), frequency adjustment is suspended and appropriate action is taken based on the anomaly, such as restoring the MCU to its previously stable operating frequency or performing fault diagnosis and repair. Once the system returns to normal, the operating frequency adjustment is resumed based on the remaining energy in the supercapacitor.

[0065] In actual application, when a power-off signal is detected, the software program processes it according to the following steps: Device tree configuration: In the board.dts device tree file, define the powerdown_protect node and set the compatible property to "powerdown-protect" to match the name in the driver file; set the state property to "okay" to enable the PA8 detection pin; set the irq-gpios property to <&pio PA 8 GPIO_ACTIVE_HIGH> to define PA8 as an interrupt pin and use a high-level trigger mode.

[0066] Power-down detection pin initialization: In the powerdown-protect.c file, perform initialization operations through the pwdown_protect_probe function: Use the of_get_named_gpio function to get the GPIO number of the specified name "irq-gpios" from the device tree node and assign it to irq_gpio.

[0067] Use the gpio_is_valid function to check whether the obtained irq_gpio is valid. If invalid, the dev_err function outputs the error message "No valid irq gpio" and returns the error code -ENODEV.

[0068] Call the devm_gpio_request function to apply for the GPIO from the system. If the application fails, the dev_err function will output the error message "irq io request failed" and return the corresponding error code.

[0069] The obtained GPIO is converted to an interrupt request (IRQ) line with the help of the gpio_to_irq function. If the conversion fails, the error message "No IRQ resource found (%d)" is output through the dev_err function, where %d is the error code, and the error code is returned.

[0070] Use the devm_request_irq function to request and register an interrupt handler, set the interrupt trigger condition to IRQF_TRIGGER_FALLING (falling edge trigger), and if the request fails, use the dev_err function to output the error message "Failed to request IRQ %d: %d", where the first %d is the interrupt number and the second %d is the error code, and return the error code; if initialization is successful, it returns 0.

[0071] Interrupt response processing: When PA8 is interrupted, the pwdown_protect_irq_handle function is triggered: Get the platform_device structure pointer pdev from the passed parameter data.

[0072] The dev_info function outputs the prompt message "Syncing FileSystem..." to the debugging serial port.

[0073] Call the orderly_poweroff function, pass in the parameter true, and perform specific power-off processing operations.

[0074] Power-off processing function implementation: The orderly_poweroff function receives a Boolean parameter force: If force is true, set the poweroff_force variable to true, ensuring that the existing "true" state is not overwritten.

[0075] Call the schedule_work function and add poweroff_work to the default work queue to complete subsequent power-off processing tasks.

[0076] The design and performance assurance of power terminal products must strictly meet the requirements of "Voltage Sags and Short Interruptions Immunity," specifically the Class A standard in GB / T17626.11-2023. This standard clearly stipulates that when the power supply voltage reaches 0% UT (no backup power) and a short voltage interruption lasts for 0.5 seconds, the terminal equipment must maintain stable operation and must not exhibit abnormalities such as malfunction, damage, freezing, restarting, or communication interruption. After the power supply voltage is restored, stored data must remain unchanged and the equipment must function normally.

[0077] This embodiment employs a specific power-off detection and handling strategy at the software level. The system continuously monitors the level of the PA8 test pin to determine if a power-off has occurred. When the PA8 test pin is first detected as low, the power-off handling process is not immediately initiated. Instead, a 0.7s delay is set, and after the delay, the PA8 pin is retested. If the PA8 pin remains low and the duration of this low level exceeds the specified 0.5s threshold, the system determines that a true power-off event has occurred and initiates the software's power-off handling mechanism.

[0078] This software-set delay and secondary voltage level detection method can effectively avoid misjudgments caused by brief voltage fluctuations or interference, ensuring that the system only performs power-off processing operations when a power outage actually occurs and meets test requirements. This fully meets the Class A standard in GB / T17626.11-2023 for the immunity of power terminal products to voltage sags and short interruptions.

[0079] In summary, this embodiment employs reverse connection protection and electronic overvoltage protection at the power input. During actual on-site installation, reverse power connection and excessive voltage often occur due to operator negligence or environmental complexity. The protection mechanism of the present invention can withstand overvoltages up to 100V. When the power supply is reversed or the voltage exceeds the safe range, the protection function is quickly activated, effectively preventing damage to the equipment due to power anomalies. This not only significantly reduces equipment maintenance costs and replacement frequency, but also improves equipment reliability and availability in complex field environments, providing a solid guarantee for the stable operation of the power system.

[0080] The present invention uses a photoelectric isolation circuit for power-off signal detection. In power systems, input analog signals are often susceptible to various electromagnetic interferences, which can affect the normal operation of the system and the accuracy of judgment. The photoelectric isolation circuit can effectively isolate the input signal from the system's internal circuits, preventing the intrusion of external interference signals. This greatly improves the system's anti-interference performance, making power-off signal detection more accurate and reliable. It can capture power-off events in a timely and accurate manner, providing an accurate basis for subsequent power-off protection measures and ensuring that the system can quickly and correctly respond to power-off events.

[0081] The present invention uses a supercapacitor as the core component of the power-off maintenance circuit, providing reliable power support for the system. Unlike traditional charge-discharge circuits that only provide a discharge function, the supercapacitor of the present invention will cut off the power supply when it is discharged to a certain voltage, ensuring that during the power outage, the system can reasonably utilize the power stored in the supercapacitor, and after completing the necessary operations, avoid affecting the performance of the supercapacitor due to excessive discharge. At the same time, when the power is restored, the system can quickly restart with the help of the remaining energy stored in the supercapacitor, reducing the system recovery time, improving the system's response speed and operating efficiency, ensuring that the power terminal can resume normal operation in a timely manner, and reducing the impact on the monitoring and control of the power system.

[0082] The present invention reasonably designs the power-on sequence of the mainboard power supply and the core board so that the mainboard power supply is powered on after the core board, thereby effectively preventing the occurrence of power backflow. In electronic equipment, power backflow may cause damage to the main chip of the core board, seriously affecting the performance and life of the equipment. The power protection design of this solution avoids the occurrence of this situation, provides a safe operating environment for the main chip of the core board, and ensures the stability and reliability of the product during long-term use. It is crucial for power terminal equipment that needs to run continuously for a long time. It can reduce equipment failures caused by power problems, reduce maintenance costs, and improve the overall operating efficiency of the power system.

[0083] The present invention uses a simple light-emitting diode (LED) circuit to implement a clock backup battery protection circuit. This circuit not only performs voltage reduction and current limiting functions, achieving voltage matching and ensuring the clock backup battery provides a stable operating voltage for the clock circuit, thus extending the service life of the clock circuit, but also provides a light-emitting indicator function, visually displaying the battery charge status. This simple and practical design reduces circuit complexity and cost, reduces potential failure points, and improves circuit reliability and maintainability. In practical applications, operators can quickly understand the battery charge status by observing the LED's illumination status, facilitating timely maintenance and handling.

[0084] The present invention significantly improves the power-off protection performance through a combination of software and hardware. In terms of hardware, it has a complete power protection circuit and a power-off detection mechanism; in terms of software, it determines the power-off event by programming the detection pin, and can flexibly set the reaction time when the power is off according to actual needs. This software and hardware collaborative working mode enables the system to better meet the test requirements of "Voltage Sag and Short Interruption Immunity" of the power terminal. When a power outage occurs, the system can use the power provided by the supercapacitor to complete key operations such as reading and writing files in an orderly manner under the control of the software, ensuring that all types of files are not affected by the power outage, ensuring the integrity of the system and the accuracy of the data. For terminal equipment in the power system that has extremely high requirements for data integrity and system stability, it has important practical application value and can effectively improve the operation management level and reliability of the power system.

[0085] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and replacements made by technicians in this field on the basis of the present invention fall within the scope of protection required by the present invention.

Claims

1. A software and hardware coordinated power protection circuit for a distribution automation terminal, characterized in that: It includes a main board and a core board. The main board includes the following components: Power input protection circuit, used to control the connection and disconnection of input power; A voltage conversion circuit, connected to the power input protection circuit, for converting the input power voltage into the operating voltage of each module; The power-off detection circuit uses photoelectric isolation technology to monitor the power input status in real time; When the power input is normal, a first level signal is output; when a power disconnection or power failure is detected, a second level signal is output to trigger power failure event detection. At the software level, the function of the power failure detection pin is defined in the device tree, configured as an interrupt trigger pin, and the interrupt trigger condition is set to a level change. When the interrupt trigger condition occurs, a power failure detection event is triggered, which includes a delayed confirmation event and an execution event of the power failure processing function. A voltage maintenance protection circuit is connected to the voltage conversion circuit and is used to maintain normal power supply to the key loads of the core board by performing a discharge operation through the first supercapacitor when an abnormality occurs in the main power supply; The clock backup battery protection circuit is connected to the clock chip and uses a second supercapacitor as a backup battery. When an abnormality occurs in the main power supply, it automatically switches to the second supercapacitor for power supply to ensure the continuous operation of the clock chip.

2. The circuit according to claim 1, characterized in that: The power input protection circuit uses an anti-reverse polarity diode D37 and an electronic overvoltage protection circuit consisting of a PNP transistor Q30 and a P-channel field-effect transistor N2. The anti-reverse polarity diode D37 is connected in series in the input path of the external input voltage. When the positive and negative poles of the power supply are reversed, the reverse polarity is cut off, the circuit is non-conductive, and reverse voltage is prevented from entering the system. The base of the PNP transistor Q30 is connected between the cathode of the anti-reverse polarity diode D37 and the cathode of the voltage-stabilizing diode D36. The anode of the voltage-stabilizing diode D36 is grounded. The collector of the PNP transistor Q30 is connected to the gate of the P-channel field-effect transistor N2. The source of the P-channel field-effect transistor N2 is connected to the 24V DC power input, and its drain is connected to the 24V power output.

3. The circuit according to claim 2, characterized in that: The external input voltage is detected. When the external input voltage is less than a preset threshold voltage, the voltage stabilizing diode D36 is in a cut-off state, causing the PNP transistor Q30 to lack a conduction loop and its collector to be in a low voltage state. When the external voltage is greater than the preset threshold voltage of 24V and the voltage difference between the base and emitter of the PNP transistor Q30 reaches the conduction voltage of the PN junction, the PNP transistor Q30 is turned on. At this time, the collector voltage of the PNP transistor Q30 is substantially equal to the external input voltage. The collector voltage of the PNP transistor Q30 is used as the control signal of the P-channel field-effect transistor N2. When the external input voltage is less than a preset threshold voltage, the collector of the PNP transistor Q30 is at a low voltage, that is, the gate voltage of the field-effect transistor N2 is at a low voltage. In this case, the drain and source of the P-channel field-effect transistor N2 are conductive, allowing the external input voltage to be normally output through the field-effect transistor. When the external voltage is greater than 24V and the PNP transistor Q30 is conductive, causing the gate voltage of the P-channel field-effect transistor N2 to be substantially equal to its source voltage, the P-channel field-effect transistor N2 is cut off, cutting off the output path of the external input voltage to prevent overvoltage from damaging the internal circuit.

4. The circuit according to claim 1, characterized in that: The power-off detection circuit includes an optical isolator U2, a Zener diode D4, a Zener diode D6, and an output pin PA8. The cathode of the Zener diode D4 is connected to the input voltage VCC-DCIN, and its anode is connected to pin 1 of the optical isolator U2. The cathode of the Zener diode D6 is connected between pin 1 of the optical isolator U2 and a resistor R16. The anode of the Zener diode D6 is connected to pin 2 of the optical isolator U2 and ground, and is used to provide voltage regulation protection for the input side of the optical isolator U2. Pin 4 of the optical isolator U2 is connected to the power supply VDD_3V3, and pin 3 of the optical isolator U2 is connected to the output pin PA8 via a resistor R17. The output pin PA8 serves as the output end of the power-off detection signal. When the output pin PA8 outputs a high level, it indicates that the input voltage VCC-DCIN is normal; when the output pin PA8 is a low level, it indicates that the input voltage VCC-DCIN is disconnected or powered off, triggering power-off event detection.

5. The circuit according to claim 4, characterized in that: The voltage-stabilizing diode D4 is set as a voltage detection element, and a specific voltage threshold range is preset. When the input voltage VCC - DCIN is greater than a specific value K1 within the threshold range, the voltage-stabilizing diode D4 meets the conduction condition and enters the conduction state, providing an input signal to the optical isolator U2. When the input voltage VCC - DCIN is disconnected or powered off, and the voltage value is less than the specific value K1, the voltage-stabilizing diode D4 cannot meet the conduction condition and enters the cut-off state. At this time, no voltage is input to pin 1 of the optical isolator U2. The optical isolator U2 is used as a key component for signal transmission and isolation. When there is voltage input to pin 1 of the optical isolator U2, pins 4 and 3 of the optical isolator U2 are turned on, causing the output pin PA8 to output a high-level signal, indicating that the power input is in a normal state; when there is no voltage input to pin 1 of the optical isolator U2, pins 4 and 3 of the optical isolator U2 cannot be turned on, and the output pin PA8 outputs a low-level signal, which serves as a detection signal for power disconnection or power failure.

6. The circuit according to any one of claims 1 to 5, characterized in that: The voltage maintenance protection circuit includes a diode D1, a first supercapacitor composed of a supercapacitor E1 and a supercapacitor E2, an overvoltage protection circuit U1, an overvoltage protection circuit U2, and a voltage monitoring circuit composed of a voltage regulator D3 and a PNP transistor Q2. The anode of the diode D1 is connected to a 5V power supply, the cathode of the diode D1 is connected to the positive electrode of the first supercapacitor, the VCC pins of the overvoltage protection circuit U1 and the overvoltage protection circuit U2 are connected to the positive electrodes of the supercapacitor E1 and the supercapacitor E2 respectively, and the overvoltage protection circuit U1, The IOUT pin of the overvoltage protection circuit U2 is connected to the ground through current discharge resistors R3 and R4 respectively; the base of the PNP transistor Q2 is connected to the anode of the voltage regulator D3 through the resistor R6, and the cathode of the voltage regulator D3 is connected to the gate of the field effect transistor Q1. When the voltage is higher than the voltage regulation value of the voltage regulator, it is turned on. The emitter of the PNP transistor Q2 is grounded, the collector of the PNP transistor Q2 is connected to the gate and source of the field effect transistor Q1, and the drain of the field effect transistor Q1 is connected to the +5V_CORE pin of the core board.

7. The circuit according to any one of claims 1 to 5, characterized in that: It also includes a mainboard power supply circuit, which includes a power chip U10, a 5V input power supply, an input filter circuit and an output filter circuit. The signal input by the 5V input power supply is converted into voltage through the power chip U10. During the power conversion process, the signal is filtered and output through the input filter circuit and the output filter circuit; the power chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power chip. When each power module in the core board reaches a stable working state, the PG_V33 signal is set to a valid state, triggering the power chip U10 to start working and complete the power-on of the peripheral IO port; wherein, the PG_V33 signal is the last power good signal sent by the core board to indicate that the mainboard power-on is completed.

8. The circuit according to any one of claims 1 to 5, characterized in that: The clock backup battery protection circuit includes a real-time clock chip, a second supercapacitor E3, and an LED lamp. The anode of the LED lamp is connected to a 5V input power supply, the cathode of the LED lamp is connected to the positive electrode of the second supercapacitor E3 and the VBAT pin of the real-time clock chip, the negative electrode of the second supercapacitor E3 is grounded, and the SCL and SDA pins of the real-time clock chip are used for I2C communication and are respectively connected to an external I2C bus; Wherein, a filter capacitor is connected to the VBAT pin of the real-time clock chip, one end of which is connected to the VBAT pin of the real-time clock chip and the other end is grounded, for filtering high-frequency noise on the power supply line.

9. The circuit according to claim 4, characterized in that The power-off processing function implements interrupt response and system protection through the following steps, and works in conjunction with the optical isolation device U2 and the device tree configuration: The optical isolator U2 monitors the power input status in real time and converts the level change on the power supply side into the optical signal strength change on the isolation side; when the power input is normal, the output side of the optical isolator U2 is turned on and outputs a first level signal to the power-off detection pin of the core board; when it is detected that the power is disconnected or the voltage drops below the threshold, the output side of the optical isolator U2 is cut off and outputs a second level signal to the power-off detection pin, triggering a level change interrupt; Define the function parameters of the power-down detection pin in the device tree, including the pin number, the interrupt type triggered by the level change, and the default level state; When the system is initialized, the following operations are completed according to the device tree configuration: Set the power-down detection pin to input mode and enable the internal pull-up / pull-down resistor; Register the power-down processing function to the interrupt vector table and set the interrupt priority to the highest level. The interrupt trigger condition is: when the power-down detection pin level jumps from the first level to the second level, the MCU jumps to the interrupt service routine and executes the delayed confirmation event. After a delay confirming that the power-off detection pin remains at the second level, the power-off processing function is executed: the current system operating status is written to the MCU's built-in retention RAM, and a command is sent to the power management chip via the I2C / SPI interface to disconnect the main power path and enable the supercapacitor as a backup power source. The dynamic voltage adjustment algorithm is then started to gradually reduce the MCU operating frequency based on the remaining energy in the supercapacitor. Turn off all non-essential peripheral clocks and keep only the RTC running to record the power-off timestamp; set the power-off flag in the Retention RAM for identification when power is restored.

10. The circuit according to claim 9, characterized in that The delayed confirmation events include: When the power-off detection pin level is detected to jump from the first level to the second level, the current timestamp is recorded immediately T detect, as the starting reference point of the delay; Start the hardware timer to execute software delay T delay , satisfying the formula: T delay = T threshold -D T error in, T threshold is the preset power-off confirmation threshold time; Δ T error It is the timer accuracy compensation value; During the delay period, when the hardware timer triggers an interrupt, a delay completion flag is generated. Flag delay_done ; when Flag delay_done =1, read the level status of the power-down detection pin again V PA8 , and execute the following decision logic: like V PA8 =First level, it is determined to be power supply noise interference, clear the interrupt flag and exit; like V PA8 = The second level confirms that the power-off event is valid and triggers the power-off processing function. At this time, the total response time of the system is T response Satisfies the formula: T response = T detect + T delay + T process in, T process This is the execution time of the power-off processing function.

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