A software and hardware cooperative power protection circuit of a power distribution automation terminal

Abstract

The application provides a kind of software and hardware coordination power protection circuit of power distribution automation terminal, including power input protection circuit, voltage conversion circuit, power failure detection circuit, voltage maintenance protection circuit, clock backup battery protection circuit, wherein, power failure detection circuit uses photoelectric isolation technology, real-time monitoring power input state;When detecting that power is disconnected or power failure, output specific level signal, trigger power failure event detection;In software level, define the function of power failure detection foot in device tree, configure it as interrupt trigger pin, initialize power failure detection foot and request interrupt, set interrupt trigger condition as level change, trigger power failure detection event when interrupt trigger condition occurs.The application excludes system damage caused by accidental power failure through software and hardware combination, significantly improves the reliability and service life of terminal, and through power failure protection, software has enough time to complete file operation, so as to achieve the purpose of protecting file system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power automation equipment, in particular to a software and hardware cooperative power protection circuit of a power distribution automation terminal, which is suitable for scenes with high requirements for power stability, such as power distribution automation terminals, smart meters, power monitoring equipment, and is especially for the power-off data protection requirements under operating systems such as Linux. BACKGROUND

[0002] The most important thing in power distribution automation terminals and other power products is power supply design, and the quality of the power supply directly affects the stability of the power product, especially the widespread use of operating systems such as Linux. If power failure or other accidents occur during data writing to the memory, it may cause data loss, or even damage the operating system files and cause the system to crash. Although various anti-power-off file systems are adopted, system crashes may still occur. Therefore, the impact of power failure should be considered in the design of the power supply, so that the operating system has time to complete the file system operation, release peripherals, and power off, thereby reducing the damage of power failure to the system to the minimum.

[0003] Although the prior art realizes basic protection through anti-power-off file systems (such as UBIFS) or relays, there are still the following problems:

[0004] 1. The relay has a slow response and a limited service life (contacts are prone to aging); 2. Pure software anti-power-off cannot cover hardware-level failures (such as instantaneous reverse connection of the power supply); 3. The backup battery charging and discharging circuit lacks precise control, which may cause system restart failure.

[0005] Therefore, there is an urgent need to design a software and hardware cooperative power protection scheme to meet the anti-interference requirements of the power industry standard (such as GB / T17626.11-2023). SUMMARY

[0006] In view of various problems existing in the prior art, the present application provides a software and hardware cooperative power protection circuit of a power distribution automation terminal, which eliminates the system damage caused by accidental power failure through the combination of software and hardware, significantly improves the reliability and service life of the terminal, and allows the software to have enough time to complete the file operation through the protection and masking processing of the power failure protection, thereby achieving the purpose of protecting the file system.

[0007] The present application achieves the above-mentioned purpose through the following technical solutions:

[0008] A software and hardware cooperative power protection circuit of a power distribution automation terminal, characterized in that it comprises a mainboard and a core board, and the mainboard comprises the following components:

[0009] A power input protection circuit for controlling the connection and disconnection of the input power supply;

[0010] The voltage conversion circuit is connected with the power input protection circuit and is used for converting the input power voltage into the working voltage of each module.

[0011] The power-off detection circuit adopts the photoelectric isolation technology to monitor the power input state in real time; when the power input is normal, a first level signal is output; when the power is disconnected or power-off is detected, a second level signal is output to trigger the power-off event detection; wherein, at the software level, the function of the power-off detection pin is defined in the device tree, and the power-off detection pin is configured as an interrupt trigger pin, the power-off detection pin is initialized and an interrupt is requested, the interrupt trigger condition is set as a level change, and when the interrupt trigger condition occurs, the power-off detection event is triggered, the event includes a delay confirmation event and an execution event of a power-off processing function;

[0012] The voltage maintenance protection circuit is connected with the voltage conversion circuit and is used for maintaining the normal power supply of the key load of the core board by performing a discharging operation by the first super capacitor when the main power supply is abnormal.

[0013] The clock backup battery protection circuit is connected with the clock chip and adopts the second super capacitor as a backup battery, and is used for automatically switching to the second super capacitor for power supply when the main power supply is abnormal, so as to ensure the continuous operation of the clock chip.

[0014] According to the power supply protection circuit for the software and hardware cooperation of the power distribution automation terminal provided by the application, the power input protection circuit adopts the anti-reverse connection diode D37 and the electronic overvoltage protection circuit composed of the PNP triode Q30 and the P-channel field effect tube N2, the anti-reverse connection diode D37 is connected in series in the input path of the external input voltage, and the circuit is not conductive when the positive and negative poles of the power supply are connected reversely, so as to prevent the reverse voltage from entering the system; the base of the PNP triode Q30 is connected between the cathode of the anti-reverse connection diode D37 and the cathode of the voltage stabilizing diode D36, the anode of the voltage stabilizing diode D36 is grounded, and the collector of the PNP triode Q30 is connected with the gate of the P-channel field effect tube N2; the source of the P-channel field effect tube N2 is connected with the 24V DC power supply input, and the drain thereof is connected with the 24V power supply output.

[0015] According to the power supply protection circuit for the software and hardware cooperation of the power distribution automation terminal provided by the application, the external input voltage is detected, when the external input voltage is less than the preset threshold voltage, the voltage stabilizing diode D36 is in the cut-off state, so that the PNP triode Q30 lacks a conduction loop, and the collector thereof presents a low voltage state; and when the external voltage is greater than the preset threshold voltage 24V, and the voltage difference between the base and the emitter of the PNP triode Q30 reaches the conduction voltage of the PN junction, the PNP triode Q30 is turned on, at this time, the collector voltage of the PNP triode Q30 is basically equal to the external input voltage.

[0016] The collector voltage of the PNP triode Q30 is used as the control signal of the P-channel field effect transistor N2.When the external input voltage is less than the preset threshold voltage, the collector voltage of the PNP triode Q30 is low, that is, the gate voltage of the field effect transistor N2 is low, in this case, the drain and source of the P-channel field effect transistor N2 are turned on, allowing the external input voltage to be normally output through the field effect transistor; when the external voltage is greater than 24V and the PNP triode Q30 is turned on, the gate voltage of the P-channel field effect transistor N2 is substantially equal to the source voltage of the P-channel field effect transistor N2, the P-channel field effect transistor N2 is turned off, and the output path of the external input voltage is cut off, so as to prevent overvoltage from damaging the internal circuit.

[0017] According to the power supply protection circuit for the power distribution automation terminal, the power-off detection circuit includes an optical isolation device U2, a zener diode D4, a zener diode D6 and an output pin PA8, the cathode of the zener diode D4 is connected to an input voltage VCC-DCIN, the anode of the zener diode D4 is connected to the pin 1 of the optical isolation device U2, the cathode of the zener diode D6 is connected between the pin 1 of the optical isolation device U2 and the resistor R16, the anode of the zener diode D6 is connected to the pin 2 of the optical isolation device U2 and the ground, for voltage protection on the input side of the optical isolation device U2, the pin 4 of the optical isolation device U2 is connected to a power supply VDD_3V3, the pin 3 of the optical isolation device U2 is connected to the output pin PA8 through the resistor R17, and the output pin PA8 is used as an output end of the power-off detection signal, when the output pin PA8 outputs a high level, it indicates that the input voltage VCC-DCIN is normal, and when the output pin PA8 outputs a low level, it indicates that the input voltage VCC-DCIN is disconnected or power-off, triggering the power-off event detection.

[0018] According to the power supply protection circuit for the power distribution automation terminal, the power-off detection circuit includes an optical isolation device U2, a zener diode D4, a zener diode D6 and an output pin PA8, the cathode of the zener diode D4 is connected to an input voltage VCC-DCIN, the anode of the zener diode D4 is connected to the pin 1 of the optical isolation device U2, the cathode of the zener diode D6 is connected between the pin 1 of the optical isolation device U2 and the resistor R16, the anode of the zener diode D6 is connected to the pin 2 of the optical isolation device U2 and the ground, for voltage protection on the input side of the optical isolation device U2, the pin 4 of the optical isolation device U2 is connected to a power supply VDD_3V3, the pin 3 of the optical isolation device U2 is connected to the output pin PA8 through the resistor R17, and the output pin PA8 is used as an output end of the power-off detection signal, when the output pin PA8 outputs a high level, it indicates that the input voltage VCC-DCIN is normal, and when the output pin PA8 outputs a low level, it indicates that the input voltage VCC-DCIN is disconnected or power-off, triggering the power-off event detection.

[0019] The optical isolation device U2 is used as a key element for signal transmission and isolation, when the pin 1 of the optical isolation device U2 has voltage input, the pins 4 and 3 of the optical isolation device U2 are turned on, so that the output pin PA8 outputs a high level signal, indicating that the power supply input is in a normal state, when the pin 1 of the optical isolation device U2 has no voltage input, the pins 4 and 3 of the optical isolation device U2 cannot be turned on, and the output pin PA8 outputs a low level signal, which is used as a detection signal of power supply disconnection or power-off.

[0020] The power supply protection circuit of the power distribution automation terminal provided by the application comprises a voltage maintenance protection circuit, a first super capacitor composed of a super capacitor E1 and a super capacitor E2, an overvoltage protection circuit U1, an overvoltage protection circuit U2, and a voltage monitoring circuit composed of a voltage stabilizing tube D3 and a PNP type triode Q2. The anode of the diode D1 is connected to a 5V power supply, the cathode of the diode D1 is connected to the positive pole of the first super capacitor, the VCC pin of the overvoltage protection circuit U1 and the VCC pin of the overvoltage protection circuit U2 are respectively connected to the positive pole of the super capacitor E1 and the positive pole of the super capacitor E2, and the IOUT pin of the overvoltage protection circuit U1 and the IOUT pin of the overvoltage protection circuit U2 are respectively connected to the ground through the current discharge resistors R3 and R4. The base of the PNP type triode Q2 is connected to the anode of the voltage stabilizing tube D3 through the resistor R6, the cathode of the voltage stabilizing tube D3 is connected to the gate of the field effect tube Q1, the PNP type triode Q2 is grounded at the emitter, the collector of the PNP type triode Q2 is connected to the gate and the source of the field effect tube Q1, and the drain of the field effect tube Q1 is connected to the +5V_CORE pin of the core board.

[0021] The power supply protection circuit of the power distribution automation terminal provided by the application further comprises a main board power supply circuit, which comprises a power supply chip U10, a 5V input power supply, an input filter circuit and an output filter circuit. The signal input by the 5V input power supply is converted in voltage by the power supply chip U10, and the signal is filtered and output by the input filter circuit and the output filter circuit during the power supply conversion process. The power supply chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power supply chip. When all the power supply modules in the core board reach the stable working state, the PG_V33 signal is set to the effective state, triggering the power supply chip U10 to start working and completing the power-on of the peripheral IO port. The PG_V33 signal is the last power good signal indicating that the power-on of the main board is completed and is sent by the core board.

[0022] The power supply protection circuit of the power distribution automation terminal provided by the application further comprises a main board power supply circuit, which comprises a power supply chip U10, a 5V input power supply, an input filter circuit and an output filter circuit. The signal input by the 5V input power supply is converted in voltage by the power supply chip U10, and the signal is filtered and output by the input filter circuit and the output filter circuit during the power supply conversion process. The power supply chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power supply chip. When all the power supply modules in the core board reach the stable working state, the PG_V33 signal is set to the effective state, triggering the power supply chip U10 to start working and completing the power-on of the peripheral IO port. The PG_V33 signal is the last power good signal indicating that the power-on of the main board is completed and is sent by the core board.

[0023] The clock backup battery protection circuit comprises a real-time clock chip, a second super capacitor E3 and an LED lamp. The anode of the LED lamp is connected to the 5V input power supply, the cathode of the LED lamp is connected to the positive pole of the second super capacitor E3 and the VBAT pin of the real-time clock chip, the negative pole of the second super capacitor E3 is grounded, and the SCL and SDA pins of the real-time clock chip are used for I2C communication and are respectively connected to the external I2C bus. The clock backup battery protection circuit comprises a real-time clock chip, a second super capacitor E3 and an LED lamp. The anode of the LED lamp is connected to the 5V input power supply, the cathode of the LED lamp is connected to the positive pole of the second super capacitor E3 and the VBAT pin of the real-time clock chip, the negative pole of the second super capacitor E3 is grounded, and the SCL and SDA pins of the real-time clock chip are used for I2C communication and are respectively connected to the external I2C bus.

[0024] According to the power supply protection circuit for power distribution automation terminal provided by the application, the power-off processing function realizes the interrupt response and system protection through the following steps and cooperates with the optical isolator U2 and the device tree configuration:

[0025] The optical isolator U2 monitors the power input state in real time and converts the level change on the power supply side into the intensity change of the optical signal on the isolation side; when the power input is normal, the output side of the optical isolator U2 is turned on, and a first level signal is output to the power-off detection pin of the core board; when it is detected that the power supply is disconnected or the voltage drops below the threshold, the output side of the optical isolator U2 is cut off, a second level signal is output to the power-off detection pin, and a level change interrupt is triggered;

[0026] The functional parameters of the power-off detection pin are defined in the device tree, including the pin number, the interrupt type triggered by the level change, and the default level state;

[0027] When the system is initialized, the following operations are completed according to the device tree configuration:

[0028] The power-off detection pin is set to the input mode, and the internal pull-up / pull-down resistor is enabled;

[0029] The power-off processing function is registered to the interrupt vector table, and the interrupt priority is set to the highest level; wherein the interrupt trigger condition is that when the power-off detection pin level jumps from the first level to the second level, the MCU jumps to the interrupt service program and executes the delay confirmation event;

[0030] When the delay confirmation power-off detection pin continues at the second level, the power-off processing function is executed: the current system running state is written into the Retention RAM of the MCU, an instruction is sent to the power management chip through the I2C / SPI interface, the main power supply path is disconnected, and the super capacitor is enabled as a backup power supply; the dynamic voltage adjustment algorithm is started, and the MCU working frequency is gradually reduced according to the remaining energy of the super capacitor;

[0031] The clocks of all unnecessary peripherals are turned off, and only the RTC is maintained to record the power-off timestamp; the power-off flag bit is set in the Retention RAM for identification when power is restored.

[0032] According to the power supply protection circuit for power distribution automation terminal provided by the application, the delay confirmation event includes:

[0033] When it is detected that the power-off detection pin level jumps from the first level to the second level, the current timestamp is immediately recorded T as the delay starting reference point;

[0034] The hardware timer is started to execute software delay T delay, meet the formula:

[0035] T delay = T threshold -Δ T error

[0036] Wherein, T threshold The preset power-off confirmation threshold time; Δ T error The timer accuracy compensation value;

[0037] During the delay period, when the hardware timer triggers an interrupt, a delay completion flag is generated Flag delay_done ;

[0038] When Flag delay_done =1, the level state of the power-off detection pin is read again V PA8 , and the following determination logic is executed:

[0039] If V PA8 = the first level, it is determined that the power supply is disturbed by noise, the interrupt flag is cleared and the exit is executed;

[0040] If V PA8 = the second level, it is confirmed that the power-off event is valid, the power-off processing function is triggered, and the total system response time T response Meet the formula:

[0041] T response = T detect + T delay + T process

[0042] Wherein, T process The execution time of the power-off processing function.

[0043] It can be seen that, compared with the prior art, the power supply protection circuit of the power distribution automation terminal proposed by the application has the advantages of stable operation of the power distribution automation terminal, data security and improved system reliability, and the specific beneficial effects are as follows:

[0044] 1、The power input protection circuit can effectively filter these bad power signals, prevent them from causing damage to the subsequent circuit, and provide a solid foundation for the stable operation of the device.

[0045] 2、The power failure detection circuit uses photoelectric isolation technology to monitor the power input state in real time and accurately, and the application of photoelectric isolation technology effectively isolates the interference signals on the power side, improving the accuracy and reliability of power failure detection.

[0046] 3、When the main power supply is abnormal, it plays a key role. When the main power supply fails or loses power, the voltage maintenance protection circuit can quickly start the discharge operation of the super capacitor, providing stable power support for the key load of the core board in a short time, maintaining its normal operation, so that the power distribution automation terminal can still complete some key operations such as data saving and state reporting under the condition of main power interruption, avoiding data loss and system disorder caused by sudden power failure, and improving the reliability and data security of the system.

[0047] 4、When the main power supply is normal, the clock chip is powered by the main power supply; when the main power supply is abnormal, the circuit can automatically and seamlessly switch to the second super capacitor power supply. The super capacitor has the advantages of low self-discharge rate and long service life, and can provide long-term stable power supply for the clock chip to ensure continuous operation of the clock chip. Accurate system time is crucial for power distribution automation terminals, as it involves time stamps for data recording, execution of timing tasks, and other key functions. The clock backup battery protection circuit ensures the accuracy of the system time, avoids the accumulation of time errors caused by clock interruption, and improves the overall performance and reliability of the system.

[0048] 5、The power protection circuit of the application realizes the deep cooperation of hardware circuit and software control, the hardware circuit provides a solid physical basis for power protection, and the software control precisely configures and flexibly schedules the hardware circuit, realizes the intelligent management of the power protection circuit through the device tree configuration, the interrupt trigger setting and the writing of the power failure processing function in the software layer, fully gives play to the high performance of hardware and the flexibility of software, can dynamically adjust the power protection strategy according to different application scenes and requirements, and improves the comprehensive performance and adaptability of the entire power distribution automation terminal system.

[0049] 6、The application prevents the occurrence of the power backflow phenomenon by reasonably designing the power-on sequence of the mainboard power supply and the core board, and making the mainboard power supply power on later than the core board.

[0050] The application will be further described in detail in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 is a principle diagram of a hardware-software cooperative power protection circuit embodiment of a power distribution automation terminal of the application.

[0052] Figure 2 is a circuit principle diagram of a power input protection circuit in the hardware-software cooperative power protection circuit embodiment of the power distribution automation terminal of the application.

[0053] Figure 3 is a circuit principle diagram of a power failure detection circuit in the hardware-software cooperative power protection circuit embodiment of the power distribution automation terminal of the application.

[0054] Figure 4 is a circuit principle diagram of a voltage maintenance protection circuit in the hardware-software cooperative power protection circuit embodiment of the power distribution automation terminal of the application.

[0055] Figure 5 is a circuit principle diagram of a mainboard power supply circuit in the hardware-software cooperative power protection circuit embodiment of the power distribution automation terminal of the application.

[0056] Figure 6 is a circuit principle diagram of a clock backup battery protection circuit in the hardware-software cooperative power protection circuit embodiment of the power distribution automation terminal of the application. DETAILED DESCRIPTION

[0057] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0058] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0059] A software and hardware cooperative power protection circuit of a power distribution automation terminal

[0060] Referring to Figure 1 The embodiment provides a software and hardware cooperative power protection circuit of a power distribution automation terminal, which comprises a mainboard and a core board, and the mainboard comprises the following components:

[0061] A power input protection circuit is used for controlling the connection and disconnection of an input power supply.

[0062] A voltage conversion circuit is connected with the power input protection circuit and is used for converting an input power supply voltage into working voltages of various modules.

[0063] A power-off detection circuit adopts photoelectric isolation technology and is used for monitoring the input state of the power supply in real time. When the input state of the power supply is normal, a first level signal is output. When it is detected that the power supply is disconnected or power-off, a second level signal is output to trigger a power-off event detection. On the software level, the function of a power-off detection pin is defined in a device tree, the power-off detection pin is configured as an interrupt trigger pin, the power-off detection pin is initialized and an interrupt is requested, the interrupt trigger condition is set as a level change, and when the interrupt trigger condition occurs, a power-off detection event is triggered, which comprises a delay confirmation event and an execution event of a power-off processing function.

[0064] A voltage maintenance protection circuit is connected with the voltage conversion circuit and is used for maintaining the normal power supply of key loads of the core board by executing a discharging operation of a first super capacitor when the main power supply is abnormal.

[0065] The clock backup battery protection circuit is connected with the clock chip, adopts a second super capacitor as a backup battery, and is used for automatically switching to the second super capacitor for power supply when the main power supply is abnormal, so as to ensure continuous running of the clock chip.

[0066] As shown in Figure 2 The power input protection circuit adopts an anti-reverse connection diode D37 and an electronic overvoltage protection circuit composed of a PNP transistor Q30 and a P-channel field effect tube N2. The anti-reverse connection diode D37 is connected in series in the input path of the external input voltage, and is reverse blocked when the positive and negative poles are connected reversely, so that the circuit is not conducted, and the reverse voltage is prevented from entering the system. The base of the PNP transistor Q30 is connected between the cathode of the anti-reverse connection diode D37 and the cathode of a voltage stabilizing diode D36, the anode of the voltage stabilizing diode D36 is grounded, and the collector of the PNP transistor Q30 is connected with the gate of the P-channel field effect tube N2. The source of the P-channel field effect tube N2 is connected with a 24V DC power input, and the drain thereof is connected with a 24V power output.

[0067] The external input voltage is detected. When the external input voltage is less than a preset threshold voltage, the voltage stabilizing diode D36 is in a cut-off state, so that the PNP transistor Q30 lacks a conduction loop, and the collector thereof presents a low voltage state. When the external voltage is greater than the preset threshold voltage 24V, and the voltage difference between the base and the emitter of the PNP transistor Q30 reaches the conduction voltage of the PN junction, the PNP transistor Q30 is conducted, and the collector voltage of the PNP transistor Q30 is substantially equal to the external input voltage at this time.

[0068] The collector voltage of the PNP transistor Q30 is used as the control signal of the P-channel field effect tube N2. When the external input voltage is less than the preset threshold voltage, the collector of the PNP transistor Q30 is low voltage, that is, the gate voltage of the field effect tube N2 is low voltage. In this case, the drain and the source of the P-channel field effect tube N2 are conducted, and the external input voltage is allowed to be normally output through the field effect tube. When the external voltage is greater than 24V and the PNP transistor Q30 is conducted, the gate voltage of the P-channel field effect tube N2 is substantially equal to the source voltage thereof, the P-channel field effect tube N2 is cut off, and the output path of the external input voltage is cut off, so as to prevent overvoltage from causing damage to the internal circuit.

[0069] Specifically, the anti-reverse connection diode D37 is reverse blocked when the positive and negative poles are connected reversely. When the positive and negative poles are connected reversely in the field, the voltage cannot enter the system, so as to protect the equipment. The overvoltage protection circuit is composed of the PNP transistor Q30 and the P-channel field effect tube N2.

[0070] When the external voltage is less than 24V, the voltage stabilizing diode D36 does not reach the conduction voltage, and is not conductive, and the PNP transistor Q30 has no conduction loop, so the 3-pin of the PNP transistor Q30 is low voltage, that is, the G-pin of the P-channel field effect transistor N2 is low voltage, the D-pin and the S-pin of the P-channel field effect transistor N2 are conductive, and the 24V voltage passes through the field effect transistor, and the 24V voltage has an output.

[0071] When the voltage is greater than 24V, the voltage stabilizing diode D36 is conductive, and the voltage is stabilized at 24V, and when the voltage between the 2-pin and the 1-pin of the PNP transistor Q30 is greater than the conduction voltage of the PN, the entire input voltage is about 25V, at this time, the 2-pin and the 3-pin of the PNP transistor Q30 are conductive, the voltage of the 3-pin of the PNP transistor Q30 is substantially equal to the voltage of the S-pin, that is, the voltage of the G-pin of the P-channel field effect transistor N2 is substantially equal to the voltage of the S-pin, and the N2 field effect transistor is cut off. The 24V output has no voltage, thereby protecting the internal circuit.

[0072] When the NCE01P05S field effect transistor shown in the P-channel field effect transistor N2 is selected, Figure 2 because VDS =-100V, the input voltage can reach 100V without being broken down, and the subsequent circuit is not affected. Therefore, the selection of the field effect transistor with high VDS can effectively protect the subsequent circuit.

[0073] Therefore, the power input protection circuit provided in the embodiment mainly uses a voltage stabilizing tube, a transistor and a field effect transistor, and the traditional circuit uses a relay to achieve the same. Because the relay exists, there is a certain time delay, and the relay also has the problem of service life times, and the contact has the problem of reliability. The power input protection circuit provided in the embodiment is completely realized by electronic devices, avoids these defects, and ensures the reliability of the circuit work, and the input protection voltage is increased to 100V.

[0074] As shown in the figure, Figure 3 The power-down detection circuit includes an optical isolation device U2, a voltage stabilizing diode D4, a voltage stabilizing diode D6, and an output pin PA8. The cathode of the voltage stabilizing diode D4 is connected to the input voltage VCC-DCIN, the anode is connected to the 1-pin of the optical isolation device U2, the cathode of the voltage stabilizing diode D6 is connected between the 1-pin of the optical isolation device U2 and the resistor R16, and the anode of the voltage stabilizing diode D6 is connected to the 2-pin of the optical isolation device U2 and the ground, for voltage stabilizing protection of the input side of the optical isolation device U2. The 4-pin of the optical isolation device U2 is connected to the power supply VDD_3V3, the 3-pin of the optical isolation device U2 is connected to the output pin PA8 through the resistor R17, and the output pin PA8 is the output end of the power-down detection signal. When the PA8 outputs a high level, it indicates that the input voltage VCC-DCIN is normal. When the PA8 is low, it indicates that the input voltage VCC-DCIN is disconnected or power down, triggering the power-down event detection.

[0075] The voltage detection element is set as the voltage stabilizing diode D4, a specific voltage threshold range is preset, when the input voltage VCC-DCIN is greater than a specific value K1 in the threshold range, the voltage stabilizing diode D4 reaches the conduction condition and enters the conduction state to provide the input signal for the optical isolation device U2; when the input voltage VCC-DCIN is disconnected or power off, the voltage value is less than the specific value K1, the voltage stabilizing diode D4 cannot meet the conduction condition and is in the cut-off state, at this time, the 1 pin of the optical isolation device U2 has no voltage input.

[0076] The optical isolation device U2 is used as the key element for signal transmission and isolation, when the 1 pin of the optical isolation device U2 has voltage input, the 4 pin and the 3 pin of the optical isolation device U2 are conductive, the output pin PA8 outputs the high level signal, indicating that the power input is in the normal state; when the 1 pin of the optical isolation device U2 has no voltage input, the 4 pin and the 3 pin of the optical isolation device U2 cannot be conductive, the output pin PA8 outputs the low level signal, which is used as the detection signal of the power disconnection or power off.

[0077] Specifically, the input voltage VCC-DCIN is the total power input of the entire power distribution terminal device, the voltage range is 12V, 24V and 48V and the like, through the voltage stabilizing diode D4-BZT52C6V2, when the input voltage is greater than 6.2V (5.8~6.6V range), the voltage stabilizing diode D4 is conductive, the optical isolation device U2 has input, so that the 4 pin and the 3 pin of the optical isolation device U2 are conductive, the PA8 outputs the high level and works normally.

[0078] When the input voltage VCC-DCIN is disconnected or power off, the voltage value is less than 6.2V, the 1 pin of the optical isolation device U2 has no voltage input, the 4 pin and the 3 pin of the optical isolation device U2 cannot be conductive, and the PA8 is low level. Among them, U2 is the optical isolation device, which can improve the anti-interference ability of the detection circuit.

[0079] As Figure 4As shown, the voltage maintenance protection circuit includes diode D1, a first super capacitor composed of super capacitor E1 and super capacitor E2, overvoltage protection circuit U1, overvoltage protection circuit U2, a voltage monitoring circuit composed of voltage stabilizing tube D3 and PNP type triode Q2, the anode of diode D1 is connected to a 5V power supply, the cathode of diode D1 is connected to the positive pole of the first super capacitor, the VCC pin of overvoltage protection circuit U1 and overvoltage protection circuit U2 is respectively connected to the positive pole of super capacitor E1 and super capacitor E2, the IOUT pin of overvoltage protection circuit U1 and overvoltage protection circuit U2 is respectively connected to the ground through current discharge resistor R3 and R4; the base of PNP type triode Q2 is connected to the anode of voltage stabilizing tube D3 through resistor R6, the cathode of voltage stabilizing tube D3 is connected to the gate of field effect tube Q1, which is turned on when the voltage is higher than the voltage stabilizing value of the voltage stabilizing tube, the emitter of PNP type triode Q2 is grounded, the collector of PNP type triode Q2 is connected to the gate and source of field effect tube Q1, and the drain of field effect tube Q1 is connected to the +5V_CORE pin of the core board.

[0080] Specifically, at the time of power failure, if the CPU is to continue to work, it is necessary to ensure that the CPU power supply part remains normal at the time of power failure, which is mainly completed by the super capacitor charging and discharging circuit.

[0081] Super capacitors E1 and E2 are 10F / 2.7V super capacitors, which complete energy storage. Diode D1 is a one-way design that can prevent super capacitor storage from powering the bottom plate and ensure that only the core board of the system is powered.

[0082] Overvoltage protection circuits U1 and U2 are capacitor monomer overvoltage protection circuits, R3 and R4 are current discharge resistors, which ensure that the protection voltage accuracy is within 1%, BW6101 chips are used, which can replace original TL431, XC61C and other discrete component solutions, the circuit is simple, the peripheral devices are small, the voltage accuracy is high, and it is a special chip specially developed for super capacitor protection.

[0083] BW6101 uses a high-precision internal voltage reference to ensure that the protection voltage accuracy is within 1%, and the built-in power tube can provide large current discharge capacity. Without external current expansion tube, it can provide 200mA current discharge capacity. If large current discharge protection is required, external expansion MOS tube can be used, the maximum discharge capacity can reach several amperes or even tens of amperes, meeting the protection requirements of large-capacity farad capacitor modules.

[0084] The voltage monitoring circuit is composed of the voltage stabilizing tube D3 and the PNP type triode Q2. Only when the voltage is higher than 3.3V (voltage stabilizing tube) + 0.66V (BE on voltage of Q2) = 3.96V, the voltage can be added to the main power supply of the core board. The purpose of the processing is to ensure that when the voltage is lower than the working voltage of the core board, the power supply is quickly cut off when power off, which is beneficial to the system to quickly restart when the next power supply. If the super capacitor is discharged slowly, the system will not start when power supply again, and the super capacitor must be fully discharged to power on again.

[0085] The calculation formula is as follows:

[0086]

[0087] The voltage drop of diode D1 (SS34) is about 0.3V when full charged, the voltage of super capacitor E1+E2 is 4.7V, Vwork=4.70V, Vmin=3.96V, the total capacity of two 10F super capacitors in series is 5F, and the calculation according to the formula is as follows:

[0088] t=(5F)X(22.09-15.6816) / (8.66X0.5)=5X6.4084 / 4.33=7.4S

[0089] According to the above formula, the effective working voltage of the circuit can be maintained for about 7.4S. If you want to increase the effective standby time, you can modify the capacity of the super capacitor, such as E1=E2=20F / 2.7V, the total capacity after series connection is 10F, which can maintain 14.8S. As long as the system can complete the file operation and complete the power down, it is not necessary to be longer.

[0090] As shown in Figure 5 , the embodiment further includes a main board power supply circuit, which includes a power supply chip U10, a 5V input power supply, an input filter circuit and an output filter circuit. The signal input by the 5V input power supply is converted in voltage by the power supply chip U10, and in the process of power conversion, the signal is filtered and output by the input filter circuit and the output filter circuit. The power supply chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power supply chip. When all the power modules in the core board reach the stable working state, the PG_V33 signal is set to an effective state, triggering the power supply chip U10 to start working and completing the power-on of the peripheral IO port. The PG_V33 signal is the last power good signal sent by the core board to indicate that the main board power-on is completed.

[0091] Specifically, the GPIO of the CPU SOC of the core board is pulled up to the power supply domain of the main board by a pull-up resistor. If the power supply domain of the main board is powered on earlier than the power supply domain of the GPIO of the SOC, backflow will occur, which may cause the SOC to work abnormally in the long term. After the core board is powered on, a signal is sent to drive the power supply chip of the main board to work. The PG_V33 is the last signal of the power supply sent by the core board to indicate that the power supply of the main board is completed, and the main board can use the signal to enable the power supply of the bottom plate to complete the power-on of the peripheral IO port. The consequences of current backflow are uncertain, diverse, and hidden. If the system has abnormal IO port for unknown reasons, it may be caused by current backflow, which may cause system crash and other faults. Therefore, the seemingly simple circuit processing of the embodiment can avoid these mysterious faults, especially in the application environment where the power system has high requirements for the device.

[0092] As shown in Figure 6 The clock backup battery protection circuit includes a real-time clock chip U16, a second super capacitor E3, and an LED lamp (NCD1206R1). The anode of the LED lamp is connected to a 5V input power supply, the cathode of the LED lamp is connected to the positive electrode of the second super capacitor E3 and the VBAT pin of the real-time clock chip U16, the negative electrode of the second super capacitor E3 is grounded, and the SCL and SDA pins of the real-time clock chip U16 are used for I2C communication and are connected to the external I2C bus respectively. A filter capacitor is connected to the VBAT pin of the real-time clock chip U16, one end of which is connected to the VBAT pin of the real-time clock chip U16 and the other end is grounded, for filtering high-frequency noise on the power supply line.

[0093] In the embodiment, as a power device, the accuracy and stability of the clock are not questionable. Since the selected clock chip is SD3078, the required power supply range of the VBAT backup battery is 2.3V~3.6V, and a 5.5V / 1F super capacitor is selected as the backup battery, which has the characteristics of long service life and can theoretically achieve unlimited charging and discharging. In addition, the LED lamp is directly used in the circuit in the embodiment, which has a charging voltage drop of 1.6V and also plays a role in current limiting. The current itself is below 25mA, and the LED itself can also be used as a charging indicator lamp. The closer to full, the darker the lamp. As can be seen from the parameter table, the LED also has a very small reverse current, which is only about 0.3uA, and only has a small loss, which can meet the requirements of power failure protection.

[0094] In the embodiment, the power failure processing function realizes interrupt response and system protection through the following steps, and cooperates with the optical isolation device U2 and the device tree configuration:

[0095] The optical isolation device U2 monitors the power input state in real time, converts the level change of the power side into the intensity change of the optical signal of the isolation side; when the power input is normal, the output side of the optical isolation device U2 is turned on, and the first level signal is output to the power failure detection pin of the core board; when it is detected that the power is disconnected or the voltage drops below the threshold, the output side of the optical isolation device U2 is cut off, and the second level signal is output to the power failure detection pin, triggering a level change interrupt;

[0096] The functional parameters of the power failure detection pin are defined in the device tree, including the pin number, the interrupt type triggered by the level change, and the default level state;

[0097] When the system is initialized, the following operations are completed according to the device tree configuration:

[0098] The power failure detection pin is set to input mode, and the internal pull-up / pull-down resistor is enabled;

[0099] The power failure processing function is registered to the interrupt vector table, and the interrupt priority is set to the highest level; wherein the interrupt trigger condition is: when the power failure detection pin level jumps from the first level to the second level, the MCU jumps to the interrupt service program and executes the delay confirmation event;

[0100] When the delay confirmation power failure detection pin continues to be at the second level, the power failure processing function is executed: the current system running state is written into the Retention RAM of the MCU, an instruction is sent to the power management chip through the I2C / SPI interface to disconnect the main power path, and the super capacitor is enabled as a backup power supply; the dynamic voltage adjustment algorithm is started, and the MCU working frequency is gradually reduced according to the remaining energy of the super capacitor;

[0101] All unnecessary peripheral clocks are turned off, and only the RTC is maintained to record the power failure timestamp; the power failure flag bit is set in the Retention RAM for identification when power is restored.

[0102] In the embodiment, the delay confirmation event includes:

[0103] When it is detected that the power failure detection pin level jumps from the first level to the second level, the current timestamp is immediately recorded T as the delay start reference point;

[0104] The hardware timer is started to execute software delay T delay , satisfying the formula:

[0105] T delay = T threshold -Δ T error

[0106] wherein, T threshold is a preset power-off confirmation threshold time; Δ T error is a timer precision compensation value;

[0107] During the delay period, when the hardware timer triggers an interrupt, a delay completion flag is generated Flag delay_done ;

[0108] When Flag delay_done = 1, the level state of the power-off detection pin is read again V PA8 , and the following determination logic is executed:

[0109] If V PA8 = the first level, it is determined that it is a power supply noise interference, the interrupt flag is cleared and the program exits;

[0110] If V PA8 = the second level, it is confirmed that the power-off event is valid, and the power-off processing function is triggered, at this time the total system response time T response satisfies the formula:

[0111] T response = T detect + T delay + T process

[0112] wherein, T process is the execution time of the power-off processing function.

[0113] In this embodiment, the dynamic voltage adjustment algorithm is started, and the working frequency of the MCU is gradually reduced according to the remaining energy of the super capacitor. The specific implementation steps are as follows:

[0114] Real-time monitoring of the voltage V sc and current I sc of the super capacitor, and the energy Δ t released by the super capacitor in a period of time Δ E sc is calculated by integration, and the calculation formula is:

[0115]

[0116] wherein, Vsc t ) and I sc t are the voltage and current of the super capacitor at time t

[0117] Record the initial energy of the super capacitor E sc0 , the remaining energy of the super capacitor at the current time is E sc

[0118]

[0119] wherein, n is the number of times of energy calculation, Δ E sci is the energy released by the super capacitor calculated for the i th time.

[0120] The maximum operating frequency f max and the minimum operating frequency f min of the MCU are preset, which are determined according to the hardware characteristics of the MCU and the performance requirements of the system. For example, f ma x = 500 MHz , f min = 100 MHz .

[0121] The remaining energy of the super capacitor E sc is mapped to the adjustment range of the operating frequency f mcu of the MCU by using a linear mapping method, wherein the lower limit of the energy threshold of the super capacitor is set as E th1 and the upper limit is set as E th2 E th1 E th2 When the remaining energy of the super capacitor E sc is between E th1 and Et h2 , the relationship between the operating frequency f mcu of the MCU and the remaining energy of the super capacitor E sc is:​​​​​​

[0122]

[0123] When E sc E th1 To ensure the basic operation of the system, the MCU operating frequency is set to the lowest operating frequency f min , that is f mcu f min When E sc E th2 To fully exert the performance of the system, the MCU operating frequency is set to the highest operating frequency f max , that is f mcu f max

[0124] According to the calculated MCU operating frequency f mcu , send a frequency adjustment instruction to the MCU through the clock control register or related interface of the MCU, and gradually adjust the operating frequency of the MCU to the calculated f mcu . For example, for an MCU with a programmable clock controller, the clock division coefficient is changed by writing a specific register value, thereby realizing the adjustment of the operating frequency.

[0125] During the adjustment of the MCU operating frequency, the running state of the system is monitored in real time, and if the system appears abnormal (such as task execution timeout, data transmission error, etc.), the frequency adjustment is suspended, and corresponding processing is performed according to the abnormal situation, such as restoring the MCU to the previous stable operating frequency or performing fault diagnosis and repair. After the system returns to normal, the adjustment of the operating frequency is continued according to the remaining energy of the super capacitor.

[0126] In actual application, when the power-down signal is detected, the software program processes according to the following steps:

[0127] ​​​​​Device tree configuration: In the device tree file board.dts, define the powerdown_protect node, set the compatible attribute to "powerdown-protect" to match the name in the driver file; set the state attribute to "okay" to enable the PA8 detection pin; set the irq-gpios attribute to <&pio PA 8 GPIO_ACTIVE_HIGH> to define PA8 as an interrupt pin with high-level trigger.

[0128] Power-down detection pin initialization: In the powerdown-protect.c file, initialize the operation through the pwdown_protect_probe function:

[0129] Use the of_get_named_gpio function to get the GPIO number of the specified name "irq-gpios" from the device tree node and assign it to irq_gpio.

[0130] Use the gpio_is_valid function to check whether the obtained irq_gpio is valid. If it is not valid, output the error message "No valid irq gpio" through the dev_err function and return the error code -ENODEV.

[0131] Call the devm_gpio_request function to apply for the GPIO in the system. If the application fails, output the error message "irq io request failed" through the dev_err function and return the corresponding error code.

[0132] Use the gpio_to_irq function to convert the obtained GPIO to an interrupt request (IRQ) line. If the conversion fails, output the error message "No IRQ resource found (%d)" through the dev_err function, where %d is the error code, and return the error code.

[0133] Use the devm_request_irq function to request and register an interrupt handler, set the interrupt trigger condition to IRQF_TRIGGER_FALLING (falling edge trigger), and if the request fails, output the error message "Failed to request IRQ %d: %d" through the dev_err function, where the first %d is the interrupt number and the second %d is the error code, and return the error code; if the initialization is successful, return 0.

[0134] Interrupt response processing: When PA8 occurs an interrupt, trigger the pwdown_protect_irq_handle function:

[0135] Get the platform_device structure pointer pdev from the incoming parameter data.

[0136] Output the prompt information "Syncing FileSystem..." to the debug serial port through the dev_info function.

[0137] Call the orderly_poweroff function, pass in the parameter true, and execute the specific power-off processing operation.

[0138] Power-off processing function implementation: The orderly_poweroff function receives a Boolean type parameter force:

[0139] If force is true, set the poweroff_force variable to true to ensure that the existing "true" state will not be overwritten.

[0140] Call the schedule_work function to add poweroff_work to the default work queue to complete the subsequent power-off processing task.

[0141] In the design and performance guarantee of power terminal products, it is necessary to strictly meet the requirements of "Voltage Sag and Short Interruption Immunity", and specifically to meet the A class standard in GB / T17626.11-2023. The standard clearly stipulates that under the condition of power supply voltage of 0%UT (i.e. no backup power supply state) and voltage short interruption for 0.5s, the terminal equipment must remain stable operation, and cannot appear abnormal conditions such as error action, damage, dead machine, restart and communication interruption; after the power supply voltage is restored, the stored data should remain unchanged, and the equipment can work normally.

[0142] The embodiment adopts a specific power-off detection and processing strategy at the software level. The system detects whether a power failure occurs by continuously monitoring the level state of PA8 detection pin. When PA8 detection pin is first detected as low level, the power-off processing flow is not started immediately. Instead, a 0.7s delay is set, and after the delay ends, the level of PA8 pin is detected again. If the level of PA8 pin is still low at this time, and the duration of the low level has exceeded the 0.5s time threshold specified in the test, the system determines that a real power failure event has occurred, and then starts the software power-off processing mechanism.

[0143] Through the way of setting the delay and the secondary detection level by the software, the misjudgment caused by the temporary voltage fluctuation or interference can be effectively avoided, and it is ensured that the system only performs the power-off processing operation in the case of real power-off and meeting the test requirements, so as to comprehensively meet the requirements of the A class standard in GB / T 17626.11-2023 on the immunity of power terminal products to voltage sag and short-time interruption.

[0144] In conclusion, in the power input end of the embodiment, anti-reverse connection and electronic overvoltage protection measures are adopted, and in the actual field installation process, due to the negligence of the operator or the complexity of the environment, the power connection is reversed and the voltage is too high from time to time. However, the protection mechanism of the application can withstand an overvoltage of 100V, and when the power is connected in reverse or the voltage exceeds the safe range, the protection function can be quickly started to effectively prevent the equipment from being damaged due to abnormal power supply, thereby greatly reducing the maintenance cost and replacement frequency of the equipment, improving the reliability and usability of the equipment in complex field environments, and providing a solid guarantee for the stable operation of the power system.

[0145] The power-off signal detection is performed by the photoelectric isolation circuit. In the power system, the input analog signal is often susceptible to various electromagnetic interferences, thereby affecting the normal operation and judgment accuracy of the system. The photoelectric isolation circuit can effectively isolate the input signal from the internal circuit of the system, prevent the intrusion of external interference signals, greatly improve the anti-interference performance of the system, make the detection of the power-off signal more accurate and reliable, and timely and accurately capture the power-off event, thereby providing an accurate basis for the subsequent power-off protection measures and ensuring that the system can quickly respond correctly under the power-off condition.

[0146] The super capacitor is used as the core element of the power-off maintenance circuit, and reliable power support is provided for the system. Unlike the traditional charge-discharge circuit which only provides discharging function, the super capacitor of the application will be cut off when discharging to a certain voltage, thereby ensuring that the system can reasonably utilize the stored power of the super capacitor during power-off, and after completing the necessary operation, the performance of the super capacitor is not affected due to excessive discharge. At the same time, when the power is restored, the system can quickly restart with the help of the remaining energy stored in the super capacitor, thereby reducing the system recovery time, improving the response speed and operation efficiency of the system, and ensuring that the power terminal can resume normal work in time, thereby reducing the influence on the power system monitoring and control.

[0147] The application prevents the power backflow phenomenon by reasonably designing the power-on sequence of the mainboard power supply and the core board, and makes the mainboard power supply power on later than the core board. In electronic equipment, the power backflow may cause the core board main chip to be damaged, and seriously affect the performance and service life of the equipment. The power protection design of the scheme avoids this situation, provides a safe operating environment for the core board main chip, and ensures the stability and reliability of the product during long-term use. It is very important for power terminal equipment that needs to run continuously for a long time, can reduce equipment failures caused by power problems, reduce maintenance costs, and improve the overall operation efficiency of the power system.

[0148] The application adopts a simple light emitting diode circuit to realize a clock backup battery protection circuit, which can not only complete the functions of voltage reduction, current limiting, voltage matching, and ensure that the clock backup battery provides stable working voltage for the clock circuit, but also prolong the service life of the clock circuit. Meanwhile, the light emitting diode also has a light emitting indication function, which can directly display the charging state of the battery. This simple and practical design reduces the complexity and cost of the circuit, reduces the failure points, and improves the reliability and maintainability of the circuit. In practical application, the operator can quickly understand the charging condition of the battery by observing the light emitting state of the light emitting diode, and conveniently maintain and handle in time.

[0149] The application significantly improves the power-down protection performance by the combination of software and hardware. In terms of hardware, the application has a perfect power protection circuit and power-down detection mechanism. In terms of software, the application can flexibly set the reaction time when power-down according to actual needs by programming detection pins to judge power-down events. The soft and hard cooperative working mode makes the system better meet the test requirements of the power terminal in the voltage sag and short-time interruption immunity. When power-down occurs, the system can use the power provided by the super capacitor to orderly complete key operations such as file reading and writing under the control of software, ensure that various files are not affected by power-down, and ensure the integrity of the system and the accuracy of the data. For terminal equipment in the power system that has high requirements for data integrity and system stability, the application has important practical application value, and can effectively improve the operation management level and reliability of the power system.

[0150] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0151] The above embodiments are only preferred embodiments of the application, and cannot be used to limit the protection scope of the application. Any non-essential changes and replacements made by those skilled in the art based on the application shall fall within the scope of the application.

Claims

1. A software and hardware coordinated power protection circuit for a distribution automation terminal, characterized in that: The main board comprises the following components: A power input protection circuit for controlling the connection and disconnection of the input power supply; A voltage conversion circuit connected with the power input protection circuit for converting the input power supply voltage into the working voltage of each module; A power-off detection circuit using photoelectric isolation technology to monitor the power input state in real time; When the power input is normal, a first level signal is output; when the power is disconnected or power-off is detected, a second level signal is output to trigger the power-off event detection; in the software layer, the function of the power-off detection pin is defined in the device tree, which is configured as an interrupt trigger pin, and the interrupt trigger condition is set as level change, the power-off detection event is triggered when the interrupt trigger condition occurs, and the event includes a delay confirmation event and an execution event of the power-off processing function; A voltage maintenance protection circuit connected with the voltage conversion circuit for maintaining the normal power supply of the key load of the core board by discharging operation of the first super capacitor when the main power supply is abnormal; A clock backup battery protection circuit connected with the clock chip, using a second super capacitor as a backup battery, for automatically switching to the second super capacitor power supply when the main power supply is abnormal to ensure the continuous operation of the clock chip; The power-off detection circuit comprises an optical isolation device U2, a zener diode D4, a zener diode D6, and an output pin PA8, the cathode of the zener diode D4 is connected to the input voltage VCC-DCIN, the anode thereof is connected to the 1 pin of the optical isolation device U2, the cathode of the zener diode D6 is connected between the 1 pin of the optical isolation device U2 and the resistor R16, the anode of the zener diode D6 is connected to the 2 pin of the optical isolation device U2 and the ground, for voltage protection of the input side of the optical isolation device U2, the 4 pin of the optical isolation device U2 is connected to the power supply VDD_3V3, the 3 pin of the optical isolation device U2 is connected to the output pin PA8 through the resistor R17, and the output pin PA8 is the output end of the power-off detection signal; when the output pin PA8 outputs a high level, it indicates that the input voltage VCC-DCIN is normal; when the output pin PA8 is low, it indicates that the input voltage VCC-DCIN is disconnected or power-off, triggering the power-off event detection; The power-off processing function realizes interrupt response and system protection through the following steps and cooperates with the optical isolation device U2 and the device tree configuration: The optical isolation device U2 monitors the power input state in real time and converts the level change on the power supply side into the intensity change of the optical signal on the isolation side; when the power input is normal, the output side of the optical isolation device U2 is turned on, outputting a first level signal to the power-off detection pin of the core board; when the power is disconnected or the voltage drops below the threshold, the output side of the optical isolation device U2 is cut off, outputting a second level signal to the power-off detection pin to trigger the level change interrupt; The function parameters of the power-off detection pin are defined in the device tree, including the pin number, the level change interrupt type, and the default level state.

2. The protection circuit of claim 1, wherein: The power input protection circuit adopts the anti-reverse connection diode D37 and the electronic overvoltage protection circuit composed of the PNP transistor Q30 and the P-channel field effect tube N2. The anti-reverse connection diode D37 is connected in series in the input path of the external input voltage, and is reversely cut off when the positive and negative poles of the power supply are connected reversely, so that the circuit is not conducted, and the reverse voltage is prevented from entering the system. The base of the PNP transistor Q30 is connected between the cathode of the anti-reverse connection diode D37 and the cathode of the voltage stabilizing diode D36. The anode of the voltage stabilizing diode D36 is grounded. The collector of the PNP transistor Q30 is connected with the gate of the P-channel field effect tube N2. The source of the P-channel field effect tube N2 is connected with the 24V DC power input, and the drain is connected with the 24V power output.

3. The protection circuit according to claim 2, characterized in that: The external input voltage is detected. When the external input voltage is less than a preset threshold voltage, the voltage stabilizing diode D36 is in a cut-off state, so that the PNP transistor Q30 lacks a conduction loop, and the collector thereof presents a low voltage state. When the external voltage is greater than the preset threshold voltage 24V, and the voltage difference between the base and the emitter of the PNP transistor Q30 reaches the conduction voltage of the PN junction, the PNP transistor Q30 is conducted, and the collector voltage of the PNP transistor Q30 is substantially equal to the external input voltage at this time. The collector voltage of the PNP transistor Q30 is used as the control signal of the P-channel field effect tube N2. When the external input voltage is less than the preset threshold voltage, the collector of the PNP transistor Q30 is low voltage, that is, the gate voltage of the field effect tube N2 is low voltage. In this case, the drain and the source of the P-channel field effect tube N2 are conducted, and the external input voltage is allowed to pass through the field effect tube and be normally output. When the external voltage is greater than 24V and the PNP transistor Q30 is conducted, the gate voltage of the P-channel field effect tube N2 is substantially equal to the source voltage thereof, the P-channel field effect tube N2 is cut off, and the output path of the external input voltage is cut off, so as to prevent the overvoltage from causing damage to the internal circuit.

4. The protection circuit according to claim 1, characterized in that: The voltage stabilizing diode D4 is set as a voltage detection element, and a specific voltage threshold range is preset. When the input voltage VCC-DCIN is greater than a specific value K1 in the threshold range, the voltage stabilizing diode D4 reaches a conduction condition and enters a conduction state, so as to provide an input signal for the optical isolation device U2. When the input voltage VCC-DCIN is disconnected or power-off, and the voltage value is less than the specific value K1, the voltage stabilizing diode D4 cannot satisfy the conduction condition and is in a cut-off state. At this time, the pin 1 of the optical isolation device U2 has no voltage input. The optical isolation device U2 is used as a key element for signal transmission and isolation. When the 1 pin of the optical isolation device U2 has a voltage input, the 4 pin and the 3 pin of the optical isolation device U2 are turned on, so that the output pin PA8 outputs a high level signal, indicating that the power input is in a normal state. When the 1 pin of the optical isolation device U2 has no voltage input, the 4 pin and the 3 pin of the optical isolation device U2 cannot be turned on, and the output pin PA8 outputs a low level signal as a detection signal of power disconnection or power failure.

5. The protection circuit according to any one of claims 1 to 4, characterized in that: The voltage maintenance protection circuit comprises a diode D1, a first super capacitor composed of a super capacitor E1 and a super capacitor E2, an overvoltage protection circuit U1, an overvoltage protection circuit U2, a voltage monitoring circuit composed of a voltage stabilizing tube D3 and a PNP type triode Q2, the anode of the diode D1 is connected to a 5V power supply, the cathode of the diode D1 is connected to the positive electrode of the first super capacitor, the VCC pin of the overvoltage protection circuit U1 and the overvoltage protection circuit U2 is respectively connected to the positive electrode of the super capacitor E1 and the super capacitor E2, the IOUT pin of the overvoltage protection circuit U1 and the overvoltage protection circuit U2 is respectively connected to the ground through the current discharge resistor R3 and R4; the base of the PNP type triode Q2 is connected to the anode of the voltage stabilizing tube D3 through the resistor R6, the cathode of the voltage stabilizing tube D3 is connected to the gate of the field effect tube Q1, which is turned on when the voltage is higher than the voltage stabilizing value of the voltage stabilizing tube, the emitter of the PNP type triode Q2 is grounded, the collector of the PNP type triode Q2 is connected to the gate and source of the field effect tube Q1, and the drain of the field effect tube Q1 is connected to the +5V_CORE pin of the core board.

6. The protection circuit according to any one of claims 1 to 4, characterized in that: It further comprises a mainboard power supply circuit, which comprises a power supply chip U10, a 5V input power supply, an input filter circuit and an output filter circuit, the signals input by the 5V input power supply are converted in voltage by the power supply chip U10, and the signals are filtered and output by the input filter circuit and the output filter circuit during the power supply conversion process; the power supply chip U10 is provided with an enable control pin, and the PG_V33 signal is connected to the enable control pin of the power supply chip, when all the power supply modules in the core board reach a stable working state, the PG_V33 signal is set to an effective state, triggering the power supply chip U10 to start working and completing the power-on of the peripheral IO port; wherein the PG_V33 signal is the last power good signal issued by the core board to indicate that the mainboard power-on is completed.

7. The protection circuit according to any one of claims 1 to 4, characterized in that: The clock backup battery protection circuit comprises a real-time clock chip, a second super capacitor E3 and an LED lamp, an anode of the LED lamp is connected to a 5V input power supply, a cathode of the LED lamp is connected to a positive electrode of the second super capacitor E3 and a VBAT pin of the real-time clock chip, a negative electrode of the second super capacitor E3 is grounded, SCL and SDA pins of the real-time clock chip are used for I2C communication and are respectively connected to external I2C buses; A filter capacitor is connected to the VBAT pin of the real-time clock chip, one end of the filter capacitor is connected to the VBAT pin of the real-time clock chip and the other end of the filter capacitor is grounded, and the filter capacitor is used for filtering high-frequency noise on a power supply line.

8. The protection circuit according to any one of claims 1 to 4, characterized in that: When the system is initialized, the following operations are completed according to the device tree configuration: Set the power-down detection pin to input mode and enable the internal pull-up / pull-down resistor; Register the power-down processing function to the interrupt vector table and set the interrupt priority to the highest level; wherein the interrupt trigger condition is that when the power-down detection pin level jumps from a first level to a second level, the MCU jumps to the interrupt service program and executes the delay confirmation event; After the delay confirmation power-down detection pin continues to be at the second level, the power-down processing function is executed: write the current system running state into the Retention RAM of the MCU, send a command to the power management chip through the I2C / SPI interface, disconnect the main power supply path and enable the super capacitor as a backup power supply; start the dynamic voltage adjustment algorithm and gradually reduce the MCU working frequency according to the super capacitor remaining energy; Turn off the clock of all unnecessary peripherals and only maintain the RTC to record the power-down timestamp; set the power-down flag bit in the Retention RAM for identification when power is restored.

9. The protection circuit according to any one of claims 1 to 4, characterized in that, The delay confirmation event comprises: immediately record a current time stamp upon detecting a jump of the brown-out detection foot level from the first level to the second level T detect, as a delay start reference point; Initiating hardware timer to perform software delay T delay satisfies the equation: T delay = T threshold -Δ T error wherein, T threshold is a predetermined power down confirmation threshold time; Δ T error is a timer accuracy compensation value; During the delay, a hardware timer triggers an interrupt, which generates a delay completion flag bit Flag delay_done ; When Flag delay_done = 1, read the level state of the power-down detection pin again V PA8 and the following decision logic is executed: If V PA8 = first level, determine that it is power noise interference, clear the interrupt flag and exit; If V PA8 = second level, confirming that the power-down event is valid, triggering the power-down handling function, at this time the system total response time T response satisfies the formula: T response = T detect + T delay + T process wherein, T process is the power down processing function execution time.

Images