Multi-channel solid state power controller based on DSP + FPGA architecture

Abstract

The invention discloses a multi-channel solid-state power controller based on a DSP + FPGA architecture. The multi-channel solid-state power controller comprises a DSP main control unit, an FPGA control unit, an SSPC channel unit, a power supply unit and a communication interface, the multi-channel power distribution control problem can be well solved; and meanwhile, a capacitive load power distribution function is realized by utilizing a PWM (Pulse Width Modulation) technology, a short-circuit state and a false short-circuit state caused by the capacitive load can be accurately judged, and the reliability of the product is further improved.

Description

Technical Field

[0001] The present invention relates to a multi-channel solid-state power controller based on DSP+FPGA architecture. Background Art

[0002] Solid-state power controllers (SSPCs) are currently a mainstream intelligent solid-state power distribution device, offering both short-circuit and overcurrent protection. Compared to traditional power distribution switchgear (such as circuit breakers, fuses, contactors, and relays), SSPCs not only offer advantages such as compact size and light weight, but also boast enhanced safety, reliability, and intelligence. Their inverse-delay I²t overcurrent protection is more precise, and the overcurrent protection level can be flexibly adjusted to meet user requirements. Current SPCs utilize a single master control unit to control a single distribution channel. Simultaneously distributing power to multiple loads requires the addition of additional master control components to manage the increased number of distribution channels. This significantly increases software development complexity. Furthermore, with the increased number of components, product failure rates increase significantly, further reducing reliability. For example, CN205335828U discloses a solid-state power controller with an anti-backflow function. The controller includes an FPGA processor connected to an A / D conversion circuit. The controller determines whether to activate the protection function based on the digital current signal and, when necessary, sends a drive signal to the drive circuit. The drive circuit is connected to the processor, a first field-effect transistor, and a second field-effect transistor, respectively, to drive the first field-effect transistor and the second field-effect transistor to shut down simultaneously. This utility model can effectively prevent power supply system failures caused by current backflow and reduce power supply losses. However, it does not use a DSP as a transfer management station, which means it lacks the capacitive debt distribution function. Summary of the Invention

[0003] In order to solve the above technical problems, the present invention provides a multi-channel solid-state power controller based on DSP+FPGA architecture.

[0004] The present invention is achieved through the following technical solutions.

[0005] The present invention provides a multi-channel solid-state power controller based on DSP+FPGA architecture; comprising a DSP main control unit, an FPGA control unit, an SSPC channel unit, a power supply unit, and a communication interface;

[0006] The DSP main control unit is used to receive control instructions from external devices and interact with the FPGA control unit through the SPI bus;

[0007] The FPGA control unit is connected to the DSP main control unit via the SPI bus and is connected to all channels of the SSPC channel unit via the isolation drive circuit;

[0008] The SSPC channel unit includes 32 SSPC channels, each of which includes a power switch circuit, a current detection module, a voltage detection module, and an isolation interface. The isolation interfaces of all channels are connected in parallel to the FPGA control unit.

[0009] The power supply unit provides multi-channel isolated power to the DSP main control unit, FPGA control unit and each SSPC channel unit;

[0010] The main control unit integrated in the DSP is used to receive external CAN bus instructions and upload channel status data.

[0011] The power switch circuit uses MOSFET as the core switch device, and its gate is connected to the isolation drive circuit through a slow-start drive circuit composed of resistors R1, R2 and capacitor C.

[0012] The FPGA control unit performs the following functions:

[0013] Based on I 2 t anti-delay algorithm to achieve over-current protection;

[0014] Compare the load current with the short-circuit threshold in real time to trigger short-circuit protection;

[0015] PWM pulse width modulation is used to realize slow start charging of capacitive loads.

[0016] The power supply unit adopts a dual-redundancy design, including anti-reverse polarity diodes, fuses and energy storage circuits, and generates through multi-channel isolated DCDC modules: 5V main power supply, 3.3V / 1.9V power supply for DSP, 3.3V / 1.8V / 0.85V power supply for FPGA, and isolated 5V power supply for each SSPC channel.

[0017] The current detection module uses a Hall effect principle micro sensor, and the collected data is converted by ADC and then input into the FPGA control unit.

[0018] Each SSPC channel unit contains a freewheeling diode to provide discharge for the reverse electromotive force when the inductive load is disconnected.

[0019] The beneficial effects of the present invention are: it can well solve the problem of multi-channel power distribution control; at the same time, it uses PWM pulse width modulation technology to realize the capacitive load power distribution function, and can accurately judge the short-circuit state and the false short-circuit state caused by the capacitive load, thereby further improving the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the DSP+FPGA framework principle of the present invention;

[0021] Figure 2It is a structural schematic diagram of the power supply unit of the present invention;

[0022] Figure 3 Schematic diagram of the SSPC channel unit structure of the present invention;

[0023] Figure 4 This is a schematic diagram of the MOS tube driving circuit structure of the present invention;

[0024] Figure 5 A capacitive load charging method is implemented for PWM pulse width modulation. DETAILED DESCRIPTION

[0025] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0026] A multi-channel solid-state power controller based on DSP+FPGA architecture; including DSP main control unit, FPGA control unit, SSPC channel unit, power supply unit, and communication interface;

[0027] The DSP main control unit is used to receive control instructions from external devices and interact with the FPGA control unit through the SPI bus;

[0028] The FPGA control unit is connected to the DSP main control unit via the SPI bus and is connected to all channels of the SSPC channel unit via the isolation drive circuit;

[0029] The SSPC channel unit includes 32 SSPC channels, each of which includes a power switch circuit, a current detection module, a voltage detection module, and an isolation interface. The isolation interfaces of all channels are connected in parallel to the FPGA control unit.

[0030] The power supply unit provides multi-channel isolated power to the DSP main control unit, FPGA control unit and each SSPC channel unit;

[0031] The main control unit integrated in the DSP is used to receive external CAN bus instructions and upload channel status data.

[0032] The power switch circuit uses MOSFET as the core switch device, and its gate is connected to the isolation drive circuit through a slow-start drive circuit composed of resistors R1, R2 and capacitor C.

[0033] The FPGA control unit performs the following functions:

[0034] Based on I 2 t anti-delay algorithm to achieve over-current protection;

[0035] Compare the load current with the short-circuit threshold in real time to trigger short-circuit protection;

[0036] PWM pulse width modulation is used to realize slow start charging of capacitive loads.

[0037] The power supply unit adopts a dual-redundancy design, including anti-reverse polarity diodes, fuses and energy storage circuits, and generates through multiple isolated DC / DC modules: 5V main power supply, 3.3V / 1.9V power supply for DSP, 3.3V / 1.8V / 0.85V power supply for FPGA, and isolated 5V power supply for each SSPC channel.

[0038] The current detection module uses a Hall effect principle micro sensor, and the collected data is converted by ADC and then input into the FPGA control unit.

[0039] Each SSPC channel unit contains a freewheeling diode to provide discharge for the reverse electromotive force when the inductive load is disconnected.

[0040] The present invention can accomplish the following functions:

[0041] 1) On / off control of up to 32 load distribution channels;

[0042] 2) Voltage and current collection for up to 32 load distribution channels;

[0043] 3) Adopt I2t reverse delay overcurrent protection function based on thermal accumulation model;

[0044] 4) Short circuit protection function;

[0045] 5) Fault locking and reset function.

[0046] In addition, it can overcome the shortcomings of previous solid-state power distribution devices, mainly in the following two aspects:

[0047] 1) In traditional solid-state power distribution devices, one main control unit controls one load distribution channel, resulting in a complex hardware circuit structure. In the present invention, 32 load distribution channels share one control unit, thereby simplifying circuit design, improving reliability, reducing failure risks, and meeting the low-cost requirements of product design.

[0048] 2) Capacitive load function is achieved through embedded software control technologies such as pulse width modulation. The present invention can distinguish and judge between load short circuit and false short circuit conditions caused by capacitive load inrush current, with a wider range of applications and higher reliability.

[0049] 32 load distribution channels share one control unit, greatly simplifying circuit design, reducing the number of components used, and significantly reducing the risk of failure. Furthermore, the DSP+FPGA control architecture fully leverages the advantages of FPGA parallel processing, further improving the stability and reliability of the product while meeting the low-cost requirements of product design. One main control unit and multiple distribution output channels reduce product size and weight while meeting the needs of simultaneous power distribution to multiple loads, meeting the current lightweight and miniaturized development needs of aircraft primary power distribution systems. Capacitive load-carrying functionality is achieved through embedded software control technologies such as pulse width modulation. The present invention can distinguish and judge between load short circuits and false short circuit conditions caused by capacitive load inrush current, further improving product stability and reliability.

[0050] Figure 1 The overall design framework is shown below. The DSP serves as a transit and management station, interacting with the outside world via the CAN bus, receiving and uploading status information for each channel. It also interacts with the FPGA via the SPI bus, receiving DSP commands and performing logical control, ultimately managing all power distribution nodes. The FPGA is interconnected with each channel in an isolated manner, controlling the corresponding channel according to commands, collecting current and voltage data for overcurrent and short-circuit protection, and identifying status based on voltage.

[0051] Figure 2 This is the design framework for the power supply. The power supply adopts a dual-redundancy design, and the fuse is used to prevent power failure caused by a short circuit. The addition of a diode gives the design an anti-reverse polarity function. The energy storage circuit consists of a diode, a capacitor, and a resistor. The resistor suppresses the charging current, and the diode achieves low-resistance discharge. The power conversion consists of four parts: a 5V power supply, a DSP power supply, an FPGA power supply, and a power supply isolation unit for each channel. The DSP power supply is converted from 5V to 3.3V and 1.9V, and the FPGA power supply is converted from 5V to 3.3V, 1.8V, and 0.85V. Each channel power supply isolation unit is composed of multiple 5V to 5V isolation units.

[0052] Figure 3 This is one of the SSPC power distribution units in a multi-channel solid-state power controller. It consists of an isolator, driver, MOSFET, microsensor, and freewheeling diode. It can support up to 32 channels, each isolated and independent. The isolator isolates and converts FPGA signals, while the driver drives the MOSFET, the core switching device in the entire design, switching the load path on and off. The microsensor uses the Hall effect principle to collect current in the circuit, which is then calculated by the FPGA. The I²t inverse delay algorithm is used to disconnect the MOSFET. The freewheeling diode provides a low-resistance path for the reverse electromotive force when the inductive load is disconnected.

[0053] Figure 4This is the MOS transistor drive circuit design, which consists of resistors R1, R2, and C. Resistors R1 and C are designed to slow down the MOS transistor and prevent excessive current from exceeding the MOS transistor's tolerance. Resistor R2 is the MOS transistor's drive resistor and is used to set the MOS transistor's turn-on time.

[0054] Figure 5 This is the PWM pulse width modulation curve for capacitive load. The capacitor is fully charged by the process of turning on and off to meet the set capacitive load.

Claims

1. A multi-channel solid-state power controller based on DSP+FPGA architecture, characterized by: Including DSP main control unit, FPGA control unit, SSPC channel unit, power supply unit, and communication interface; The DSP main control unit is used to receive control instructions from external devices and interact with the FPGA control unit through the SPI bus; The FPGA control unit is connected to the DSP main control unit via the SPI bus and is connected to all channels of the SSPC channel unit via the isolation drive circuit; The SSPC channel unit includes 32 SSPC channels, each of which includes a power switch circuit, a current detection module, a voltage detection module, and an isolation interface. The isolation interfaces of all channels are connected in parallel to the FPGA control unit. The power supply unit provides multi-channel isolated power to the DSP main control unit, FPGA control unit and each SSPC channel unit; The main control unit integrated in the DSP is used to receive external CAN bus instructions and upload channel status data.

2. The multi-channel solid-state power controller according to claim 1, wherein: The power switch circuit uses MOSFET as the core switch device, and its gate is connected to the isolation drive circuit through a slow-start drive circuit composed of resistors R1, R2 and capacitor C.

3. The multi-channel solid-state power controller according to claim 1, wherein: The FPGA control unit performs the following functions: Based on I 2 t anti-delay algorithm to achieve over-current protection; Compare the load current with the short-circuit threshold in real time to trigger short-circuit protection; PWM pulse width modulation is used to realize slow start charging of capacitive loads.

4. The multi-channel solid-state power controller according to claim 1, wherein: The power supply unit adopts a dual-redundancy design, including anti-reverse polarity diodes, fuses and energy storage circuits, and generates through multi-channel isolated DCDC modules: 5V main power supply, 3.3V / 1.9V power supply for DSP, 3.3V / 1.8V / 0.85V power supply for FPGA, and isolated 5V power supply for each SSPC channel.

5. The multi-channel solid-state power controller according to claim 1, wherein: The current detection module uses a Hall effect principle micro sensor, and the collected data is converted by ADC and then input into the FPGA control unit.

6. The multi-channel solid-state power controller according to claim 1, wherein: Each SSPC channel unit contains a freewheeling diode to provide a discharge path for the reverse electromotive force when the inductive load is disconnected.

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