PCIE-to-EMMC bridging method based on Feiteng D2000 + FPGA architecture
By using the PCIE to EMMC bridging method of Phytium D2000+FPGA architecture, the interconnection problem between Phytium 2000 series processors and EMMC memory chips was solved, enabling storage capacity expansion and compatibility, and reducing the maintenance costs and risks of aviation equipment.
Patent Information
- Application Number
- CN202511389830.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-01-09
AI Technical Summary
The Phytium 2000 series processors cannot be directly interconnected with eMMC storage chips, and existing PCIe interface SSD chips are unstable and have incompatible packaging, making it difficult to expand the storage capacity of aviation equipment and posing a risk of relying on a single supplier.
A PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture is adopted. The Phytium processor D2000 and the EMMC memory chip are read and write accessed through the FPGA. The FPGA is used to complete the bridging from the PCIE interface to the EMMC interface.
It achieves compatibility between the eMMC memory chip and the Phytium D2000 processor, reducing maintenance costs and risks, meeting the design requirements of multiple suppliers, avoiding the risks of a single supplier, and supporting a 1.8V general-purpose GPIO interface and 1X, 2X, 4X, 2.5G, and 5G adaptive.
Smart Images
Figure CN121301256A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of Phytium 2000 series processor extended storage capacity design, specifically involving a PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture. Background Technology
[0002] Currently, in the aviation field, the mainstream domestic CPUs use the domestic Phytium 2000 series processors. Such projects generally require storage capacity of GB or more to store map information, or to store status data and backup programs.
[0003] The Phytium 2000 series processors primarily use PCIe interfaces, typically employing SATA or PCIe SSDs to expand storage capacity. However, these domestically produced high-capacity storage chips are still immature, and different manufacturers use different packaging methods, resulting in the lack of a unified industry standard. This poses significant risks for their use in the aerospace field.
[0004] Currently, eMMC memory chips are consistent with foreign chips and have formed a unified industry standard. The products from different manufacturers are packaged and compatible, and can be replaced in place, which can solve the risk of using a single supplier. However, eMMC memory chips do not support PCIe interfaces, and the Phytium processor D2000 does not support eMMC interfaces, so they cannot be directly interconnected.
[0005] In the aerospace industry, 100% domestic production of all projects has become an inevitable trend. However, SSD chips supporting the PCIe interface do not currently meet the temperature range requirements of the aerospace field, and the packaging of products from different manufacturers is incompatible, making them uninterrupted and unable to achieve dual-pipeline backup, posing certain risks to the use of aerospace equipment. Domestic eMMC storage chips follow imported standards, and the packaging of products from different manufacturers is compatible, allowing for direct substitution and mitigating the risks of relying on a single supplier. However, eMMC storage chips do not support the PCIe interface, and the mainstream domestic processor, Phytium 2000, only supports the PCIe interface and cannot directly access eMMC storage chips.
[0006] Therefore, SSDs supporting the PCIe interface suffer from unstable performance and incompatible packaging among different manufacturers. For mainstream domestic processors like the Phytium 2000, direct replacement is not possible, posing a single-supplier risk to aviation equipment. While eMMC storage chips have become an industry standard with compatible packaging across different manufacturers, the Phytium D2000 processor lacks an eMMC interface. In light of this, this application is submitted. Summary of the Invention
[0007] The purpose of this application is to expand the storage capacity of Phytium 2000 series processors. Due to the unstable quality of SSDs from various manufacturers and the incompatible packaging of PCIe interfaces, this application provides a PCIe to EMMC bridging method based on the Phytium D2000+FPGA architecture to replace SSDs. The FPGA is used to complete the PCIe to EMMC interface conversion, enabling the Phytium D2000 processor to read and write to the EMMC storage chip, thus solving the incompatibility problem between the EMMC storage chip and the D2000 interface.
[0008] The technical solution of this application is:
[0009] A PCIE to EMMC bridging method based on Phytium D2000+ FPGA architecture, including bridging connection steps and bridging operation steps;
[0010] The bridging connection steps are as follows:
[0011] Connects the Phytium D2000 processor to the FPGA, and connects the FPGA to the EMMC memory chip;
[0012] The Phytium processor D2000 connects to the FPGA's PCIe IP core via the PCIe interface. A reset signal line RST_n is set between the Phytium processor D2000 and the FPGA, which is connected via the GPIO interface.
[0013] A reset signal line RST_n, a clock signal line CLK, a control signal CMD, and a data bus DATA[0-7] are set between the FPGA and the EMMC memory chip and connected through the GPIO interface.
[0014] The Phytium processor D2000 is responsible for FPGA enumeration and reading / writing access to the EMMC memory chip. The EMMC memory chip is the object being read and written, used to expand the storage capacity of the Phytium processor D2000.
[0015] The FPGA can control the reset of the Phytium processor D2000 and the EMMC memory chip, and is responsible for the power-on initialization of the EMMC memory chip, realizing the bridging of the PCIe to EMMC interface.
[0016] The bridging operation steps include:
[0017] Step 1: Power on the Phytium processor D2000, FPGA, and EMMC memory chip;
[0018] Step 2: After the FPGA is loaded, keep the Phytium processor D2000 reset;
[0019] Step 3: Reset the EMMC memory chip using the FPGA and initialize the EMMC memory chip.
[0020] Step 4: Determine if the eMMC memory chip initialization was successful;
[0021] If unsuccessful, the EMMC memory chip will be reset and initialized again using the FPGA;
[0022] If successful, the FPGA maps the address space of the EMMC memory chip to the function register space of the PCIe IP core via the AXI bus.
[0023] Step 5: Release the reset of the Phytium processor D2000 from the FPGA;
[0024] Step 6: After the Phytium processor D2000 loads the program, it performs a PCIE enumeration operation to allocate address space for the FPGA-side device.
[0025] If the enumeration operation fails, the Phytium processor D2000 is reset using the FPGA, and the reset of the Phytium processor D2000 is released again to perform the PCIE enumeration operation.
[0026] According to at least one embodiment of this application, in the above-described PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture, the FPGA supports providing a 1.8V general-purpose GPIO interface.
[0027] According to at least one embodiment of this application, in the above-described PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture, the PCIE interface supports 1X, 2X, 4X, 2.5G, and 5G adaptive switching.
[0028] According to at least one embodiment of this application, in the above-described PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture, in step three of the bridging operation steps, when the FPGA initializes the EMMC memory chip, address allocation and data bit width mode selection are completed.
[0029] According to at least one embodiment of this application, in the above-described PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture, in step three of the bridging operation steps, when the FPGA initializes the EMMC memory chip, the CLK clock frequency cannot exceed 400kHz.
[0030] According to at least one embodiment of this application, in the above-described PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture, in step three of the bridging operation steps, when the FPGA initializes the EMMC memory chip, the CLK clock frequency is set to 200kHz.
[0031] According to at least one embodiment of this application, in the above-described PCIE to EMMC bridging method based on Phytium D2000+FPGA architecture, in step three of the bridging operation steps, when the FPGA initializes the EMMC memory chip, the EMMC memory chip needs to return a response each time the FPGA sends a control command before the next control command can be issued.
[0032] This application has at least the following beneficial technical effects:
[0033] This paper presents a PCIe to EMMC bridging method based on the Phytium D2000+FPGA architecture. The design uses a unified standard EMMC memory chip to replace the memory chips with incompatible PCIe interfaces from various manufacturers, avoiding the risk of relying on a single supplier. The FPGA completes the PCIe interface to EMMC interface conversion, enabling the Phytium processor D2000 to read and write to the EMMC memory chip. This solves the incompatibility problem between the EMMC memory chip and the D2000 interface, meets the design requirements of multiple component suppliers, and can significantly reduce maintenance costs and risks. Attached Figure Description
[0034] Figure 1 This application provides a PCIe converter based on Phytium D2000+FPGA. A schematic diagram of the connection relationship in the EMMC bridging method;
[0035] Figure 2 This application provides a PCIe converter based on Phytium D2000+FPGA. A flowchart of the EMMC bridging method operation.
[0036] To better illustrate this embodiment, some content in the accompanying drawings may be omitted, enlarged, or reduced. They are for illustrative purposes only and should not be construed as limiting the scope of this application. Detailed Implementation
[0037] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, and other related parts can be referred to the general design.
[0038] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The word "comprising" as used in this application description indicates that the concept preceding the word encompasses the concepts listed following the word and their equivalents, without excluding other related concepts.
[0039] The FPGA chip supports the high-speed PCIe interface and the general GPIO interface. Most Phytium processor D2000 boards have FPGAs. The FPGA is used to bridge the PCIe interface to the eMMC chip, which solves the incompatibility problem between the eMMC storage chip and the Phytium processor D2000 PCIe interface. Since the eMMC products from different manufacturers are packaged compatiblely, it can well meet the dual pipeline design requirements of domestic boards and effectively reduce the risk of relying on a single supplier for PCIe interface SSD chips. Based on this, this application provides a PCIe to eMMC bridging method based on the Phytium D2000+FPGA architecture.
[0040] Bridging connection steps, such as Figure 1 As shown.
[0041] Connect the Phytium D2000 processor to the FPGA, and connect the FPGA to the EMMC memory chip.
[0042] The Phytium processor D2000 connects to the FPGA's PCIe IP core via a PCIe interface. A reset signal line RST_n is set between the Phytium processor D2000 and the FPGA, which is connected via a GPIO interface.
[0043] The FPGA and the EMMC memory chip are connected via a reset signal line RST_n, a clock signal line CLK, a control signal CMD, and a data bus DATA[0-7], which are connected through a GPIO interface.
[0044] The Phytium processor D2000 is responsible for FPGA enumeration and reading / writing access to the EMMC memory chip. The EMMC memory chip is the object being read and written, used to expand the storage capacity of the Phytium processor D2000.
[0045] The FPGA supports PCIe interface and internal AXI bus, and can provide a 1.8V general GPIO interface. It can control the reset of Phytium processor D2000 and EMMC memory chip, and is responsible for the power-on initialization of EMMC memory chip, realizing the bridging of PCIe to EMMC interface.
[0046] The PCIe interface supports 1X, 2X, 4X, 2.5G, and 5G adaptive speeds.
[0047] Bridging operation steps, such as Figure 2 As shown:
[0048] Step 1: Power on the Phytium processor D2000, FPGA, and EMMC memory chip.
[0049] Step 2: After the FPGA is loaded, keep the Phytium processor D2000 reset.
[0050] Step 3: Reset the EMMC memory chip using the FPGA and initialize the EMMC memory chip.
[0051] The initialization process requires address allocation, data bit width mode selection, and other operations.
[0052] During initialization, the CLK clock frequency cannot exceed 400kHz, but can be set to 200kHz.
[0053] During initialization, each time the FPGA sends a control command, it needs the EMMC memory chip to return a response before it can send the next control command.
[0054] Step 4: Determine whether the EMMC memory chip initialization was successful.
[0055] If unsuccessful, the FPGA will be used to reset and initialize the EMMC memory chip.
[0056] If successful, the FPGA maps the address space of the EMMC memory chip to the function register space of the PCIe IP core via the AXI bus.
[0057] Step 5: Release the reset of the Phytium processor D2000 on the FPGA.
[0058] Step 6: After the Phytium processor D2000 loads the program, it performs a PCIE enumeration operation to allocate address space for the FPGA-side device.
[0059] If the enumeration is successful, it means that the FPGA has completed the PCIe to eMMC interface operation, and the Phytium processor D2000 can read and write the eMMC memory chip. If it is unsuccessful, the FPGA will reset the Phytium processor D2000 and release the reset of the Phytium processor D2000 to perform the PCIe enumeration operation.
[0060] Since the Phytium D2000 processor only has a PCIe interface, and the packaging of domestically produced PCIe SSDs from different manufacturers is incompatible, once a product is selected, if chip quality issues or discontinuation occur, other manufacturers' products cannot be used for on-site replacement unless the printed circuit board is modified. The resulting costs and risks are incalculable. Considering that the packaging of eMMC memory chips from various manufacturers is currently compatible, on-site replacement is possible, thus avoiding the risks associated with a single supplier. Even if eMMC memory chip quality issues or discontinuation occur later, products from other manufacturers can be used for on-site replacement without modifying the printed circuit board. This greatly improves the security of the product's component source, reduces maintenance burden, and lowers risks. The PCIe to eMMC bridging method based on the Phytium D2000+FPGA architecture disclosed in the above embodiments uses a unified standard eMMC memory chip to replace the memory chips with incompatible packaging of PCIe interfaces from different manufacturers, avoiding the risks of a single supplier. The FPGA completes the PCIe interface to eMMC interface conversion, meeting the design requirements of multiple component suppliers and significantly reducing maintenance costs and risks.
[0061] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.
Claims
1. A PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture, characterized in that, This includes bridging connection steps and bridging operation steps; The bridging connection steps are as follows: Connects the Phytium D2000 processor to the FPGA, and connects the FPGA to the EMMC memory chip; The Phytium processor D2000 connects to the FPGA's PCIe IP core via the PCIe interface. A reset signal line RST_n is set between the Phytium processor D2000 and the FPGA, which is connected via the GPIO interface. A reset signal line RST_n, a clock signal line CLK, a control signal CMD, and a data bus DATA[0-7] are set between the FPGA and the EMMC memory chip and connected through the GPIO interface. The Phytium processor D2000 is responsible for FPGA enumeration and reading / writing access to the EMMC memory chip. The EMMC memory chip is the object being read and written, used to expand the storage capacity of the Phytium processor D2000. The FPGA can control the reset of the Phytium processor D2000 and the EMMC memory chip, and is responsible for the power-on initialization of the EMMC memory chip, realizing the bridging of the PCIe to EMMC interface. The bridging operation steps include: Step 1: Power on the Phytium processor D2000, FPGA, and EMMC memory chip; Step 2: After the FPGA is loaded, keep the Phytium processor D2000 reset; Step 3: Reset and initialize the EMMC memory chip using the FPGA; Step 4: Determine if the eMMC memory chip initialization was successful; If unsuccessful, the EMMC memory chip will be reset and initialized again using the FPGA; If successful, the FPGA maps the address space of the EMMC memory chip to the function register space of the PCIe IP core via the AXI bus. Step 5: Release the reset of the Phytium processor D2000 from the FPGA; Step 6: After the Phytium processor D2000 loads the program, it performs a PCIE enumeration operation to allocate address space for the FPGA-side device. If the enumeration operation fails, the Phytium processor D2000 is reset using the FPGA, and the reset of the Phytium processor D2000 is released again to perform the PCIE enumeration operation.
2. The PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture according to claim 1, characterized in that, The FPGA supports providing a general-purpose GPIO interface at 1.8V.
3. The PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture according to claim 1, characterized in that, The PCIe interface supports 1X, 2X, 4X, 2.5G, and 5G adaptive speeds.
4. The PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture according to claim 3, characterized in that, In step three of the bridging operation, when the FPGA initializes the EMMC memory chip, address allocation and data bit width mode selection are completed.
5. The PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture according to claim 4, characterized in that, In step three of the bridging operation, when initializing the EMMC memory chip with the FPGA, the CLK clock frequency cannot exceed 400kHz.
6. The PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture according to claim 5, characterized in that, In step three of the bridging operation, when initializing the EMMC memory chip with the FPGA, the CLK clock frequency is set to 200kHz.
7. The PCIe to eMMC bridging method based on Phytium D2000+FPGA architecture according to claim 5, characterized in that, In step three of the bridging operation, when the FPGA initializes the EMMC memory chip, the FPGA needs the EMMC memory chip to return a response each time it sends a control command before it can send the next control command.