A method and device for parsing and drawing an FPGA chip model
By reverse-engineering the chip and circuit design information of FPGA chip models, generating structure, layout and wiring diagrams, this solves the problems of complex modeling languages and high costs of commercial EDA tools in existing technologies, and realizes the visualization of FPGA chip models and the needs of academic research.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2022-05-12
- Publication Date
- 2026-05-12
AI Technical Summary
Existing FPGA chip modeling languages are obscure and difficult to understand, requiring a high level of professional knowledge to read. Commercial chip models are cumbersome and cannot meet the needs of academic research. Furthermore, commercial EDA tools are expensive to use and have version limitations.
This paper provides a method for analyzing and drawing FPGA chip models. By reverse analyzing chip and circuit design information, it generates chip structure, layout and wiring diagrams, and uses chip structure drawing, layout drawing and wiring drawing algorithms to achieve visualization.
It enables the visualization of FPGA chip models, meets the needs of academic research, reduces reliance on professional knowledge, and reduces the cost of using commercial EDA tools.
Smart Images
Figure CN117094262B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of FPGA architecture design and electronic design automation technology, specifically relating to a method and apparatus for analyzing and drawing FPGA chip models. Background Technology
[0002] FPGAs are currently widely used in civilian digital fields such as mobile phones, communication equipment, automobiles, and home appliances, as well as in weapon systems such as ships, missiles, and fighter jets. Their application scope continues to expand, making them a critical infrastructure related to national defense security. In recent years, with the development of semiconductor manufacturing processes, the number of logic cells in FPGA chips has exceeded ten million, supporting ultra-large-scale complex circuit designs. The most advanced devices now contain billions of transistors and countless features. This exponential growth and feature evolution has brought profound challenges to the functional architecture of devices, posing new challenges to the dedicated EDA tools required for FPGA device design.
[0003] Currently, software such as ISE and Vivado are the primary choices for designers. However, these software programs have strong confidentiality requirements, different versions of EDA tools can only support certain series of FPGA chips, and using EDA tools requires regular and expensive payments.
[0004] Chip modeling languages, as a method for abstracting and describing chips, have been widely used in academic EDA software such as VTR and Yosys+nextpnr. Chip modeling languages are based on Extensible Markup Language (XML) and consist of closed, hierarchical modeling tags. These tags add additional information through custom attributes. Structured modeling methods utilize XML to construct a model standard, a set of modeling tags, and modeling constraints, offering high scalability and flexibility.
[0005] However, chip modeling languages are obscure and difficult to understand, requiring researchers to have extremely high levels of expertise and a huge workload to read chip models. Moreover, current academic FPGA research is based on chip models described using structured modeling languages, while the abstract description methods make commercial chip models too cumbersome and unable to meet the needs of academic researchers. Summary of the Invention
[0006] To address the aforementioned problems in the existing technology, this invention provides a method and apparatus for analyzing and drawing FPGA chip models. The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] This invention provides a method for analytical drawing of FPGA chip models, including:
[0008] S1: Obtain chip and circuit design information;
[0009] S2: Based on the chip and circuit design information, reverse analyze to obtain the FPGA chip structure data, and draw a diagram based on the chip structure data to obtain the FPGA structure diagram;
[0010] S3: Based on the chip and circuit design information, reverse analyze to obtain the network data and circuit layout data of the FPGA, and draw on the structure diagram based on the network data and the circuit layout data to obtain the layout diagram of the FPGA and the interconnection diagram of the circuit layout;
[0011] S4: Based on the chip and circuit design information, reverse analyze to obtain the circuit routing data of the FPGA, and draw on the layout diagram based on the circuit routing data to obtain the routing diagram of the FPGA.
[0012] In one embodiment of the present invention, the chip and circuit design information includes a chip description file, a packaged netlist file, a circuit layout file, and a circuit routing file.
[0013] In one embodiment of the present invention, S2 includes:
[0014] S21: Based on the chip description file, reverse-engineer the FPGA chip structure data and convert it into a grid array with s_block as its element.
[0015] Each element in the grid array corresponds to a physical unit information, which includes the name, type, location distribution, pin type, and number of pins of the physical unit.
[0016] S22: Traverse the grid array, parse the coordinates of each physical unit and draw the boundary of the physical unit, fill in the corresponding color and text description according to the type of the physical unit, and obtain the structure diagram of the FPGA.
[0017] In one embodiment of the present invention, in step S22, if there are sub-units in the physical unit, then all sub-units of the physical unit are traversed, the coordinates of each sub-unit are resolved, and the boundary of the sub-unit is drawn inside the physical unit.
[0018] In one embodiment of the present invention, S3 includes:
[0019] S31: Based on the packaged netlist file, reverse-parse to obtain the FPGA network data, and convert the network data into a clb_nets array with s_net structures as elements.
[0020] Each element in the clb_nets array corresponds to a network information, which includes the total number of networks, physical unit locations, interconnection relationships, and physical unit occupancy rate.
[0021] S32: Based on the circuit layout file, reverse-engineer the FPGA circuit layout data and convert it into a blocks array with s_block structures as elements.
[0022] Each element in the blocks array corresponds to an occupied physical unit information, which includes the coordinates of the occupied physical unit, its network, input node, and output node.
[0023] S33: Update the occupancy information of physical units in the grid array according to the clb_nets array and the blocks array;
[0024] S34: Based on the updated grid array and the clb_nets array, mark all occupied physical units in the structure diagram to obtain the layout diagram of the FPGA, and draw the connection between the SOURCE node and SINK node corresponding to each network to obtain the interconnection diagram of the circuit layout.
[0025] In one embodiment of the present invention, S4 includes:
[0026] S41: Based on the circuit routing file, reverse analyze to obtain the circuit routing data of the FPGA, and convert the circuit routing data into a trace_head array with route_node structures as elements.
[0027] Each element in the trace_head array corresponds to a wiring network information, which includes the SOURCE node, SINK node, wiring resource node, and wiring driver relationship of the wiring network.
[0028] S42: Traverse the trace_head array, read the SOURCE node of each routing network, and draw the routing relationship of each routing network from the SOURCE node downwards in a chain structure on the layout diagram to obtain the routing diagram of the FPGA.
[0029] This invention provides a device for analyzing and drawing FPGA chip models, comprising:
[0030] Chip information acquisition module, used to acquire chip and circuit design information;
[0031] The chip structure drawing module is used to reverse analyze the chip structure data of the FPGA based on the chip and circuit design information, and to draw the structure diagram of the FPGA based on the chip structure data.
[0032] The layout drawing module is used to reverse analyze the network data and circuit layout data of the FPGA based on the chip and circuit design information, and to draw on the structure diagram based on the network data and the circuit layout data to obtain the layout diagram of the FPGA and the interconnection relationship diagram of the circuit layout.
[0033] The wiring diagram module is used to reverse analyze the circuit wiring data of the FPGA based on the chip and circuit design information, and draw the wiring diagram of the FPGA on the layout diagram based on the circuit wiring data.
[0034] This invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein...
[0035] The processor, communication interface, and memory communicate with each other through a communication bus;
[0036] Memory, used to store computer programs;
[0037] When a processor executes a program stored in memory, it implements the steps of the method described in any of the above embodiments.
[0038] The present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method described in any of the above embodiments.
[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0040] The analytical drawing method for FPGA chip models of the present invention utilizes resource analysis at different stages to complete data analysis, and uses three effective drawing algorithms to complete the visualization of chip structure, circuit layout and circuit routing stages, thus meeting the needs of the academic community for commercial FPGA architecture design and EDA algorithm research.
[0041] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0042] Figure 1This is a schematic diagram of an analytical drawing method for an FPGA chip model provided in an embodiment of the present invention;
[0043] Figure 2 This is a logical relationship diagram of drawing logic provided in an embodiment of the present invention;
[0044] Figure 3 This is a schematic diagram of an FPGA chip model analysis and drawing device provided in an embodiment of the present invention. Detailed Implementation
[0045] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a method and apparatus for analyzing and drawing FPGA chip models according to the present invention.
[0046] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0047] Example 1
[0048] In this embodiment, chip analysis and drawing refers to the process during the operation of FPGA EDA software. The chip model and circuit description file have been imported as input to the EDA software. The EDA software has already obtained the chip and circuit design information. The analysis and drawing software uses the existing data to complete the visualization work such as chip structure, cell layout, cell connection, layout occupancy, and wiring interconnection relationship. This guides FPGA architecture design and EDA algorithm research, avoiding the problem of mismatch between design and expected requirements in the early stage of design.
[0049] Please see Figure 1 , Figure 1 This is a schematic diagram of an analytical drawing method for an FPGA chip model provided in an embodiment of the present invention. As shown in the figure, the analytical drawing method for an FPGA chip model in this embodiment is characterized by including:
[0050] S1: Obtain chip and circuit design information;
[0051] In this embodiment, the chip and circuit design information includes chip description files, packaged netlist files, circuit layout files, and circuit routing files. In addition, the chip and circuit design information also includes other basic information such as circuit structure, behavioral synthesis netlist, and process-mapped netlist.
[0052] S2: Based on the chip and circuit design information, reverse analyze to obtain the FPGA chip structure data, and draw the FPGA structure diagram based on the chip structure data;
[0053] Specifically, S2 includes:
[0054] S21: Based on the chip description file, reverse analyze to obtain the FPGA chip structure data, and convert the chip structure data into a grid array with s_block as the element;
[0055] In this embodiment, the input .xml format chip description file is reverse-parsed to obtain the FPGA chip structure data. The FPGA chip structure data includes attributes such as the current FPGA chip size, functional primitives, spatial domain, interconnect resources, switch box, cell type, cell distribution, and pin distribution.
[0056] Each element in the grid array corresponds to a physical unit information, which includes the name, type, location distribution, pin type, and number of pins of the physical unit.
[0057] S22: Traverse the grid array, parse the coordinates of each physical unit and draw the boundary of the physical unit. Fill in the corresponding color and text description according to the type of physical unit to obtain the structure diagram of the FPGA.
[0058] In this embodiment, the obtained FPGA chip structure data is visualized using a chip structure drawing algorithm.
[0059] Specifically, S22 includes the following steps:
[0060] Step 1): Set the drawing configuration properties, which include setting the drawing font, font size, line style, line width, and fill color corresponding to the physical unit type.
[0061] Step 2): Traverse the grid array and call the chip structure drawing algorithm;
[0062] It should be noted that when traversing the grid array, empty areas, chip corners, blank cells, and cells whose current coordinates are not the starting physical cell are ignored.
[0063] Step 3): Parse the coordinates of each physical unit, draw its unit boundary, and fill in the corresponding colors and text descriptions according to the physical unit type to obtain the FPGA structure diagram.
[0064] The physical unit types include IOB, CLB, DSP, RAM, etc.
[0065] In this embodiment, the position of each element in the grid array represents the coordinates of its corresponding physical unit.
[0066] Specifically, in this embodiment, the diagonal coordinates of the physical unit are first calculated based on the grid[i][j] index and the order of the physical units. Then, the set_color and set_line_style methods in the drawing method library are used to bind colors and set line styles for the physical units. Subsequently, the draw_rectangle and fill_rectangle methods are used to draw rectangular or polygonal areas according to the diagonal coordinates of the physical units and fill the areas with color. When zooming in and out of the main window view, if the horizontal width of a single physical block is greater than the font length of the physical block name in the current view, the unit name is marked using draw_text.
[0067] Furthermore, in S22, if there are sub-units in a physical unit, then all sub-units of the physical unit are traversed, the coordinates of each sub-unit are resolved, and the sub-unit boundary is drawn inside the physical unit.
[0068] Specifically, the coordinate analysis and drawing methods are similar to the drawing methods of physical units. Optionally, the draw_child method can be called to draw the sub-units composed inside the physical unit.
[0069] It should be noted that in this embodiment, during the execution of the chip structure drawing algorithm, an event listening loop is started. The event listening loop can continuously listen for user operation events, such as mouse clicks, button clicks, and mouse wheel scrolling, during the algorithm's execution.
[0070] S3: Based on the chip and circuit design information, reverse analyze to obtain the FPGA network data and circuit layout data, and draw on the structure diagram based on the network data and circuit layout data to obtain the FPGA layout diagram.
[0071] Specifically, S3 includes:
[0072] S31: Based on the packaged netlist file, reverse-parse to obtain the FPGA network data, and convert the network data into a clb_nets array with s_net structures as elements;
[0073] In this embodiment, the input packaged .NET format circuit netlist file is reverse-parsed to obtain the FPGA network data. The FPGA network data includes attributes such as the number of networks after circuit packaging, network structure, physical unit composition of each network, physical unit distribution of each network, and configuration functions.
[0074] Each element in the clb_nets array corresponds to a network information, which includes the total number of networks, physical unit locations, interconnection relationships, and physical unit occupancy rate.
[0075] S32: Based on the circuit layout file, reverse analyze to obtain the FPGA circuit layout data, and convert the circuit layout data into a blocks array with s_block structure as elements;
[0076] In this embodiment, the input packaged .place format circuit layout file is reverse-parsed to obtain the FPGA circuit layout data. The FPGA circuit layout data includes attributes such as: the occupancy of each physical unit after circuit layout, the distribution of occupied physical units, the composition of physical units in each network, the distribution of physical units in each network, configuration functions, interconnection relationships of occupied physical units, and interconnection data.
[0077] Each element in the blocks array corresponds to an occupied physical unit information, which includes the coordinates of the occupied physical unit, its network, input node, and output node.
[0078] S33: Update the occupancy information of physical units in the grid array based on the clb_nets array and the blocks array;
[0079] In this embodiment, the occupancy information includes attributes such as whether the physical unit is occupied and the occupancy ratio.
[0080] Specifically, S33 includes:
[0081] The circuit layout data is read in a loop, with one logic cell read in each loop. The name, coordinates, sub-cell coordinates, clock region, and number of the current physical cell are recorded. Then, all functional cells block_list obtained from the netlist are traversed. The name attribute of the current block cell is used to find the matching functional cell. The coordinate information in the circuit layout data is then filled into the blocks array with s_block structures as elements. The types and number of physical cells occupied after the circuit layout are counted to obtain all occupied physical cells after the circuit layout. Finally, the occupancy information of the physical cell coordinates in the chip structure grid array is updated according to the coordinate information of the occupied physical cells.
[0082] In this embodiment, all network structures are obtained at the netlist parsing node, and each network stores all the unit information of the current network. However, the units are not laid out at this time. block_list can be understood as the set of all internal units of the network obtained by parsing the netlist.
[0083] S34: Based on the updated grid array and clb_nets array, mark all occupied physical units in the structure diagram to obtain the FPGA layout diagram, and draw the connection between the SOURCE node and SINK node corresponding to each network to obtain the interconnection diagram of the circuit layout.
[0084] In this embodiment, the network structure data and circuit layout data of the FPGA obtained by parsing are visualized on the FPGA structure diagram using layout drawing algorithms and layout interconnection drawing algorithms.
[0085] Specifically, S34 includes the following steps:
[0086] Step 1): Obtain the FPGA structure diagram and locate the chip boundary vertices;
[0087] Step 2): After locating the boundary, calculate the coordinate information of each unit inside the chip body;
[0088] Step 3): Traverse the updated grid array and call the layout drawing algorithm:
[0089] It should be noted that when traversing the grid array, cells that are not occupied physical cells and cells whose current coordinates are not the starting physical cell are ignored.
[0090] Step 4): Modify the marker color of the occupied physical units according to the type of physical unit, and change the line style of the physical units to solid lines to obtain the FPGA layout diagram;
[0091] In this embodiment, optionally, the set_color method is used to mark all occupied physical units.
[0092] It should be noted that if the name of a physical unit occupies more than or equal to 3 / 4 of the width of the physical unit, the actual name of the physical unit will be displayed at the center of the physical unit. If a physical unit contains sub-units, such as SLICE, the internal structure of the physical unit will be displayed.
[0093] Step 5): Traverse the clb_nets array and call the layout interconnection drawing algorithm;
[0094] It should be noted that when traversing the clb_nets array, the global network is ignored. The global network is a logical network and is not actually wired, so it cannot be plotted.
[0095] Step 6): Obtain the SOURCE node of the current network and calculate the center coordinates of the SOURCE node.
[0096] Step 7): Traverse all SINK nodes in the current network and draw a solid black line from the center coordinates of the SOURCE node to the center of all SINK nodes to obtain the interconnection diagram of the circuit layout.
[0097] The SOURCE node is the starting point of the network connection, and the SINK node is the ending point of the network connection. A network consists of one starting point and several ending points. Generally, the starting point and ending point of the network connection are the input node and output node of the physical unit.
[0098] In this embodiment, optionally, the draw_line method is used to draw a black straight line connecting the SOURCE node to the SINK node corresponding to the network.
[0099] S4: Based on the chip and circuit design information, reverse analyze to obtain the FPGA circuit routing data, and draw on the layout diagram according to the circuit routing data to obtain the FPGA routing diagram.
[0100] Specifically, S4 includes:
[0101] S41: Based on the circuit routing file, reverse analyze to obtain the FPGA circuit routing data, and convert the circuit routing data into a trace_head array with route_node structure as its element;
[0102] In this embodiment, the input .route format circuit routing file is reverse-parsed to obtain the FPGA circuit routing data. The FPGA circuit routing data includes attributes such as the network distribution after circuit routing, the number of networks, network source nodes, network sink nodes, routing resource nodes, and routing driver relationships.
[0103] Each element in the trace_head array corresponds to a routing network information, which includes the SOURCE node, SINK node, routing resource node, and routing driver relationship of the routing network.
[0104] S42: Traverse the trace_head array, read the SOURCE node of each routing network, and draw the routing relationship of each routing network from the SOURCE node downwards in a chain structure on the layout diagram to obtain the FPGA routing diagram.
[0105] In this embodiment, the circuit routing data of the FPGA obtained by parsing is visualized on the FPGA layout using a routing drawing algorithm.
[0106] Specifically, S42 includes the following steps:
[0107] Step 1): Initialize the recursive nodes and the linked recursive structure;
[0108] Step 2): Traverse the trace_head array, obtain the SOURCE node of the current network and assign it to the recursion starting point;
[0109] It should be noted that when traversing the trace_head array, the global network and unwired networks are ignored.
[0110] Step 3): Use the cabling resource map to query cabling resource node information;
[0111] In this embodiment, the wiring resource diagram is an external resource, which is obtained by reading the external file when parsing the circuit wiring file. The wiring resource diagram stores information about each connection resource on the chip.
[0112] Step 4): Traverse all nodes in the current SOURCE node driver chain, and draw the wiring relationship from the SOURCE node downwards in a chain structure according to different types of drawing logic to obtain the FPGA wiring diagram.
[0113] In this embodiment, the drawing logic is categorized into SOURCE, SINK, OPIN, IPIN, CHANX, and CHANNY based on type.
[0114] like Figure 2 The diagram shown illustrates the logic of drawing different types of nodes, illustrating the core logic for drawing different types of nodes. Specifically, SOURCE and SINK types are drawn directly. Figure 2 The drawing logic for OPIN, IPIN, CHANX, and CHANNY types is described in detail.
[0115] Specifically, the OPIN type represents the physical unit output pin, and the node and pin distribution are drawn by calling the draw_rr_pin method of the drawing method library.
[0116] The IPIN type represents the physical unit input pin. After drawing the node and pin distribution by calling draw_rr_pin, it is necessary to determine whether the predecessor node is of type OPIN. If it is, the draw_pin_to_pin_edge method is called to draw the interconnect between the predecessor node and the current node; otherwise, it means that the predecessor node is an interconnect node in the routing channel, and the draw_pin_to_chan_edge method is called to draw the interconnect relationship between the current node and the routing channel resource.
[0117] The CHANX type represents a horizontal routing channel resource. First, the draw_rr_chanx method is called to draw the routing channel connection resource. Then, the predecessor node type is determined, and the three methods draw_chanx_to_chanx_edge, draw_pin_chan_edge, and draw_chanx_to_chany_edge in the drawing method library are called according to the predecessor node type to draw the connection information.
[0118] The CHANY type represents vertical routing channel resources. The drawing logic is consistent with the CHANX logic. That is, first, the draw_rr_chanx method is called to draw the routing channel connection resources, then the predecessor node type is determined, and the three methods draw_chanx_to_chanx_edge, draw_pin_chan_edge, and draw_chanx_to_chany_edge in the drawing method library are called according to the predecessor node type to draw the connection information.
[0119] The FPGA chip model analysis and drawing method in this embodiment utilizes resource analysis at different stages to complete data analysis, and uses three effective drawing algorithms to complete the visualization of chip structure, circuit layout and circuit routing stages, thus meeting the academic community's needs for commercial FPGA architecture design and EDA algorithm research.
[0120] Example 2
[0121] This embodiment provides an analytical drawing apparatus for FPGA chip models, implementing the analytical drawing method for FPGA chip models described in Embodiment 1 above. Please refer to [link to previous document]. Figure 3 , Figure 3 yes Figure 3 This is a schematic diagram of an FPGA chip model parsing and drawing device provided in an embodiment of the present invention. As shown in the figure, the FPGA chip model parsing and drawing device of this embodiment includes: an information acquisition module, a chip structure drawing module, a layout drawing module, and a routing drawing module, wherein...
[0122] The information acquisition module is used to acquire chip and circuit design information;
[0123] In this embodiment, the chip and circuit design information includes chip description files, packaged netlist files, circuit layout files, and circuit routing files;
[0124] The chip structure drawing module is used to reverse analyze the chip structure data of the FPGA based on the chip and circuit design information, and to draw the structure diagram of the FPGA based on the chip structure data.
[0125] The layout drawing module is used to reverse analyze the FPGA network data and circuit layout data based on the chip and circuit design information, and draw on the structure diagram based on the network data and circuit layout data to obtain the FPGA layout diagram and the interconnection relationship diagram of the circuit layout.
[0126] The wiring diagram module is used to reverse analyze the FPGA circuit wiring data based on the chip and circuit design information, and draw the wiring diagram on the layout diagram based on the circuit wiring data to obtain the FPGA wiring diagram.
[0127] Specifically, the chip structure drawing module includes: a chip analysis unit and a chip drawing unit, wherein,
[0128] The chip parsing unit is used to reverse parse the chip description file to obtain the chip structure data of the FPGA, and convert the chip structure data into a grid array with s_block as the element;
[0129] Each element in the grid array corresponds to a physical unit information, which includes the name, type, location distribution, pin type, and number of pins of the physical unit.
[0130] The chip drawing unit is used to traverse the grid array, parse the coordinates of each physical unit and draw the boundaries of the physical units, and fill in the corresponding colors and text descriptions according to the type of physical unit to obtain the structure diagram of the FPGA.
[0131] Furthermore, the layout drawing module includes: a network parsing unit, a layout parsing unit, and a layout drawing unit, wherein,
[0132] The network parsing unit is used to reverse parse the FPGA network data based on the packaged netlist file, and convert the network data into a clb_nets array with s_net structures as elements;
[0133] Each element in the clb_nets array corresponds to a network information, which includes the total number of networks, physical unit locations, interconnection relationships, and physical unit occupancy rate.
[0134] The layout parsing unit reverse-parses the circuit layout file to obtain the FPGA circuit layout data, and converts the circuit layout data into a blocks array with s_block structure as its elements;
[0135] Each element in the blocks array corresponds to an occupied physical unit information, which includes the coordinates of the occupied physical unit, its network, input node, and output node.
[0136] The layout drawing unit is used to update the occupancy information of physical units in the grid array according to the clb_nets array and the blocks array. Based on the updated grid array and clb_nets array, it marks all occupied physical units in the structure diagram to obtain the FPGA layout diagram. It also draws the connection between the SOURCE node and SINK node corresponding to each network to obtain the interconnection diagram of the circuit layout.
[0137] Furthermore, the wiring drawing module includes: a wiring parsing unit and a wiring drawing unit, wherein,
[0138] The routing parsing unit is used to reverse parse the FPGA's circuit routing data based on the circuit routing file, and convert the circuit routing data into a trace_head array with route_node structure as its element;
[0139] Each element in the trace_head array corresponds to a routing network information, which includes the SOURCE node, SINK node, routing resource node, and routing driver relationship of the routing network.
[0140] The routing drawing unit is used to traverse the trace_head array, read the SOURCE node of each routing network, and draw the routing relationship of each routing network from the SOURCE node downwards in a chain structure on the layout diagram to obtain the FPGA routing diagram.
[0141] It should be noted that in this embodiment, the chip and circuit design information is generated by VTR software. By reading the comprehensive netlist, packaged netlist, circuit layout and circuit routing files generated by VTR software, the internal data of different files is parsed and stored in the corresponding structure.
[0142] In this embodiment, after reading the data parsed by the chip parsing unit, network parsing unit, layout parsing unit, and routing parsing unit, the drawing process at different stages is completed in sequence using a self-built drawing interface library.
[0143] Furthermore, this embodiment also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; when the processor executes the program stored in the memory, it implements the method steps of the FPGA chip model analysis and drawing method described in Embodiment 1 above.
[0144] The electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.
[0145] The communication bus mentioned in the aforementioned electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not indicate that there is only one bus or one type of bus. The communication interface is used for communication between the aforementioned electronic device and other devices. The memory can include Random Access Memory (RAM), or Non-Volatile Memory (NVM), such as at least one disk storage device. Optionally, the memory can also be at least one storage device located remotely from the aforementioned processor.
[0146] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0147] Furthermore, this embodiment also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method steps of the analytical drawing method for the FPGA chip model described in Embodiment 1.
[0148] It should be noted that the descriptions of the apparatus, electronic device, and storage medium embodiments are relatively simple because they are basically similar to the method embodiments. For relevant details, please refer to the descriptions in the method embodiments. The apparatus, electronic device, and storage medium in these embodiments are respectively apparatus, electronic device, and storage medium applying the above-described analytical drawing method for FPGA chip models. Therefore, all embodiments of the above-described analytical drawing method for FPGA chip models are applicable to the apparatus, electronic device, and storage medium, and can achieve the same or similar beneficial effects.
[0149] It should be noted that, in this document, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.
[0150] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for analytical drawing of an FPGA chip model, characterized in that, include: S1: Obtain chip and circuit design information; the chip and circuit design information includes chip description files, packaged netlist files, circuit layout files, and circuit routing files; S2: Based on the chip and circuit design information, reverse engineer the FPGA chip structure data, and draw the FPGA structure diagram based on the chip structure data; S2 includes: S21: Based on the chip description file, reverse analyze to obtain the FPGA chip structure data, and convert the chip structure data into a grid array with s_block as the element. Each element in the grid array corresponds to a physical unit information, which includes the name, type, location distribution, pin type, and number of pins of the physical unit. S22: Traverse the grid array, parse the coordinates of each physical unit and draw the boundary of the physical unit, fill in the corresponding color and text description according to the type of the physical unit, and obtain the structure diagram of the FPGA; S3: Based on the chip and circuit design information, reverse engineer the network data and circuit layout data of the FPGA, and draw the diagram on the structure diagram based on the network data and circuit layout data to obtain the layout diagram of the FPGA and the interconnection diagram of the circuit layout; S3 includes: S31: Based on the packaged netlist file, reverse parse to obtain the FPGA network data, and convert the network data into a clb_nets array with s_net structures as elements. Each element in the clb_nets array corresponds to a network information, which includes the total number of networks, physical unit location, interconnection relationship and physical unit occupancy rate. S32: Based on the circuit layout file, reverse-parse to obtain the FPGA circuit layout data, and convert the circuit layout data into a blocks array with s_block structure as elements. Each element in the blocks array corresponds to an occupied physical unit information, which includes the coordinates of the occupied physical unit, its network, input node, and output node. S33: Update the occupancy information of physical units in the grid array according to the clb_nets array and the blocks array; S34: Based on the updated grid array and the clb_nets array, mark all occupied physical units in the structure diagram to obtain the layout diagram of the FPGA, and draw the connection between the SOURCE node and SINK node corresponding to each network to obtain the interconnection diagram of the circuit layout. S4: Based on the chip and circuit design information, reverse engineer the circuit routing data of the FPGA, and draw the circuit routing data on the layout diagram to obtain the FPGA routing diagram; S4 includes: S41: Based on the circuit routing file, reverse parse to obtain the circuit routing data of the FPGA, and convert the circuit routing data into a trace_head array with route_node structure as elements. Each element in the trace_head array corresponds to a routing network information, which includes the SOURCE node, SINK node, routing resource node and routing driver relationship of the routing network. S42: Traverse the trace_head array, read the SOURCE node of each routing network, and draw the routing relationship of each routing network from the SOURCE node downwards in a chain structure on the layout diagram to obtain the routing diagram of the FPGA.
2. The analytical drawing method for FPGA chip models according to claim 1, characterized in that, In step S22, if there are sub-units in the physical unit, then all sub-units of the physical unit are traversed, the coordinates of each sub-unit are resolved, and the boundary of the sub-unit is drawn inside the physical unit.
3. A device for analyzing and drawing FPGA chip models, characterized in that, Implementing the method steps of any one of claims 1-2 includes: The information acquisition module is used to acquire chip and circuit design information; The chip structure drawing module is used to reverse analyze the chip structure data of the FPGA based on the chip and circuit design information, and to draw the structure diagram of the FPGA based on the chip structure data. The layout drawing module is used to reverse analyze the network data and circuit layout data of the FPGA based on the chip and circuit design information, and to draw on the structure diagram based on the network data and the circuit layout data to obtain the layout diagram of the FPGA and the interconnection relationship diagram of the circuit layout. The wiring diagram module is used to reverse analyze the circuit wiring data of the FPGA based on the chip and circuit design information, and draw the wiring diagram of the FPGA on the layout diagram based on the circuit wiring data.
4. An electronic device, characterized in that, This includes a processor, communication interface, memory, and communication bus, among which... The processor, communication interface, and memory communicate with each other through a communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-2.
5. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-2.